1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 545d24bcf1STomer Tayar 555d24bcf1STomer Tayar #define QED_MAJOR_VERSION 8 5642dbcd6bSManish Chopra #define QED_MINOR_VERSION 37 5741e87c91STomer Tayar #define QED_REVISION_VERSION 0 5841e87c91STomer Tayar #define QED_ENGINEERING_VERSION 20 595d24bcf1STomer Tayar 605d24bcf1STomer Tayar #define QED_VERSION \ 615d24bcf1STomer Tayar ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 625d24bcf1STomer Tayar (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 635d24bcf1STomer Tayar 645d24bcf1STomer Tayar #define STORM_FW_VERSION \ 655d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 665d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 69fe56b9e6SYuval Mintz #define NAME_SIZE 16 70fe56b9e6SYuval Mintz #define VER_SIZE 16 71fe56b9e6SYuval Mintz 72bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 73bcd197c8SManish Chopra 7451ff1725SRam Amrani #define QED_WID_SIZE (1024) 75107392b7SRam Amrani #define QED_MIN_WIDS (4) 7651ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 7751ff1725SRam Amrani 78fe56b9e6SYuval Mintz /* cau states */ 79fe56b9e6SYuval Mintz enum qed_coalescing_mode { 80fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 81fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 82fe56b9e6SYuval Mintz }; 83fe56b9e6SYuval Mintz 8462e4d438SSudarsana Reddy Kalluru enum qed_nvm_cmd { 8562e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 8662e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 8762e4d438SSudarsana Reddy Kalluru QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 8862e4d438SSudarsana Reddy Kalluru QED_GET_MCP_NVM_RESP = 0xFFFFFF00 8962e4d438SSudarsana Reddy Kalluru }; 9062e4d438SSudarsana Reddy Kalluru 91fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 92fe56b9e6SYuval Mintz struct qed_dev_info; 936c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 946c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 952528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type; 962528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data; 97fe56b9e6SYuval Mintz 98fe56b9e6SYuval Mintz /* helpers */ 995d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \ 1005d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 1015d24bcf1STomer Tayar 1025d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \ 1035d24bcf1STomer Tayar do { \ 104b19601bbSTomer Tayar (name) &= ~(field ## _MASK); \ 1055d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 1065d24bcf1STomer Tayar } while (0) 1075d24bcf1STomer Tayar 108fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 109fe56b9e6SYuval Mintz { 110fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 11151ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 11251ff1725SRam Amrani 11351ff1725SRam Amrani return db_addr; 11451ff1725SRam Amrani } 11551ff1725SRam Amrani 11651ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 11751ff1725SRam Amrani { 11851ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 119fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz return db_addr; 122fe56b9e6SYuval Mintz } 123fe56b9e6SYuval Mintz 124fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 125fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 126fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 129fe56b9e6SYuval Mintz 130fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 131fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 132fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz /* forward */ 135fe56b9e6SYuval Mintz struct qed_ptt_pool; 136fe56b9e6SYuval Mintz struct qed_spq; 137fe56b9e6SYuval Mintz struct qed_sb_info; 138fe56b9e6SYuval Mintz struct qed_sb_attn_info; 139fe56b9e6SYuval Mintz struct qed_cxt_mngr; 140fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1410a7fb11cSYuval Mintz struct qed_ll2_info; 142fe56b9e6SYuval Mintz struct qed_mcp_info; 14379284adeSMichal Kalderon struct qed_llh_info; 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz struct qed_rt_data { 146fc48b7a6SYuval Mintz u32 *init_val; 147fc48b7a6SYuval Mintz bool *b_valid; 148fe56b9e6SYuval Mintz }; 149fe56b9e6SYuval Mintz 150464f6645SManish Chopra enum qed_tunn_mode { 151464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 152464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 153464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 154464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 155464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 156464f6645SManish Chopra }; 157464f6645SManish Chopra 158464f6645SManish Chopra enum qed_tunn_clss { 159464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 160464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 161464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 162464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 16319968430SChopra, Manish QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 164464f6645SManish Chopra MAX_QED_TUNN_CLSS, 165464f6645SManish Chopra }; 166464f6645SManish Chopra 16719968430SChopra, Manish struct qed_tunn_update_type { 16819968430SChopra, Manish bool b_update_mode; 16919968430SChopra, Manish bool b_mode_enabled; 17019968430SChopra, Manish enum qed_tunn_clss tun_cls; 17119968430SChopra, Manish }; 17219968430SChopra, Manish 17319968430SChopra, Manish struct qed_tunn_update_udp_port { 17419968430SChopra, Manish bool b_update_port; 17519968430SChopra, Manish u16 port; 17619968430SChopra, Manish }; 17719968430SChopra, Manish 17819968430SChopra, Manish struct qed_tunnel_info { 17919968430SChopra, Manish struct qed_tunn_update_type vxlan; 18019968430SChopra, Manish struct qed_tunn_update_type l2_geneve; 18119968430SChopra, Manish struct qed_tunn_update_type ip_geneve; 18219968430SChopra, Manish struct qed_tunn_update_type l2_gre; 18319968430SChopra, Manish struct qed_tunn_update_type ip_gre; 18419968430SChopra, Manish 18519968430SChopra, Manish struct qed_tunn_update_udp_port vxlan_port; 18619968430SChopra, Manish struct qed_tunn_update_udp_port geneve_port; 18719968430SChopra, Manish 18819968430SChopra, Manish bool b_update_rx_cls; 18919968430SChopra, Manish bool b_update_tx_cls; 19019968430SChopra, Manish }; 19119968430SChopra, Manish 192464f6645SManish Chopra struct qed_tunn_start_params { 193464f6645SManish Chopra unsigned long tunn_mode; 194464f6645SManish Chopra u16 vxlan_udp_port; 195464f6645SManish Chopra u16 geneve_udp_port; 196464f6645SManish Chopra u8 update_vxlan_udp_port; 197464f6645SManish Chopra u8 update_geneve_udp_port; 198464f6645SManish Chopra u8 tunn_clss_vxlan; 199464f6645SManish Chopra u8 tunn_clss_l2geneve; 200464f6645SManish Chopra u8 tunn_clss_ipgeneve; 201464f6645SManish Chopra u8 tunn_clss_l2gre; 202464f6645SManish Chopra u8 tunn_clss_ipgre; 203464f6645SManish Chopra }; 204464f6645SManish Chopra 205464f6645SManish Chopra struct qed_tunn_update_params { 206464f6645SManish Chopra unsigned long tunn_mode_update_mask; 207464f6645SManish Chopra unsigned long tunn_mode; 208464f6645SManish Chopra u16 vxlan_udp_port; 209464f6645SManish Chopra u16 geneve_udp_port; 210464f6645SManish Chopra u8 update_rx_pf_clss; 211464f6645SManish Chopra u8 update_tx_pf_clss; 212464f6645SManish Chopra u8 update_vxlan_udp_port; 213464f6645SManish Chopra u8 update_geneve_udp_port; 214464f6645SManish Chopra u8 tunn_clss_vxlan; 215464f6645SManish Chopra u8 tunn_clss_l2geneve; 216464f6645SManish Chopra u8 tunn_clss_ipgeneve; 217464f6645SManish Chopra u8 tunn_clss_l2gre; 218464f6645SManish Chopra u8 tunn_clss_ipgre; 219464f6645SManish Chopra }; 220464f6645SManish Chopra 221fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 222fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 223c851a9dcSKalderon, Michal * 2. The Ethernet personality may support also the RoCE/iWARP protocol 224fe56b9e6SYuval Mintz */ 225fe56b9e6SYuval Mintz enum qed_pci_personality { 226fe56b9e6SYuval Mintz QED_PCI_ETH, 2271e128c81SArun Easi QED_PCI_FCOE, 228c5ac9319SYuval Mintz QED_PCI_ISCSI, 229c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 230c851a9dcSKalderon, Michal QED_PCI_ETH_IWARP, 231c851a9dcSKalderon, Michal QED_PCI_ETH_RDMA, 232c851a9dcSKalderon, Michal QED_PCI_DEFAULT, /* default in shmem */ 233fe56b9e6SYuval Mintz }; 234fe56b9e6SYuval Mintz 235fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 236fe56b9e6SYuval Mintz struct qed_qm_iids { 237fe56b9e6SYuval Mintz u32 cids; 238fe56b9e6SYuval Mintz u32 vf_cids; 239fe56b9e6SYuval Mintz u32 tids; 240fe56b9e6SYuval Mintz }; 241fe56b9e6SYuval Mintz 2422edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 2432edbff8dSTomer Tayar * is received from MFW. 2442edbff8dSTomer Tayar */ 2452edbff8dSTomer Tayar enum qed_resources { 246fe56b9e6SYuval Mintz QED_SB, 24725c089d7SYuval Mintz QED_L2_QUEUE, 248fe56b9e6SYuval Mintz QED_VPORT, 24925c089d7SYuval Mintz QED_RSS_ENG, 250fe56b9e6SYuval Mintz QED_PQ, 251fe56b9e6SYuval Mintz QED_RL, 25225c089d7SYuval Mintz QED_MAC, 25325c089d7SYuval Mintz QED_VLAN, 25451ff1725SRam Amrani QED_RDMA_CNQ_RAM, 255fe56b9e6SYuval Mintz QED_ILT, 256997af5dfSMichal Kalderon QED_LL2_RAM_QUEUE, 257997af5dfSMichal Kalderon QED_LL2_CTX_QUEUE, 2582edbff8dSTomer Tayar QED_CMDQS_CQS, 25951ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 2609c8517c4STomer Tayar QED_BDQ, 261fe56b9e6SYuval Mintz QED_MAX_RESC, 262fe56b9e6SYuval Mintz }; 263fe56b9e6SYuval Mintz 26425c089d7SYuval Mintz enum QED_FEATURE { 26525c089d7SYuval Mintz QED_PF_L2_QUE, 26632a47e72SYuval Mintz QED_VF, 26751ff1725SRam Amrani QED_RDMA_CNQ, 26808737a3fSMintz, Yuval QED_ISCSI_CQ, 2691e128c81SArun Easi QED_FCOE_CQ, 27008737a3fSMintz, Yuval QED_VF_L2_QUE, 27125c089d7SYuval Mintz QED_MAX_FEATURES, 27225c089d7SYuval Mintz }; 27325c089d7SYuval Mintz 274cc875c2eSYuval Mintz enum QED_PORT_MODE { 275cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 276cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 277cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 278cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 279cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 280cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 281cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 282cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 2839c79ddaaSMintz, Yuval QED_PORT_MODE_DE_1X25G, 2849c79ddaaSMintz, Yuval QED_PORT_MODE_DE_4X25G, 2859c79ddaaSMintz, Yuval QED_PORT_MODE_DE_2X10G, 286cc875c2eSYuval Mintz }; 287cc875c2eSYuval Mintz 288fc48b7a6SYuval Mintz enum qed_dev_cap { 289fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 2901e128c81SArun Easi QED_DEV_CAP_FCOE, 291c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 292c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 293c851a9dcSKalderon, Michal QED_DEV_CAP_IWARP, 294fc48b7a6SYuval Mintz }; 295fc48b7a6SYuval Mintz 29614d39648SMintz, Yuval enum qed_wol_support { 29714d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 29814d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 29914d39648SMintz, Yuval }; 30014d39648SMintz, Yuval 30136907cd5SAriel Elior enum qed_db_rec_exec { 30236907cd5SAriel Elior DB_REC_DRY_RUN, 30336907cd5SAriel Elior DB_REC_REAL_DEAL, 30436907cd5SAriel Elior DB_REC_ONCE, 30536907cd5SAriel Elior }; 30636907cd5SAriel Elior 307fe56b9e6SYuval Mintz struct qed_hw_info { 308fe56b9e6SYuval Mintz /* PCI personality */ 309fe56b9e6SYuval Mintz enum qed_pci_personality personality; 310c851a9dcSKalderon, Michal #define QED_IS_RDMA_PERSONALITY(dev) \ 311c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 312c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 313c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 314c851a9dcSKalderon, Michal #define QED_IS_ROCE_PERSONALITY(dev) \ 315c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 316c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 317c851a9dcSKalderon, Michal #define QED_IS_IWARP_PERSONALITY(dev) \ 318c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 319c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 320c851a9dcSKalderon, Michal #define QED_IS_L2_PERSONALITY(dev) \ 321c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH || \ 322c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(dev)) 323c851a9dcSKalderon, Michal #define QED_IS_FCOE_PERSONALITY(dev) \ 324c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_FCOE) 325c851a9dcSKalderon, Michal #define QED_IS_ISCSI_PERSONALITY(dev) \ 326c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ISCSI) 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 329fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 330fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 33125c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 334fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 335dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 336dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 337fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 338fe56b9e6SYuval Mintz 339b5a9ee7cSAriel Elior /* Amount of traffic classes HW supports */ 340b5a9ee7cSAriel Elior u8 num_hw_tc; 341b5a9ee7cSAriel Elior 342b5a9ee7cSAriel Elior /* Amount of TCs which should be active according to DCBx or upper 343b5a9ee7cSAriel Elior * layer driver configuration. 344b5a9ee7cSAriel Elior */ 345b5a9ee7cSAriel Elior u8 num_active_tc; 346fe56b9e6SYuval Mintz u8 offload_tc; 347c4259ddaSDenis Bolotin bool offload_tc_set; 348fe56b9e6SYuval Mintz 34961be82b0SDenis Bolotin bool multi_tc_roce_en; 35061be82b0SDenis Bolotin #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en)) 35161be82b0SDenis Bolotin 352fe56b9e6SYuval Mintz u32 concrete_fid; 353fe56b9e6SYuval Mintz u16 opaque_fid; 354fe56b9e6SYuval Mintz u16 ovlan; 355fe56b9e6SYuval Mintz u32 part_num[4]; 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 3581e128c81SArun Easi u64 node_wwn; 3591e128c81SArun Easi u64 port_wwn; 3601e128c81SArun Easi 3611e128c81SArun Easi u16 num_fcoe_conns; 362fe56b9e6SYuval Mintz 363fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 364fe56b9e6SYuval Mintz 365fe56b9e6SYuval Mintz u32 port_mode; 366fe56b9e6SYuval Mintz u32 hw_mode; 367fc48b7a6SYuval Mintz unsigned long device_capabilities; 3680fefbfbaSSudarsana Kalluru u16 mtu; 36914d39648SMintz, Yuval 37014d39648SMintz, Yuval enum qed_wol_support b_wol_support; 371fe56b9e6SYuval Mintz }; 372fe56b9e6SYuval Mintz 373fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 374fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz struct qed_dmae_info { 377fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 378fe56b9e6SYuval Mintz struct mutex mutex; 379fe56b9e6SYuval Mintz 380fe56b9e6SYuval Mintz u8 channel; 381fe56b9e6SYuval Mintz 382fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 383fe56b9e6SYuval Mintz 384fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 385fe56b9e6SYuval Mintz * value when an operation is finished on this context. 386fe56b9e6SYuval Mintz */ 387fe56b9e6SYuval Mintz u32 *p_completion_word; 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 390fe56b9e6SYuval Mintz 391fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 392fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 393fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 394fe56b9e6SYuval Mintz */ 395fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 396fe56b9e6SYuval Mintz 397fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 398fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 399fe56b9e6SYuval Mintz }; 400fe56b9e6SYuval Mintz 401bcd197c8SManish Chopra struct qed_wfq_data { 402bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 403bcd197c8SManish Chopra u32 min_speed; 404bcd197c8SManish Chopra bool configured; 405bcd197c8SManish Chopra }; 406bcd197c8SManish Chopra 407fe56b9e6SYuval Mintz struct qed_qm_info { 408fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 409fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 410fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 411fe56b9e6SYuval Mintz u16 start_pq; 412fe56b9e6SYuval Mintz u8 start_vport; 413b5a9ee7cSAriel Elior u16 pure_lb_pq; 41461be82b0SDenis Bolotin u16 first_ofld_pq; 41561be82b0SDenis Bolotin u16 first_llt_pq; 416b5a9ee7cSAriel Elior u16 pure_ack_pq; 417b5a9ee7cSAriel Elior u16 ooo_pq; 418b5a9ee7cSAriel Elior u16 first_vf_pq; 419b5a9ee7cSAriel Elior u16 first_mcos_pq; 420b5a9ee7cSAriel Elior u16 first_rl_pq; 421fe56b9e6SYuval Mintz u16 num_pqs; 422fe56b9e6SYuval Mintz u16 num_vf_pqs; 423fe56b9e6SYuval Mintz u8 num_vports; 424fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 425b5a9ee7cSAriel Elior u8 ooo_tc; 426fe56b9e6SYuval Mintz bool pf_rl_en; 427fe56b9e6SYuval Mintz bool pf_wfq_en; 428fe56b9e6SYuval Mintz bool vport_rl_en; 429fe56b9e6SYuval Mintz bool vport_wfq_en; 430fe56b9e6SYuval Mintz u8 pf_wfq; 431fe56b9e6SYuval Mintz u32 pf_rl; 432bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 433dbb799c3SYuval Mintz u8 num_pf_rls; 434fe56b9e6SYuval Mintz }; 435fe56b9e6SYuval Mintz 4360d72c2acSDenis Bolotin #define QED_OVERFLOW_BIT 1 4370d72c2acSDenis Bolotin 43836907cd5SAriel Elior struct qed_db_recovery_info { 43936907cd5SAriel Elior struct list_head list; 44036907cd5SAriel Elior 44136907cd5SAriel Elior /* Lock to protect the doorbell recovery mechanism list */ 44236907cd5SAriel Elior spinlock_t lock; 443d4476b8aSDenis Bolotin bool dorq_attn; 44436907cd5SAriel Elior u32 db_recovery_counter; 4450d72c2acSDenis Bolotin unsigned long overflow; 44636907cd5SAriel Elior }; 44736907cd5SAriel Elior 4489df2ed04SManish Chopra struct storm_stats { 4499df2ed04SManish Chopra u32 address; 4509df2ed04SManish Chopra u32 len; 4519df2ed04SManish Chopra }; 4529df2ed04SManish Chopra 4539df2ed04SManish Chopra struct qed_storm_stats { 4549df2ed04SManish Chopra struct storm_stats mstats; 4559df2ed04SManish Chopra struct storm_stats pstats; 4569df2ed04SManish Chopra struct storm_stats tstats; 4579df2ed04SManish Chopra struct storm_stats ustats; 4589df2ed04SManish Chopra }; 4599df2ed04SManish Chopra 460fe56b9e6SYuval Mintz struct qed_fw_data { 4619df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 462fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 463fe56b9e6SYuval Mintz union init_op *init_ops; 464fe56b9e6SYuval Mintz const u32 *arr_data; 46530d5f858SMichal Kalderon const u32 *fw_overlays; 46630d5f858SMichal Kalderon u32 fw_overlays_len; 467fe56b9e6SYuval Mintz u32 init_ops_size; 468fe56b9e6SYuval Mintz }; 469fe56b9e6SYuval Mintz 4700bc5fe85SSudarsana Reddy Kalluru enum qed_mf_mode_bit { 4710bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on tag */ 4720bc5fe85SSudarsana Reddy Kalluru QED_MF_OVLAN_CLSS, 4730bc5fe85SSudarsana Reddy Kalluru 4740bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on MAC */ 4750bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_MAC_CLSS, 4760bc5fe85SSudarsana Reddy Kalluru 4770bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on protocol type */ 4780bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_PROTO_CLSS, 4790bc5fe85SSudarsana Reddy Kalluru 4800bc5fe85SSudarsana Reddy Kalluru /* Requires a default PF to be set */ 4810bc5fe85SSudarsana Reddy Kalluru QED_MF_NEED_DEF_PF, 4820bc5fe85SSudarsana Reddy Kalluru 4830bc5fe85SSudarsana Reddy Kalluru /* Allow LL2 to multicast/broadcast */ 4840bc5fe85SSudarsana Reddy Kalluru QED_MF_LL2_NON_UNICAST, 4850bc5fe85SSudarsana Reddy Kalluru 4860bc5fe85SSudarsana Reddy Kalluru /* Allow Cross-PF [& child VFs] Tx-switching */ 4870bc5fe85SSudarsana Reddy Kalluru QED_MF_INTER_PF_SWITCH, 4880bc5fe85SSudarsana Reddy Kalluru 4890bc5fe85SSudarsana Reddy Kalluru /* Unified Fabtic Port support enabled */ 4900bc5fe85SSudarsana Reddy Kalluru QED_MF_UFP_SPECIFIC, 4910bc5fe85SSudarsana Reddy Kalluru 4920bc5fe85SSudarsana Reddy Kalluru /* Disable Accelerated Receive Flow Steering (aRFS) */ 4930bc5fe85SSudarsana Reddy Kalluru QED_MF_DISABLE_ARFS, 4940bc5fe85SSudarsana Reddy Kalluru 4950bc5fe85SSudarsana Reddy Kalluru /* Use vlan for steering */ 4960bc5fe85SSudarsana Reddy Kalluru QED_MF_8021Q_TAGGING, 4970bc5fe85SSudarsana Reddy Kalluru 4980bc5fe85SSudarsana Reddy Kalluru /* Use stag for steering */ 4990bc5fe85SSudarsana Reddy Kalluru QED_MF_8021AD_TAGGING, 5000bc5fe85SSudarsana Reddy Kalluru 5010bc5fe85SSudarsana Reddy Kalluru /* Allow DSCP to TC mapping */ 5020bc5fe85SSudarsana Reddy Kalluru QED_MF_DSCP_TO_TC_MAP, 5031a3ca250SSudarsana Reddy Kalluru 5041a3ca250SSudarsana Reddy Kalluru /* Do not insert a vlan tag with id 0 */ 5051a3ca250SSudarsana Reddy Kalluru QED_MF_DONT_ADD_VLAN0_TAG, 5060bc5fe85SSudarsana Reddy Kalluru }; 5070bc5fe85SSudarsana Reddy Kalluru 508cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode { 509cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_ETS, 510cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_VNIC_BW, 511cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_UNKNOWN 512cac6f691SSudarsana Reddy Kalluru }; 513cac6f691SSudarsana Reddy Kalluru 514cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type { 515cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_OS, 516cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_VNIC, 517cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_UNKNOWN 518cac6f691SSudarsana Reddy Kalluru }; 519cac6f691SSudarsana Reddy Kalluru 520cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info { 521cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type pri_type; 522cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode mode; 523cac6f691SSudarsana Reddy Kalluru u8 tc; 524cac6f691SSudarsana Reddy Kalluru }; 525cac6f691SSudarsana Reddy Kalluru 5261a850bfcSMintz, Yuval enum BAR_ID { 5271a850bfcSMintz, Yuval BAR_ID_0, /* used for GRC */ 5281a850bfcSMintz, Yuval BAR_ID_1 /* Used for doorbells */ 5291a850bfcSMintz, Yuval }; 5301a850bfcSMintz, Yuval 53143645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info { 53243645ce0SSudarsana Reddy Kalluru u32 num_images; 53343645ce0SSudarsana Reddy Kalluru struct bist_nvm_image_att *image_att; 5345e7ba042SDenis Bolotin bool valid; 53543645ce0SSudarsana Reddy Kalluru }; 53643645ce0SSudarsana Reddy Kalluru 5371392d19fSMichal Kalderon enum qed_hsi_def_type { 5381392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_VFS, 5391392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_L2_QUEUES, 5401392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_PORTS, 5411392d19fSMichal Kalderon QED_HSI_DEF_MAX_SB_PER_PATH, 5421392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_PFS, 5431392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_VPORTS, 5441392d19fSMichal Kalderon QED_HSI_DEF_NUM_ETH_RSS_ENGINE, 5451392d19fSMichal Kalderon QED_HSI_DEF_MAX_QM_TX_QUEUES, 5461392d19fSMichal Kalderon QED_HSI_DEF_NUM_PXP_ILT_RECORDS, 5471392d19fSMichal Kalderon QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS, 5481392d19fSMichal Kalderon QED_HSI_DEF_MAX_QM_GLOBAL_RLS, 5491392d19fSMichal Kalderon QED_HSI_DEF_MAX_PBF_CMD_LINES, 5501392d19fSMichal Kalderon QED_HSI_DEF_MAX_BTB_BLOCKS, 5511392d19fSMichal Kalderon QED_NUM_HSI_DEFS 5521392d19fSMichal Kalderon }; 5531392d19fSMichal Kalderon 5545d24bcf1STomer Tayar #define DRV_MODULE_VERSION \ 5555d24bcf1STomer Tayar __stringify(QED_MAJOR_VERSION) "." \ 5565d24bcf1STomer Tayar __stringify(QED_MINOR_VERSION) "." \ 5575d24bcf1STomer Tayar __stringify(QED_REVISION_VERSION) "." \ 5585d24bcf1STomer Tayar __stringify(QED_ENGINEERING_VERSION) 5595d24bcf1STomer Tayar 560fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 561fe56b9e6SYuval Mintz void *token; 562fe56b9e6SYuval Mintz void (*func)(void *); 563fe56b9e6SYuval Mintz }; 564fe56b9e6SYuval Mintz 56559ccf86fSSudarsana Reddy Kalluru enum qed_slowpath_wq_flag { 56659ccf86fSSudarsana Reddy Kalluru QED_SLOWPATH_MFW_TLV_REQ, 567a1b469b8SAriel Elior QED_SLOWPATH_PERIODIC_DB_REC, 56859ccf86fSSudarsana Reddy Kalluru }; 56959ccf86fSSudarsana Reddy Kalluru 570fe56b9e6SYuval Mintz struct qed_hwfn { 571fe56b9e6SYuval Mintz struct qed_dev *cdev; 572fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 573fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 574fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 575fe56b9e6SYuval Mintz u8 abs_pf_id; 5769c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \ 5779c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 578fe56b9e6SYuval Mintz u8 port_id; 579fe56b9e6SYuval Mintz bool b_active; 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz u32 dp_module; 582fe56b9e6SYuval Mintz u8 dp_level; 583fe56b9e6SYuval Mintz char name[NAME_SIZE]; 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz bool hw_init_done; 586fe56b9e6SYuval Mintz 5871408cc1fSYuval Mintz u8 num_funcs_on_engine; 588dbb799c3SYuval Mintz u8 enabled_func_idx; 5891408cc1fSYuval Mintz 590fe56b9e6SYuval Mintz /* BAR access */ 591fe56b9e6SYuval Mintz void __iomem *regview; 592fe56b9e6SYuval Mintz void __iomem *doorbells; 593fe56b9e6SYuval Mintz u64 db_phys_addr; 594fe56b9e6SYuval Mintz unsigned long db_size; 595fe56b9e6SYuval Mintz 596fe56b9e6SYuval Mintz /* PTT pool */ 597fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 598fe56b9e6SYuval Mintz 599fe56b9e6SYuval Mintz /* HW info */ 600fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 601fe56b9e6SYuval Mintz 602fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 603fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 604fe56b9e6SYuval Mintz 605fe56b9e6SYuval Mintz /* SPQ */ 606fe56b9e6SYuval Mintz struct qed_spq *p_spq; 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz /* EQ */ 609fe56b9e6SYuval Mintz struct qed_eq *p_eq; 610fe56b9e6SYuval Mintz 611fe56b9e6SYuval Mintz /* Consolidate Q*/ 612fe56b9e6SYuval Mintz struct qed_consq *p_consq; 613fe56b9e6SYuval Mintz 614fe56b9e6SYuval Mintz /* Slow-Path definitions */ 615fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 616fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 617fe56b9e6SYuval Mintz 618fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 619fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 620fe56b9e6SYuval Mintz 621d179bd16Ssudarsana.kalluru@cavium.com /* PTP will be used only by the leading function. 622d179bd16Ssudarsana.kalluru@cavium.com * Usage of all PTP-apis should be synchronized as result. 623d179bd16Ssudarsana.kalluru@cavium.com */ 624d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptp_ptt; 625d179bd16Ssudarsana.kalluru@cavium.com 626fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 627fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 628fe56b9e6SYuval Mintz 629fe56b9e6SYuval Mintz /* Protocol related */ 6300a7fb11cSYuval Mintz bool using_ll2; 6310a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 6321d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 63351ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 634fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 6351e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 636fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 637fe56b9e6SYuval Mintz 638dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 639dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 640dbb799c3SYuval Mintz 641fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 644fe56b9e6SYuval Mintz bool b_int_enabled; 6458f16bc97SSudarsana Kalluru bool b_int_requested; 646fe56b9e6SYuval Mintz 647fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 648fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 649fc916ff2SSudarsana Reddy Kalluru 6501408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 65132a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 652fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 653fe56b9e6SYuval Mintz 65439651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 65539651abdSSudarsana Reddy Kalluru 656cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info ufp_info; 657cac6f691SSudarsana Reddy Kalluru 658fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 659fe56b9e6SYuval Mintz 660fe56b9e6SYuval Mintz /* QM init */ 661fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 6629df2ed04SManish Chopra struct qed_storm_stats storm_stats; 663fe56b9e6SYuval Mintz 664fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 665fe56b9e6SYuval Mintz void *unzip_buf; 666fe56b9e6SYuval Mintz 667c965db44STomer Tayar struct dbg_tools_data dbg_info; 668a3f72307SDenis Bolotin void *dbg_user_info; 6692d22bc83SMichal Kalderon struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE]; 670c965db44STomer Tayar 67151ff1725SRam Amrani /* PWM region specific data */ 67220b1bd96SRam Amrani u16 wid_count; 67351ff1725SRam Amrani u32 dpi_size; 67451ff1725SRam Amrani u32 dpi_count; 67551ff1725SRam Amrani 67651ff1725SRam Amrani /* This is used to calculate the doorbell address */ 67751ff1725SRam Amrani u32 dpi_start_offset; 67851ff1725SRam Amrani 67951ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 68051ff1725SRam Amrani u8 dcbx_no_edpm; 68151ff1725SRam Amrani u8 db_bar_no_edpm; 68251ff1725SRam Amrani 6830db711bbSMintz, Yuval /* L2-related */ 6840db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 6850db711bbSMintz, Yuval 68636907cd5SAriel Elior /* Mechanism for recovering from doorbell drop */ 68736907cd5SAriel Elior struct qed_db_recovery_info db_recovery_info; 68836907cd5SAriel Elior 68943645ce0SSudarsana Reddy Kalluru /* Nvm images number and attributes */ 69043645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info nvm_info; 69143645ce0SSudarsana Reddy Kalluru 69230d5f858SMichal Kalderon struct phys_mem_desc *fw_overlay_mem; 693d51e4af5SChopra, Manish struct qed_ptt *p_arfs_ptt; 694d51e4af5SChopra, Manish 695fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 696fe56b9e6SYuval Mintz 69737bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 69837bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 69937bff2b9SYuval Mintz struct delayed_work iov_task; 70037bff2b9SYuval Mintz unsigned long iov_task_flags; 70137bff2b9SYuval Mintz #endif 702fe56b9e6SYuval Mintz struct z_stream_s *stream; 703a1b469b8SAriel Elior bool slowpath_wq_active; 70459ccf86fSSudarsana Reddy Kalluru struct workqueue_struct *slowpath_wq; 70559ccf86fSSudarsana Reddy Kalluru struct delayed_work slowpath_task; 70659ccf86fSSudarsana Reddy Kalluru unsigned long slowpath_task_flags; 707a1b469b8SAriel Elior u32 periodic_db_rec_count; 708fe56b9e6SYuval Mintz }; 709fe56b9e6SYuval Mintz 710fe56b9e6SYuval Mintz struct pci_params { 711fe56b9e6SYuval Mintz int pm_cap; 712fe56b9e6SYuval Mintz 713fe56b9e6SYuval Mintz unsigned long mem_start; 714fe56b9e6SYuval Mintz unsigned long mem_end; 715fe56b9e6SYuval Mintz unsigned int irq; 716fe56b9e6SYuval Mintz u8 pf_num; 717fe56b9e6SYuval Mintz }; 718fe56b9e6SYuval Mintz 719fe56b9e6SYuval Mintz struct qed_int_param { 720fe56b9e6SYuval Mintz u32 int_mode; 721fe56b9e6SYuval Mintz u8 num_vectors; 722fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 723fe56b9e6SYuval Mintz }; 724fe56b9e6SYuval Mintz 725fe56b9e6SYuval Mintz struct qed_int_params { 726fe56b9e6SYuval Mintz struct qed_int_param in; 727fe56b9e6SYuval Mintz struct qed_int_param out; 728fe56b9e6SYuval Mintz struct msix_entry *msix_table; 729fe56b9e6SYuval Mintz bool fp_initialized; 730fe56b9e6SYuval Mintz u8 fp_msix_base; 731fe56b9e6SYuval Mintz u8 fp_msix_cnt; 73251ff1725SRam Amrani u8 rdma_msix_base; 73351ff1725SRam Amrani u8 rdma_msix_cnt; 734fe56b9e6SYuval Mintz }; 735fe56b9e6SYuval Mintz 736c965db44STomer Tayar struct qed_dbg_feature { 737c965db44STomer Tayar struct dentry *dentry; 738c965db44STomer Tayar u8 *dump_buf; 739c965db44STomer Tayar u32 buf_size; 740c965db44STomer Tayar u32 dumped_dwords; 741c965db44STomer Tayar }; 742c965db44STomer Tayar 743c965db44STomer Tayar struct qed_dbg_params { 744c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 745c965db44STomer Tayar u8 engine_for_debug; 746c965db44STomer Tayar bool print_data; 747c965db44STomer Tayar }; 748c965db44STomer Tayar 749fe56b9e6SYuval Mintz struct qed_dev { 750fe56b9e6SYuval Mintz u32 dp_module; 751fe56b9e6SYuval Mintz u8 dp_level; 752fe56b9e6SYuval Mintz char name[NAME_SIZE]; 753fe56b9e6SYuval Mintz 7549c79ddaaSMintz, Yuval enum qed_dev_type type; 755fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 756fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 757fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 758fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 759c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 760c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 761fc48b7a6SYuval Mintz 762fc48b7a6SYuval Mintz u16 vendor_id; 763fc48b7a6SYuval Mintz u16 device_id; 7649c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00 7659c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600 7669c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000 76779284adeSMichal Kalderon #define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev)) 768fe56b9e6SYuval Mintz 769fe56b9e6SYuval Mintz u16 chip_num; 770fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 771fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 772fe56b9e6SYuval Mintz 773fe56b9e6SYuval Mintz u16 chip_rev; 774fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 775fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 776fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 777fe56b9e6SYuval Mintz 778fe56b9e6SYuval Mintz u16 chip_metal; 779fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 780fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 781fe56b9e6SYuval Mintz 782fe56b9e6SYuval Mintz u16 chip_bond_id; 783fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 784fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 785fe56b9e6SYuval Mintz 786fe56b9e6SYuval Mintz u8 num_engines; 7870ebcebbeSSudarsana Reddy Kalluru u8 num_ports; 78878cea9ffSTomer Tayar u8 num_ports_in_engine; 789fe56b9e6SYuval Mintz u8 num_funcs_in_port; 790fe56b9e6SYuval Mintz 791fe56b9e6SYuval Mintz u8 path_id; 7920bc5fe85SSudarsana Reddy Kalluru 7930bc5fe85SSudarsana Reddy Kalluru unsigned long mf_bits; 794fe56b9e6SYuval Mintz 795fe56b9e6SYuval Mintz int pcie_width; 796fe56b9e6SYuval Mintz int pcie_speed; 797fe56b9e6SYuval Mintz 798fe56b9e6SYuval Mintz /* Add MF related configuration */ 799fe56b9e6SYuval Mintz u8 mcp_rev; 800fe56b9e6SYuval Mintz u8 boot_mode; 801fe56b9e6SYuval Mintz 80214d39648SMintz, Yuval /* WoL related configurations */ 80314d39648SMintz, Yuval u8 wol_config; 80414d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 805fe56b9e6SYuval Mintz 806fe56b9e6SYuval Mintz u32 int_mode; 807fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 80851d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 80951d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 810fe56b9e6SYuval Mintz 811fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 812fe56b9e6SYuval Mintz void __iomem *regview; 813fe56b9e6SYuval Mintz void __iomem *doorbells; 814fe56b9e6SYuval Mintz u64 db_phys_addr; 815fe56b9e6SYuval Mintz unsigned long db_size; 816fe56b9e6SYuval Mintz 817fe56b9e6SYuval Mintz /* PCI */ 818fe56b9e6SYuval Mintz u8 cache_shift; 819fe56b9e6SYuval Mintz 820fe56b9e6SYuval Mintz /* Init */ 8212924e069SMichal Kalderon const u32 *iro_arr; 8222924e069SMichal Kalderon #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr) 823fe56b9e6SYuval Mintz 824fe56b9e6SYuval Mintz /* HW functions */ 825fe56b9e6SYuval Mintz u8 num_hwfns; 826fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 827fe56b9e6SYuval Mintz 82879284adeSMichal Kalderon /* Engine affinity */ 82979284adeSMichal Kalderon u8 l2_affin_hint; 83079284adeSMichal Kalderon u8 fir_affin; 83179284adeSMichal Kalderon u8 iwarp_affin; 83279284adeSMichal Kalderon 83332a47e72SYuval Mintz /* SRIOV */ 83432a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 83532a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 83619968430SChopra, Manish struct qed_tunnel_info tunnel; 8371408cc1fSYuval Mintz bool b_is_vf; 838fe56b9e6SYuval Mintz u32 drv_type; 839fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 840fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 841fe56b9e6SYuval Mintz 842fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 843fe56b9e6SYuval Mintz 84464515dc8STomer Tayar /* Recovery */ 84564515dc8STomer Tayar bool recov_in_prog; 84664515dc8STomer Tayar 84779284adeSMichal Kalderon /* LLH info */ 84879284adeSMichal Kalderon u8 ppfid_bitmap; 84979284adeSMichal Kalderon struct qed_llh_info *p_llh_info; 85079284adeSMichal Kalderon 851fe56b9e6SYuval Mintz /* Linux specific here */ 852fe56b9e6SYuval Mintz struct qede_dev *edev; 853fe56b9e6SYuval Mintz struct pci_dev *pdev; 854fc831825SYuval Mintz u32 flags; 855fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 856fe56b9e6SYuval Mintz int msg_enable; 857fe56b9e6SYuval Mintz 858fe56b9e6SYuval Mintz struct pci_params pci_params; 859fe56b9e6SYuval Mintz 860fe56b9e6SYuval Mintz struct qed_int_params int_params; 861fe56b9e6SYuval Mintz 862fe56b9e6SYuval Mintz u8 protocol; 863fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 8641e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 865fe56b9e6SYuval Mintz 866cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 867cc875c2eSYuval Mintz union { 868cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 869cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 8701e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe; 871fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 872cc875c2eSYuval Mintz } protocol_ops; 873cc875c2eSYuval Mintz void *ops_cookie; 874cc875c2eSYuval Mintz 875c965db44STomer Tayar struct qed_dbg_params dbg_params; 876c965db44STomer Tayar 8770a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 8780a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 8790a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 8800a7fb11cSYuval Mintz #endif 8812d22bc83SMichal Kalderon struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM]; 8828a52bbabSMichal Kalderon bool disable_ilt_dump; 883fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 884fe56b9e6SYuval Mintz const struct firmware *firmware; 88551ff1725SRam Amrani 88651ff1725SRam Amrani u32 rdma_max_sge; 88751ff1725SRam Amrani u32 rdma_max_inline; 88851ff1725SRam Amrani u32 rdma_max_srq_sge; 889eaf3c0c6SChopra, Manish u16 tunn_feature_mask; 89024e04879SMichal Kalderon 89124e04879SMichal Kalderon struct devlink *dl; 89224e04879SMichal Kalderon bool iwarp_cmt; 893fe56b9e6SYuval Mintz }; 894fe56b9e6SYuval Mintz 8951392d19fSMichal Kalderon u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type); 8961392d19fSMichal Kalderon 8971392d19fSMichal Kalderon #define NUM_OF_VFS(dev) \ 8981392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS) 8991392d19fSMichal Kalderon #define NUM_OF_L2_QUEUES(dev) \ 9001392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES) 9011392d19fSMichal Kalderon #define NUM_OF_PORTS(dev) \ 9021392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS) 9031392d19fSMichal Kalderon #define NUM_OF_SBS(dev) \ 9041392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH) 9051392d19fSMichal Kalderon #define NUM_OF_ENG_PFS(dev) \ 9061392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS) 9071392d19fSMichal Kalderon #define NUM_OF_VPORTS(dev) \ 9081392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS) 9091392d19fSMichal Kalderon #define NUM_OF_RSS_ENGINES(dev) \ 9101392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE) 9111392d19fSMichal Kalderon #define NUM_OF_QM_TX_QUEUES(dev) \ 9121392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES) 9131392d19fSMichal Kalderon #define NUM_OF_PXP_ILT_RECORDS(dev) \ 9141392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS) 9151392d19fSMichal Kalderon #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \ 9161392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS) 9171392d19fSMichal Kalderon #define NUM_OF_QM_GLOBAL_RLS(dev) \ 9181392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS) 9191392d19fSMichal Kalderon #define NUM_OF_PBF_CMD_LINES(dev) \ 9201392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES) 9211392d19fSMichal Kalderon #define NUM_OF_BTB_BLOCKS(dev) \ 9221392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS) 9231392d19fSMichal Kalderon 924fe56b9e6SYuval Mintz 925fe56b9e6SYuval Mintz /** 926fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 927fe56b9e6SYuval Mintz * the concrete value. 928fe56b9e6SYuval Mintz * 929fe56b9e6SYuval Mintz * @param concrete_fid 930fe56b9e6SYuval Mintz * 931fe56b9e6SYuval Mintz * @return inline u8 932fe56b9e6SYuval Mintz */ 933fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 934fe56b9e6SYuval Mintz u32 concrete_fid) 935fe56b9e6SYuval Mintz { 9364870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 937fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 9384870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 9394870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 9404870e704SYuval Mintz u8 sw_fid; 941fe56b9e6SYuval Mintz 9424870e704SYuval Mintz if (vf_valid) 9434870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 9444870e704SYuval Mintz else 9454870e704SYuval Mintz sw_fid = pfid; 9464870e704SYuval Mintz 9474870e704SYuval Mintz return sw_fid; 948fe56b9e6SYuval Mintz } 949fe56b9e6SYuval Mintz 950526d1d05SKalderon, Michal #define PKT_LB_TC 9 951da090917STomer Tayar #define MAX_NUM_VOQS_E4 20 952fe56b9e6SYuval Mintz 953733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 9546f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 9556f437d43SMintz, Yuval struct qed_ptt *p_ptt, 9566f437d43SMintz, Yuval u32 min_pf_rate); 957bcd197c8SManish Chopra 958733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 9599c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev); 960456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 961456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); 962fe56b9e6SYuval Mintz 963b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 96479284adeSMichal Kalderon #define QED_IS_CMT(dev) ((dev)->num_hwfns > 1) 96579284adeSMichal Kalderon /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */ 96679284adeSMichal Kalderon #define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin]) 96779284adeSMichal Kalderon #define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin]) 96879284adeSMichal Kalderon #define QED_AFFIN_HWFN(dev) \ 96979284adeSMichal Kalderon (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \ 97079284adeSMichal Kalderon QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev)) 97179284adeSMichal Kalderon #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1) 972b5a9ee7cSAriel Elior 973b5a9ee7cSAriel Elior /* Flags for indication of required queues */ 974b5a9ee7cSAriel Elior #define PQ_FLAGS_RLS (BIT(0)) 975b5a9ee7cSAriel Elior #define PQ_FLAGS_MCOS (BIT(1)) 976b5a9ee7cSAriel Elior #define PQ_FLAGS_LB (BIT(2)) 977b5a9ee7cSAriel Elior #define PQ_FLAGS_OOO (BIT(3)) 978b5a9ee7cSAriel Elior #define PQ_FLAGS_ACK (BIT(4)) 979b5a9ee7cSAriel Elior #define PQ_FLAGS_OFLD (BIT(5)) 980b5a9ee7cSAriel Elior #define PQ_FLAGS_VFS (BIT(6)) 981b5a9ee7cSAriel Elior #define PQ_FLAGS_LLT (BIT(7)) 98261be82b0SDenis Bolotin #define PQ_FLAGS_MTC (BIT(8)) 983b5a9ee7cSAriel Elior 984b5a9ee7cSAriel Elior /* physical queue index for cm context intialization */ 985b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 986b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 987b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 98861be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc); 98961be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc); 990b5a9ee7cSAriel Elior 991a1b469b8SAriel Elior /* doorbell recovery mechanism */ 992a1b469b8SAriel Elior void qed_db_recovery_dp(struct qed_hwfn *p_hwfn); 9939ac6bb14SDenis Bolotin void qed_db_recovery_execute(struct qed_hwfn *p_hwfn); 994a1b469b8SAriel Elior bool qed_edpm_enabled(struct qed_hwfn *p_hwfn); 995a1b469b8SAriel Elior 996fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 997fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 998fe56b9e6SYuval Mintz 999fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 1000fe56b9e6SYuval Mintz (cdev->regview) + \ 1001fe56b9e6SYuval Mintz (offset)) 1002fe56b9e6SYuval Mintz 1003fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 1004fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 1005fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 1006fe56b9e6SYuval Mintz 1007fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 1008fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 1009fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 1010fe56b9e6SYuval Mintz 10110ebcebbeSSudarsana Reddy Kalluru #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 10120ebcebbeSSudarsana Reddy Kalluru qed_device_num_ports((_p_hwfn)->cdev)) 10130ebcebbeSSudarsana Reddy Kalluru int qed_device_num_ports(struct qed_dev *cdev); 10140ebcebbeSSudarsana Reddy Kalluru 1015fe56b9e6SYuval Mintz /* Prototypes */ 1016fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 1017fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 1018706d0891SRahul Verma void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt); 1019699fed4aSSudarsana Reddy Kalluru void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt); 1020fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 1021fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 1022fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 102364515dc8STomer Tayar void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn); 10246c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 10256c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 10266c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 10278f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 10281226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 102959ccf86fSSudarsana Reddy Kalluru int qed_mfw_tlv_req(struct qed_hwfn *hwfn); 10308f16bc97SSudarsana Kalluru 10312528c389SSudarsana Reddy Kalluru int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, 10322528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type type, 10332528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data *tlv_data); 1034c4259ddaSDenis Bolotin 1035c4259ddaSDenis Bolotin void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc); 1036a1b469b8SAriel Elior 1037a1b469b8SAriel Elior void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn); 1038fe56b9e6SYuval Mintz #endif /* _QED_H */ 1039