1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 545d24bcf1STomer Tayar 555d24bcf1STomer Tayar #define QED_MAJOR_VERSION 8 5641e87c91STomer Tayar #define QED_MINOR_VERSION 33 5741e87c91STomer Tayar #define QED_REVISION_VERSION 0 5841e87c91STomer Tayar #define QED_ENGINEERING_VERSION 20 595d24bcf1STomer Tayar 605d24bcf1STomer Tayar #define QED_VERSION \ 615d24bcf1STomer Tayar ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 625d24bcf1STomer Tayar (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 635d24bcf1STomer Tayar 645d24bcf1STomer Tayar #define STORM_FW_VERSION \ 655d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 665d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 69fe56b9e6SYuval Mintz #define NAME_SIZE 16 70fe56b9e6SYuval Mintz #define VER_SIZE 16 71fe56b9e6SYuval Mintz 72bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 73bcd197c8SManish Chopra 7451ff1725SRam Amrani #define QED_WID_SIZE (1024) 75107392b7SRam Amrani #define QED_MIN_WIDS (4) 7651ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 7751ff1725SRam Amrani 78fe56b9e6SYuval Mintz /* cau states */ 79fe56b9e6SYuval Mintz enum qed_coalescing_mode { 80fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 81fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 82fe56b9e6SYuval Mintz }; 83fe56b9e6SYuval Mintz 8462e4d438SSudarsana Reddy Kalluru enum qed_nvm_cmd { 8562e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 8662e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 8762e4d438SSudarsana Reddy Kalluru QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 8862e4d438SSudarsana Reddy Kalluru QED_GET_MCP_NVM_RESP = 0xFFFFFF00 8962e4d438SSudarsana Reddy Kalluru }; 9062e4d438SSudarsana Reddy Kalluru 91fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 92fe56b9e6SYuval Mintz struct qed_dev_info; 936c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 946c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 952528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type; 962528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data; 97fe56b9e6SYuval Mintz 98fe56b9e6SYuval Mintz /* helpers */ 995d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \ 1005d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 1015d24bcf1STomer Tayar 1025d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \ 1035d24bcf1STomer Tayar do { \ 104b19601bbSTomer Tayar (name) &= ~(field ## _MASK); \ 1055d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 1065d24bcf1STomer Tayar } while (0) 1075d24bcf1STomer Tayar 108fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 109fe56b9e6SYuval Mintz { 110fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 11151ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 11251ff1725SRam Amrani 11351ff1725SRam Amrani return db_addr; 11451ff1725SRam Amrani } 11551ff1725SRam Amrani 11651ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 11751ff1725SRam Amrani { 11851ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 119fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz return db_addr; 122fe56b9e6SYuval Mintz } 123fe56b9e6SYuval Mintz 124fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 125fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 126fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 129fe56b9e6SYuval Mintz 130fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 131fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 132fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz /* forward */ 135fe56b9e6SYuval Mintz struct qed_ptt_pool; 136fe56b9e6SYuval Mintz struct qed_spq; 137fe56b9e6SYuval Mintz struct qed_sb_info; 138fe56b9e6SYuval Mintz struct qed_sb_attn_info; 139fe56b9e6SYuval Mintz struct qed_cxt_mngr; 140fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1410a7fb11cSYuval Mintz struct qed_ll2_info; 142fe56b9e6SYuval Mintz struct qed_mcp_info; 143fe56b9e6SYuval Mintz 144fe56b9e6SYuval Mintz struct qed_rt_data { 145fc48b7a6SYuval Mintz u32 *init_val; 146fc48b7a6SYuval Mintz bool *b_valid; 147fe56b9e6SYuval Mintz }; 148fe56b9e6SYuval Mintz 149464f6645SManish Chopra enum qed_tunn_mode { 150464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 151464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 152464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 153464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 154464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 155464f6645SManish Chopra }; 156464f6645SManish Chopra 157464f6645SManish Chopra enum qed_tunn_clss { 158464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 159464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 160464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 161464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 16219968430SChopra, Manish QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 163464f6645SManish Chopra MAX_QED_TUNN_CLSS, 164464f6645SManish Chopra }; 165464f6645SManish Chopra 16619968430SChopra, Manish struct qed_tunn_update_type { 16719968430SChopra, Manish bool b_update_mode; 16819968430SChopra, Manish bool b_mode_enabled; 16919968430SChopra, Manish enum qed_tunn_clss tun_cls; 17019968430SChopra, Manish }; 17119968430SChopra, Manish 17219968430SChopra, Manish struct qed_tunn_update_udp_port { 17319968430SChopra, Manish bool b_update_port; 17419968430SChopra, Manish u16 port; 17519968430SChopra, Manish }; 17619968430SChopra, Manish 17719968430SChopra, Manish struct qed_tunnel_info { 17819968430SChopra, Manish struct qed_tunn_update_type vxlan; 17919968430SChopra, Manish struct qed_tunn_update_type l2_geneve; 18019968430SChopra, Manish struct qed_tunn_update_type ip_geneve; 18119968430SChopra, Manish struct qed_tunn_update_type l2_gre; 18219968430SChopra, Manish struct qed_tunn_update_type ip_gre; 18319968430SChopra, Manish 18419968430SChopra, Manish struct qed_tunn_update_udp_port vxlan_port; 18519968430SChopra, Manish struct qed_tunn_update_udp_port geneve_port; 18619968430SChopra, Manish 18719968430SChopra, Manish bool b_update_rx_cls; 18819968430SChopra, Manish bool b_update_tx_cls; 18919968430SChopra, Manish }; 19019968430SChopra, Manish 191464f6645SManish Chopra struct qed_tunn_start_params { 192464f6645SManish Chopra unsigned long tunn_mode; 193464f6645SManish Chopra u16 vxlan_udp_port; 194464f6645SManish Chopra u16 geneve_udp_port; 195464f6645SManish Chopra u8 update_vxlan_udp_port; 196464f6645SManish Chopra u8 update_geneve_udp_port; 197464f6645SManish Chopra u8 tunn_clss_vxlan; 198464f6645SManish Chopra u8 tunn_clss_l2geneve; 199464f6645SManish Chopra u8 tunn_clss_ipgeneve; 200464f6645SManish Chopra u8 tunn_clss_l2gre; 201464f6645SManish Chopra u8 tunn_clss_ipgre; 202464f6645SManish Chopra }; 203464f6645SManish Chopra 204464f6645SManish Chopra struct qed_tunn_update_params { 205464f6645SManish Chopra unsigned long tunn_mode_update_mask; 206464f6645SManish Chopra unsigned long tunn_mode; 207464f6645SManish Chopra u16 vxlan_udp_port; 208464f6645SManish Chopra u16 geneve_udp_port; 209464f6645SManish Chopra u8 update_rx_pf_clss; 210464f6645SManish Chopra u8 update_tx_pf_clss; 211464f6645SManish Chopra u8 update_vxlan_udp_port; 212464f6645SManish Chopra u8 update_geneve_udp_port; 213464f6645SManish Chopra u8 tunn_clss_vxlan; 214464f6645SManish Chopra u8 tunn_clss_l2geneve; 215464f6645SManish Chopra u8 tunn_clss_ipgeneve; 216464f6645SManish Chopra u8 tunn_clss_l2gre; 217464f6645SManish Chopra u8 tunn_clss_ipgre; 218464f6645SManish Chopra }; 219464f6645SManish Chopra 220fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 221fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 222c851a9dcSKalderon, Michal * 2. The Ethernet personality may support also the RoCE/iWARP protocol 223fe56b9e6SYuval Mintz */ 224fe56b9e6SYuval Mintz enum qed_pci_personality { 225fe56b9e6SYuval Mintz QED_PCI_ETH, 2261e128c81SArun Easi QED_PCI_FCOE, 227c5ac9319SYuval Mintz QED_PCI_ISCSI, 228c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 229c851a9dcSKalderon, Michal QED_PCI_ETH_IWARP, 230c851a9dcSKalderon, Michal QED_PCI_ETH_RDMA, 231c851a9dcSKalderon, Michal QED_PCI_DEFAULT, /* default in shmem */ 232fe56b9e6SYuval Mintz }; 233fe56b9e6SYuval Mintz 234fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 235fe56b9e6SYuval Mintz struct qed_qm_iids { 236fe56b9e6SYuval Mintz u32 cids; 237fe56b9e6SYuval Mintz u32 vf_cids; 238fe56b9e6SYuval Mintz u32 tids; 239fe56b9e6SYuval Mintz }; 240fe56b9e6SYuval Mintz 2412edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 2422edbff8dSTomer Tayar * is received from MFW. 2432edbff8dSTomer Tayar */ 2442edbff8dSTomer Tayar enum qed_resources { 245fe56b9e6SYuval Mintz QED_SB, 24625c089d7SYuval Mintz QED_L2_QUEUE, 247fe56b9e6SYuval Mintz QED_VPORT, 24825c089d7SYuval Mintz QED_RSS_ENG, 249fe56b9e6SYuval Mintz QED_PQ, 250fe56b9e6SYuval Mintz QED_RL, 25125c089d7SYuval Mintz QED_MAC, 25225c089d7SYuval Mintz QED_VLAN, 25351ff1725SRam Amrani QED_RDMA_CNQ_RAM, 254fe56b9e6SYuval Mintz QED_ILT, 2550a7fb11cSYuval Mintz QED_LL2_QUEUE, 2562edbff8dSTomer Tayar QED_CMDQS_CQS, 25751ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 2589c8517c4STomer Tayar QED_BDQ, 259fe56b9e6SYuval Mintz QED_MAX_RESC, 260fe56b9e6SYuval Mintz }; 261fe56b9e6SYuval Mintz 26225c089d7SYuval Mintz enum QED_FEATURE { 26325c089d7SYuval Mintz QED_PF_L2_QUE, 26432a47e72SYuval Mintz QED_VF, 26551ff1725SRam Amrani QED_RDMA_CNQ, 26608737a3fSMintz, Yuval QED_ISCSI_CQ, 2671e128c81SArun Easi QED_FCOE_CQ, 26808737a3fSMintz, Yuval QED_VF_L2_QUE, 26925c089d7SYuval Mintz QED_MAX_FEATURES, 27025c089d7SYuval Mintz }; 27125c089d7SYuval Mintz 272cc875c2eSYuval Mintz enum QED_PORT_MODE { 273cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 274cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 275cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 276cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 277cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 278cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 279cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 280cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 2819c79ddaaSMintz, Yuval QED_PORT_MODE_DE_1X25G, 2829c79ddaaSMintz, Yuval QED_PORT_MODE_DE_4X25G, 2839c79ddaaSMintz, Yuval QED_PORT_MODE_DE_2X10G, 284cc875c2eSYuval Mintz }; 285cc875c2eSYuval Mintz 286fc48b7a6SYuval Mintz enum qed_dev_cap { 287fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 2881e128c81SArun Easi QED_DEV_CAP_FCOE, 289c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 290c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 291c851a9dcSKalderon, Michal QED_DEV_CAP_IWARP, 292fc48b7a6SYuval Mintz }; 293fc48b7a6SYuval Mintz 29414d39648SMintz, Yuval enum qed_wol_support { 29514d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 29614d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 29714d39648SMintz, Yuval }; 29814d39648SMintz, Yuval 299fe56b9e6SYuval Mintz struct qed_hw_info { 300fe56b9e6SYuval Mintz /* PCI personality */ 301fe56b9e6SYuval Mintz enum qed_pci_personality personality; 302c851a9dcSKalderon, Michal #define QED_IS_RDMA_PERSONALITY(dev) \ 303c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 304c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 305c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 306c851a9dcSKalderon, Michal #define QED_IS_ROCE_PERSONALITY(dev) \ 307c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 308c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 309c851a9dcSKalderon, Michal #define QED_IS_IWARP_PERSONALITY(dev) \ 310c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 311c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 312c851a9dcSKalderon, Michal #define QED_IS_L2_PERSONALITY(dev) \ 313c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH || \ 314c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(dev)) 315c851a9dcSKalderon, Michal #define QED_IS_FCOE_PERSONALITY(dev) \ 316c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_FCOE) 317c851a9dcSKalderon, Michal #define QED_IS_ISCSI_PERSONALITY(dev) \ 318c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ISCSI) 319fe56b9e6SYuval Mintz 320fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 321fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 322fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 32325c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 324fe56b9e6SYuval Mintz 325fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 326fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 327dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 328dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 329fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 330fe56b9e6SYuval Mintz 331b5a9ee7cSAriel Elior /* Amount of traffic classes HW supports */ 332b5a9ee7cSAriel Elior u8 num_hw_tc; 333b5a9ee7cSAriel Elior 334b5a9ee7cSAriel Elior /* Amount of TCs which should be active according to DCBx or upper 335b5a9ee7cSAriel Elior * layer driver configuration. 336b5a9ee7cSAriel Elior */ 337b5a9ee7cSAriel Elior u8 num_active_tc; 338fe56b9e6SYuval Mintz u8 offload_tc; 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz u32 concrete_fid; 341fe56b9e6SYuval Mintz u16 opaque_fid; 342fe56b9e6SYuval Mintz u16 ovlan; 343fe56b9e6SYuval Mintz u32 part_num[4]; 344fe56b9e6SYuval Mintz 345fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 3461e128c81SArun Easi u64 node_wwn; 3471e128c81SArun Easi u64 port_wwn; 3481e128c81SArun Easi 3491e128c81SArun Easi u16 num_fcoe_conns; 350fe56b9e6SYuval Mintz 351fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 352fe56b9e6SYuval Mintz 353fe56b9e6SYuval Mintz u32 port_mode; 354fe56b9e6SYuval Mintz u32 hw_mode; 355fc48b7a6SYuval Mintz unsigned long device_capabilities; 3560fefbfbaSSudarsana Kalluru u16 mtu; 35714d39648SMintz, Yuval 35814d39648SMintz, Yuval enum qed_wol_support b_wol_support; 359fe56b9e6SYuval Mintz }; 360fe56b9e6SYuval Mintz 361fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 362fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 363fe56b9e6SYuval Mintz 364fe56b9e6SYuval Mintz struct qed_dmae_info { 365fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 366fe56b9e6SYuval Mintz struct mutex mutex; 367fe56b9e6SYuval Mintz 368fe56b9e6SYuval Mintz u8 channel; 369fe56b9e6SYuval Mintz 370fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 371fe56b9e6SYuval Mintz 372fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 373fe56b9e6SYuval Mintz * value when an operation is finished on this context. 374fe56b9e6SYuval Mintz */ 375fe56b9e6SYuval Mintz u32 *p_completion_word; 376fe56b9e6SYuval Mintz 377fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 378fe56b9e6SYuval Mintz 379fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 380fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 381fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 382fe56b9e6SYuval Mintz */ 383fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 384fe56b9e6SYuval Mintz 385fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 386fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 387fe56b9e6SYuval Mintz }; 388fe56b9e6SYuval Mintz 389bcd197c8SManish Chopra struct qed_wfq_data { 390bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 391bcd197c8SManish Chopra u32 min_speed; 392bcd197c8SManish Chopra bool configured; 393bcd197c8SManish Chopra }; 394bcd197c8SManish Chopra 395fe56b9e6SYuval Mintz struct qed_qm_info { 396fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 397fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 398fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 399fe56b9e6SYuval Mintz u16 start_pq; 400fe56b9e6SYuval Mintz u8 start_vport; 401b5a9ee7cSAriel Elior u16 pure_lb_pq; 402b5a9ee7cSAriel Elior u16 offload_pq; 403b5a9ee7cSAriel Elior u16 low_latency_pq; 404b5a9ee7cSAriel Elior u16 pure_ack_pq; 405b5a9ee7cSAriel Elior u16 ooo_pq; 406b5a9ee7cSAriel Elior u16 first_vf_pq; 407b5a9ee7cSAriel Elior u16 first_mcos_pq; 408b5a9ee7cSAriel Elior u16 first_rl_pq; 409fe56b9e6SYuval Mintz u16 num_pqs; 410fe56b9e6SYuval Mintz u16 num_vf_pqs; 411fe56b9e6SYuval Mintz u8 num_vports; 412fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 413b5a9ee7cSAriel Elior u8 ooo_tc; 414fe56b9e6SYuval Mintz bool pf_rl_en; 415fe56b9e6SYuval Mintz bool pf_wfq_en; 416fe56b9e6SYuval Mintz bool vport_rl_en; 417fe56b9e6SYuval Mintz bool vport_wfq_en; 418fe56b9e6SYuval Mintz u8 pf_wfq; 419fe56b9e6SYuval Mintz u32 pf_rl; 420bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 421dbb799c3SYuval Mintz u8 num_pf_rls; 422fe56b9e6SYuval Mintz }; 423fe56b9e6SYuval Mintz 4249df2ed04SManish Chopra struct storm_stats { 4259df2ed04SManish Chopra u32 address; 4269df2ed04SManish Chopra u32 len; 4279df2ed04SManish Chopra }; 4289df2ed04SManish Chopra 4299df2ed04SManish Chopra struct qed_storm_stats { 4309df2ed04SManish Chopra struct storm_stats mstats; 4319df2ed04SManish Chopra struct storm_stats pstats; 4329df2ed04SManish Chopra struct storm_stats tstats; 4339df2ed04SManish Chopra struct storm_stats ustats; 4349df2ed04SManish Chopra }; 4359df2ed04SManish Chopra 436fe56b9e6SYuval Mintz struct qed_fw_data { 4379df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 438fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 439fe56b9e6SYuval Mintz union init_op *init_ops; 440fe56b9e6SYuval Mintz const u32 *arr_data; 441fe56b9e6SYuval Mintz u32 init_ops_size; 442fe56b9e6SYuval Mintz }; 443fe56b9e6SYuval Mintz 4440bc5fe85SSudarsana Reddy Kalluru enum qed_mf_mode_bit { 4450bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on tag */ 4460bc5fe85SSudarsana Reddy Kalluru QED_MF_OVLAN_CLSS, 4470bc5fe85SSudarsana Reddy Kalluru 4480bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on MAC */ 4490bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_MAC_CLSS, 4500bc5fe85SSudarsana Reddy Kalluru 4510bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on protocol type */ 4520bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_PROTO_CLSS, 4530bc5fe85SSudarsana Reddy Kalluru 4540bc5fe85SSudarsana Reddy Kalluru /* Requires a default PF to be set */ 4550bc5fe85SSudarsana Reddy Kalluru QED_MF_NEED_DEF_PF, 4560bc5fe85SSudarsana Reddy Kalluru 4570bc5fe85SSudarsana Reddy Kalluru /* Allow LL2 to multicast/broadcast */ 4580bc5fe85SSudarsana Reddy Kalluru QED_MF_LL2_NON_UNICAST, 4590bc5fe85SSudarsana Reddy Kalluru 4600bc5fe85SSudarsana Reddy Kalluru /* Allow Cross-PF [& child VFs] Tx-switching */ 4610bc5fe85SSudarsana Reddy Kalluru QED_MF_INTER_PF_SWITCH, 4620bc5fe85SSudarsana Reddy Kalluru 4630bc5fe85SSudarsana Reddy Kalluru /* Unified Fabtic Port support enabled */ 4640bc5fe85SSudarsana Reddy Kalluru QED_MF_UFP_SPECIFIC, 4650bc5fe85SSudarsana Reddy Kalluru 4660bc5fe85SSudarsana Reddy Kalluru /* Disable Accelerated Receive Flow Steering (aRFS) */ 4670bc5fe85SSudarsana Reddy Kalluru QED_MF_DISABLE_ARFS, 4680bc5fe85SSudarsana Reddy Kalluru 4690bc5fe85SSudarsana Reddy Kalluru /* Use vlan for steering */ 4700bc5fe85SSudarsana Reddy Kalluru QED_MF_8021Q_TAGGING, 4710bc5fe85SSudarsana Reddy Kalluru 4720bc5fe85SSudarsana Reddy Kalluru /* Use stag for steering */ 4730bc5fe85SSudarsana Reddy Kalluru QED_MF_8021AD_TAGGING, 4740bc5fe85SSudarsana Reddy Kalluru 4750bc5fe85SSudarsana Reddy Kalluru /* Allow DSCP to TC mapping */ 4760bc5fe85SSudarsana Reddy Kalluru QED_MF_DSCP_TO_TC_MAP, 4770bc5fe85SSudarsana Reddy Kalluru }; 4780bc5fe85SSudarsana Reddy Kalluru 479cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode { 480cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_ETS, 481cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_VNIC_BW, 482cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_UNKNOWN 483cac6f691SSudarsana Reddy Kalluru }; 484cac6f691SSudarsana Reddy Kalluru 485cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type { 486cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_OS, 487cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_VNIC, 488cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_UNKNOWN 489cac6f691SSudarsana Reddy Kalluru }; 490cac6f691SSudarsana Reddy Kalluru 491cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info { 492cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type pri_type; 493cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode mode; 494cac6f691SSudarsana Reddy Kalluru u8 tc; 495cac6f691SSudarsana Reddy Kalluru }; 496cac6f691SSudarsana Reddy Kalluru 4971a850bfcSMintz, Yuval enum BAR_ID { 4981a850bfcSMintz, Yuval BAR_ID_0, /* used for GRC */ 4991a850bfcSMintz, Yuval BAR_ID_1 /* Used for doorbells */ 5001a850bfcSMintz, Yuval }; 5011a850bfcSMintz, Yuval 50243645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info { 50343645ce0SSudarsana Reddy Kalluru u32 num_images; 50443645ce0SSudarsana Reddy Kalluru struct bist_nvm_image_att *image_att; 5055e7ba042SDenis Bolotin bool valid; 50643645ce0SSudarsana Reddy Kalluru }; 50743645ce0SSudarsana Reddy Kalluru 5085d24bcf1STomer Tayar #define DRV_MODULE_VERSION \ 5095d24bcf1STomer Tayar __stringify(QED_MAJOR_VERSION) "." \ 5105d24bcf1STomer Tayar __stringify(QED_MINOR_VERSION) "." \ 5115d24bcf1STomer Tayar __stringify(QED_REVISION_VERSION) "." \ 5125d24bcf1STomer Tayar __stringify(QED_ENGINEERING_VERSION) 5135d24bcf1STomer Tayar 514fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 515fe56b9e6SYuval Mintz void *token; 516fe56b9e6SYuval Mintz void (*func)(void *); 517fe56b9e6SYuval Mintz }; 518fe56b9e6SYuval Mintz 51959ccf86fSSudarsana Reddy Kalluru enum qed_slowpath_wq_flag { 52059ccf86fSSudarsana Reddy Kalluru QED_SLOWPATH_MFW_TLV_REQ, 52159ccf86fSSudarsana Reddy Kalluru }; 52259ccf86fSSudarsana Reddy Kalluru 523fe56b9e6SYuval Mintz struct qed_hwfn { 524fe56b9e6SYuval Mintz struct qed_dev *cdev; 525fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 526fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 527fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 528fe56b9e6SYuval Mintz u8 abs_pf_id; 5299c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \ 5309c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 531fe56b9e6SYuval Mintz u8 port_id; 532fe56b9e6SYuval Mintz bool b_active; 533fe56b9e6SYuval Mintz 534fe56b9e6SYuval Mintz u32 dp_module; 535fe56b9e6SYuval Mintz u8 dp_level; 536fe56b9e6SYuval Mintz char name[NAME_SIZE]; 537fe56b9e6SYuval Mintz 538fe56b9e6SYuval Mintz bool first_on_engine; 539fe56b9e6SYuval Mintz bool hw_init_done; 540fe56b9e6SYuval Mintz 5411408cc1fSYuval Mintz u8 num_funcs_on_engine; 542dbb799c3SYuval Mintz u8 enabled_func_idx; 5431408cc1fSYuval Mintz 544fe56b9e6SYuval Mintz /* BAR access */ 545fe56b9e6SYuval Mintz void __iomem *regview; 546fe56b9e6SYuval Mintz void __iomem *doorbells; 547fe56b9e6SYuval Mintz u64 db_phys_addr; 548fe56b9e6SYuval Mintz unsigned long db_size; 549fe56b9e6SYuval Mintz 550fe56b9e6SYuval Mintz /* PTT pool */ 551fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 552fe56b9e6SYuval Mintz 553fe56b9e6SYuval Mintz /* HW info */ 554fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 557fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 558fe56b9e6SYuval Mintz 559fe56b9e6SYuval Mintz /* SPQ */ 560fe56b9e6SYuval Mintz struct qed_spq *p_spq; 561fe56b9e6SYuval Mintz 562fe56b9e6SYuval Mintz /* EQ */ 563fe56b9e6SYuval Mintz struct qed_eq *p_eq; 564fe56b9e6SYuval Mintz 565fe56b9e6SYuval Mintz /* Consolidate Q*/ 566fe56b9e6SYuval Mintz struct qed_consq *p_consq; 567fe56b9e6SYuval Mintz 568fe56b9e6SYuval Mintz /* Slow-Path definitions */ 569fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 570fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 571fe56b9e6SYuval Mintz 572fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 573fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 574fe56b9e6SYuval Mintz 575d179bd16Ssudarsana.kalluru@cavium.com /* PTP will be used only by the leading function. 576d179bd16Ssudarsana.kalluru@cavium.com * Usage of all PTP-apis should be synchronized as result. 577d179bd16Ssudarsana.kalluru@cavium.com */ 578d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptp_ptt; 579d179bd16Ssudarsana.kalluru@cavium.com 580fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 581fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 582fe56b9e6SYuval Mintz 583fe56b9e6SYuval Mintz /* Protocol related */ 5840a7fb11cSYuval Mintz bool using_ll2; 5850a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 5861d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 58751ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 588fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 5891e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 590fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 591fe56b9e6SYuval Mintz 592dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 593dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 594dbb799c3SYuval Mintz 595fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 596fe56b9e6SYuval Mintz 597fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 598fe56b9e6SYuval Mintz bool b_int_enabled; 5998f16bc97SSudarsana Kalluru bool b_int_requested; 600fe56b9e6SYuval Mintz 601fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 602fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 603fc916ff2SSudarsana Reddy Kalluru 6041408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 60532a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 606fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 607fe56b9e6SYuval Mintz 60839651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 60939651abdSSudarsana Reddy Kalluru 610cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info ufp_info; 611cac6f691SSudarsana Reddy Kalluru 612fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 613fe56b9e6SYuval Mintz 614fe56b9e6SYuval Mintz /* QM init */ 615fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 6169df2ed04SManish Chopra struct qed_storm_stats storm_stats; 617fe56b9e6SYuval Mintz 618fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 619fe56b9e6SYuval Mintz void *unzip_buf; 620fe56b9e6SYuval Mintz 621c965db44STomer Tayar struct dbg_tools_data dbg_info; 622c965db44STomer Tayar 62351ff1725SRam Amrani /* PWM region specific data */ 62420b1bd96SRam Amrani u16 wid_count; 62551ff1725SRam Amrani u32 dpi_size; 62651ff1725SRam Amrani u32 dpi_count; 62751ff1725SRam Amrani 62851ff1725SRam Amrani /* This is used to calculate the doorbell address */ 62951ff1725SRam Amrani u32 dpi_start_offset; 63051ff1725SRam Amrani 63151ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 63251ff1725SRam Amrani u8 dcbx_no_edpm; 63351ff1725SRam Amrani u8 db_bar_no_edpm; 63451ff1725SRam Amrani 6350db711bbSMintz, Yuval /* L2-related */ 6360db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 6370db711bbSMintz, Yuval 63843645ce0SSudarsana Reddy Kalluru /* Nvm images number and attributes */ 63943645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info nvm_info; 64043645ce0SSudarsana Reddy Kalluru 641d51e4af5SChopra, Manish struct qed_ptt *p_arfs_ptt; 642d51e4af5SChopra, Manish 643fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 644fe56b9e6SYuval Mintz 64537bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 64637bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 64737bff2b9SYuval Mintz struct delayed_work iov_task; 64837bff2b9SYuval Mintz unsigned long iov_task_flags; 64937bff2b9SYuval Mintz #endif 65037bff2b9SYuval Mintz 651fe56b9e6SYuval Mintz struct z_stream_s *stream; 65259ccf86fSSudarsana Reddy Kalluru struct workqueue_struct *slowpath_wq; 65359ccf86fSSudarsana Reddy Kalluru struct delayed_work slowpath_task; 65459ccf86fSSudarsana Reddy Kalluru unsigned long slowpath_task_flags; 655fe56b9e6SYuval Mintz }; 656fe56b9e6SYuval Mintz 657fe56b9e6SYuval Mintz struct pci_params { 658fe56b9e6SYuval Mintz int pm_cap; 659fe56b9e6SYuval Mintz 660fe56b9e6SYuval Mintz unsigned long mem_start; 661fe56b9e6SYuval Mintz unsigned long mem_end; 662fe56b9e6SYuval Mintz unsigned int irq; 663fe56b9e6SYuval Mintz u8 pf_num; 664fe56b9e6SYuval Mintz }; 665fe56b9e6SYuval Mintz 666fe56b9e6SYuval Mintz struct qed_int_param { 667fe56b9e6SYuval Mintz u32 int_mode; 668fe56b9e6SYuval Mintz u8 num_vectors; 669fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 670fe56b9e6SYuval Mintz }; 671fe56b9e6SYuval Mintz 672fe56b9e6SYuval Mintz struct qed_int_params { 673fe56b9e6SYuval Mintz struct qed_int_param in; 674fe56b9e6SYuval Mintz struct qed_int_param out; 675fe56b9e6SYuval Mintz struct msix_entry *msix_table; 676fe56b9e6SYuval Mintz bool fp_initialized; 677fe56b9e6SYuval Mintz u8 fp_msix_base; 678fe56b9e6SYuval Mintz u8 fp_msix_cnt; 67951ff1725SRam Amrani u8 rdma_msix_base; 68051ff1725SRam Amrani u8 rdma_msix_cnt; 681fe56b9e6SYuval Mintz }; 682fe56b9e6SYuval Mintz 683c965db44STomer Tayar struct qed_dbg_feature { 684c965db44STomer Tayar struct dentry *dentry; 685c965db44STomer Tayar u8 *dump_buf; 686c965db44STomer Tayar u32 buf_size; 687c965db44STomer Tayar u32 dumped_dwords; 688c965db44STomer Tayar }; 689c965db44STomer Tayar 690c965db44STomer Tayar struct qed_dbg_params { 691c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 692c965db44STomer Tayar u8 engine_for_debug; 693c965db44STomer Tayar bool print_data; 694c965db44STomer Tayar }; 695c965db44STomer Tayar 696fe56b9e6SYuval Mintz struct qed_dev { 697fe56b9e6SYuval Mintz u32 dp_module; 698fe56b9e6SYuval Mintz u8 dp_level; 699fe56b9e6SYuval Mintz char name[NAME_SIZE]; 700fe56b9e6SYuval Mintz 7019c79ddaaSMintz, Yuval enum qed_dev_type type; 702fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 703fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 704fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 705fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 706c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 707c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 708fc48b7a6SYuval Mintz 709fc48b7a6SYuval Mintz u16 vendor_id; 710fc48b7a6SYuval Mintz u16 device_id; 7119c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00 7129c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600 7139c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000 714fe56b9e6SYuval Mintz 715fe56b9e6SYuval Mintz u16 chip_num; 716fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 717fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 718fe56b9e6SYuval Mintz 719fe56b9e6SYuval Mintz u16 chip_rev; 720fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 721fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 722fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 723fe56b9e6SYuval Mintz 724fe56b9e6SYuval Mintz u16 chip_metal; 725fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 726fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 727fe56b9e6SYuval Mintz 728fe56b9e6SYuval Mintz u16 chip_bond_id; 729fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 730fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 731fe56b9e6SYuval Mintz 732fe56b9e6SYuval Mintz u8 num_engines; 73378cea9ffSTomer Tayar u8 num_ports_in_engine; 734fe56b9e6SYuval Mintz u8 num_funcs_in_port; 735fe56b9e6SYuval Mintz 736fe56b9e6SYuval Mintz u8 path_id; 7370bc5fe85SSudarsana Reddy Kalluru 7380bc5fe85SSudarsana Reddy Kalluru unsigned long mf_bits; 739fe56b9e6SYuval Mintz 740fe56b9e6SYuval Mintz int pcie_width; 741fe56b9e6SYuval Mintz int pcie_speed; 742fe56b9e6SYuval Mintz 743fe56b9e6SYuval Mintz /* Add MF related configuration */ 744fe56b9e6SYuval Mintz u8 mcp_rev; 745fe56b9e6SYuval Mintz u8 boot_mode; 746fe56b9e6SYuval Mintz 74714d39648SMintz, Yuval /* WoL related configurations */ 74814d39648SMintz, Yuval u8 wol_config; 74914d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 750fe56b9e6SYuval Mintz 751fe56b9e6SYuval Mintz u32 int_mode; 752fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 75351d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 75451d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 755fe56b9e6SYuval Mintz 756fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 757fe56b9e6SYuval Mintz void __iomem *regview; 758fe56b9e6SYuval Mintz void __iomem *doorbells; 759fe56b9e6SYuval Mintz u64 db_phys_addr; 760fe56b9e6SYuval Mintz unsigned long db_size; 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz /* PCI */ 763fe56b9e6SYuval Mintz u8 cache_shift; 764fe56b9e6SYuval Mintz 765fe56b9e6SYuval Mintz /* Init */ 766fe56b9e6SYuval Mintz const struct iro *iro_arr; 767fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 768fe56b9e6SYuval Mintz 769fe56b9e6SYuval Mintz /* HW functions */ 770fe56b9e6SYuval Mintz u8 num_hwfns; 771fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 772fe56b9e6SYuval Mintz 77332a47e72SYuval Mintz /* SRIOV */ 77432a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 77532a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 77619968430SChopra, Manish struct qed_tunnel_info tunnel; 7771408cc1fSYuval Mintz bool b_is_vf; 778fe56b9e6SYuval Mintz u32 drv_type; 779fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 780fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 781fe56b9e6SYuval Mintz 782fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 783fe56b9e6SYuval Mintz 784fe56b9e6SYuval Mintz /* Linux specific here */ 785fe56b9e6SYuval Mintz struct qede_dev *edev; 786fe56b9e6SYuval Mintz struct pci_dev *pdev; 787fc831825SYuval Mintz u32 flags; 788fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 789fe56b9e6SYuval Mintz int msg_enable; 790fe56b9e6SYuval Mintz 791fe56b9e6SYuval Mintz struct pci_params pci_params; 792fe56b9e6SYuval Mintz 793fe56b9e6SYuval Mintz struct qed_int_params int_params; 794fe56b9e6SYuval Mintz 795fe56b9e6SYuval Mintz u8 protocol; 796fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 7971e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 798fe56b9e6SYuval Mintz 799cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 800cc875c2eSYuval Mintz union { 801cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 802cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 8031e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe; 804fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 805cc875c2eSYuval Mintz } protocol_ops; 806cc875c2eSYuval Mintz void *ops_cookie; 807cc875c2eSYuval Mintz 808c965db44STomer Tayar struct qed_dbg_params dbg_params; 809c965db44STomer Tayar 8100a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 8110a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 8120a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 8130a7fb11cSYuval Mintz #endif 814fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 815fe56b9e6SYuval Mintz const struct firmware *firmware; 81651ff1725SRam Amrani 81751ff1725SRam Amrani u32 rdma_max_sge; 81851ff1725SRam Amrani u32 rdma_max_inline; 81951ff1725SRam Amrani u32 rdma_max_srq_sge; 820eaf3c0c6SChopra, Manish u16 tunn_feature_mask; 821fe56b9e6SYuval Mintz }; 822fe56b9e6SYuval Mintz 8239c79ddaaSMintz, Yuval #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 8249c79ddaaSMintz, Yuval : MAX_NUM_VFS_K2) 8259c79ddaaSMintz, Yuval #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 8269c79ddaaSMintz, Yuval : MAX_NUM_L2_QUEUES_K2) 8279c79ddaaSMintz, Yuval #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 8289c79ddaaSMintz, Yuval : MAX_NUM_PORTS_K2) 8299c79ddaaSMintz, Yuval #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 8309c79ddaaSMintz, Yuval : MAX_SB_PER_PATH_K2) 8319c79ddaaSMintz, Yuval #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 8329c79ddaaSMintz, Yuval : MAX_NUM_PFS_K2) 833fe56b9e6SYuval Mintz 834fe56b9e6SYuval Mintz /** 835fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 836fe56b9e6SYuval Mintz * the concrete value. 837fe56b9e6SYuval Mintz * 838fe56b9e6SYuval Mintz * @param concrete_fid 839fe56b9e6SYuval Mintz * 840fe56b9e6SYuval Mintz * @return inline u8 841fe56b9e6SYuval Mintz */ 842fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 843fe56b9e6SYuval Mintz u32 concrete_fid) 844fe56b9e6SYuval Mintz { 8454870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 846fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 8474870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 8484870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 8494870e704SYuval Mintz u8 sw_fid; 850fe56b9e6SYuval Mintz 8514870e704SYuval Mintz if (vf_valid) 8524870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 8534870e704SYuval Mintz else 8544870e704SYuval Mintz sw_fid = pfid; 8554870e704SYuval Mintz 8564870e704SYuval Mintz return sw_fid; 857fe56b9e6SYuval Mintz } 858fe56b9e6SYuval Mintz 859526d1d05SKalderon, Michal #define PKT_LB_TC 9 860da090917STomer Tayar #define MAX_NUM_VOQS_E4 20 861fe56b9e6SYuval Mintz 862733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 8636f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 8646f437d43SMintz, Yuval struct qed_ptt *p_ptt, 8656f437d43SMintz, Yuval u32 min_pf_rate); 866bcd197c8SManish Chopra 867733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 8689c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev); 869db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev); 870456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 871456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); 872fe56b9e6SYuval Mintz 873b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 874b5a9ee7cSAriel Elior 875b5a9ee7cSAriel Elior /* Flags for indication of required queues */ 876b5a9ee7cSAriel Elior #define PQ_FLAGS_RLS (BIT(0)) 877b5a9ee7cSAriel Elior #define PQ_FLAGS_MCOS (BIT(1)) 878b5a9ee7cSAriel Elior #define PQ_FLAGS_LB (BIT(2)) 879b5a9ee7cSAriel Elior #define PQ_FLAGS_OOO (BIT(3)) 880b5a9ee7cSAriel Elior #define PQ_FLAGS_ACK (BIT(4)) 881b5a9ee7cSAriel Elior #define PQ_FLAGS_OFLD (BIT(5)) 882b5a9ee7cSAriel Elior #define PQ_FLAGS_VFS (BIT(6)) 883b5a9ee7cSAriel Elior #define PQ_FLAGS_LLT (BIT(7)) 884b5a9ee7cSAriel Elior 885b5a9ee7cSAriel Elior /* physical queue index for cm context intialization */ 886b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 887b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 888b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 889b5a9ee7cSAriel Elior 890b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 891b5a9ee7cSAriel Elior 892fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 893fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 894fe56b9e6SYuval Mintz 895fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 896fe56b9e6SYuval Mintz (cdev->regview) + \ 897fe56b9e6SYuval Mintz (offset)) 898fe56b9e6SYuval Mintz 899fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 900fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 901fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 902fe56b9e6SYuval Mintz 903fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 904fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 905fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 906fe56b9e6SYuval Mintz 907fe56b9e6SYuval Mintz /* Prototypes */ 908fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 909fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 910cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 911fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 912fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 913fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 9146c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 9156c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 9166c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 9178f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 9181226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 91959ccf86fSSudarsana Reddy Kalluru int qed_mfw_tlv_req(struct qed_hwfn *hwfn); 9208f16bc97SSudarsana Kalluru 9212528c389SSudarsana Reddy Kalluru int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, 9222528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type type, 9232528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data *tlv_data); 924fe56b9e6SYuval Mintz #endif /* _QED_H */ 925