1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #ifndef _QED_H 10fe56b9e6SYuval Mintz #define _QED_H 11fe56b9e6SYuval Mintz 12fe56b9e6SYuval Mintz #include <linux/types.h> 13fe56b9e6SYuval Mintz #include <linux/io.h> 14fe56b9e6SYuval Mintz #include <linux/delay.h> 15fe56b9e6SYuval Mintz #include <linux/firmware.h> 16fe56b9e6SYuval Mintz #include <linux/interrupt.h> 17fe56b9e6SYuval Mintz #include <linux/list.h> 18fe56b9e6SYuval Mintz #include <linux/mutex.h> 19fe56b9e6SYuval Mintz #include <linux/pci.h> 20fe56b9e6SYuval Mintz #include <linux/slab.h> 21fe56b9e6SYuval Mintz #include <linux/string.h> 22fe56b9e6SYuval Mintz #include <linux/workqueue.h> 23fe56b9e6SYuval Mintz #include <linux/zlib.h> 24fe56b9e6SYuval Mintz #include <linux/hashtable.h> 25fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 26fe56b9e6SYuval Mintz #include "qed_hsi.h" 27fe56b9e6SYuval Mintz 2825c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 297c2d7d74SYuval Mintz #define DRV_MODULE_VERSION "8.7.1.20" 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 32fe56b9e6SYuval Mintz #define NAME_SIZE 16 33fe56b9e6SYuval Mintz #define VER_SIZE 16 34fe56b9e6SYuval Mintz 35bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 36bcd197c8SManish Chopra 37fe56b9e6SYuval Mintz /* cau states */ 38fe56b9e6SYuval Mintz enum qed_coalescing_mode { 39fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 40fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 41fe56b9e6SYuval Mintz }; 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 44fe56b9e6SYuval Mintz struct qed_dev_info; 45fe56b9e6SYuval Mintz 46fe56b9e6SYuval Mintz /* helpers */ 47fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 48fe56b9e6SYuval Mintz { 49fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 50fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz return db_addr; 53fe56b9e6SYuval Mintz } 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 56fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 57fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 62fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 63fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz /* forward */ 66fe56b9e6SYuval Mintz struct qed_ptt_pool; 67fe56b9e6SYuval Mintz struct qed_spq; 68fe56b9e6SYuval Mintz struct qed_sb_info; 69fe56b9e6SYuval Mintz struct qed_sb_attn_info; 70fe56b9e6SYuval Mintz struct qed_cxt_mngr; 71fe56b9e6SYuval Mintz struct qed_sb_sp_info; 72fe56b9e6SYuval Mintz struct qed_mcp_info; 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz struct qed_rt_data { 75fc48b7a6SYuval Mintz u32 *init_val; 76fc48b7a6SYuval Mintz bool *b_valid; 77fe56b9e6SYuval Mintz }; 78fe56b9e6SYuval Mintz 79464f6645SManish Chopra enum qed_tunn_mode { 80464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 81464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 82464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 83464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 84464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 85464f6645SManish Chopra }; 86464f6645SManish Chopra 87464f6645SManish Chopra enum qed_tunn_clss { 88464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 89464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 90464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 91464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 92464f6645SManish Chopra MAX_QED_TUNN_CLSS, 93464f6645SManish Chopra }; 94464f6645SManish Chopra 95464f6645SManish Chopra struct qed_tunn_start_params { 96464f6645SManish Chopra unsigned long tunn_mode; 97464f6645SManish Chopra u16 vxlan_udp_port; 98464f6645SManish Chopra u16 geneve_udp_port; 99464f6645SManish Chopra u8 update_vxlan_udp_port; 100464f6645SManish Chopra u8 update_geneve_udp_port; 101464f6645SManish Chopra u8 tunn_clss_vxlan; 102464f6645SManish Chopra u8 tunn_clss_l2geneve; 103464f6645SManish Chopra u8 tunn_clss_ipgeneve; 104464f6645SManish Chopra u8 tunn_clss_l2gre; 105464f6645SManish Chopra u8 tunn_clss_ipgre; 106464f6645SManish Chopra }; 107464f6645SManish Chopra 108464f6645SManish Chopra struct qed_tunn_update_params { 109464f6645SManish Chopra unsigned long tunn_mode_update_mask; 110464f6645SManish Chopra unsigned long tunn_mode; 111464f6645SManish Chopra u16 vxlan_udp_port; 112464f6645SManish Chopra u16 geneve_udp_port; 113464f6645SManish Chopra u8 update_rx_pf_clss; 114464f6645SManish Chopra u8 update_tx_pf_clss; 115464f6645SManish Chopra u8 update_vxlan_udp_port; 116464f6645SManish Chopra u8 update_geneve_udp_port; 117464f6645SManish Chopra u8 tunn_clss_vxlan; 118464f6645SManish Chopra u8 tunn_clss_l2geneve; 119464f6645SManish Chopra u8 tunn_clss_ipgeneve; 120464f6645SManish Chopra u8 tunn_clss_l2gre; 121464f6645SManish Chopra u8 tunn_clss_ipgre; 122464f6645SManish Chopra }; 123464f6645SManish Chopra 124fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 125fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 126fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 127fe56b9e6SYuval Mintz */ 128fe56b9e6SYuval Mintz enum qed_pci_personality { 129fe56b9e6SYuval Mintz QED_PCI_ETH, 130c5ac9319SYuval Mintz QED_PCI_ISCSI, 131c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 132fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 133fe56b9e6SYuval Mintz }; 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 136fe56b9e6SYuval Mintz struct qed_qm_iids { 137fe56b9e6SYuval Mintz u32 cids; 138fe56b9e6SYuval Mintz u32 vf_cids; 139fe56b9e6SYuval Mintz u32 tids; 140fe56b9e6SYuval Mintz }; 141fe56b9e6SYuval Mintz 142fe56b9e6SYuval Mintz enum QED_RESOURCES { 143fe56b9e6SYuval Mintz QED_SB, 14425c089d7SYuval Mintz QED_L2_QUEUE, 145fe56b9e6SYuval Mintz QED_VPORT, 14625c089d7SYuval Mintz QED_RSS_ENG, 147fe56b9e6SYuval Mintz QED_PQ, 148fe56b9e6SYuval Mintz QED_RL, 14925c089d7SYuval Mintz QED_MAC, 15025c089d7SYuval Mintz QED_VLAN, 151fe56b9e6SYuval Mintz QED_ILT, 152fe56b9e6SYuval Mintz QED_MAX_RESC, 153fe56b9e6SYuval Mintz }; 154fe56b9e6SYuval Mintz 15525c089d7SYuval Mintz enum QED_FEATURE { 15625c089d7SYuval Mintz QED_PF_L2_QUE, 15732a47e72SYuval Mintz QED_VF, 15825c089d7SYuval Mintz QED_MAX_FEATURES, 15925c089d7SYuval Mintz }; 16025c089d7SYuval Mintz 161cc875c2eSYuval Mintz enum QED_PORT_MODE { 162cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 163cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 164cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 165cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 166cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 167cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 168cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 169cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 170cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X25G 171cc875c2eSYuval Mintz }; 172cc875c2eSYuval Mintz 173fc48b7a6SYuval Mintz enum qed_dev_cap { 174fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 175c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 176c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 177fc48b7a6SYuval Mintz }; 178fc48b7a6SYuval Mintz 179fe56b9e6SYuval Mintz struct qed_hw_info { 180fe56b9e6SYuval Mintz /* PCI personality */ 181fe56b9e6SYuval Mintz enum qed_pci_personality personality; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 184fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 185fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 18625c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 187fe56b9e6SYuval Mintz 188fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 189fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 190dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 191dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 192fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 193fe56b9e6SYuval Mintz 194fe56b9e6SYuval Mintz u8 num_tc; 195fe56b9e6SYuval Mintz u8 offload_tc; 196fe56b9e6SYuval Mintz u8 non_offload_tc; 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz u32 concrete_fid; 199fe56b9e6SYuval Mintz u16 opaque_fid; 200fe56b9e6SYuval Mintz u16 ovlan; 201fe56b9e6SYuval Mintz u32 part_num[4]; 202fe56b9e6SYuval Mintz 203fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 204fe56b9e6SYuval Mintz 205fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 206fe56b9e6SYuval Mintz 207fe56b9e6SYuval Mintz u32 port_mode; 208fe56b9e6SYuval Mintz u32 hw_mode; 209fc48b7a6SYuval Mintz unsigned long device_capabilities; 210fe56b9e6SYuval Mintz }; 211fe56b9e6SYuval Mintz 212fe56b9e6SYuval Mintz struct qed_hw_cid_data { 213fe56b9e6SYuval Mintz u32 cid; 214fe56b9e6SYuval Mintz bool b_cid_allocated; 215fe56b9e6SYuval Mintz 216fe56b9e6SYuval Mintz /* Additional identifiers */ 217fe56b9e6SYuval Mintz u16 opaque_fid; 218fe56b9e6SYuval Mintz u8 vport_id; 219fe56b9e6SYuval Mintz }; 220fe56b9e6SYuval Mintz 221fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 222fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz struct qed_dmae_info { 225fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 226fe56b9e6SYuval Mintz struct mutex mutex; 227fe56b9e6SYuval Mintz 228fe56b9e6SYuval Mintz u8 channel; 229fe56b9e6SYuval Mintz 230fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 231fe56b9e6SYuval Mintz 232fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 233fe56b9e6SYuval Mintz * value when an operation is finished on this context. 234fe56b9e6SYuval Mintz */ 235fe56b9e6SYuval Mintz u32 *p_completion_word; 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 240fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 241fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 242fe56b9e6SYuval Mintz */ 243fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 244fe56b9e6SYuval Mintz 245fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 246fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 247fe56b9e6SYuval Mintz }; 248fe56b9e6SYuval Mintz 249bcd197c8SManish Chopra struct qed_wfq_data { 250bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 251bcd197c8SManish Chopra u32 min_speed; 252bcd197c8SManish Chopra bool configured; 253bcd197c8SManish Chopra }; 254bcd197c8SManish Chopra 255fe56b9e6SYuval Mintz struct qed_qm_info { 256fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 257fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 258fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 259fe56b9e6SYuval Mintz u16 start_pq; 260fe56b9e6SYuval Mintz u8 start_vport; 261fe56b9e6SYuval Mintz u8 pure_lb_pq; 262fe56b9e6SYuval Mintz u8 offload_pq; 263fe56b9e6SYuval Mintz u8 pure_ack_pq; 264dbb799c3SYuval Mintz u8 ooo_pq; 265fe56b9e6SYuval Mintz u8 vf_queues_offset; 266fe56b9e6SYuval Mintz u16 num_pqs; 267fe56b9e6SYuval Mintz u16 num_vf_pqs; 268fe56b9e6SYuval Mintz u8 num_vports; 269fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 270fe56b9e6SYuval Mintz bool pf_rl_en; 271fe56b9e6SYuval Mintz bool pf_wfq_en; 272fe56b9e6SYuval Mintz bool vport_rl_en; 273fe56b9e6SYuval Mintz bool vport_wfq_en; 274fe56b9e6SYuval Mintz u8 pf_wfq; 275fe56b9e6SYuval Mintz u32 pf_rl; 276bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 277dbb799c3SYuval Mintz u8 num_pf_rls; 278fe56b9e6SYuval Mintz }; 279fe56b9e6SYuval Mintz 2809df2ed04SManish Chopra struct storm_stats { 2819df2ed04SManish Chopra u32 address; 2829df2ed04SManish Chopra u32 len; 2839df2ed04SManish Chopra }; 2849df2ed04SManish Chopra 2859df2ed04SManish Chopra struct qed_storm_stats { 2869df2ed04SManish Chopra struct storm_stats mstats; 2879df2ed04SManish Chopra struct storm_stats pstats; 2889df2ed04SManish Chopra struct storm_stats tstats; 2899df2ed04SManish Chopra struct storm_stats ustats; 2909df2ed04SManish Chopra }; 2919df2ed04SManish Chopra 292fe56b9e6SYuval Mintz struct qed_fw_data { 2939df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 294fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 295fe56b9e6SYuval Mintz union init_op *init_ops; 296fe56b9e6SYuval Mintz const u32 *arr_data; 297fe56b9e6SYuval Mintz u32 init_ops_size; 298fe56b9e6SYuval Mintz }; 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 301fe56b9e6SYuval Mintz void *token; 302fe56b9e6SYuval Mintz void (*func)(void *); 303fe56b9e6SYuval Mintz }; 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz struct qed_hwfn { 306fe56b9e6SYuval Mintz struct qed_dev *cdev; 307fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 308fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 309fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 310fe56b9e6SYuval Mintz u8 abs_pf_id; 311fe56b9e6SYuval Mintz #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 312fe56b9e6SYuval Mintz u8 port_id; 313fe56b9e6SYuval Mintz bool b_active; 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz u32 dp_module; 316fe56b9e6SYuval Mintz u8 dp_level; 317fe56b9e6SYuval Mintz char name[NAME_SIZE]; 318fe56b9e6SYuval Mintz 319fe56b9e6SYuval Mintz bool first_on_engine; 320fe56b9e6SYuval Mintz bool hw_init_done; 321fe56b9e6SYuval Mintz 3221408cc1fSYuval Mintz u8 num_funcs_on_engine; 323dbb799c3SYuval Mintz u8 enabled_func_idx; 3241408cc1fSYuval Mintz 325fe56b9e6SYuval Mintz /* BAR access */ 326fe56b9e6SYuval Mintz void __iomem *regview; 327fe56b9e6SYuval Mintz void __iomem *doorbells; 328fe56b9e6SYuval Mintz u64 db_phys_addr; 329fe56b9e6SYuval Mintz unsigned long db_size; 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz /* PTT pool */ 332fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 333fe56b9e6SYuval Mintz 334fe56b9e6SYuval Mintz /* HW info */ 335fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 336fe56b9e6SYuval Mintz 337fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 338fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz /* SPQ */ 341fe56b9e6SYuval Mintz struct qed_spq *p_spq; 342fe56b9e6SYuval Mintz 343fe56b9e6SYuval Mintz /* EQ */ 344fe56b9e6SYuval Mintz struct qed_eq *p_eq; 345fe56b9e6SYuval Mintz 346fe56b9e6SYuval Mintz /* Consolidate Q*/ 347fe56b9e6SYuval Mintz struct qed_consq *p_consq; 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz /* Slow-Path definitions */ 350fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 351fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 352fe56b9e6SYuval Mintz 353fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 354fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 355fe56b9e6SYuval Mintz 356fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 357fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 358fe56b9e6SYuval Mintz 359fe56b9e6SYuval Mintz /* Protocol related */ 360fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 361fe56b9e6SYuval Mintz 362dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 363dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 364dbb799c3SYuval Mintz 365fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 366fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 367fe56b9e6SYuval Mintz u16 num_sbs; 368fe56b9e6SYuval Mintz 369fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 370fe56b9e6SYuval Mintz 371fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 372fe56b9e6SYuval Mintz bool b_int_enabled; 3738f16bc97SSudarsana Kalluru bool b_int_requested; 374fe56b9e6SYuval Mintz 375fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 376fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 377fc916ff2SSudarsana Reddy Kalluru 3781408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 37932a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 380fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 381fe56b9e6SYuval Mintz 38239651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 38339651abdSSudarsana Reddy Kalluru 38425c089d7SYuval Mintz struct qed_hw_cid_data *p_tx_cids; 38525c089d7SYuval Mintz struct qed_hw_cid_data *p_rx_cids; 38625c089d7SYuval Mintz 387fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz /* QM init */ 390fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 3919df2ed04SManish Chopra struct qed_storm_stats storm_stats; 392fe56b9e6SYuval Mintz 393fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 394fe56b9e6SYuval Mintz void *unzip_buf; 395fe56b9e6SYuval Mintz 396fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 397fe56b9e6SYuval Mintz 39837bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 39937bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 40037bff2b9SYuval Mintz struct delayed_work iov_task; 40137bff2b9SYuval Mintz unsigned long iov_task_flags; 40237bff2b9SYuval Mintz #endif 40337bff2b9SYuval Mintz 404fe56b9e6SYuval Mintz struct z_stream_s *stream; 405fe56b9e6SYuval Mintz }; 406fe56b9e6SYuval Mintz 407fe56b9e6SYuval Mintz struct pci_params { 408fe56b9e6SYuval Mintz int pm_cap; 409fe56b9e6SYuval Mintz 410fe56b9e6SYuval Mintz unsigned long mem_start; 411fe56b9e6SYuval Mintz unsigned long mem_end; 412fe56b9e6SYuval Mintz unsigned int irq; 413fe56b9e6SYuval Mintz u8 pf_num; 414fe56b9e6SYuval Mintz }; 415fe56b9e6SYuval Mintz 416fe56b9e6SYuval Mintz struct qed_int_param { 417fe56b9e6SYuval Mintz u32 int_mode; 418fe56b9e6SYuval Mintz u8 num_vectors; 419fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 420fe56b9e6SYuval Mintz }; 421fe56b9e6SYuval Mintz 422fe56b9e6SYuval Mintz struct qed_int_params { 423fe56b9e6SYuval Mintz struct qed_int_param in; 424fe56b9e6SYuval Mintz struct qed_int_param out; 425fe56b9e6SYuval Mintz struct msix_entry *msix_table; 426fe56b9e6SYuval Mintz bool fp_initialized; 427fe56b9e6SYuval Mintz u8 fp_msix_base; 428fe56b9e6SYuval Mintz u8 fp_msix_cnt; 429fe56b9e6SYuval Mintz }; 430fe56b9e6SYuval Mintz 431fe56b9e6SYuval Mintz struct qed_dev { 432fe56b9e6SYuval Mintz u32 dp_module; 433fe56b9e6SYuval Mintz u8 dp_level; 434fe56b9e6SYuval Mintz char name[NAME_SIZE]; 435fe56b9e6SYuval Mintz 436fe56b9e6SYuval Mintz u8 type; 437fc48b7a6SYuval Mintz #define QED_DEV_TYPE_BB (0 << 0) 438fc48b7a6SYuval Mintz #define QED_DEV_TYPE_AH BIT(0) 439fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 440fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 441fc48b7a6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 442fc48b7a6SYuval Mintz CHIP_REV_IS_A0(dev)) 443fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 444fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 445fc48b7a6SYuval Mintz 446fc48b7a6SYuval Mintz #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 447fc48b7a6SYuval Mintz QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 448fc48b7a6SYuval Mintz 449fc48b7a6SYuval Mintz u16 vendor_id; 450fc48b7a6SYuval Mintz u16 device_id; 451fe56b9e6SYuval Mintz 452fe56b9e6SYuval Mintz u16 chip_num; 453fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 454fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 455fe56b9e6SYuval Mintz 456fe56b9e6SYuval Mintz u16 chip_rev; 457fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 458fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 459fc48b7a6SYuval Mintz #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 460fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz u16 chip_metal; 463fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 464fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 465fe56b9e6SYuval Mintz 466fe56b9e6SYuval Mintz u16 chip_bond_id; 467fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 468fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 469fe56b9e6SYuval Mintz 470fe56b9e6SYuval Mintz u8 num_engines; 471fe56b9e6SYuval Mintz u8 num_ports_in_engines; 472fe56b9e6SYuval Mintz u8 num_funcs_in_port; 473fe56b9e6SYuval Mintz 474fe56b9e6SYuval Mintz u8 path_id; 475fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 476fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 477fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 478fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 479fe56b9e6SYuval Mintz 480fe56b9e6SYuval Mintz int pcie_width; 481fe56b9e6SYuval Mintz int pcie_speed; 482fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 483fe56b9e6SYuval Mintz 484fe56b9e6SYuval Mintz /* Add MF related configuration */ 485fe56b9e6SYuval Mintz u8 mcp_rev; 486fe56b9e6SYuval Mintz u8 boot_mode; 487fe56b9e6SYuval Mintz 488fe56b9e6SYuval Mintz u8 wol; 489fe56b9e6SYuval Mintz 490fe56b9e6SYuval Mintz u32 int_mode; 491fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 49251d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 49351d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 494fe56b9e6SYuval Mintz 495fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 496fe56b9e6SYuval Mintz void __iomem *regview; 497fe56b9e6SYuval Mintz void __iomem *doorbells; 498fe56b9e6SYuval Mintz u64 db_phys_addr; 499fe56b9e6SYuval Mintz unsigned long db_size; 500fe56b9e6SYuval Mintz 501fe56b9e6SYuval Mintz /* PCI */ 502fe56b9e6SYuval Mintz u8 cache_shift; 503fe56b9e6SYuval Mintz 504fe56b9e6SYuval Mintz /* Init */ 505fe56b9e6SYuval Mintz const struct iro *iro_arr; 506fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 507fe56b9e6SYuval Mintz 508fe56b9e6SYuval Mintz /* HW functions */ 509fe56b9e6SYuval Mintz u8 num_hwfns; 510fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 511fe56b9e6SYuval Mintz 51232a47e72SYuval Mintz /* SRIOV */ 51332a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 51432a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 51532a47e72SYuval Mintz 516464f6645SManish Chopra unsigned long tunn_mode; 5171408cc1fSYuval Mintz 5181408cc1fSYuval Mintz bool b_is_vf; 519fe56b9e6SYuval Mintz u32 drv_type; 520fe56b9e6SYuval Mintz 521fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 522fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 523fe56b9e6SYuval Mintz 524fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 525fe56b9e6SYuval Mintz 526fe56b9e6SYuval Mintz /* Linux specific here */ 527fe56b9e6SYuval Mintz struct qede_dev *edev; 528fe56b9e6SYuval Mintz struct pci_dev *pdev; 529fe56b9e6SYuval Mintz int msg_enable; 530fe56b9e6SYuval Mintz 531fe56b9e6SYuval Mintz struct pci_params pci_params; 532fe56b9e6SYuval Mintz 533fe56b9e6SYuval Mintz struct qed_int_params int_params; 534fe56b9e6SYuval Mintz 535fe56b9e6SYuval Mintz u8 protocol; 536fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 537fe56b9e6SYuval Mintz 538cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 539cc875c2eSYuval Mintz union { 540cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 541cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 542cc875c2eSYuval Mintz } protocol_ops; 543cc875c2eSYuval Mintz void *ops_cookie; 544cc875c2eSYuval Mintz 545fe56b9e6SYuval Mintz const struct firmware *firmware; 546fe56b9e6SYuval Mintz }; 547fe56b9e6SYuval Mintz 54832a47e72SYuval Mintz #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 549dacd88d6SYuval Mintz #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB 550fe56b9e6SYuval Mintz #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 551fe56b9e6SYuval Mintz #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 552fe56b9e6SYuval Mintz 553fe56b9e6SYuval Mintz /** 554fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 555fe56b9e6SYuval Mintz * the concrete value. 556fe56b9e6SYuval Mintz * 557fe56b9e6SYuval Mintz * @param concrete_fid 558fe56b9e6SYuval Mintz * 559fe56b9e6SYuval Mintz * @return inline u8 560fe56b9e6SYuval Mintz */ 561fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 562fe56b9e6SYuval Mintz u32 concrete_fid) 563fe56b9e6SYuval Mintz { 564fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 565fe56b9e6SYuval Mintz 566fe56b9e6SYuval Mintz return pfid; 567fe56b9e6SYuval Mintz } 568fe56b9e6SYuval Mintz 569fe56b9e6SYuval Mintz #define PURE_LB_TC 8 570dbb799c3SYuval Mintz #define OOO_LB_TC 9 571fe56b9e6SYuval Mintz 572733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 573bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); 574bcd197c8SManish Chopra 575733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 576fe56b9e6SYuval Mintz #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 577fe56b9e6SYuval Mintz 578fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 579fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 582fe56b9e6SYuval Mintz (cdev->regview) + \ 583fe56b9e6SYuval Mintz (offset)) 584fe56b9e6SYuval Mintz 585fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 586fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 587fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 588fe56b9e6SYuval Mintz 589fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 590fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 591fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 592fe56b9e6SYuval Mintz 593fe56b9e6SYuval Mintz /* Prototypes */ 594fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 595fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 596cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 597fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 598fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 599fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 600fe56b9e6SYuval Mintz 6018f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 6028f16bc97SSudarsana Kalluru 603fe56b9e6SYuval Mintz #endif /* _QED_H */ 604