1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #ifndef _QED_H 10fe56b9e6SYuval Mintz #define _QED_H 11fe56b9e6SYuval Mintz 12fe56b9e6SYuval Mintz #include <linux/types.h> 13fe56b9e6SYuval Mintz #include <linux/io.h> 14fe56b9e6SYuval Mintz #include <linux/delay.h> 15fe56b9e6SYuval Mintz #include <linux/firmware.h> 16fe56b9e6SYuval Mintz #include <linux/interrupt.h> 17fe56b9e6SYuval Mintz #include <linux/list.h> 18fe56b9e6SYuval Mintz #include <linux/mutex.h> 19fe56b9e6SYuval Mintz #include <linux/pci.h> 20fe56b9e6SYuval Mintz #include <linux/slab.h> 21fe56b9e6SYuval Mintz #include <linux/string.h> 22fe56b9e6SYuval Mintz #include <linux/workqueue.h> 23fe56b9e6SYuval Mintz #include <linux/zlib.h> 24fe56b9e6SYuval Mintz #include <linux/hashtable.h> 25fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 26fe56b9e6SYuval Mintz #include "qed_hsi.h" 27fe56b9e6SYuval Mintz 2825c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 297c2d7d74SYuval Mintz #define DRV_MODULE_VERSION "8.7.1.20" 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 32fe56b9e6SYuval Mintz #define NAME_SIZE 16 33fe56b9e6SYuval Mintz #define VER_SIZE 16 34fe56b9e6SYuval Mintz 35bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 36bcd197c8SManish Chopra 37fe56b9e6SYuval Mintz /* cau states */ 38fe56b9e6SYuval Mintz enum qed_coalescing_mode { 39fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 40fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 41fe56b9e6SYuval Mintz }; 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 44fe56b9e6SYuval Mintz struct qed_dev_info; 45fe56b9e6SYuval Mintz 46fe56b9e6SYuval Mintz /* helpers */ 47fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 48fe56b9e6SYuval Mintz { 49fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 50fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz return db_addr; 53fe56b9e6SYuval Mintz } 54fe56b9e6SYuval Mintz 55fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 56fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 57fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 62fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 63fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz /* forward */ 66fe56b9e6SYuval Mintz struct qed_ptt_pool; 67fe56b9e6SYuval Mintz struct qed_spq; 68fe56b9e6SYuval Mintz struct qed_sb_info; 69fe56b9e6SYuval Mintz struct qed_sb_attn_info; 70fe56b9e6SYuval Mintz struct qed_cxt_mngr; 71fe56b9e6SYuval Mintz struct qed_sb_sp_info; 72fe56b9e6SYuval Mintz struct qed_mcp_info; 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz struct qed_rt_data { 75fc48b7a6SYuval Mintz u32 *init_val; 76fc48b7a6SYuval Mintz bool *b_valid; 77fe56b9e6SYuval Mintz }; 78fe56b9e6SYuval Mintz 79464f6645SManish Chopra enum qed_tunn_mode { 80464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 81464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 82464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 83464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 84464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 85464f6645SManish Chopra }; 86464f6645SManish Chopra 87464f6645SManish Chopra enum qed_tunn_clss { 88464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 89464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 90464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 91464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 92464f6645SManish Chopra MAX_QED_TUNN_CLSS, 93464f6645SManish Chopra }; 94464f6645SManish Chopra 95464f6645SManish Chopra struct qed_tunn_start_params { 96464f6645SManish Chopra unsigned long tunn_mode; 97464f6645SManish Chopra u16 vxlan_udp_port; 98464f6645SManish Chopra u16 geneve_udp_port; 99464f6645SManish Chopra u8 update_vxlan_udp_port; 100464f6645SManish Chopra u8 update_geneve_udp_port; 101464f6645SManish Chopra u8 tunn_clss_vxlan; 102464f6645SManish Chopra u8 tunn_clss_l2geneve; 103464f6645SManish Chopra u8 tunn_clss_ipgeneve; 104464f6645SManish Chopra u8 tunn_clss_l2gre; 105464f6645SManish Chopra u8 tunn_clss_ipgre; 106464f6645SManish Chopra }; 107464f6645SManish Chopra 108464f6645SManish Chopra struct qed_tunn_update_params { 109464f6645SManish Chopra unsigned long tunn_mode_update_mask; 110464f6645SManish Chopra unsigned long tunn_mode; 111464f6645SManish Chopra u16 vxlan_udp_port; 112464f6645SManish Chopra u16 geneve_udp_port; 113464f6645SManish Chopra u8 update_rx_pf_clss; 114464f6645SManish Chopra u8 update_tx_pf_clss; 115464f6645SManish Chopra u8 update_vxlan_udp_port; 116464f6645SManish Chopra u8 update_geneve_udp_port; 117464f6645SManish Chopra u8 tunn_clss_vxlan; 118464f6645SManish Chopra u8 tunn_clss_l2geneve; 119464f6645SManish Chopra u8 tunn_clss_ipgeneve; 120464f6645SManish Chopra u8 tunn_clss_l2gre; 121464f6645SManish Chopra u8 tunn_clss_ipgre; 122464f6645SManish Chopra }; 123464f6645SManish Chopra 124fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 125fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 126fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 127fe56b9e6SYuval Mintz */ 128fe56b9e6SYuval Mintz enum qed_pci_personality { 129fe56b9e6SYuval Mintz QED_PCI_ETH, 130fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 131fe56b9e6SYuval Mintz }; 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 134fe56b9e6SYuval Mintz struct qed_qm_iids { 135fe56b9e6SYuval Mintz u32 cids; 136fe56b9e6SYuval Mintz u32 vf_cids; 137fe56b9e6SYuval Mintz u32 tids; 138fe56b9e6SYuval Mintz }; 139fe56b9e6SYuval Mintz 140fe56b9e6SYuval Mintz enum QED_RESOURCES { 141fe56b9e6SYuval Mintz QED_SB, 14225c089d7SYuval Mintz QED_L2_QUEUE, 143fe56b9e6SYuval Mintz QED_VPORT, 14425c089d7SYuval Mintz QED_RSS_ENG, 145fe56b9e6SYuval Mintz QED_PQ, 146fe56b9e6SYuval Mintz QED_RL, 14725c089d7SYuval Mintz QED_MAC, 14825c089d7SYuval Mintz QED_VLAN, 149fe56b9e6SYuval Mintz QED_ILT, 150fe56b9e6SYuval Mintz QED_MAX_RESC, 151fe56b9e6SYuval Mintz }; 152fe56b9e6SYuval Mintz 15325c089d7SYuval Mintz enum QED_FEATURE { 15425c089d7SYuval Mintz QED_PF_L2_QUE, 15532a47e72SYuval Mintz QED_VF, 15625c089d7SYuval Mintz QED_MAX_FEATURES, 15725c089d7SYuval Mintz }; 15825c089d7SYuval Mintz 159cc875c2eSYuval Mintz enum QED_PORT_MODE { 160cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 161cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 162cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 163cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 164cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 165cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 166cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 167cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 168cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X25G 169cc875c2eSYuval Mintz }; 170cc875c2eSYuval Mintz 171fc48b7a6SYuval Mintz enum qed_dev_cap { 172fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 173fc48b7a6SYuval Mintz }; 174fc48b7a6SYuval Mintz 175fe56b9e6SYuval Mintz struct qed_hw_info { 176fe56b9e6SYuval Mintz /* PCI personality */ 177fe56b9e6SYuval Mintz enum qed_pci_personality personality; 178fe56b9e6SYuval Mintz 179fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 180fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 181fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 18225c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 183fe56b9e6SYuval Mintz 184fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 185fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 186fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 187fe56b9e6SYuval Mintz 188fe56b9e6SYuval Mintz u8 num_tc; 189fe56b9e6SYuval Mintz u8 offload_tc; 190fe56b9e6SYuval Mintz u8 non_offload_tc; 191fe56b9e6SYuval Mintz 192fe56b9e6SYuval Mintz u32 concrete_fid; 193fe56b9e6SYuval Mintz u16 opaque_fid; 194fe56b9e6SYuval Mintz u16 ovlan; 195fe56b9e6SYuval Mintz u32 part_num[4]; 196fe56b9e6SYuval Mintz 197fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 198fe56b9e6SYuval Mintz 199fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 200fe56b9e6SYuval Mintz 201fe56b9e6SYuval Mintz u32 port_mode; 202fe56b9e6SYuval Mintz u32 hw_mode; 203fc48b7a6SYuval Mintz unsigned long device_capabilities; 204fe56b9e6SYuval Mintz }; 205fe56b9e6SYuval Mintz 206fe56b9e6SYuval Mintz struct qed_hw_cid_data { 207fe56b9e6SYuval Mintz u32 cid; 208fe56b9e6SYuval Mintz bool b_cid_allocated; 209fe56b9e6SYuval Mintz 210fe56b9e6SYuval Mintz /* Additional identifiers */ 211fe56b9e6SYuval Mintz u16 opaque_fid; 212fe56b9e6SYuval Mintz u8 vport_id; 213fe56b9e6SYuval Mintz }; 214fe56b9e6SYuval Mintz 215fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 216fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 217fe56b9e6SYuval Mintz 218fe56b9e6SYuval Mintz struct qed_dmae_info { 219fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 220fe56b9e6SYuval Mintz struct mutex mutex; 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz u8 channel; 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 225fe56b9e6SYuval Mintz 226fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 227fe56b9e6SYuval Mintz * value when an operation is finished on this context. 228fe56b9e6SYuval Mintz */ 229fe56b9e6SYuval Mintz u32 *p_completion_word; 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 232fe56b9e6SYuval Mintz 233fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 234fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 235fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 236fe56b9e6SYuval Mintz */ 237fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 240fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 241fe56b9e6SYuval Mintz }; 242fe56b9e6SYuval Mintz 243bcd197c8SManish Chopra struct qed_wfq_data { 244bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 245bcd197c8SManish Chopra u32 min_speed; 246bcd197c8SManish Chopra bool configured; 247bcd197c8SManish Chopra }; 248bcd197c8SManish Chopra 249fe56b9e6SYuval Mintz struct qed_qm_info { 250fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 251fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 252fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 253fe56b9e6SYuval Mintz u16 start_pq; 254fe56b9e6SYuval Mintz u8 start_vport; 255fe56b9e6SYuval Mintz u8 pure_lb_pq; 256fe56b9e6SYuval Mintz u8 offload_pq; 257fe56b9e6SYuval Mintz u8 pure_ack_pq; 258fe56b9e6SYuval Mintz u8 vf_queues_offset; 259fe56b9e6SYuval Mintz u16 num_pqs; 260fe56b9e6SYuval Mintz u16 num_vf_pqs; 261fe56b9e6SYuval Mintz u8 num_vports; 262fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 263fe56b9e6SYuval Mintz bool pf_rl_en; 264fe56b9e6SYuval Mintz bool pf_wfq_en; 265fe56b9e6SYuval Mintz bool vport_rl_en; 266fe56b9e6SYuval Mintz bool vport_wfq_en; 267fe56b9e6SYuval Mintz u8 pf_wfq; 268fe56b9e6SYuval Mintz u32 pf_rl; 269bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 270fe56b9e6SYuval Mintz }; 271fe56b9e6SYuval Mintz 2729df2ed04SManish Chopra struct storm_stats { 2739df2ed04SManish Chopra u32 address; 2749df2ed04SManish Chopra u32 len; 2759df2ed04SManish Chopra }; 2769df2ed04SManish Chopra 2779df2ed04SManish Chopra struct qed_storm_stats { 2789df2ed04SManish Chopra struct storm_stats mstats; 2799df2ed04SManish Chopra struct storm_stats pstats; 2809df2ed04SManish Chopra struct storm_stats tstats; 2819df2ed04SManish Chopra struct storm_stats ustats; 2829df2ed04SManish Chopra }; 2839df2ed04SManish Chopra 284fe56b9e6SYuval Mintz struct qed_fw_data { 2859df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 286fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 287fe56b9e6SYuval Mintz union init_op *init_ops; 288fe56b9e6SYuval Mintz const u32 *arr_data; 289fe56b9e6SYuval Mintz u32 init_ops_size; 290fe56b9e6SYuval Mintz }; 291fe56b9e6SYuval Mintz 292fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 293fe56b9e6SYuval Mintz void *token; 294fe56b9e6SYuval Mintz void (*func)(void *); 295fe56b9e6SYuval Mintz }; 296fe56b9e6SYuval Mintz 297fe56b9e6SYuval Mintz struct qed_hwfn { 298fe56b9e6SYuval Mintz struct qed_dev *cdev; 299fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 300fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 301fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 302fe56b9e6SYuval Mintz u8 abs_pf_id; 303fe56b9e6SYuval Mintz #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 304fe56b9e6SYuval Mintz u8 port_id; 305fe56b9e6SYuval Mintz bool b_active; 306fe56b9e6SYuval Mintz 307fe56b9e6SYuval Mintz u32 dp_module; 308fe56b9e6SYuval Mintz u8 dp_level; 309fe56b9e6SYuval Mintz char name[NAME_SIZE]; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz bool first_on_engine; 312fe56b9e6SYuval Mintz bool hw_init_done; 313fe56b9e6SYuval Mintz 314fe56b9e6SYuval Mintz /* BAR access */ 315fe56b9e6SYuval Mintz void __iomem *regview; 316fe56b9e6SYuval Mintz void __iomem *doorbells; 317fe56b9e6SYuval Mintz u64 db_phys_addr; 318fe56b9e6SYuval Mintz unsigned long db_size; 319fe56b9e6SYuval Mintz 320fe56b9e6SYuval Mintz /* PTT pool */ 321fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz /* HW info */ 324fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 325fe56b9e6SYuval Mintz 326fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 327fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 328fe56b9e6SYuval Mintz 329fe56b9e6SYuval Mintz /* SPQ */ 330fe56b9e6SYuval Mintz struct qed_spq *p_spq; 331fe56b9e6SYuval Mintz 332fe56b9e6SYuval Mintz /* EQ */ 333fe56b9e6SYuval Mintz struct qed_eq *p_eq; 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz /* Consolidate Q*/ 336fe56b9e6SYuval Mintz struct qed_consq *p_consq; 337fe56b9e6SYuval Mintz 338fe56b9e6SYuval Mintz /* Slow-Path definitions */ 339fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 340fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 343fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 344fe56b9e6SYuval Mintz 345fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 346fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz /* Protocol related */ 349fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 350fe56b9e6SYuval Mintz 351fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 352fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 353fe56b9e6SYuval Mintz u16 num_sbs; 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 358fe56b9e6SYuval Mintz bool b_int_enabled; 3598f16bc97SSudarsana Kalluru bool b_int_requested; 360fe56b9e6SYuval Mintz 361fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 362fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 363fc916ff2SSudarsana Reddy Kalluru 36432a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 365fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 366fe56b9e6SYuval Mintz 36725c089d7SYuval Mintz struct qed_hw_cid_data *p_tx_cids; 36825c089d7SYuval Mintz struct qed_hw_cid_data *p_rx_cids; 36925c089d7SYuval Mintz 370fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 371fe56b9e6SYuval Mintz 372fe56b9e6SYuval Mintz /* QM init */ 373fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 3749df2ed04SManish Chopra struct qed_storm_stats storm_stats; 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 377fe56b9e6SYuval Mintz void *unzip_buf; 378fe56b9e6SYuval Mintz 379fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 380fe56b9e6SYuval Mintz 381fe56b9e6SYuval Mintz struct z_stream_s *stream; 382fe56b9e6SYuval Mintz }; 383fe56b9e6SYuval Mintz 384fe56b9e6SYuval Mintz struct pci_params { 385fe56b9e6SYuval Mintz int pm_cap; 386fe56b9e6SYuval Mintz 387fe56b9e6SYuval Mintz unsigned long mem_start; 388fe56b9e6SYuval Mintz unsigned long mem_end; 389fe56b9e6SYuval Mintz unsigned int irq; 390fe56b9e6SYuval Mintz u8 pf_num; 391fe56b9e6SYuval Mintz }; 392fe56b9e6SYuval Mintz 393fe56b9e6SYuval Mintz struct qed_int_param { 394fe56b9e6SYuval Mintz u32 int_mode; 395fe56b9e6SYuval Mintz u8 num_vectors; 396fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 397fe56b9e6SYuval Mintz }; 398fe56b9e6SYuval Mintz 399fe56b9e6SYuval Mintz struct qed_int_params { 400fe56b9e6SYuval Mintz struct qed_int_param in; 401fe56b9e6SYuval Mintz struct qed_int_param out; 402fe56b9e6SYuval Mintz struct msix_entry *msix_table; 403fe56b9e6SYuval Mintz bool fp_initialized; 404fe56b9e6SYuval Mintz u8 fp_msix_base; 405fe56b9e6SYuval Mintz u8 fp_msix_cnt; 406fe56b9e6SYuval Mintz }; 407fe56b9e6SYuval Mintz 408fe56b9e6SYuval Mintz struct qed_dev { 409fe56b9e6SYuval Mintz u32 dp_module; 410fe56b9e6SYuval Mintz u8 dp_level; 411fe56b9e6SYuval Mintz char name[NAME_SIZE]; 412fe56b9e6SYuval Mintz 413fe56b9e6SYuval Mintz u8 type; 414fc48b7a6SYuval Mintz #define QED_DEV_TYPE_BB (0 << 0) 415fc48b7a6SYuval Mintz #define QED_DEV_TYPE_AH BIT(0) 416fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 417fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 418fc48b7a6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 419fc48b7a6SYuval Mintz CHIP_REV_IS_A0(dev)) 420fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 421fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 422fc48b7a6SYuval Mintz 423fc48b7a6SYuval Mintz #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 424fc48b7a6SYuval Mintz QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 425fc48b7a6SYuval Mintz 426fc48b7a6SYuval Mintz u16 vendor_id; 427fc48b7a6SYuval Mintz u16 device_id; 428fe56b9e6SYuval Mintz 429fe56b9e6SYuval Mintz u16 chip_num; 430fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 431fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 432fe56b9e6SYuval Mintz 433fe56b9e6SYuval Mintz u16 chip_rev; 434fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 435fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 436fc48b7a6SYuval Mintz #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 437fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 438fe56b9e6SYuval Mintz 439fe56b9e6SYuval Mintz u16 chip_metal; 440fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 441fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz u16 chip_bond_id; 444fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 445fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 446fe56b9e6SYuval Mintz 447fe56b9e6SYuval Mintz u8 num_engines; 448fe56b9e6SYuval Mintz u8 num_ports_in_engines; 449fe56b9e6SYuval Mintz u8 num_funcs_in_port; 450fe56b9e6SYuval Mintz 451fe56b9e6SYuval Mintz u8 path_id; 452fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 453fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 454fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 455fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 456fe56b9e6SYuval Mintz 457fe56b9e6SYuval Mintz int pcie_width; 458fe56b9e6SYuval Mintz int pcie_speed; 459fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 460fe56b9e6SYuval Mintz 461fe56b9e6SYuval Mintz /* Add MF related configuration */ 462fe56b9e6SYuval Mintz u8 mcp_rev; 463fe56b9e6SYuval Mintz u8 boot_mode; 464fe56b9e6SYuval Mintz 465fe56b9e6SYuval Mintz u8 wol; 466fe56b9e6SYuval Mintz 467fe56b9e6SYuval Mintz u32 int_mode; 468fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 469fe56b9e6SYuval Mintz u8 rx_coalesce_usecs; 470fe56b9e6SYuval Mintz u8 tx_coalesce_usecs; 471fe56b9e6SYuval Mintz 472fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 473fe56b9e6SYuval Mintz void __iomem *regview; 474fe56b9e6SYuval Mintz void __iomem *doorbells; 475fe56b9e6SYuval Mintz u64 db_phys_addr; 476fe56b9e6SYuval Mintz unsigned long db_size; 477fe56b9e6SYuval Mintz 478fe56b9e6SYuval Mintz /* PCI */ 479fe56b9e6SYuval Mintz u8 cache_shift; 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz /* Init */ 482fe56b9e6SYuval Mintz const struct iro *iro_arr; 483fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 484fe56b9e6SYuval Mintz 485fe56b9e6SYuval Mintz /* HW functions */ 486fe56b9e6SYuval Mintz u8 num_hwfns; 487fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 488fe56b9e6SYuval Mintz 48932a47e72SYuval Mintz /* SRIOV */ 49032a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 49132a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 49232a47e72SYuval Mintz 493464f6645SManish Chopra unsigned long tunn_mode; 494fe56b9e6SYuval Mintz u32 drv_type; 495fe56b9e6SYuval Mintz 496fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 497fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 498fe56b9e6SYuval Mintz 499fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 500fe56b9e6SYuval Mintz 501fe56b9e6SYuval Mintz /* Linux specific here */ 502fe56b9e6SYuval Mintz struct qede_dev *edev; 503fe56b9e6SYuval Mintz struct pci_dev *pdev; 504fe56b9e6SYuval Mintz int msg_enable; 505fe56b9e6SYuval Mintz 506fe56b9e6SYuval Mintz struct pci_params pci_params; 507fe56b9e6SYuval Mintz 508fe56b9e6SYuval Mintz struct qed_int_params int_params; 509fe56b9e6SYuval Mintz 510fe56b9e6SYuval Mintz u8 protocol; 511fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 512fe56b9e6SYuval Mintz 513cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 514cc875c2eSYuval Mintz union { 515cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 516cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 517cc875c2eSYuval Mintz } protocol_ops; 518cc875c2eSYuval Mintz void *ops_cookie; 519cc875c2eSYuval Mintz 520fe56b9e6SYuval Mintz const struct firmware *firmware; 521fe56b9e6SYuval Mintz }; 522fe56b9e6SYuval Mintz 52332a47e72SYuval Mintz #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 524fe56b9e6SYuval Mintz #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 525fe56b9e6SYuval Mintz #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 526fe56b9e6SYuval Mintz 527fe56b9e6SYuval Mintz /** 528fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 529fe56b9e6SYuval Mintz * the concrete value. 530fe56b9e6SYuval Mintz * 531fe56b9e6SYuval Mintz * @param concrete_fid 532fe56b9e6SYuval Mintz * 533fe56b9e6SYuval Mintz * @return inline u8 534fe56b9e6SYuval Mintz */ 535fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 536fe56b9e6SYuval Mintz u32 concrete_fid) 537fe56b9e6SYuval Mintz { 538fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 539fe56b9e6SYuval Mintz 540fe56b9e6SYuval Mintz return pfid; 541fe56b9e6SYuval Mintz } 542fe56b9e6SYuval Mintz 543fe56b9e6SYuval Mintz #define PURE_LB_TC 8 544fe56b9e6SYuval Mintz 545bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); 546bcd197c8SManish Chopra 547fe56b9e6SYuval Mintz #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 548fe56b9e6SYuval Mintz 549fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 550fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 551fe56b9e6SYuval Mintz 552fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 553fe56b9e6SYuval Mintz (cdev->regview) + \ 554fe56b9e6SYuval Mintz (offset)) 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 557fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 558fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 559fe56b9e6SYuval Mintz 560fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 561fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 562fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz /* Prototypes */ 565fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 566fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 567cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 568fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 569fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 570fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 571fe56b9e6SYuval Mintz 5728f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 5738f16bc97SSudarsana Kalluru 574fe56b9e6SYuval Mintz #endif /* _QED_H */ 575