11f4d4ed6SAlexander Lobakin /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation
4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd.
5fe56b9e6SYuval Mintz */
6fe56b9e6SYuval Mintz
7fe56b9e6SYuval Mintz #ifndef _QED_H
8fe56b9e6SYuval Mintz #define _QED_H
9fe56b9e6SYuval Mintz
10fe56b9e6SYuval Mintz #include <linux/types.h>
11fe56b9e6SYuval Mintz #include <linux/io.h>
12fe56b9e6SYuval Mintz #include <linux/delay.h>
13fe56b9e6SYuval Mintz #include <linux/firmware.h>
14fe56b9e6SYuval Mintz #include <linux/interrupt.h>
15fe56b9e6SYuval Mintz #include <linux/list.h>
16fe56b9e6SYuval Mintz #include <linux/mutex.h>
17fe56b9e6SYuval Mintz #include <linux/pci.h>
18fe56b9e6SYuval Mintz #include <linux/slab.h>
19fe56b9e6SYuval Mintz #include <linux/string.h>
20fe56b9e6SYuval Mintz #include <linux/workqueue.h>
21fe56b9e6SYuval Mintz #include <linux/zlib.h>
22fe56b9e6SYuval Mintz #include <linux/hashtable.h>
23fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h>
24c965db44STomer Tayar #include "qed_debug.h"
25fe56b9e6SYuval Mintz #include "qed_hsi.h"
26ee824f4bSOmkar Kulkarni #include "qed_dbg_hsi.h"
27ee824f4bSOmkar Kulkarni #include "qed_mfw_hsi.h"
28fe56b9e6SYuval Mintz
2925c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass;
305d24bcf1STomer Tayar
315d24bcf1STomer Tayar #define STORM_FW_VERSION \
325d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \
335d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION)
34fe56b9e6SYuval Mintz
35fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4)
36fe56b9e6SYuval Mintz #define NAME_SIZE 16
37fe56b9e6SYuval Mintz #define VER_SIZE 16
38fe56b9e6SYuval Mintz
39bcd197c8SManish Chopra #define QED_WFQ_UNIT 100
40bcd197c8SManish Chopra
4151ff1725SRam Amrani #define QED_WID_SIZE (1024)
42107392b7SRam Amrani #define QED_MIN_WIDS (4)
4351ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4)
4451ff1725SRam Amrani
45203d136eSPrabhakar Kushwaha #define QED_LLH_DONT_CARE 0
46203d136eSPrabhakar Kushwaha
47fe56b9e6SYuval Mintz /* cau states */
48fe56b9e6SYuval Mintz enum qed_coalescing_mode {
49fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE,
50fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE
51fe56b9e6SYuval Mintz };
52fe56b9e6SYuval Mintz
5362e4d438SSudarsana Reddy Kalluru enum qed_nvm_cmd {
5462e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN,
5562e4d438SSudarsana Reddy Kalluru QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA,
5662e4d438SSudarsana Reddy Kalluru QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM,
5762e4d438SSudarsana Reddy Kalluru QED_GET_MCP_NVM_RESP = 0xFFFFFF00
5862e4d438SSudarsana Reddy Kalluru };
5962e4d438SSudarsana Reddy Kalluru
60fe56b9e6SYuval Mintz struct qed_eth_cb_ops;
61fe56b9e6SYuval Mintz struct qed_dev_info;
626c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats;
636c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type;
642528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type;
652528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data;
66fe56b9e6SYuval Mintz
67fe56b9e6SYuval Mintz /* helpers */
685d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \
695d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT))
705d24bcf1STomer Tayar
715d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \
725d24bcf1STomer Tayar do { \
73b19601bbSTomer Tayar (name) &= ~(field ## _MASK); \
745d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\
755d24bcf1STomer Tayar } while (0)
765d24bcf1STomer Tayar
qed_db_addr(u32 cid,u32 DEMS)77fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS)
78fe56b9e6SYuval Mintz {
79fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
8051ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE);
8151ff1725SRam Amrani
8251ff1725SRam Amrani return db_addr;
8351ff1725SRam Amrani }
8451ff1725SRam Amrani
qed_db_addr_vf(u32 cid,u32 DEMS)8551ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS)
8651ff1725SRam Amrani {
8751ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) |
88fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid);
89fe56b9e6SYuval Mintz
90fe56b9e6SYuval Mintz return db_addr;
91fe56b9e6SYuval Mintz }
92fe56b9e6SYuval Mintz
93fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \
94b90cb538SOmkar Kulkarni ((sizeof(type_name) + (u32)(1 << ((p_hwfn)->cdev->cache_shift)) - 1) & \
95fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1))
96fe56b9e6SYuval Mintz
97b90cb538SOmkar Kulkarni #define for_each_hwfn(cdev, i) for (i = 0; i < (cdev)->num_hwfns; i++)
98fe56b9e6SYuval Mintz
99fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \
100b90cb538SOmkar Kulkarni ((val) == (cond1) ? true1 : \
101b90cb538SOmkar Kulkarni ((val) == (cond2) ? true2 : def))
102fe56b9e6SYuval Mintz
103fe56b9e6SYuval Mintz /* forward */
104fe56b9e6SYuval Mintz struct qed_ptt_pool;
105fe56b9e6SYuval Mintz struct qed_spq;
106fe56b9e6SYuval Mintz struct qed_sb_info;
107fe56b9e6SYuval Mintz struct qed_sb_attn_info;
108fe56b9e6SYuval Mintz struct qed_cxt_mngr;
109fe56b9e6SYuval Mintz struct qed_sb_sp_info;
1100a7fb11cSYuval Mintz struct qed_ll2_info;
111fe56b9e6SYuval Mintz struct qed_mcp_info;
11279284adeSMichal Kalderon struct qed_llh_info;
113fe56b9e6SYuval Mintz
114fe56b9e6SYuval Mintz struct qed_rt_data {
115fc48b7a6SYuval Mintz u32 *init_val;
116fc48b7a6SYuval Mintz bool *b_valid;
117fe56b9e6SYuval Mintz };
118fe56b9e6SYuval Mintz
119464f6645SManish Chopra enum qed_tunn_mode {
120464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN,
121464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN,
122464f6645SManish Chopra QED_MODE_L2GRE_TUNN,
123464f6645SManish Chopra QED_MODE_IPGRE_TUNN,
124464f6645SManish Chopra QED_MODE_VXLAN_TUNN,
125464f6645SManish Chopra };
126464f6645SManish Chopra
127464f6645SManish Chopra enum qed_tunn_clss {
128464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN,
129464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI,
130464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN,
131464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI,
13219968430SChopra, Manish QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
133464f6645SManish Chopra MAX_QED_TUNN_CLSS,
134464f6645SManish Chopra };
135464f6645SManish Chopra
13619968430SChopra, Manish struct qed_tunn_update_type {
13719968430SChopra, Manish bool b_update_mode;
13819968430SChopra, Manish bool b_mode_enabled;
13919968430SChopra, Manish enum qed_tunn_clss tun_cls;
14019968430SChopra, Manish };
14119968430SChopra, Manish
14219968430SChopra, Manish struct qed_tunn_update_udp_port {
14319968430SChopra, Manish bool b_update_port;
14419968430SChopra, Manish u16 port;
14519968430SChopra, Manish };
14619968430SChopra, Manish
14719968430SChopra, Manish struct qed_tunnel_info {
14819968430SChopra, Manish struct qed_tunn_update_type vxlan;
14919968430SChopra, Manish struct qed_tunn_update_type l2_geneve;
15019968430SChopra, Manish struct qed_tunn_update_type ip_geneve;
15119968430SChopra, Manish struct qed_tunn_update_type l2_gre;
15219968430SChopra, Manish struct qed_tunn_update_type ip_gre;
15319968430SChopra, Manish
15419968430SChopra, Manish struct qed_tunn_update_udp_port vxlan_port;
15519968430SChopra, Manish struct qed_tunn_update_udp_port geneve_port;
15619968430SChopra, Manish
15719968430SChopra, Manish bool b_update_rx_cls;
15819968430SChopra, Manish bool b_update_tx_cls;
15919968430SChopra, Manish };
16019968430SChopra, Manish
161464f6645SManish Chopra struct qed_tunn_start_params {
162464f6645SManish Chopra unsigned long tunn_mode;
163464f6645SManish Chopra u16 vxlan_udp_port;
164464f6645SManish Chopra u16 geneve_udp_port;
165464f6645SManish Chopra u8 update_vxlan_udp_port;
166464f6645SManish Chopra u8 update_geneve_udp_port;
167464f6645SManish Chopra u8 tunn_clss_vxlan;
168464f6645SManish Chopra u8 tunn_clss_l2geneve;
169464f6645SManish Chopra u8 tunn_clss_ipgeneve;
170464f6645SManish Chopra u8 tunn_clss_l2gre;
171464f6645SManish Chopra u8 tunn_clss_ipgre;
172464f6645SManish Chopra };
173464f6645SManish Chopra
174464f6645SManish Chopra struct qed_tunn_update_params {
175464f6645SManish Chopra unsigned long tunn_mode_update_mask;
176464f6645SManish Chopra unsigned long tunn_mode;
177464f6645SManish Chopra u16 vxlan_udp_port;
178464f6645SManish Chopra u16 geneve_udp_port;
179464f6645SManish Chopra u8 update_rx_pf_clss;
180464f6645SManish Chopra u8 update_tx_pf_clss;
181464f6645SManish Chopra u8 update_vxlan_udp_port;
182464f6645SManish Chopra u8 update_geneve_udp_port;
183464f6645SManish Chopra u8 tunn_clss_vxlan;
184464f6645SManish Chopra u8 tunn_clss_l2geneve;
185464f6645SManish Chopra u8 tunn_clss_ipgeneve;
186464f6645SManish Chopra u8 tunn_clss_l2gre;
187464f6645SManish Chopra u8 tunn_clss_ipgre;
188464f6645SManish Chopra };
189464f6645SManish Chopra
190fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID:
191fe56b9e6SYuval Mintz * 1. All personalities need CORE connections
192c851a9dcSKalderon, Michal * 2. The Ethernet personality may support also the RoCE/iWARP protocol
193fe56b9e6SYuval Mintz */
194fe56b9e6SYuval Mintz enum qed_pci_personality {
195fe56b9e6SYuval Mintz QED_PCI_ETH,
1961e128c81SArun Easi QED_PCI_FCOE,
197c5ac9319SYuval Mintz QED_PCI_ISCSI,
198897e87a1SShai Malin QED_PCI_NVMETCP,
199c5ac9319SYuval Mintz QED_PCI_ETH_ROCE,
200c851a9dcSKalderon, Michal QED_PCI_ETH_IWARP,
201c851a9dcSKalderon, Michal QED_PCI_ETH_RDMA,
202c851a9dcSKalderon, Michal QED_PCI_DEFAULT, /* default in shmem */
203fe56b9e6SYuval Mintz };
204fe56b9e6SYuval Mintz
205fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */
206fe56b9e6SYuval Mintz struct qed_qm_iids {
207fe56b9e6SYuval Mintz u32 cids;
208fe56b9e6SYuval Mintz u32 vf_cids;
209fe56b9e6SYuval Mintz u32 tids;
210fe56b9e6SYuval Mintz };
211fe56b9e6SYuval Mintz
2122edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information
2132edbff8dSTomer Tayar * is received from MFW.
2142edbff8dSTomer Tayar */
2152edbff8dSTomer Tayar enum qed_resources {
216fe56b9e6SYuval Mintz QED_SB,
21725c089d7SYuval Mintz QED_L2_QUEUE,
218fe56b9e6SYuval Mintz QED_VPORT,
21925c089d7SYuval Mintz QED_RSS_ENG,
220fe56b9e6SYuval Mintz QED_PQ,
221fe56b9e6SYuval Mintz QED_RL,
22225c089d7SYuval Mintz QED_MAC,
22325c089d7SYuval Mintz QED_VLAN,
22451ff1725SRam Amrani QED_RDMA_CNQ_RAM,
225fe56b9e6SYuval Mintz QED_ILT,
226997af5dfSMichal Kalderon QED_LL2_RAM_QUEUE,
227997af5dfSMichal Kalderon QED_LL2_CTX_QUEUE,
2282edbff8dSTomer Tayar QED_CMDQS_CQS,
22951ff1725SRam Amrani QED_RDMA_STATS_QUEUE,
2309c8517c4STomer Tayar QED_BDQ,
231fe56b9e6SYuval Mintz QED_MAX_RESC,
232fe56b9e6SYuval Mintz };
233fe56b9e6SYuval Mintz
23425c089d7SYuval Mintz enum QED_FEATURE {
23525c089d7SYuval Mintz QED_PF_L2_QUE,
23632a47e72SYuval Mintz QED_VF,
23751ff1725SRam Amrani QED_RDMA_CNQ,
238897e87a1SShai Malin QED_NVMETCP_CQ,
23908737a3fSMintz, Yuval QED_ISCSI_CQ,
2401e128c81SArun Easi QED_FCOE_CQ,
24108737a3fSMintz, Yuval QED_VF_L2_QUE,
24225c089d7SYuval Mintz QED_MAX_FEATURES,
24325c089d7SYuval Mintz };
24425c089d7SYuval Mintz
245fc48b7a6SYuval Mintz enum qed_dev_cap {
246fc48b7a6SYuval Mintz QED_DEV_CAP_ETH,
2471e128c81SArun Easi QED_DEV_CAP_FCOE,
248c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI,
249c5ac9319SYuval Mintz QED_DEV_CAP_ROCE,
250c851a9dcSKalderon, Michal QED_DEV_CAP_IWARP,
251fc48b7a6SYuval Mintz };
252fc48b7a6SYuval Mintz
25314d39648SMintz, Yuval enum qed_wol_support {
25414d39648SMintz, Yuval QED_WOL_SUPPORT_NONE,
25514d39648SMintz, Yuval QED_WOL_SUPPORT_PME,
25614d39648SMintz, Yuval };
25714d39648SMintz, Yuval
25836907cd5SAriel Elior enum qed_db_rec_exec {
25936907cd5SAriel Elior DB_REC_DRY_RUN,
26036907cd5SAriel Elior DB_REC_REAL_DEAL,
26136907cd5SAriel Elior DB_REC_ONCE,
26236907cd5SAriel Elior };
26336907cd5SAriel Elior
264fe56b9e6SYuval Mintz struct qed_hw_info {
265fe56b9e6SYuval Mintz /* PCI personality */
266fe56b9e6SYuval Mintz enum qed_pci_personality personality;
267c851a9dcSKalderon, Michal #define QED_IS_RDMA_PERSONALITY(dev) \
268c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
269c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
270c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
271c851a9dcSKalderon, Michal #define QED_IS_ROCE_PERSONALITY(dev) \
272c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \
273c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
274c851a9dcSKalderon, Michal #define QED_IS_IWARP_PERSONALITY(dev) \
275c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \
276c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA)
277c851a9dcSKalderon, Michal #define QED_IS_L2_PERSONALITY(dev) \
278c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH || \
279c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(dev))
280c851a9dcSKalderon, Michal #define QED_IS_FCOE_PERSONALITY(dev) \
281c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_FCOE)
282c851a9dcSKalderon, Michal #define QED_IS_ISCSI_PERSONALITY(dev) \
283c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ISCSI)
284897e87a1SShai Malin #define QED_IS_NVMETCP_PERSONALITY(dev) \
285897e87a1SShai Malin ((dev)->hw_info.personality == QED_PCI_NVMETCP)
286fe56b9e6SYuval Mintz
287fe56b9e6SYuval Mintz /* Resource Allocation scheme results */
288fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC];
289fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC];
290fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc])
291fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc])
292dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \
293dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc))
2945d4193c6SAlexander Lobakin
2955d4193c6SAlexander Lobakin u32 feat_num[QED_MAX_FEATURES];
296fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
297fe56b9e6SYuval Mintz
298b5a9ee7cSAriel Elior /* Amount of traffic classes HW supports */
299b5a9ee7cSAriel Elior u8 num_hw_tc;
300b5a9ee7cSAriel Elior
301b5a9ee7cSAriel Elior /* Amount of TCs which should be active according to DCBx or upper
302b5a9ee7cSAriel Elior * layer driver configuration.
303b5a9ee7cSAriel Elior */
304b5a9ee7cSAriel Elior u8 num_active_tc;
3055d4193c6SAlexander Lobakin
306fe56b9e6SYuval Mintz u8 offload_tc;
307c4259ddaSDenis Bolotin bool offload_tc_set;
308fe56b9e6SYuval Mintz
30961be82b0SDenis Bolotin bool multi_tc_roce_en;
3105d4193c6SAlexander Lobakin #define IS_QED_MULTI_TC_ROCE(p_hwfn) ((p_hwfn)->hw_info.multi_tc_roce_en)
31161be82b0SDenis Bolotin
312fe56b9e6SYuval Mintz u32 concrete_fid;
313fe56b9e6SYuval Mintz u16 opaque_fid;
314fe56b9e6SYuval Mintz u16 ovlan;
315fe56b9e6SYuval Mintz u32 part_num[4];
316fe56b9e6SYuval Mintz
317fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN];
3181e128c81SArun Easi u64 node_wwn;
3191e128c81SArun Easi u64 port_wwn;
3201e128c81SArun Easi
3211e128c81SArun Easi u16 num_fcoe_conns;
322fe56b9e6SYuval Mintz
323fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info;
324fe56b9e6SYuval Mintz
325fe56b9e6SYuval Mintz u32 hw_mode;
326fc48b7a6SYuval Mintz unsigned long device_capabilities;
3270fefbfbaSSudarsana Kalluru u16 mtu;
32814d39648SMintz, Yuval
32914d39648SMintz, Yuval enum qed_wol_support b_wol_support;
330fe56b9e6SYuval Mintz };
331fe56b9e6SYuval Mintz
332fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */
333fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000
334fe56b9e6SYuval Mintz
335fe56b9e6SYuval Mintz struct qed_dmae_info {
336fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */
337fe56b9e6SYuval Mintz struct mutex mutex;
338fe56b9e6SYuval Mintz
339fe56b9e6SYuval Mintz u8 channel;
340fe56b9e6SYuval Mintz
341fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr;
342fe56b9e6SYuval Mintz
343fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion
344fe56b9e6SYuval Mintz * value when an operation is finished on this context.
345fe56b9e6SYuval Mintz */
346fe56b9e6SYuval Mintz u32 *p_completion_word;
347fe56b9e6SYuval Mintz
348fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr;
349fe56b9e6SYuval Mintz
350fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual
351fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then
352fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address
353fe56b9e6SYuval Mintz */
354fe56b9e6SYuval Mintz u32 *p_intermediate_buffer;
355fe56b9e6SYuval Mintz
356fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr;
357fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd;
358fe56b9e6SYuval Mintz };
359fe56b9e6SYuval Mintz
360bcd197c8SManish Chopra struct qed_wfq_data {
361bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */
362bcd197c8SManish Chopra u32 min_speed;
363bcd197c8SManish Chopra bool configured;
364bcd197c8SManish Chopra };
365bcd197c8SManish Chopra
366fe56b9e6SYuval Mintz struct qed_qm_info {
367fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params;
368fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params;
369fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params;
370fe56b9e6SYuval Mintz u16 start_pq;
371fe56b9e6SYuval Mintz u8 start_vport;
372b5a9ee7cSAriel Elior u16 pure_lb_pq;
37361be82b0SDenis Bolotin u16 first_ofld_pq;
37461be82b0SDenis Bolotin u16 first_llt_pq;
375b5a9ee7cSAriel Elior u16 pure_ack_pq;
376b5a9ee7cSAriel Elior u16 ooo_pq;
377b5a9ee7cSAriel Elior u16 first_vf_pq;
378b5a9ee7cSAriel Elior u16 first_mcos_pq;
379b5a9ee7cSAriel Elior u16 first_rl_pq;
380fe56b9e6SYuval Mintz u16 num_pqs;
381fe56b9e6SYuval Mintz u16 num_vf_pqs;
382fe56b9e6SYuval Mintz u8 num_vports;
383fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port;
384b5a9ee7cSAriel Elior u8 ooo_tc;
385fe56b9e6SYuval Mintz bool pf_rl_en;
386fe56b9e6SYuval Mintz bool pf_wfq_en;
387fe56b9e6SYuval Mintz bool vport_rl_en;
388fe56b9e6SYuval Mintz bool vport_wfq_en;
389fe56b9e6SYuval Mintz u8 pf_wfq;
390fe56b9e6SYuval Mintz u32 pf_rl;
391bcd197c8SManish Chopra struct qed_wfq_data *wfq_data;
392dbb799c3SYuval Mintz u8 num_pf_rls;
393fe56b9e6SYuval Mintz };
394fe56b9e6SYuval Mintz
3950d72c2acSDenis Bolotin #define QED_OVERFLOW_BIT 1
3960d72c2acSDenis Bolotin
39736907cd5SAriel Elior struct qed_db_recovery_info {
39836907cd5SAriel Elior struct list_head list;
39936907cd5SAriel Elior
40036907cd5SAriel Elior /* Lock to protect the doorbell recovery mechanism list */
40136907cd5SAriel Elior spinlock_t lock;
402d4476b8aSDenis Bolotin bool dorq_attn;
40336907cd5SAriel Elior u32 db_recovery_counter;
4040d72c2acSDenis Bolotin unsigned long overflow;
40536907cd5SAriel Elior };
40636907cd5SAriel Elior
4079df2ed04SManish Chopra struct storm_stats {
4089df2ed04SManish Chopra u32 address;
4099df2ed04SManish Chopra u32 len;
4109df2ed04SManish Chopra };
4119df2ed04SManish Chopra
4129df2ed04SManish Chopra struct qed_storm_stats {
4139df2ed04SManish Chopra struct storm_stats mstats;
4149df2ed04SManish Chopra struct storm_stats pstats;
4159df2ed04SManish Chopra struct storm_stats tstats;
4169df2ed04SManish Chopra struct storm_stats ustats;
4179df2ed04SManish Chopra };
4189df2ed04SManish Chopra
419fe56b9e6SYuval Mintz struct qed_fw_data {
4209df2ed04SManish Chopra struct fw_ver_info *fw_ver_info;
421fe56b9e6SYuval Mintz const u8 *modes_tree_buf;
422fe56b9e6SYuval Mintz union init_op *init_ops;
423fe56b9e6SYuval Mintz const u32 *arr_data;
42430d5f858SMichal Kalderon const u32 *fw_overlays;
42530d5f858SMichal Kalderon u32 fw_overlays_len;
426fe56b9e6SYuval Mintz u32 init_ops_size;
427fe56b9e6SYuval Mintz };
428fe56b9e6SYuval Mintz
4290bc5fe85SSudarsana Reddy Kalluru enum qed_mf_mode_bit {
4300bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on tag */
4310bc5fe85SSudarsana Reddy Kalluru QED_MF_OVLAN_CLSS,
4320bc5fe85SSudarsana Reddy Kalluru
4330bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on MAC */
4340bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_MAC_CLSS,
4350bc5fe85SSudarsana Reddy Kalluru
4360bc5fe85SSudarsana Reddy Kalluru /* Supports PF-classification based on protocol type */
4370bc5fe85SSudarsana Reddy Kalluru QED_MF_LLH_PROTO_CLSS,
4380bc5fe85SSudarsana Reddy Kalluru
4390bc5fe85SSudarsana Reddy Kalluru /* Requires a default PF to be set */
4400bc5fe85SSudarsana Reddy Kalluru QED_MF_NEED_DEF_PF,
4410bc5fe85SSudarsana Reddy Kalluru
4420bc5fe85SSudarsana Reddy Kalluru /* Allow LL2 to multicast/broadcast */
4430bc5fe85SSudarsana Reddy Kalluru QED_MF_LL2_NON_UNICAST,
4440bc5fe85SSudarsana Reddy Kalluru
4450bc5fe85SSudarsana Reddy Kalluru /* Allow Cross-PF [& child VFs] Tx-switching */
4460bc5fe85SSudarsana Reddy Kalluru QED_MF_INTER_PF_SWITCH,
4470bc5fe85SSudarsana Reddy Kalluru
4480bc5fe85SSudarsana Reddy Kalluru /* Unified Fabtic Port support enabled */
4490bc5fe85SSudarsana Reddy Kalluru QED_MF_UFP_SPECIFIC,
4500bc5fe85SSudarsana Reddy Kalluru
4510bc5fe85SSudarsana Reddy Kalluru /* Disable Accelerated Receive Flow Steering (aRFS) */
4520bc5fe85SSudarsana Reddy Kalluru QED_MF_DISABLE_ARFS,
4530bc5fe85SSudarsana Reddy Kalluru
4540bc5fe85SSudarsana Reddy Kalluru /* Use vlan for steering */
4550bc5fe85SSudarsana Reddy Kalluru QED_MF_8021Q_TAGGING,
4560bc5fe85SSudarsana Reddy Kalluru
4570bc5fe85SSudarsana Reddy Kalluru /* Use stag for steering */
4580bc5fe85SSudarsana Reddy Kalluru QED_MF_8021AD_TAGGING,
4590bc5fe85SSudarsana Reddy Kalluru
4600bc5fe85SSudarsana Reddy Kalluru /* Allow DSCP to TC mapping */
4610bc5fe85SSudarsana Reddy Kalluru QED_MF_DSCP_TO_TC_MAP,
4621a3ca250SSudarsana Reddy Kalluru
4631a3ca250SSudarsana Reddy Kalluru /* Do not insert a vlan tag with id 0 */
4641a3ca250SSudarsana Reddy Kalluru QED_MF_DONT_ADD_VLAN0_TAG,
4650bc5fe85SSudarsana Reddy Kalluru };
4660bc5fe85SSudarsana Reddy Kalluru
467cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode {
468cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_ETS,
469cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_VNIC_BW,
470cac6f691SSudarsana Reddy Kalluru QED_UFP_MODE_UNKNOWN
471cac6f691SSudarsana Reddy Kalluru };
472cac6f691SSudarsana Reddy Kalluru
473cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type {
474cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_OS,
475cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_VNIC,
476cac6f691SSudarsana Reddy Kalluru QED_UFP_PRI_UNKNOWN
477cac6f691SSudarsana Reddy Kalluru };
478cac6f691SSudarsana Reddy Kalluru
479cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info {
480cac6f691SSudarsana Reddy Kalluru enum qed_ufp_pri_type pri_type;
481cac6f691SSudarsana Reddy Kalluru enum qed_ufp_mode mode;
482cac6f691SSudarsana Reddy Kalluru u8 tc;
483cac6f691SSudarsana Reddy Kalluru };
484cac6f691SSudarsana Reddy Kalluru
4851a850bfcSMintz, Yuval enum BAR_ID {
4861a850bfcSMintz, Yuval BAR_ID_0, /* used for GRC */
4871a850bfcSMintz, Yuval BAR_ID_1 /* Used for doorbells */
4881a850bfcSMintz, Yuval };
4891a850bfcSMintz, Yuval
49043645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info {
49143645ce0SSudarsana Reddy Kalluru u32 num_images;
49243645ce0SSudarsana Reddy Kalluru struct bist_nvm_image_att *image_att;
4935e7ba042SDenis Bolotin bool valid;
49443645ce0SSudarsana Reddy Kalluru };
49543645ce0SSudarsana Reddy Kalluru
4961392d19fSMichal Kalderon enum qed_hsi_def_type {
4971392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_VFS,
4981392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_L2_QUEUES,
4991392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_PORTS,
5001392d19fSMichal Kalderon QED_HSI_DEF_MAX_SB_PER_PATH,
5011392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_PFS,
5021392d19fSMichal Kalderon QED_HSI_DEF_MAX_NUM_VPORTS,
5031392d19fSMichal Kalderon QED_HSI_DEF_NUM_ETH_RSS_ENGINE,
5041392d19fSMichal Kalderon QED_HSI_DEF_MAX_QM_TX_QUEUES,
5051392d19fSMichal Kalderon QED_HSI_DEF_NUM_PXP_ILT_RECORDS,
5061392d19fSMichal Kalderon QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS,
5071392d19fSMichal Kalderon QED_HSI_DEF_MAX_QM_GLOBAL_RLS,
5081392d19fSMichal Kalderon QED_HSI_DEF_MAX_PBF_CMD_LINES,
5091392d19fSMichal Kalderon QED_HSI_DEF_MAX_BTB_BLOCKS,
5101392d19fSMichal Kalderon QED_NUM_HSI_DEFS
5111392d19fSMichal Kalderon };
5121392d19fSMichal Kalderon
513fe56b9e6SYuval Mintz struct qed_simd_fp_handler {
514fe56b9e6SYuval Mintz void *token;
515b90cb538SOmkar Kulkarni void (*func)(void *cookie);
516fe56b9e6SYuval Mintz };
517fe56b9e6SYuval Mintz
51859ccf86fSSudarsana Reddy Kalluru enum qed_slowpath_wq_flag {
51959ccf86fSSudarsana Reddy Kalluru QED_SLOWPATH_MFW_TLV_REQ,
520a1b469b8SAriel Elior QED_SLOWPATH_PERIODIC_DB_REC,
52159ccf86fSSudarsana Reddy Kalluru };
52259ccf86fSSudarsana Reddy Kalluru
523fe56b9e6SYuval Mintz struct qed_hwfn {
524fe56b9e6SYuval Mintz struct qed_dev *cdev;
525fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */
526fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id))
527fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/
528fe56b9e6SYuval Mintz u8 abs_pf_id;
5299c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \
5309c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1))
531fe56b9e6SYuval Mintz u8 port_id;
532fe56b9e6SYuval Mintz bool b_active;
533fe56b9e6SYuval Mintz
534fe56b9e6SYuval Mintz u32 dp_module;
535fe56b9e6SYuval Mintz u8 dp_level;
536fe56b9e6SYuval Mintz char name[NAME_SIZE];
537fe56b9e6SYuval Mintz
538fe56b9e6SYuval Mintz bool hw_init_done;
539fe56b9e6SYuval Mintz
5401408cc1fSYuval Mintz u8 num_funcs_on_engine;
541dbb799c3SYuval Mintz u8 enabled_func_idx;
5421408cc1fSYuval Mintz
543fe56b9e6SYuval Mintz /* BAR access */
544fe56b9e6SYuval Mintz void __iomem *regview;
545fe56b9e6SYuval Mintz void __iomem *doorbells;
546fe56b9e6SYuval Mintz u64 db_phys_addr;
547fe56b9e6SYuval Mintz unsigned long db_size;
548fe56b9e6SYuval Mintz
549fe56b9e6SYuval Mintz /* PTT pool */
550fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool;
551fe56b9e6SYuval Mintz
552fe56b9e6SYuval Mintz /* HW info */
553fe56b9e6SYuval Mintz struct qed_hw_info hw_info;
554fe56b9e6SYuval Mintz
555fe56b9e6SYuval Mintz /* rt_array (for init-tool) */
556fc48b7a6SYuval Mintz struct qed_rt_data rt_data;
557fe56b9e6SYuval Mintz
558fe56b9e6SYuval Mintz /* SPQ */
559fe56b9e6SYuval Mintz struct qed_spq *p_spq;
560fe56b9e6SYuval Mintz
561fe56b9e6SYuval Mintz /* EQ */
562fe56b9e6SYuval Mintz struct qed_eq *p_eq;
563fe56b9e6SYuval Mintz
564fe56b9e6SYuval Mintz /* Consolidate Q*/
565fe56b9e6SYuval Mintz struct qed_consq *p_consq;
566fe56b9e6SYuval Mintz
567fe56b9e6SYuval Mintz /* Slow-Path definitions */
568b5f0a3bfSAllen Pais struct tasklet_struct sp_dpc;
569fe56b9e6SYuval Mintz bool b_sp_dpc_enabled;
570fe56b9e6SYuval Mintz
571fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt;
572fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt;
573fe56b9e6SYuval Mintz
574d179bd16Ssudarsana.kalluru@cavium.com /* PTP will be used only by the leading function.
575d179bd16Ssudarsana.kalluru@cavium.com * Usage of all PTP-apis should be synchronized as result.
576d179bd16Ssudarsana.kalluru@cavium.com */
577d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptp_ptt;
578d179bd16Ssudarsana.kalluru@cavium.com
579fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb;
580fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn;
581fe56b9e6SYuval Mintz
582fe56b9e6SYuval Mintz /* Protocol related */
5830a7fb11cSYuval Mintz bool using_ll2;
5840a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info;
5851d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info;
58651ff1725SRam Amrani struct qed_rdma_info *p_rdma_info;
587fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info;
588897e87a1SShai Malin struct qed_nvmetcp_info *p_nvmetcp_info;
5891e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info;
590fe56b9e6SYuval Mintz struct qed_pf_params pf_params;
591fe56b9e6SYuval Mintz
592dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs;
593dbb799c3SYuval Mintz u32 rdma_prs_search_reg;
594dbb799c3SYuval Mintz
595fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr;
596fe56b9e6SYuval Mintz
597fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/
598fe56b9e6SYuval Mintz bool b_int_enabled;
5998f16bc97SSudarsana Kalluru bool b_int_requested;
600fe56b9e6SYuval Mintz
601fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */
602fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init;
603fc916ff2SSudarsana Reddy Kalluru
6041408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info;
60532a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info;
606fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info;
607fe56b9e6SYuval Mintz
60839651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info;
60939651abdSSudarsana Reddy Kalluru
610cac6f691SSudarsana Reddy Kalluru struct qed_ufp_info ufp_info;
611cac6f691SSudarsana Reddy Kalluru
612fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info;
613fe56b9e6SYuval Mintz
614fe56b9e6SYuval Mintz /* QM init */
615fe56b9e6SYuval Mintz struct qed_qm_info qm_info;
6169df2ed04SManish Chopra struct qed_storm_stats storm_stats;
617fe56b9e6SYuval Mintz
618fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */
619fe56b9e6SYuval Mintz void *unzip_buf;
620fe56b9e6SYuval Mintz
621c965db44STomer Tayar struct dbg_tools_data dbg_info;
622a3f72307SDenis Bolotin void *dbg_user_info;
6232d22bc83SMichal Kalderon struct virt_mem_desc dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE];
624c965db44STomer Tayar
62551ff1725SRam Amrani /* PWM region specific data */
62620b1bd96SRam Amrani u16 wid_count;
62751ff1725SRam Amrani u32 dpi_size;
62851ff1725SRam Amrani u32 dpi_count;
62951ff1725SRam Amrani
63051ff1725SRam Amrani /* This is used to calculate the doorbell address */
63151ff1725SRam Amrani u32 dpi_start_offset;
63251ff1725SRam Amrani
63351ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */
63451ff1725SRam Amrani u8 dcbx_no_edpm;
63551ff1725SRam Amrani u8 db_bar_no_edpm;
63651ff1725SRam Amrani
6370db711bbSMintz, Yuval /* L2-related */
6380db711bbSMintz, Yuval struct qed_l2_info *p_l2_info;
6390db711bbSMintz, Yuval
64036907cd5SAriel Elior /* Mechanism for recovering from doorbell drop */
64136907cd5SAriel Elior struct qed_db_recovery_info db_recovery_info;
64236907cd5SAriel Elior
64343645ce0SSudarsana Reddy Kalluru /* Nvm images number and attributes */
64443645ce0SSudarsana Reddy Kalluru struct qed_nvm_image_info nvm_info;
64543645ce0SSudarsana Reddy Kalluru
64630d5f858SMichal Kalderon struct phys_mem_desc *fw_overlay_mem;
647d51e4af5SChopra, Manish struct qed_ptt *p_arfs_ptt;
648d51e4af5SChopra, Manish
649fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64];
650fe56b9e6SYuval Mintz
65137bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV
65237bff2b9SYuval Mintz struct workqueue_struct *iov_wq;
65337bff2b9SYuval Mintz struct delayed_work iov_task;
65437bff2b9SYuval Mintz unsigned long iov_task_flags;
65537bff2b9SYuval Mintz #endif
656fe56b9e6SYuval Mintz struct z_stream_s *stream;
657a1b469b8SAriel Elior bool slowpath_wq_active;
65859ccf86fSSudarsana Reddy Kalluru struct workqueue_struct *slowpath_wq;
65959ccf86fSSudarsana Reddy Kalluru struct delayed_work slowpath_task;
66059ccf86fSSudarsana Reddy Kalluru unsigned long slowpath_task_flags;
661a1b469b8SAriel Elior u32 periodic_db_rec_count;
662fe56b9e6SYuval Mintz };
663fe56b9e6SYuval Mintz
664fe56b9e6SYuval Mintz struct pci_params {
665fe56b9e6SYuval Mintz int pm_cap;
666fe56b9e6SYuval Mintz
667fe56b9e6SYuval Mintz unsigned long mem_start;
668fe56b9e6SYuval Mintz unsigned long mem_end;
669fe56b9e6SYuval Mintz unsigned int irq;
670fe56b9e6SYuval Mintz u8 pf_num;
671fe56b9e6SYuval Mintz };
672fe56b9e6SYuval Mintz
673fe56b9e6SYuval Mintz struct qed_int_param {
674fe56b9e6SYuval Mintz u32 int_mode;
675fe56b9e6SYuval Mintz u8 num_vectors;
676fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */
677fe56b9e6SYuval Mintz };
678fe56b9e6SYuval Mintz
679fe56b9e6SYuval Mintz struct qed_int_params {
680fe56b9e6SYuval Mintz struct qed_int_param in;
681fe56b9e6SYuval Mintz struct qed_int_param out;
682fe56b9e6SYuval Mintz struct msix_entry *msix_table;
683fe56b9e6SYuval Mintz bool fp_initialized;
684fe56b9e6SYuval Mintz u8 fp_msix_base;
685fe56b9e6SYuval Mintz u8 fp_msix_cnt;
68651ff1725SRam Amrani u8 rdma_msix_base;
68751ff1725SRam Amrani u8 rdma_msix_cnt;
688fe56b9e6SYuval Mintz };
689fe56b9e6SYuval Mintz
690c965db44STomer Tayar struct qed_dbg_feature {
691c965db44STomer Tayar struct dentry *dentry;
692c965db44STomer Tayar u8 *dump_buf;
693c965db44STomer Tayar u32 buf_size;
694c965db44STomer Tayar u32 dumped_dwords;
695c965db44STomer Tayar };
696c965db44STomer Tayar
697fe56b9e6SYuval Mintz struct qed_dev {
698fe56b9e6SYuval Mintz u32 dp_module;
699fe56b9e6SYuval Mintz u8 dp_level;
700fe56b9e6SYuval Mintz char name[NAME_SIZE];
701fe56b9e6SYuval Mintz
7029c79ddaaSMintz, Yuval enum qed_dev_type type;
703fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */
704fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB)
7055d4193c6SAlexander Lobakin #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && CHIP_REV_IS_B0(dev))
706c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH)
707c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev)
708fc48b7a6SYuval Mintz
709fc48b7a6SYuval Mintz u16 vendor_id;
7105d4193c6SAlexander Lobakin
711fc48b7a6SYuval Mintz u16 device_id;
7129c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00
7139c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600
7149c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000
715fe56b9e6SYuval Mintz
716fe56b9e6SYuval Mintz u16 chip_num;
717fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff
718fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16
719fe56b9e6SYuval Mintz
720fe56b9e6SYuval Mintz u16 chip_rev;
721fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf
722fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12
723fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1)
724fe56b9e6SYuval Mintz
725fe56b9e6SYuval Mintz u16 chip_metal;
726fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff
727fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4
728fe56b9e6SYuval Mintz
729fe56b9e6SYuval Mintz u16 chip_bond_id;
730fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf
731fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0
732fe56b9e6SYuval Mintz
733fe56b9e6SYuval Mintz u8 num_engines;
7340ebcebbeSSudarsana Reddy Kalluru u8 num_ports;
73578cea9ffSTomer Tayar u8 num_ports_in_engine;
736fe56b9e6SYuval Mintz u8 num_funcs_in_port;
737fe56b9e6SYuval Mintz
738fe56b9e6SYuval Mintz u8 path_id;
7390bc5fe85SSudarsana Reddy Kalluru
7400bc5fe85SSudarsana Reddy Kalluru unsigned long mf_bits;
741fe56b9e6SYuval Mintz
742fe56b9e6SYuval Mintz int pcie_width;
743fe56b9e6SYuval Mintz int pcie_speed;
744fe56b9e6SYuval Mintz
745fe56b9e6SYuval Mintz /* Add MF related configuration */
746fe56b9e6SYuval Mintz u8 mcp_rev;
747fe56b9e6SYuval Mintz u8 boot_mode;
748fe56b9e6SYuval Mintz
74914d39648SMintz, Yuval /* WoL related configurations */
75014d39648SMintz, Yuval u8 wol_config;
75114d39648SMintz, Yuval u8 wol_mac[ETH_ALEN];
752fe56b9e6SYuval Mintz
753fe56b9e6SYuval Mintz u32 int_mode;
754fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode;
75551d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs;
75651d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs;
757fe56b9e6SYuval Mintz
758fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */
759fe56b9e6SYuval Mintz void __iomem *regview;
760fe56b9e6SYuval Mintz void __iomem *doorbells;
761fe56b9e6SYuval Mintz u64 db_phys_addr;
762fe56b9e6SYuval Mintz unsigned long db_size;
763fe56b9e6SYuval Mintz
764fe56b9e6SYuval Mintz /* PCI */
765fe56b9e6SYuval Mintz u8 cache_shift;
766fe56b9e6SYuval Mintz
767fe56b9e6SYuval Mintz /* Init */
7682924e069SMichal Kalderon const u32 *iro_arr;
7692924e069SMichal Kalderon #define IRO ((const struct iro *)p_hwfn->cdev->iro_arr)
770fe56b9e6SYuval Mintz
771fe56b9e6SYuval Mintz /* HW functions */
772fe56b9e6SYuval Mintz u8 num_hwfns;
773fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
774fe56b9e6SYuval Mintz
77579284adeSMichal Kalderon /* Engine affinity */
77679284adeSMichal Kalderon u8 l2_affin_hint;
77779284adeSMichal Kalderon u8 fir_affin;
77879284adeSMichal Kalderon u8 iwarp_affin;
77979284adeSMichal Kalderon
78032a47e72SYuval Mintz /* SRIOV */
78132a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info;
78232a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info)
78319968430SChopra, Manish struct qed_tunnel_info tunnel;
7841408cc1fSYuval Mintz bool b_is_vf;
785fe56b9e6SYuval Mintz u32 drv_type;
786fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats;
787fe56b9e6SYuval Mintz struct qed_fw_data *fw_data;
788fe56b9e6SYuval Mintz
789fe56b9e6SYuval Mintz u32 mcp_nvm_resp;
790fe56b9e6SYuval Mintz
79164515dc8STomer Tayar /* Recovery */
79264515dc8STomer Tayar bool recov_in_prog;
79364515dc8STomer Tayar
794936c7ba4SIgor Russkikh /* Indicates whether should prevent attentions from being reasserted */
795936c7ba4SIgor Russkikh bool attn_clr_en;
796936c7ba4SIgor Russkikh
79779284adeSMichal Kalderon /* LLH info */
79879284adeSMichal Kalderon u8 ppfid_bitmap;
79979284adeSMichal Kalderon struct qed_llh_info *p_llh_info;
80079284adeSMichal Kalderon
801fe56b9e6SYuval Mintz /* Linux specific here */
80253916a67SIgor Russkikh struct qed_dev_info common_dev_info;
803fe56b9e6SYuval Mintz struct qede_dev *edev;
804fe56b9e6SYuval Mintz struct pci_dev *pdev;
805fc831825SYuval Mintz u32 flags;
806fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0))
807fe56b9e6SYuval Mintz int msg_enable;
808fe56b9e6SYuval Mintz
809fe56b9e6SYuval Mintz struct pci_params pci_params;
810fe56b9e6SYuval Mintz
811fe56b9e6SYuval Mintz struct qed_int_params int_params;
812fe56b9e6SYuval Mintz
813fe56b9e6SYuval Mintz u8 protocol;
814fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH)
8151e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE)
816fe56b9e6SYuval Mintz
817cc875c2eSYuval Mintz /* Callbacks to protocol driver */
818cc875c2eSYuval Mintz union {
819cc875c2eSYuval Mintz struct qed_common_cb_ops *common;
820cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth;
8211e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe;
822fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi;
823897e87a1SShai Malin struct qed_nvmetcp_cb_ops *nvmetcp;
824cc875c2eSYuval Mintz } protocol_ops;
825cc875c2eSYuval Mintz void *ops_cookie;
826cc875c2eSYuval Mintz
8270a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2
8280a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2;
8290a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN];
8300a7fb11cSYuval Mintz #endif
8312d22bc83SMichal Kalderon struct qed_dbg_feature dbg_features[DBG_FEATURE_NUM];
832ca352f00SIgor Russkikh u8 engine_for_debug;
8338a52bbabSMichal Kalderon bool disable_ilt_dump;
834da328711SAlexander Lobakin bool dbg_bin_dump;
835da328711SAlexander Lobakin
836fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10);
837fe56b9e6SYuval Mintz const struct firmware *firmware;
83851ff1725SRam Amrani
839ca352f00SIgor Russkikh bool print_dbg_data;
840ca352f00SIgor Russkikh
84151ff1725SRam Amrani u32 rdma_max_sge;
84251ff1725SRam Amrani u32 rdma_max_inline;
84351ff1725SRam Amrani u32 rdma_max_srq_sge;
844eaf3c0c6SChopra, Manish u16 tunn_feature_mask;
84524e04879SMichal Kalderon
84624e04879SMichal Kalderon bool iwarp_cmt;
847fe56b9e6SYuval Mintz };
848fe56b9e6SYuval Mintz
8491392d19fSMichal Kalderon u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type);
8501392d19fSMichal Kalderon
8511392d19fSMichal Kalderon #define NUM_OF_VFS(dev) \
8521392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VFS)
8531392d19fSMichal Kalderon #define NUM_OF_L2_QUEUES(dev) \
8541392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_L2_QUEUES)
8551392d19fSMichal Kalderon #define NUM_OF_PORTS(dev) \
8561392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PORTS)
8571392d19fSMichal Kalderon #define NUM_OF_SBS(dev) \
8581392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_SB_PER_PATH)
8591392d19fSMichal Kalderon #define NUM_OF_ENG_PFS(dev) \
8601392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_PFS)
8611392d19fSMichal Kalderon #define NUM_OF_VPORTS(dev) \
8621392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_NUM_VPORTS)
8631392d19fSMichal Kalderon #define NUM_OF_RSS_ENGINES(dev) \
8641392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_ETH_RSS_ENGINE)
8651392d19fSMichal Kalderon #define NUM_OF_QM_TX_QUEUES(dev) \
8661392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_TX_QUEUES)
8671392d19fSMichal Kalderon #define NUM_OF_PXP_ILT_RECORDS(dev) \
8681392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_PXP_ILT_RECORDS)
8691392d19fSMichal Kalderon #define NUM_OF_RDMA_STATISTIC_COUNTERS(dev) \
8701392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_NUM_RDMA_STATISTIC_COUNTERS)
8711392d19fSMichal Kalderon #define NUM_OF_QM_GLOBAL_RLS(dev) \
8721392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_QM_GLOBAL_RLS)
8731392d19fSMichal Kalderon #define NUM_OF_PBF_CMD_LINES(dev) \
8741392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_PBF_CMD_LINES)
8751392d19fSMichal Kalderon #define NUM_OF_BTB_BLOCKS(dev) \
8761392d19fSMichal Kalderon qed_get_hsi_def_val(dev, QED_HSI_DEF_MAX_BTB_BLOCKS)
8771392d19fSMichal Kalderon
878fe56b9e6SYuval Mintz /**
87919198e4eSPrabhakar Kushwaha * qed_concrete_to_sw_fid(): Get the sw function id from
880fe56b9e6SYuval Mintz * the concrete value.
881fe56b9e6SYuval Mintz *
88219198e4eSPrabhakar Kushwaha * @cdev: Qed dev pointer.
88319198e4eSPrabhakar Kushwaha * @concrete_fid: Concrete fid.
884fe56b9e6SYuval Mintz *
88519198e4eSPrabhakar Kushwaha * Return: inline u8.
886fe56b9e6SYuval Mintz */
qed_concrete_to_sw_fid(struct qed_dev * cdev,u32 concrete_fid)887fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev,
888fe56b9e6SYuval Mintz u32 concrete_fid)
889fe56b9e6SYuval Mintz {
8904870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID);
891fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID);
8924870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid,
8934870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID);
8944870e704SYuval Mintz u8 sw_fid;
895fe56b9e6SYuval Mintz
8964870e704SYuval Mintz if (vf_valid)
8974870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS;
8984870e704SYuval Mintz else
8994870e704SYuval Mintz sw_fid = pfid;
9004870e704SYuval Mintz
9014870e704SYuval Mintz return sw_fid;
902fe56b9e6SYuval Mintz }
903fe56b9e6SYuval Mintz
904526d1d05SKalderon, Michal #define PKT_LB_TC 9
905fe56b9e6SYuval Mintz
906733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate);
9076f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev,
9086f437d43SMintz, Yuval struct qed_ptt *p_ptt,
9096f437d43SMintz, Yuval u32 min_pf_rate);
910bcd197c8SManish Chopra
911733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt);
912456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb,
913456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac);
914fe56b9e6SYuval Mintz
915b90cb538SOmkar Kulkarni #define QED_LEADING_HWFN(dev) (&(dev)->hwfns[0])
91679284adeSMichal Kalderon #define QED_IS_CMT(dev) ((dev)->num_hwfns > 1)
91779284adeSMichal Kalderon /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */
91879284adeSMichal Kalderon #define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin])
91979284adeSMichal Kalderon #define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin])
92079284adeSMichal Kalderon #define QED_AFFIN_HWFN(dev) \
92179284adeSMichal Kalderon (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \
92279284adeSMichal Kalderon QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev))
92379284adeSMichal Kalderon #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1)
924b5a9ee7cSAriel Elior
925b5a9ee7cSAriel Elior /* Flags for indication of required queues */
926b5a9ee7cSAriel Elior #define PQ_FLAGS_RLS (BIT(0))
927b5a9ee7cSAriel Elior #define PQ_FLAGS_MCOS (BIT(1))
928b5a9ee7cSAriel Elior #define PQ_FLAGS_LB (BIT(2))
929b5a9ee7cSAriel Elior #define PQ_FLAGS_OOO (BIT(3))
930b5a9ee7cSAriel Elior #define PQ_FLAGS_ACK (BIT(4))
931b5a9ee7cSAriel Elior #define PQ_FLAGS_OFLD (BIT(5))
932b5a9ee7cSAriel Elior #define PQ_FLAGS_VFS (BIT(6))
933b5a9ee7cSAriel Elior #define PQ_FLAGS_LLT (BIT(7))
93461be82b0SDenis Bolotin #define PQ_FLAGS_MTC (BIT(8))
935b5a9ee7cSAriel Elior
936b90cb538SOmkar Kulkarni /* physical queue index for cm context initialization */
937b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags);
938b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc);
939b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf);
94061be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc);
94161be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc);
942b5a9ee7cSAriel Elior
943a1b469b8SAriel Elior /* doorbell recovery mechanism */
944a1b469b8SAriel Elior void qed_db_recovery_dp(struct qed_hwfn *p_hwfn);
9459ac6bb14SDenis Bolotin void qed_db_recovery_execute(struct qed_hwfn *p_hwfn);
946a1b469b8SAriel Elior bool qed_edpm_enabled(struct qed_hwfn *p_hwfn);
947a1b469b8SAriel Elior
948e2dbc223SPrabhakar Kushwaha #define GET_GTT_REG_ADDR(__base, __offset, __idx) \
949e2dbc223SPrabhakar Kushwaha ((__base) + __offset ## _GTT_OFFSET((__idx)))
950e2dbc223SPrabhakar Kushwaha
951e2dbc223SPrabhakar Kushwaha #define GET_GTT_BDQ_REG_ADDR(__base, __offset, __idx, __bdq_idx) \
952e2dbc223SPrabhakar Kushwaha ((__base) + __offset ## _GTT_OFFSET((__idx), (__bdq_idx)))
953e2dbc223SPrabhakar Kushwaha
954fe56b9e6SYuval Mintz /* Other Linux specific common definitions */
955fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name)
956fe56b9e6SYuval Mintz
957b90cb538SOmkar Kulkarni #define REG_ADDR(cdev, offset) ((void __iomem *)((u8 __iomem *)\
958b90cb538SOmkar Kulkarni ((cdev)->regview) + \
959b90cb538SOmkar Kulkarni (offset)))
960fe56b9e6SYuval Mintz
961fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset))
962fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset))
963fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset))
964fe56b9e6SYuval Mintz
965fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \
966fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\
967b90cb538SOmkar Kulkarni ((cdev)->doorbells) + (db_addr)))
968fe56b9e6SYuval Mintz
9690ebcebbeSSudarsana Reddy Kalluru #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
9700ebcebbeSSudarsana Reddy Kalluru qed_device_num_ports((_p_hwfn)->cdev))
9710ebcebbeSSudarsana Reddy Kalluru int qed_device_num_ports(struct qed_dev *cdev);
9720ebcebbeSSudarsana Reddy Kalluru
973fe56b9e6SYuval Mintz /* Prototypes */
974fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev,
975fe56b9e6SYuval Mintz struct qed_dev_info *dev_info);
976706d0891SRahul Verma void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
977699fed4aSSudarsana Reddy Kalluru void qed_bw_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt);
978fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn,
979fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf,
980fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf);
981b228cb16SIgor Russkikh int qed_recovery_process(struct qed_dev *cdev);
98264515dc8STomer Tayar void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn);
983d639836aSIgor Russkikh void qed_hw_error_occurred(struct qed_hwfn *p_hwfn,
984d639836aSIgor Russkikh enum qed_hw_err_type err_type);
9856c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev,
9866c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type,
9876c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats);
9888f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn);
9891226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn);
99059ccf86fSSudarsana Reddy Kalluru int qed_mfw_tlv_req(struct qed_hwfn *hwfn);
9918f16bc97SSudarsana Kalluru
9922528c389SSudarsana Reddy Kalluru int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn,
9932528c389SSudarsana Reddy Kalluru enum qed_mfw_tlv_type type,
9942528c389SSudarsana Reddy Kalluru union qed_mfw_tlv_data *tlv_data);
995c4259ddaSDenis Bolotin
996c4259ddaSDenis Bolotin void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc);
997a1b469b8SAriel Elior
998a1b469b8SAriel Elior void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn);
999203d136eSPrabhakar Kushwaha
1000203d136eSPrabhakar Kushwaha int qed_llh_add_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1001203d136eSPrabhakar Kushwaha int qed_llh_add_dst_tcp_port_filter(struct qed_dev *cdev, u16 dest_port);
1002203d136eSPrabhakar Kushwaha void qed_llh_remove_src_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1003203d136eSPrabhakar Kushwaha void qed_llh_remove_dst_tcp_port_filter(struct qed_dev *cdev, u16 src_port);
1004203d136eSPrabhakar Kushwaha void qed_llh_clear_all_filters(struct qed_dev *cdev);
1005*6c95dd8fSPrabhakar Kushwaha unsigned long qed_get_epoch_time(void);
1006fe56b9e6SYuval Mintz #endif /* _QED_H */
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