1 /* 2 * Copyright (C) 2003 - 2009 NetXen, Inc. 3 * Copyright (C) 2009 - QLogic Corporation. 4 * All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, 19 * MA 02111-1307, USA. 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called "COPYING". 23 * 24 */ 25 26 #ifndef _NETXEN_NIC_H_ 27 #define _NETXEN_NIC_H_ 28 29 #include <linux/module.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/ioport.h> 33 #include <linux/pci.h> 34 #include <linux/netdevice.h> 35 #include <linux/etherdevice.h> 36 #include <linux/ip.h> 37 #include <linux/in.h> 38 #include <linux/tcp.h> 39 #include <linux/skbuff.h> 40 #include <linux/firmware.h> 41 42 #include <linux/ethtool.h> 43 #include <linux/mii.h> 44 #include <linux/timer.h> 45 46 #include <linux/vmalloc.h> 47 48 #include <asm/io.h> 49 #include <asm/byteorder.h> 50 51 #include "netxen_nic_hdr.h" 52 #include "netxen_nic_hw.h" 53 54 #define _NETXEN_NIC_LINUX_MAJOR 4 55 #define _NETXEN_NIC_LINUX_MINOR 0 56 #define _NETXEN_NIC_LINUX_SUBVERSION 78 57 #define NETXEN_NIC_LINUX_VERSIONID "4.0.78" 58 59 #define NETXEN_VERSION_CODE(a, b, c) (((a) << 24) + ((b) << 16) + (c)) 60 #define _major(v) (((v) >> 24) & 0xff) 61 #define _minor(v) (((v) >> 16) & 0xff) 62 #define _build(v) ((v) & 0xffff) 63 64 /* version in image has weird encoding: 65 * 7:0 - major 66 * 15:8 - minor 67 * 31:16 - build (little endian) 68 */ 69 #define NETXEN_DECODE_VERSION(v) \ 70 NETXEN_VERSION_CODE(((v) & 0xff), (((v) >> 8) & 0xff), ((v) >> 16)) 71 72 #define NETXEN_NUM_FLASH_SECTORS (64) 73 #define NETXEN_FLASH_SECTOR_SIZE (64 * 1024) 74 #define NETXEN_FLASH_TOTAL_SIZE (NETXEN_NUM_FLASH_SECTORS \ 75 * NETXEN_FLASH_SECTOR_SIZE) 76 77 #define RCV_DESC_RINGSIZE(rds_ring) \ 78 (sizeof(struct rcv_desc) * (rds_ring)->num_desc) 79 #define RCV_BUFF_RINGSIZE(rds_ring) \ 80 (sizeof(struct netxen_rx_buffer) * rds_ring->num_desc) 81 #define STATUS_DESC_RINGSIZE(sds_ring) \ 82 (sizeof(struct status_desc) * (sds_ring)->num_desc) 83 #define TX_BUFF_RINGSIZE(tx_ring) \ 84 (sizeof(struct netxen_cmd_buffer) * tx_ring->num_desc) 85 #define TX_DESC_RINGSIZE(tx_ring) \ 86 (sizeof(struct cmd_desc_type0) * tx_ring->num_desc) 87 88 #define find_diff_among(a,b,range) ((a)<(b)?((b)-(a)):((b)+(range)-(a))) 89 90 #define NETXEN_RCV_PRODUCER_OFFSET 0 91 #define NETXEN_RCV_PEG_DB_ID 2 92 #define NETXEN_HOST_DUMMY_DMA_SIZE 1024 93 #define FLASH_SUCCESS 0 94 95 #define ADDR_IN_WINDOW1(off) \ 96 ((off > NETXEN_CRB_PCIX_HOST2) && (off < NETXEN_CRB_MAX)) ? 1 : 0 97 98 #define ADDR_IN_RANGE(addr, low, high) \ 99 (((addr) < (high)) && ((addr) >= (low))) 100 101 /* 102 * normalize a 64MB crb address to 32MB PCI window 103 * To use NETXEN_CRB_NORMALIZE, window _must_ be set to 1 104 */ 105 #define NETXEN_CRB_NORMAL(reg) \ 106 ((reg) - NETXEN_CRB_PCIX_HOST2 + NETXEN_CRB_PCIX_HOST) 107 108 #define NETXEN_CRB_NORMALIZE(adapter, reg) \ 109 pci_base_offset(adapter, NETXEN_CRB_NORMAL(reg)) 110 111 #define DB_NORMALIZE(adapter, off) \ 112 (adapter->ahw.db_base + (off)) 113 114 #define NX_P2_C0 0x24 115 #define NX_P2_C1 0x25 116 #define NX_P3_A0 0x30 117 #define NX_P3_A2 0x30 118 #define NX_P3_B0 0x40 119 #define NX_P3_B1 0x41 120 #define NX_P3_B2 0x42 121 #define NX_P3P_A0 0x50 122 123 #define NX_IS_REVISION_P2(REVISION) (REVISION <= NX_P2_C1) 124 #define NX_IS_REVISION_P3(REVISION) (REVISION >= NX_P3_A0) 125 #define NX_IS_REVISION_P3P(REVISION) (REVISION >= NX_P3P_A0) 126 127 #define FIRST_PAGE_GROUP_START 0 128 #define FIRST_PAGE_GROUP_END 0x100000 129 130 #define SECOND_PAGE_GROUP_START 0x6000000 131 #define SECOND_PAGE_GROUP_END 0x68BC000 132 133 #define THIRD_PAGE_GROUP_START 0x70E4000 134 #define THIRD_PAGE_GROUP_END 0x8000000 135 136 #define FIRST_PAGE_GROUP_SIZE FIRST_PAGE_GROUP_END - FIRST_PAGE_GROUP_START 137 #define SECOND_PAGE_GROUP_SIZE SECOND_PAGE_GROUP_END - SECOND_PAGE_GROUP_START 138 #define THIRD_PAGE_GROUP_SIZE THIRD_PAGE_GROUP_END - THIRD_PAGE_GROUP_START 139 140 #define P2_MAX_MTU (8000) 141 #define P3_MAX_MTU (9600) 142 #define NX_ETHERMTU 1500 143 #define NX_MAX_ETHERHDR 32 /* This contains some padding */ 144 145 #define NX_P2_RX_BUF_MAX_LEN 1760 146 #define NX_P3_RX_BUF_MAX_LEN (NX_MAX_ETHERHDR + NX_ETHERMTU) 147 #define NX_P2_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P2_MAX_MTU) 148 #define NX_P3_RX_JUMBO_BUF_MAX_LEN (NX_MAX_ETHERHDR + P3_MAX_MTU) 149 #define NX_CT_DEFAULT_RX_BUF_LEN 2048 150 #define NX_LRO_BUFFER_EXTRA 2048 151 152 #define NX_RX_LRO_BUFFER_LENGTH (8060) 153 154 /* 155 * Maximum number of ring contexts 156 */ 157 #define MAX_RING_CTX 1 158 159 /* Opcodes to be used with the commands */ 160 #define TX_ETHER_PKT 0x01 161 #define TX_TCP_PKT 0x02 162 #define TX_UDP_PKT 0x03 163 #define TX_IP_PKT 0x04 164 #define TX_TCP_LSO 0x05 165 #define TX_TCP_LSO6 0x06 166 #define TX_IPSEC 0x07 167 #define TX_IPSEC_CMD 0x0a 168 #define TX_TCPV6_PKT 0x0b 169 #define TX_UDPV6_PKT 0x0c 170 171 /* The following opcodes are for internal consumption. */ 172 #define NETXEN_CONTROL_OP 0x10 173 #define PEGNET_REQUEST 0x11 174 175 #define MAX_NUM_CARDS 4 176 177 #define NETXEN_MAX_FRAGS_PER_TX 14 178 #define MAX_TSO_HEADER_DESC 2 179 #define MGMT_CMD_DESC_RESV 4 180 #define TX_STOP_THRESH ((MAX_SKB_FRAGS >> 2) + MAX_TSO_HEADER_DESC \ 181 + MGMT_CMD_DESC_RESV) 182 #define NX_MAX_TX_TIMEOUTS 2 183 184 /* 185 * Following are the states of the Phantom. Phantom will set them and 186 * Host will read to check if the fields are correct. 187 */ 188 #define PHAN_INITIALIZE_START 0xff00 189 #define PHAN_INITIALIZE_FAILED 0xffff 190 #define PHAN_INITIALIZE_COMPLETE 0xff01 191 192 /* Host writes the following to notify that it has done the init-handshake */ 193 #define PHAN_INITIALIZE_ACK 0xf00f 194 195 #define NUM_RCV_DESC_RINGS 3 196 #define NUM_STS_DESC_RINGS 4 197 198 #define RCV_RING_NORMAL 0 199 #define RCV_RING_JUMBO 1 200 #define RCV_RING_LRO 2 201 202 #define MIN_CMD_DESCRIPTORS 64 203 #define MIN_RCV_DESCRIPTORS 64 204 #define MIN_JUMBO_DESCRIPTORS 32 205 206 #define MAX_CMD_DESCRIPTORS 1024 207 #define MAX_RCV_DESCRIPTORS_1G 4096 208 #define MAX_RCV_DESCRIPTORS_10G 8192 209 #define MAX_JUMBO_RCV_DESCRIPTORS_1G 512 210 #define MAX_JUMBO_RCV_DESCRIPTORS_10G 1024 211 #define MAX_LRO_RCV_DESCRIPTORS 8 212 213 #define DEFAULT_RCV_DESCRIPTORS_1G 2048 214 #define DEFAULT_RCV_DESCRIPTORS_10G 4096 215 216 #define NETXEN_CTX_SIGNATURE 0xdee0 217 #define NETXEN_CTX_SIGNATURE_V2 0x0002dee0 218 #define NETXEN_CTX_RESET 0xbad0 219 #define NETXEN_CTX_D3_RESET 0xacc0 220 #define NETXEN_RCV_PRODUCER(ringid) (ringid) 221 222 #define PHAN_PEG_RCV_INITIALIZED 0xff01 223 #define PHAN_PEG_RCV_START_INITIALIZE 0xff00 224 225 #define get_next_index(index, length) \ 226 (((index) + 1) & ((length) - 1)) 227 228 #define get_index_range(index,length,count) \ 229 (((index) + (count)) & ((length) - 1)) 230 231 #define MPORT_SINGLE_FUNCTION_MODE 0x1111 232 #define MPORT_MULTI_FUNCTION_MODE 0x2222 233 234 #define NX_MAX_PCI_FUNC 8 235 236 /* 237 * NetXen host-peg signal message structure 238 * 239 * Bit 0-1 : peg_id => 0x2 for tx and 01 for rx 240 * Bit 2 : priv_id => must be 1 241 * Bit 3-17 : count => for doorbell 242 * Bit 18-27 : ctx_id => Context id 243 * Bit 28-31 : opcode 244 */ 245 246 typedef u32 netxen_ctx_msg; 247 248 #define netxen_set_msg_peg_id(config_word, val) \ 249 ((config_word) &= ~3, (config_word) |= val & 3) 250 #define netxen_set_msg_privid(config_word) \ 251 ((config_word) |= 1 << 2) 252 #define netxen_set_msg_count(config_word, val) \ 253 ((config_word) &= ~(0x7fff<<3), (config_word) |= (val & 0x7fff) << 3) 254 #define netxen_set_msg_ctxid(config_word, val) \ 255 ((config_word) &= ~(0x3ff<<18), (config_word) |= (val & 0x3ff) << 18) 256 #define netxen_set_msg_opcode(config_word, val) \ 257 ((config_word) &= ~(0xf<<28), (config_word) |= (val & 0xf) << 28) 258 259 struct netxen_rcv_ring { 260 __le64 addr; 261 __le32 size; 262 __le32 rsrvd; 263 }; 264 265 struct netxen_sts_ring { 266 __le64 addr; 267 __le32 size; 268 __le16 msi_index; 269 __le16 rsvd; 270 } ; 271 272 struct netxen_ring_ctx { 273 274 /* one command ring */ 275 __le64 cmd_consumer_offset; 276 __le64 cmd_ring_addr; 277 __le32 cmd_ring_size; 278 __le32 rsrvd; 279 280 /* three receive rings */ 281 struct netxen_rcv_ring rcv_rings[NUM_RCV_DESC_RINGS]; 282 283 __le64 sts_ring_addr; 284 __le32 sts_ring_size; 285 286 __le32 ctx_id; 287 288 __le64 rsrvd_2[3]; 289 __le32 sts_ring_count; 290 __le32 rsrvd_3; 291 struct netxen_sts_ring sts_rings[NUM_STS_DESC_RINGS]; 292 293 } __attribute__ ((aligned(64))); 294 295 /* 296 * Following data structures describe the descriptors that will be used. 297 * Added fileds of tcpHdrSize and ipHdrSize, The driver needs to do it only when 298 * we are doing LSO (above the 1500 size packet) only. 299 */ 300 301 /* 302 * The size of reference handle been changed to 16 bits to pass the MSS fields 303 * for the LSO packet 304 */ 305 306 #define FLAGS_CHECKSUM_ENABLED 0x01 307 #define FLAGS_LSO_ENABLED 0x02 308 #define FLAGS_IPSEC_SA_ADD 0x04 309 #define FLAGS_IPSEC_SA_DELETE 0x08 310 #define FLAGS_VLAN_TAGGED 0x10 311 #define FLAGS_VLAN_OOB 0x40 312 313 #define netxen_set_tx_vlan_tci(cmd_desc, v) \ 314 (cmd_desc)->vlan_TCI = cpu_to_le16(v); 315 316 #define netxen_set_cmd_desc_port(cmd_desc, var) \ 317 ((cmd_desc)->port_ctxid |= ((var) & 0x0F)) 318 #define netxen_set_cmd_desc_ctxid(cmd_desc, var) \ 319 ((cmd_desc)->port_ctxid |= ((var) << 4 & 0xF0)) 320 321 #define netxen_set_tx_port(_desc, _port) \ 322 (_desc)->port_ctxid = ((_port) & 0xf) | (((_port) << 4) & 0xf0) 323 324 #define netxen_set_tx_flags_opcode(_desc, _flags, _opcode) \ 325 (_desc)->flags_opcode = \ 326 cpu_to_le16(((_flags) & 0x7f) | (((_opcode) & 0x3f) << 7)) 327 328 #define netxen_set_tx_frags_len(_desc, _frags, _len) \ 329 (_desc)->nfrags__length = \ 330 cpu_to_le32(((_frags) & 0xff) | (((_len) & 0xffffff) << 8)) 331 332 struct cmd_desc_type0 { 333 u8 tcp_hdr_offset; /* For LSO only */ 334 u8 ip_hdr_offset; /* For LSO only */ 335 __le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */ 336 __le32 nfrags__length; /* 31:8 total len, 7:0 frag count */ 337 338 __le64 addr_buffer2; 339 340 __le16 reference_handle; 341 __le16 mss; 342 u8 port_ctxid; /* 7:4 ctxid 3:0 port */ 343 u8 total_hdr_length; /* LSO only : MAC+IP+TCP Hdr size */ 344 __le16 conn_id; /* IPSec offoad only */ 345 346 __le64 addr_buffer3; 347 __le64 addr_buffer1; 348 349 __le16 buffer_length[4]; 350 351 __le64 addr_buffer4; 352 353 __le32 reserved2; 354 __le16 reserved; 355 __le16 vlan_TCI; 356 357 } __attribute__ ((aligned(64))); 358 359 /* Note: sizeof(rcv_desc) should always be a mutliple of 2 */ 360 struct rcv_desc { 361 __le16 reference_handle; 362 __le16 reserved; 363 __le32 buffer_length; /* allocated buffer length (usually 2K) */ 364 __le64 addr_buffer; 365 }; 366 367 /* opcode field in status_desc */ 368 #define NETXEN_NIC_SYN_OFFLOAD 0x03 369 #define NETXEN_NIC_RXPKT_DESC 0x04 370 #define NETXEN_OLD_RXPKT_DESC 0x3f 371 #define NETXEN_NIC_RESPONSE_DESC 0x05 372 #define NETXEN_NIC_LRO_DESC 0x12 373 374 /* for status field in status_desc */ 375 #define STATUS_NEED_CKSUM (1) 376 #define STATUS_CKSUM_OK (2) 377 378 /* owner bits of status_desc */ 379 #define STATUS_OWNER_HOST (0x1ULL << 56) 380 #define STATUS_OWNER_PHANTOM (0x2ULL << 56) 381 382 /* Status descriptor: 383 0-3 port, 4-7 status, 8-11 type, 12-27 total_length 384 28-43 reference_handle, 44-47 protocol, 48-52 pkt_offset 385 53-55 desc_cnt, 56-57 owner, 58-63 opcode 386 */ 387 #define netxen_get_sts_port(sts_data) \ 388 ((sts_data) & 0x0F) 389 #define netxen_get_sts_status(sts_data) \ 390 (((sts_data) >> 4) & 0x0F) 391 #define netxen_get_sts_type(sts_data) \ 392 (((sts_data) >> 8) & 0x0F) 393 #define netxen_get_sts_totallength(sts_data) \ 394 (((sts_data) >> 12) & 0xFFFF) 395 #define netxen_get_sts_refhandle(sts_data) \ 396 (((sts_data) >> 28) & 0xFFFF) 397 #define netxen_get_sts_prot(sts_data) \ 398 (((sts_data) >> 44) & 0x0F) 399 #define netxen_get_sts_pkt_offset(sts_data) \ 400 (((sts_data) >> 48) & 0x1F) 401 #define netxen_get_sts_desc_cnt(sts_data) \ 402 (((sts_data) >> 53) & 0x7) 403 #define netxen_get_sts_opcode(sts_data) \ 404 (((sts_data) >> 58) & 0x03F) 405 406 #define netxen_get_lro_sts_refhandle(sts_data) \ 407 ((sts_data) & 0x0FFFF) 408 #define netxen_get_lro_sts_length(sts_data) \ 409 (((sts_data) >> 16) & 0x0FFFF) 410 #define netxen_get_lro_sts_l2_hdr_offset(sts_data) \ 411 (((sts_data) >> 32) & 0x0FF) 412 #define netxen_get_lro_sts_l4_hdr_offset(sts_data) \ 413 (((sts_data) >> 40) & 0x0FF) 414 #define netxen_get_lro_sts_timestamp(sts_data) \ 415 (((sts_data) >> 48) & 0x1) 416 #define netxen_get_lro_sts_type(sts_data) \ 417 (((sts_data) >> 49) & 0x7) 418 #define netxen_get_lro_sts_push_flag(sts_data) \ 419 (((sts_data) >> 52) & 0x1) 420 #define netxen_get_lro_sts_seq_number(sts_data) \ 421 ((sts_data) & 0x0FFFFFFFF) 422 423 424 struct status_desc { 425 __le64 status_desc_data[2]; 426 } __attribute__ ((aligned(16))); 427 428 /* UNIFIED ROMIMAGE *************************/ 429 #define NX_UNI_DIR_SECT_PRODUCT_TBL 0x0 430 #define NX_UNI_DIR_SECT_BOOTLD 0x6 431 #define NX_UNI_DIR_SECT_FW 0x7 432 433 /*Offsets */ 434 #define NX_UNI_CHIP_REV_OFF 10 435 #define NX_UNI_FLAGS_OFF 11 436 #define NX_UNI_BIOS_VERSION_OFF 12 437 #define NX_UNI_BOOTLD_IDX_OFF 27 438 #define NX_UNI_FIRMWARE_IDX_OFF 29 439 440 struct uni_table_desc{ 441 uint32_t findex; 442 uint32_t num_entries; 443 uint32_t entry_size; 444 uint32_t reserved[5]; 445 }; 446 447 struct uni_data_desc{ 448 uint32_t findex; 449 uint32_t size; 450 uint32_t reserved[5]; 451 }; 452 453 /* UNIFIED ROMIMAGE *************************/ 454 455 /* The version of the main data structure */ 456 #define NETXEN_BDINFO_VERSION 1 457 458 /* Magic number to let user know flash is programmed */ 459 #define NETXEN_BDINFO_MAGIC 0x12345678 460 461 /* Max number of Gig ports on a Phantom board */ 462 #define NETXEN_MAX_PORTS 4 463 464 #define NETXEN_BRDTYPE_P1_BD 0x0000 465 #define NETXEN_BRDTYPE_P1_SB 0x0001 466 #define NETXEN_BRDTYPE_P1_SMAX 0x0002 467 #define NETXEN_BRDTYPE_P1_SOCK 0x0003 468 469 #define NETXEN_BRDTYPE_P2_SOCK_31 0x0008 470 #define NETXEN_BRDTYPE_P2_SOCK_35 0x0009 471 #define NETXEN_BRDTYPE_P2_SB35_4G 0x000a 472 #define NETXEN_BRDTYPE_P2_SB31_10G 0x000b 473 #define NETXEN_BRDTYPE_P2_SB31_2G 0x000c 474 475 #define NETXEN_BRDTYPE_P2_SB31_10G_IMEZ 0x000d 476 #define NETXEN_BRDTYPE_P2_SB31_10G_HMEZ 0x000e 477 #define NETXEN_BRDTYPE_P2_SB31_10G_CX4 0x000f 478 479 #define NETXEN_BRDTYPE_P3_REF_QG 0x0021 480 #define NETXEN_BRDTYPE_P3_HMEZ 0x0022 481 #define NETXEN_BRDTYPE_P3_10G_CX4_LP 0x0023 482 #define NETXEN_BRDTYPE_P3_4_GB 0x0024 483 #define NETXEN_BRDTYPE_P3_IMEZ 0x0025 484 #define NETXEN_BRDTYPE_P3_10G_SFP_PLUS 0x0026 485 #define NETXEN_BRDTYPE_P3_10000_BASE_T 0x0027 486 #define NETXEN_BRDTYPE_P3_XG_LOM 0x0028 487 #define NETXEN_BRDTYPE_P3_4_GB_MM 0x0029 488 #define NETXEN_BRDTYPE_P3_10G_SFP_CT 0x002a 489 #define NETXEN_BRDTYPE_P3_10G_SFP_QT 0x002b 490 #define NETXEN_BRDTYPE_P3_10G_CX4 0x0031 491 #define NETXEN_BRDTYPE_P3_10G_XFP 0x0032 492 #define NETXEN_BRDTYPE_P3_10G_TP 0x0080 493 494 /* Flash memory map */ 495 #define NETXEN_CRBINIT_START 0 /* crbinit section */ 496 #define NETXEN_BRDCFG_START 0x4000 /* board config */ 497 #define NETXEN_INITCODE_START 0x6000 /* pegtune code */ 498 #define NETXEN_BOOTLD_START 0x10000 /* bootld */ 499 #define NETXEN_IMAGE_START 0x43000 /* compressed image */ 500 #define NETXEN_SECONDARY_START 0x200000 /* backup images */ 501 #define NETXEN_PXE_START 0x3E0000 /* PXE boot rom */ 502 #define NETXEN_USER_START 0x3E8000 /* Firmare info */ 503 #define NETXEN_FIXED_START 0x3F0000 /* backup of crbinit */ 504 #define NETXEN_USER_START_OLD NETXEN_PXE_START /* very old flash */ 505 506 #define NX_OLD_MAC_ADDR_OFFSET (NETXEN_USER_START) 507 #define NX_FW_VERSION_OFFSET (NETXEN_USER_START+0x408) 508 #define NX_FW_SIZE_OFFSET (NETXEN_USER_START+0x40c) 509 #define NX_FW_MAC_ADDR_OFFSET (NETXEN_USER_START+0x418) 510 #define NX_FW_SERIAL_NUM_OFFSET (NETXEN_USER_START+0x81c) 511 #define NX_BIOS_VERSION_OFFSET (NETXEN_USER_START+0x83c) 512 513 #define NX_HDR_VERSION_OFFSET (NETXEN_BRDCFG_START) 514 #define NX_BRDTYPE_OFFSET (NETXEN_BRDCFG_START+0x8) 515 #define NX_FW_MAGIC_OFFSET (NETXEN_BRDCFG_START+0x128) 516 517 #define NX_FW_MIN_SIZE (0x3fffff) 518 #define NX_P2_MN_ROMIMAGE 0 519 #define NX_P3_CT_ROMIMAGE 1 520 #define NX_P3_MN_ROMIMAGE 2 521 #define NX_UNIFIED_ROMIMAGE 3 522 #define NX_FLASH_ROMIMAGE 4 523 #define NX_UNKNOWN_ROMIMAGE 0xff 524 525 #define NX_P2_MN_ROMIMAGE_NAME "nxromimg.bin" 526 #define NX_P3_CT_ROMIMAGE_NAME "nx3fwct.bin" 527 #define NX_P3_MN_ROMIMAGE_NAME "nx3fwmn.bin" 528 #define NX_UNIFIED_ROMIMAGE_NAME "phanfw.bin" 529 #define NX_FLASH_ROMIMAGE_NAME "flash" 530 531 extern char netxen_nic_driver_name[]; 532 533 /* Number of status descriptors to handle per interrupt */ 534 #define MAX_STATUS_HANDLE (64) 535 536 /* 537 * netxen_skb_frag{} is to contain mapping info for each SG list. This 538 * has to be freed when DMA is complete. This is part of netxen_tx_buffer{}. 539 */ 540 struct netxen_skb_frag { 541 u64 dma; 542 u64 length; 543 }; 544 545 struct netxen_recv_crb { 546 u32 crb_rcv_producer[NUM_RCV_DESC_RINGS]; 547 u32 crb_sts_consumer[NUM_STS_DESC_RINGS]; 548 u32 sw_int_mask[NUM_STS_DESC_RINGS]; 549 }; 550 551 /* Following defines are for the state of the buffers */ 552 #define NETXEN_BUFFER_FREE 0 553 #define NETXEN_BUFFER_BUSY 1 554 555 /* 556 * There will be one netxen_buffer per skb packet. These will be 557 * used to save the dma info for pci_unmap_page() 558 */ 559 struct netxen_cmd_buffer { 560 struct sk_buff *skb; 561 struct netxen_skb_frag frag_array[MAX_SKB_FRAGS + 1]; 562 u32 frag_count; 563 }; 564 565 /* In rx_buffer, we do not need multiple fragments as is a single buffer */ 566 struct netxen_rx_buffer { 567 struct list_head list; 568 struct sk_buff *skb; 569 u64 dma; 570 u16 ref_handle; 571 u16 state; 572 }; 573 574 /* Board types */ 575 #define NETXEN_NIC_GBE 0x01 576 #define NETXEN_NIC_XGBE 0x02 577 578 /* 579 * One hardware_context{} per adapter 580 * contains interrupt info as well shared hardware info. 581 */ 582 struct netxen_hardware_context { 583 void __iomem *pci_base0; 584 void __iomem *pci_base1; 585 void __iomem *pci_base2; 586 void __iomem *db_base; 587 void __iomem *ocm_win_crb; 588 589 unsigned long db_len; 590 unsigned long pci_len0; 591 592 u32 ocm_win; 593 u32 crb_win; 594 595 rwlock_t crb_lock; 596 spinlock_t mem_lock; 597 598 u8 cut_through; 599 u8 revision_id; 600 u8 pci_func; 601 u8 linkup; 602 u16 port_type; 603 u16 board_type; 604 }; 605 606 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 607 #define ETHERNET_FCS_SIZE 4 608 609 struct netxen_adapter_stats { 610 u64 xmitcalled; 611 u64 xmitfinished; 612 u64 rxdropped; 613 u64 txdropped; 614 u64 csummed; 615 u64 rx_pkts; 616 u64 lro_pkts; 617 u64 rxbytes; 618 u64 txbytes; 619 }; 620 621 /* 622 * Rcv Descriptor Context. One such per Rcv Descriptor. There may 623 * be one Rcv Descriptor for normal packets, one for jumbo and may be others. 624 */ 625 struct nx_host_rds_ring { 626 u32 producer; 627 u32 num_desc; 628 u32 dma_size; 629 u32 skb_size; 630 u32 flags; 631 void __iomem *crb_rcv_producer; 632 struct rcv_desc *desc_head; 633 struct netxen_rx_buffer *rx_buf_arr; 634 struct list_head free_list; 635 spinlock_t lock; 636 dma_addr_t phys_addr; 637 }; 638 639 struct nx_host_sds_ring { 640 u32 consumer; 641 u32 num_desc; 642 void __iomem *crb_sts_consumer; 643 void __iomem *crb_intr_mask; 644 645 struct status_desc *desc_head; 646 struct netxen_adapter *adapter; 647 struct napi_struct napi; 648 struct list_head free_list[NUM_RCV_DESC_RINGS]; 649 650 int irq; 651 652 dma_addr_t phys_addr; 653 char name[IFNAMSIZ+4]; 654 }; 655 656 struct nx_host_tx_ring { 657 u32 producer; 658 __le32 *hw_consumer; 659 u32 sw_consumer; 660 void __iomem *crb_cmd_producer; 661 void __iomem *crb_cmd_consumer; 662 u32 num_desc; 663 664 struct netdev_queue *txq; 665 666 struct netxen_cmd_buffer *cmd_buf_arr; 667 struct cmd_desc_type0 *desc_head; 668 dma_addr_t phys_addr; 669 }; 670 671 /* 672 * Receive context. There is one such structure per instance of the 673 * receive processing. Any state information that is relevant to 674 * the receive, and is must be in this structure. The global data may be 675 * present elsewhere. 676 */ 677 struct netxen_recv_context { 678 u32 state; 679 u16 context_id; 680 u16 virt_port; 681 682 struct nx_host_rds_ring *rds_rings; 683 struct nx_host_sds_ring *sds_rings; 684 685 struct netxen_ring_ctx *hwctx; 686 dma_addr_t phys_addr; 687 }; 688 689 struct _cdrp_cmd { 690 u32 cmd; 691 u32 arg1; 692 u32 arg2; 693 u32 arg3; 694 }; 695 696 struct netxen_cmd_args { 697 struct _cdrp_cmd req; 698 struct _cdrp_cmd rsp; 699 }; 700 701 /* New HW context creation */ 702 703 #define NX_OS_CRB_RETRY_COUNT 4000 704 #define NX_CDRP_SIGNATURE_MAKE(pcifn, version) \ 705 (((pcifn) & 0xff) | (((version) & 0xff) << 8) | (0xcafe << 16)) 706 707 #define NX_CDRP_CLEAR 0x00000000 708 #define NX_CDRP_CMD_BIT 0x80000000 709 710 /* 711 * All responses must have the NX_CDRP_CMD_BIT cleared 712 * in the crb NX_CDRP_CRB_OFFSET. 713 */ 714 #define NX_CDRP_FORM_RSP(rsp) (rsp) 715 #define NX_CDRP_IS_RSP(rsp) (((rsp) & NX_CDRP_CMD_BIT) == 0) 716 717 #define NX_CDRP_RSP_OK 0x00000001 718 #define NX_CDRP_RSP_FAIL 0x00000002 719 #define NX_CDRP_RSP_TIMEOUT 0x00000003 720 721 /* 722 * All commands must have the NX_CDRP_CMD_BIT set in 723 * the crb NX_CDRP_CRB_OFFSET. 724 */ 725 #define NX_CDRP_FORM_CMD(cmd) (NX_CDRP_CMD_BIT | (cmd)) 726 #define NX_CDRP_IS_CMD(cmd) (((cmd) & NX_CDRP_CMD_BIT) != 0) 727 728 #define NX_CDRP_CMD_SUBMIT_CAPABILITIES 0x00000001 729 #define NX_CDRP_CMD_READ_MAX_RDS_PER_CTX 0x00000002 730 #define NX_CDRP_CMD_READ_MAX_SDS_PER_CTX 0x00000003 731 #define NX_CDRP_CMD_READ_MAX_RULES_PER_CTX 0x00000004 732 #define NX_CDRP_CMD_READ_MAX_RX_CTX 0x00000005 733 #define NX_CDRP_CMD_READ_MAX_TX_CTX 0x00000006 734 #define NX_CDRP_CMD_CREATE_RX_CTX 0x00000007 735 #define NX_CDRP_CMD_DESTROY_RX_CTX 0x00000008 736 #define NX_CDRP_CMD_CREATE_TX_CTX 0x00000009 737 #define NX_CDRP_CMD_DESTROY_TX_CTX 0x0000000a 738 #define NX_CDRP_CMD_SETUP_STATISTICS 0x0000000e 739 #define NX_CDRP_CMD_GET_STATISTICS 0x0000000f 740 #define NX_CDRP_CMD_DELETE_STATISTICS 0x00000010 741 #define NX_CDRP_CMD_SET_MTU 0x00000012 742 #define NX_CDRP_CMD_READ_PHY 0x00000013 743 #define NX_CDRP_CMD_WRITE_PHY 0x00000014 744 #define NX_CDRP_CMD_READ_HW_REG 0x00000015 745 #define NX_CDRP_CMD_GET_FLOW_CTL 0x00000016 746 #define NX_CDRP_CMD_SET_FLOW_CTL 0x00000017 747 #define NX_CDRP_CMD_READ_MAX_MTU 0x00000018 748 #define NX_CDRP_CMD_READ_MAX_LRO 0x00000019 749 #define NX_CDRP_CMD_CONFIGURE_TOE 0x0000001a 750 #define NX_CDRP_CMD_FUNC_ATTRIB 0x0000001b 751 #define NX_CDRP_CMD_READ_PEXQ_PARAMETERS 0x0000001c 752 #define NX_CDRP_CMD_GET_LIC_CAPABILITIES 0x0000001d 753 #define NX_CDRP_CMD_READ_MAX_LRO_PER_BOARD 0x0000001e 754 #define NX_CDRP_CMD_CONFIG_GBE_PORT 0x0000001f 755 #define NX_CDRP_CMD_MAX 0x00000020 756 757 #define NX_RCODE_SUCCESS 0 758 #define NX_RCODE_NO_HOST_MEM 1 759 #define NX_RCODE_NO_HOST_RESOURCE 2 760 #define NX_RCODE_NO_CARD_CRB 3 761 #define NX_RCODE_NO_CARD_MEM 4 762 #define NX_RCODE_NO_CARD_RESOURCE 5 763 #define NX_RCODE_INVALID_ARGS 6 764 #define NX_RCODE_INVALID_ACTION 7 765 #define NX_RCODE_INVALID_STATE 8 766 #define NX_RCODE_NOT_SUPPORTED 9 767 #define NX_RCODE_NOT_PERMITTED 10 768 #define NX_RCODE_NOT_READY 11 769 #define NX_RCODE_DOES_NOT_EXIST 12 770 #define NX_RCODE_ALREADY_EXISTS 13 771 #define NX_RCODE_BAD_SIGNATURE 14 772 #define NX_RCODE_CMD_NOT_IMPL 15 773 #define NX_RCODE_CMD_INVALID 16 774 #define NX_RCODE_TIMEOUT 17 775 #define NX_RCODE_CMD_FAILED 18 776 #define NX_RCODE_MAX_EXCEEDED 19 777 #define NX_RCODE_MAX 20 778 779 #define NX_DESTROY_CTX_RESET 0 780 #define NX_DESTROY_CTX_D3_RESET 1 781 #define NX_DESTROY_CTX_MAX 2 782 783 /* 784 * Capabilities 785 */ 786 #define NX_CAP_BIT(class, bit) (1 << bit) 787 #define NX_CAP0_LEGACY_CONTEXT NX_CAP_BIT(0, 0) 788 #define NX_CAP0_MULTI_CONTEXT NX_CAP_BIT(0, 1) 789 #define NX_CAP0_LEGACY_MN NX_CAP_BIT(0, 2) 790 #define NX_CAP0_LEGACY_MS NX_CAP_BIT(0, 3) 791 #define NX_CAP0_CUT_THROUGH NX_CAP_BIT(0, 4) 792 #define NX_CAP0_LRO NX_CAP_BIT(0, 5) 793 #define NX_CAP0_LSO NX_CAP_BIT(0, 6) 794 #define NX_CAP0_JUMBO_CONTIGUOUS NX_CAP_BIT(0, 7) 795 #define NX_CAP0_LRO_CONTIGUOUS NX_CAP_BIT(0, 8) 796 #define NX_CAP0_HW_LRO NX_CAP_BIT(0, 10) 797 798 /* 799 * Context state 800 */ 801 #define NX_HOST_CTX_STATE_FREED 0 802 #define NX_HOST_CTX_STATE_ALLOCATED 1 803 #define NX_HOST_CTX_STATE_ACTIVE 2 804 #define NX_HOST_CTX_STATE_DISABLED 3 805 #define NX_HOST_CTX_STATE_QUIESCED 4 806 #define NX_HOST_CTX_STATE_MAX 5 807 808 /* 809 * Rx context 810 */ 811 812 typedef struct { 813 __le64 host_phys_addr; /* Ring base addr */ 814 __le32 ring_size; /* Ring entries */ 815 __le16 msi_index; 816 __le16 rsvd; /* Padding */ 817 } nx_hostrq_sds_ring_t; 818 819 typedef struct { 820 __le64 host_phys_addr; /* Ring base addr */ 821 __le64 buff_size; /* Packet buffer size */ 822 __le32 ring_size; /* Ring entries */ 823 __le32 ring_kind; /* Class of ring */ 824 } nx_hostrq_rds_ring_t; 825 826 typedef struct { 827 __le64 host_rsp_dma_addr; /* Response dma'd here */ 828 __le32 capabilities[4]; /* Flag bit vector */ 829 __le32 host_int_crb_mode; /* Interrupt crb usage */ 830 __le32 host_rds_crb_mode; /* RDS crb usage */ 831 /* These ring offsets are relative to data[0] below */ 832 __le32 rds_ring_offset; /* Offset to RDS config */ 833 __le32 sds_ring_offset; /* Offset to SDS config */ 834 __le16 num_rds_rings; /* Count of RDS rings */ 835 __le16 num_sds_rings; /* Count of SDS rings */ 836 __le16 rsvd1; /* Padding */ 837 __le16 rsvd2; /* Padding */ 838 u8 reserved[128]; /* reserve space for future expansion*/ 839 /* MUST BE 64-bit aligned. 840 The following is packed: 841 - N hostrq_rds_rings 842 - N hostrq_sds_rings */ 843 char data[0]; 844 } nx_hostrq_rx_ctx_t; 845 846 typedef struct { 847 __le32 host_producer_crb; /* Crb to use */ 848 __le32 rsvd1; /* Padding */ 849 } nx_cardrsp_rds_ring_t; 850 851 typedef struct { 852 __le32 host_consumer_crb; /* Crb to use */ 853 __le32 interrupt_crb; /* Crb to use */ 854 } nx_cardrsp_sds_ring_t; 855 856 typedef struct { 857 /* These ring offsets are relative to data[0] below */ 858 __le32 rds_ring_offset; /* Offset to RDS config */ 859 __le32 sds_ring_offset; /* Offset to SDS config */ 860 __le32 host_ctx_state; /* Starting State */ 861 __le32 num_fn_per_port; /* How many PCI fn share the port */ 862 __le16 num_rds_rings; /* Count of RDS rings */ 863 __le16 num_sds_rings; /* Count of SDS rings */ 864 __le16 context_id; /* Handle for context */ 865 u8 phys_port; /* Physical id of port */ 866 u8 virt_port; /* Virtual/Logical id of port */ 867 u8 reserved[128]; /* save space for future expansion */ 868 /* MUST BE 64-bit aligned. 869 The following is packed: 870 - N cardrsp_rds_rings 871 - N cardrs_sds_rings */ 872 char data[0]; 873 } nx_cardrsp_rx_ctx_t; 874 875 #define SIZEOF_HOSTRQ_RX(HOSTRQ_RX, rds_rings, sds_rings) \ 876 (sizeof(HOSTRQ_RX) + \ 877 (rds_rings)*(sizeof(nx_hostrq_rds_ring_t)) + \ 878 (sds_rings)*(sizeof(nx_hostrq_sds_ring_t))) 879 880 #define SIZEOF_CARDRSP_RX(CARDRSP_RX, rds_rings, sds_rings) \ 881 (sizeof(CARDRSP_RX) + \ 882 (rds_rings)*(sizeof(nx_cardrsp_rds_ring_t)) + \ 883 (sds_rings)*(sizeof(nx_cardrsp_sds_ring_t))) 884 885 /* 886 * Tx context 887 */ 888 889 typedef struct { 890 __le64 host_phys_addr; /* Ring base addr */ 891 __le32 ring_size; /* Ring entries */ 892 __le32 rsvd; /* Padding */ 893 } nx_hostrq_cds_ring_t; 894 895 typedef struct { 896 __le64 host_rsp_dma_addr; /* Response dma'd here */ 897 __le64 cmd_cons_dma_addr; /* */ 898 __le64 dummy_dma_addr; /* */ 899 __le32 capabilities[4]; /* Flag bit vector */ 900 __le32 host_int_crb_mode; /* Interrupt crb usage */ 901 __le32 rsvd1; /* Padding */ 902 __le16 rsvd2; /* Padding */ 903 __le16 interrupt_ctl; 904 __le16 msi_index; 905 __le16 rsvd3; /* Padding */ 906 nx_hostrq_cds_ring_t cds_ring; /* Desc of cds ring */ 907 u8 reserved[128]; /* future expansion */ 908 } nx_hostrq_tx_ctx_t; 909 910 typedef struct { 911 __le32 host_producer_crb; /* Crb to use */ 912 __le32 interrupt_crb; /* Crb to use */ 913 } nx_cardrsp_cds_ring_t; 914 915 typedef struct { 916 __le32 host_ctx_state; /* Starting state */ 917 __le16 context_id; /* Handle for context */ 918 u8 phys_port; /* Physical id of port */ 919 u8 virt_port; /* Virtual/Logical id of port */ 920 nx_cardrsp_cds_ring_t cds_ring; /* Card cds settings */ 921 u8 reserved[128]; /* future expansion */ 922 } nx_cardrsp_tx_ctx_t; 923 924 #define SIZEOF_HOSTRQ_TX(HOSTRQ_TX) (sizeof(HOSTRQ_TX)) 925 #define SIZEOF_CARDRSP_TX(CARDRSP_TX) (sizeof(CARDRSP_TX)) 926 927 /* CRB */ 928 929 #define NX_HOST_RDS_CRB_MODE_UNIQUE 0 930 #define NX_HOST_RDS_CRB_MODE_SHARED 1 931 #define NX_HOST_RDS_CRB_MODE_CUSTOM 2 932 #define NX_HOST_RDS_CRB_MODE_MAX 3 933 934 #define NX_HOST_INT_CRB_MODE_UNIQUE 0 935 #define NX_HOST_INT_CRB_MODE_SHARED 1 936 #define NX_HOST_INT_CRB_MODE_NORX 2 937 #define NX_HOST_INT_CRB_MODE_NOTX 3 938 #define NX_HOST_INT_CRB_MODE_NORXTX 4 939 940 941 /* MAC */ 942 943 #define MC_COUNT_P2 16 944 #define MC_COUNT_P3 38 945 946 #define NETXEN_MAC_NOOP 0 947 #define NETXEN_MAC_ADD 1 948 #define NETXEN_MAC_DEL 2 949 950 typedef struct nx_mac_list_s { 951 struct list_head list; 952 uint8_t mac_addr[ETH_ALEN+2]; 953 } nx_mac_list_t; 954 955 struct nx_vlan_ip_list { 956 struct list_head list; 957 __be32 ip_addr; 958 }; 959 960 /* 961 * Interrupt coalescing defaults. The defaults are for 1500 MTU. It is 962 * adjusted based on configured MTU. 963 */ 964 #define NETXEN_DEFAULT_INTR_COALESCE_RX_TIME_US 3 965 #define NETXEN_DEFAULT_INTR_COALESCE_RX_PACKETS 256 966 #define NETXEN_DEFAULT_INTR_COALESCE_TX_PACKETS 64 967 #define NETXEN_DEFAULT_INTR_COALESCE_TX_TIME_US 4 968 969 #define NETXEN_NIC_INTR_DEFAULT 0x04 970 971 typedef union { 972 struct { 973 uint16_t rx_packets; 974 uint16_t rx_time_us; 975 uint16_t tx_packets; 976 uint16_t tx_time_us; 977 } data; 978 uint64_t word; 979 } nx_nic_intr_coalesce_data_t; 980 981 typedef struct { 982 uint16_t stats_time_us; 983 uint16_t rate_sample_time; 984 uint16_t flags; 985 uint16_t rsvd_1; 986 uint32_t low_threshold; 987 uint32_t high_threshold; 988 nx_nic_intr_coalesce_data_t normal; 989 nx_nic_intr_coalesce_data_t low; 990 nx_nic_intr_coalesce_data_t high; 991 nx_nic_intr_coalesce_data_t irq; 992 } nx_nic_intr_coalesce_t; 993 994 #define NX_HOST_REQUEST 0x13 995 #define NX_NIC_REQUEST 0x14 996 997 #define NX_MAC_EVENT 0x1 998 999 #define NX_IP_UP 2 1000 #define NX_IP_DOWN 3 1001 1002 /* 1003 * Driver --> Firmware 1004 */ 1005 #define NX_NIC_H2C_OPCODE_START 0 1006 #define NX_NIC_H2C_OPCODE_CONFIG_RSS 1 1007 #define NX_NIC_H2C_OPCODE_CONFIG_RSS_TBL 2 1008 #define NX_NIC_H2C_OPCODE_CONFIG_INTR_COALESCE 3 1009 #define NX_NIC_H2C_OPCODE_CONFIG_LED 4 1010 #define NX_NIC_H2C_OPCODE_CONFIG_PROMISCUOUS 5 1011 #define NX_NIC_H2C_OPCODE_CONFIG_L2_MAC 6 1012 #define NX_NIC_H2C_OPCODE_LRO_REQUEST 7 1013 #define NX_NIC_H2C_OPCODE_GET_SNMP_STATS 8 1014 #define NX_NIC_H2C_OPCODE_PROXY_START_REQUEST 9 1015 #define NX_NIC_H2C_OPCODE_PROXY_STOP_REQUEST 10 1016 #define NX_NIC_H2C_OPCODE_PROXY_SET_MTU 11 1017 #define NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE 12 1018 #define NX_NIC_H2C_OPCODE_GET_FINGER_PRINT_REQUEST 13 1019 #define NX_NIC_H2C_OPCODE_INSTALL_LICENSE_REQUEST 14 1020 #define NX_NIC_H2C_OPCODE_GET_LICENSE_CAPABILITY_REQUEST 15 1021 #define NX_NIC_H2C_OPCODE_GET_NET_STATS 16 1022 #define NX_NIC_H2C_OPCODE_PROXY_UPDATE_P2V 17 1023 #define NX_NIC_H2C_OPCODE_CONFIG_IPADDR 18 1024 #define NX_NIC_H2C_OPCODE_CONFIG_LOOPBACK 19 1025 #define NX_NIC_H2C_OPCODE_PROXY_STOP_DONE 20 1026 #define NX_NIC_H2C_OPCODE_GET_LINKEVENT 21 1027 #define NX_NIC_C2C_OPCODE 22 1028 #define NX_NIC_H2C_OPCODE_CONFIG_BRIDGING 23 1029 #define NX_NIC_H2C_OPCODE_CONFIG_HW_LRO 24 1030 #define NX_NIC_H2C_OPCODE_LAST 25 1031 1032 /* 1033 * Firmware --> Driver 1034 */ 1035 1036 #define NX_NIC_C2H_OPCODE_START 128 1037 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_RESPONSE 129 1038 #define NX_NIC_C2H_OPCODE_CONFIG_RSS_TBL_RESPONSE 130 1039 #define NX_NIC_C2H_OPCODE_CONFIG_MAC_RESPONSE 131 1040 #define NX_NIC_C2H_OPCODE_CONFIG_PROMISCUOUS_RESPONSE 132 1041 #define NX_NIC_C2H_OPCODE_CONFIG_L2_MAC_RESPONSE 133 1042 #define NX_NIC_C2H_OPCODE_LRO_DELETE_RESPONSE 134 1043 #define NX_NIC_C2H_OPCODE_LRO_ADD_FAILURE_RESPONSE 135 1044 #define NX_NIC_C2H_OPCODE_GET_SNMP_STATS 136 1045 #define NX_NIC_C2H_OPCODE_GET_FINGER_PRINT_REPLY 137 1046 #define NX_NIC_C2H_OPCODE_INSTALL_LICENSE_REPLY 138 1047 #define NX_NIC_C2H_OPCODE_GET_LICENSE_CAPABILITIES_REPLY 139 1048 #define NX_NIC_C2H_OPCODE_GET_NET_STATS_RESPONSE 140 1049 #define NX_NIC_C2H_OPCODE_GET_LINKEVENT_RESPONSE 141 1050 #define NX_NIC_C2H_OPCODE_LAST 142 1051 1052 #define VPORT_MISS_MODE_DROP 0 /* drop all unmatched */ 1053 #define VPORT_MISS_MODE_ACCEPT_ALL 1 /* accept all packets */ 1054 #define VPORT_MISS_MODE_ACCEPT_MULTI 2 /* accept unmatched multicast */ 1055 1056 #define NX_NIC_LRO_REQUEST_FIRST 0 1057 #define NX_NIC_LRO_REQUEST_ADD_FLOW 1 1058 #define NX_NIC_LRO_REQUEST_DELETE_FLOW 2 1059 #define NX_NIC_LRO_REQUEST_TIMER 3 1060 #define NX_NIC_LRO_REQUEST_CLEANUP 4 1061 #define NX_NIC_LRO_REQUEST_ADD_FLOW_SCHEDULED 5 1062 #define NX_TOE_LRO_REQUEST_ADD_FLOW 6 1063 #define NX_TOE_LRO_REQUEST_ADD_FLOW_RESPONSE 7 1064 #define NX_TOE_LRO_REQUEST_DELETE_FLOW 8 1065 #define NX_TOE_LRO_REQUEST_DELETE_FLOW_RESPONSE 9 1066 #define NX_TOE_LRO_REQUEST_TIMER 10 1067 #define NX_NIC_LRO_REQUEST_LAST 11 1068 1069 #define NX_FW_CAPABILITY_LINK_NOTIFICATION (1 << 5) 1070 #define NX_FW_CAPABILITY_SWITCHING (1 << 6) 1071 #define NX_FW_CAPABILITY_PEXQ (1 << 7) 1072 #define NX_FW_CAPABILITY_BDG (1 << 8) 1073 #define NX_FW_CAPABILITY_FVLANTX (1 << 9) 1074 #define NX_FW_CAPABILITY_HW_LRO (1 << 10) 1075 #define NX_FW_CAPABILITY_GBE_LINK_CFG (1 << 11) 1076 1077 /* module types */ 1078 #define LINKEVENT_MODULE_NOT_PRESENT 1 1079 #define LINKEVENT_MODULE_OPTICAL_UNKNOWN 2 1080 #define LINKEVENT_MODULE_OPTICAL_SRLR 3 1081 #define LINKEVENT_MODULE_OPTICAL_LRM 4 1082 #define LINKEVENT_MODULE_OPTICAL_SFP_1G 5 1083 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE 6 1084 #define LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN 7 1085 #define LINKEVENT_MODULE_TWINAX 8 1086 1087 #define LINKSPEED_10GBPS 10000 1088 #define LINKSPEED_1GBPS 1000 1089 #define LINKSPEED_100MBPS 100 1090 #define LINKSPEED_10MBPS 10 1091 1092 #define LINKSPEED_ENCODED_10MBPS 0 1093 #define LINKSPEED_ENCODED_100MBPS 1 1094 #define LINKSPEED_ENCODED_1GBPS 2 1095 1096 #define LINKEVENT_AUTONEG_DISABLED 0 1097 #define LINKEVENT_AUTONEG_ENABLED 1 1098 1099 #define LINKEVENT_HALF_DUPLEX 0 1100 #define LINKEVENT_FULL_DUPLEX 1 1101 1102 #define LINKEVENT_LINKSPEED_MBPS 0 1103 #define LINKEVENT_LINKSPEED_ENCODED 1 1104 1105 #define AUTO_FW_RESET_ENABLED 0xEF10AF12 1106 #define AUTO_FW_RESET_DISABLED 0xDCBAAF12 1107 1108 /* firmware response header: 1109 * 63:58 - message type 1110 * 57:56 - owner 1111 * 55:53 - desc count 1112 * 52:48 - reserved 1113 * 47:40 - completion id 1114 * 39:32 - opcode 1115 * 31:16 - error code 1116 * 15:00 - reserved 1117 */ 1118 #define netxen_get_nic_msgtype(msg_hdr) \ 1119 ((msg_hdr >> 58) & 0x3F) 1120 #define netxen_get_nic_msg_compid(msg_hdr) \ 1121 ((msg_hdr >> 40) & 0xFF) 1122 #define netxen_get_nic_msg_opcode(msg_hdr) \ 1123 ((msg_hdr >> 32) & 0xFF) 1124 #define netxen_get_nic_msg_errcode(msg_hdr) \ 1125 ((msg_hdr >> 16) & 0xFFFF) 1126 1127 typedef struct { 1128 union { 1129 struct { 1130 u64 hdr; 1131 u64 body[7]; 1132 }; 1133 u64 words[8]; 1134 }; 1135 } nx_fw_msg_t; 1136 1137 typedef struct { 1138 __le64 qhdr; 1139 __le64 req_hdr; 1140 __le64 words[6]; 1141 } nx_nic_req_t; 1142 1143 typedef struct { 1144 u8 op; 1145 u8 tag; 1146 u8 mac_addr[6]; 1147 } nx_mac_req_t; 1148 1149 #define MAX_PENDING_DESC_BLOCK_SIZE 64 1150 1151 #define NETXEN_NIC_MSI_ENABLED 0x02 1152 #define NETXEN_NIC_MSIX_ENABLED 0x04 1153 #define NETXEN_NIC_LRO_ENABLED 0x08 1154 #define NETXEN_NIC_LRO_DISABLED 0x00 1155 #define NETXEN_NIC_BRIDGE_ENABLED 0X10 1156 #define NETXEN_NIC_DIAG_ENABLED 0x20 1157 #define NETXEN_FW_RESET_OWNER 0x40 1158 #define NETXEN_IS_MSI_FAMILY(adapter) \ 1159 ((adapter)->flags & (NETXEN_NIC_MSI_ENABLED | NETXEN_NIC_MSIX_ENABLED)) 1160 1161 #define MSIX_ENTRIES_PER_ADAPTER NUM_STS_DESC_RINGS 1162 #define NETXEN_MSIX_TBL_SPACE 8192 1163 #define NETXEN_PCI_REG_MSIX_TBL 0x44 1164 1165 #define NETXEN_DB_MAPSIZE_BYTES 0x1000 1166 1167 #define NETXEN_NETDEV_WEIGHT 128 1168 #define NETXEN_ADAPTER_UP_MAGIC 777 1169 #define NETXEN_NIC_PEG_TUNE 0 1170 1171 #define __NX_FW_ATTACHED 0 1172 #define __NX_DEV_UP 1 1173 #define __NX_RESETTING 2 1174 1175 /* Mini Coredump FW supported version */ 1176 #define NX_MD_SUPPORT_MAJOR 4 1177 #define NX_MD_SUPPORT_MINOR 0 1178 #define NX_MD_SUPPORT_SUBVERSION 579 1179 1180 #define LSW(x) ((uint16_t)(x)) 1181 #define LSD(x) ((uint32_t)((uint64_t)(x))) 1182 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16)) 1183 1184 /* Mini Coredump mask level */ 1185 #define NX_DUMP_MASK_MIN 0x03 1186 #define NX_DUMP_MASK_DEF 0x1f 1187 #define NX_DUMP_MASK_MAX 0xff 1188 1189 /* Mini Coredump CDRP commands */ 1190 #define NX_CDRP_CMD_TEMP_SIZE 0x0000002f 1191 #define NX_CDRP_CMD_GET_TEMP_HDR 0x00000030 1192 1193 1194 #define NX_DUMP_STATE_ARRAY_LEN 16 1195 #define NX_DUMP_CAP_SIZE_ARRAY_LEN 8 1196 1197 /* Mini Coredump sysfs entries flags*/ 1198 #define NX_FORCE_FW_DUMP_KEY 0xdeadfeed 1199 #define NX_ENABLE_FW_DUMP 0xaddfeed 1200 #define NX_DISABLE_FW_DUMP 0xbadfeed 1201 #define NX_FORCE_FW_RESET 0xdeaddead 1202 1203 1204 /* Flash read/write address */ 1205 #define NX_FW_DUMP_REG1 0x00130060 1206 #define NX_FW_DUMP_REG2 0x001e0000 1207 #define NX_FLASH_SEM2_LK 0x0013C010 1208 #define NX_FLASH_SEM2_ULK 0x0013C014 1209 #define NX_FLASH_LOCK_ID 0x001B2100 1210 #define FLASH_ROM_WINDOW 0x42110030 1211 #define FLASH_ROM_DATA 0x42150000 1212 1213 /* Mini Coredump register read/write routine */ 1214 #define NX_RD_DUMP_REG(addr, bar0, data) do { \ 1215 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \ 1216 NX_FW_DUMP_REG1)); \ 1217 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \ 1218 *data = readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + \ 1219 LSW(addr))); \ 1220 } while (0) 1221 1222 #define NX_WR_DUMP_REG(addr, bar0, data) do { \ 1223 writel((addr & 0xFFFF0000), (void __iomem *) (bar0 + \ 1224 NX_FW_DUMP_REG1)); \ 1225 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG1)); \ 1226 writel(data, (void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr)));\ 1227 readl((void __iomem *) (bar0 + NX_FW_DUMP_REG2 + LSW(addr))); \ 1228 } while (0) 1229 1230 1231 /* 1232 Entry Type Defines 1233 */ 1234 1235 #define RDNOP 0 1236 #define RDCRB 1 1237 #define RDMUX 2 1238 #define QUEUE 3 1239 #define BOARD 4 1240 #define RDSRE 5 1241 #define RDOCM 6 1242 #define PREGS 7 1243 #define L1DTG 8 1244 #define L1ITG 9 1245 #define CACHE 10 1246 1247 #define L1DAT 11 1248 #define L1INS 12 1249 #define RDSTK 13 1250 #define RDCON 14 1251 1252 #define L2DTG 21 1253 #define L2ITG 22 1254 #define L2DAT 23 1255 #define L2INS 24 1256 #define RDOC3 25 1257 1258 #define MEMBK 32 1259 1260 #define RDROM 71 1261 #define RDMEM 72 1262 #define RDMN 73 1263 1264 #define INFOR 81 1265 #define CNTRL 98 1266 1267 #define TLHDR 99 1268 #define RDEND 255 1269 1270 #define PRIMQ 103 1271 #define SQG2Q 104 1272 #define SQG3Q 105 1273 1274 /* 1275 * Opcodes for Control Entries. 1276 * These Flags are bit fields. 1277 */ 1278 #define NX_DUMP_WCRB 0x01 1279 #define NX_DUMP_RWCRB 0x02 1280 #define NX_DUMP_ANDCRB 0x04 1281 #define NX_DUMP_ORCRB 0x08 1282 #define NX_DUMP_POLLCRB 0x10 1283 #define NX_DUMP_RD_SAVE 0x20 1284 #define NX_DUMP_WRT_SAVED 0x40 1285 #define NX_DUMP_MOD_SAVE_ST 0x80 1286 1287 /* Driver Flags */ 1288 #define NX_DUMP_SKIP 0x80 /* driver skipped this entry */ 1289 #define NX_DUMP_SIZE_ERR 0x40 /*entry size vs capture size mismatch*/ 1290 1291 #define NX_PCI_READ_32(ADDR) readl((ADDR)) 1292 #define NX_PCI_WRITE_32(DATA, ADDR) writel(DATA, (ADDR)) 1293 1294 1295 1296 struct netxen_minidump { 1297 u32 pos; /* position in the dump buffer */ 1298 u8 fw_supports_md; /* FW supports Mini cordump */ 1299 u8 has_valid_dump; /* indicates valid dump */ 1300 u8 md_capture_mask; /* driver capture mask */ 1301 u8 md_enabled; /* Turn Mini Coredump on/off */ 1302 u32 md_dump_size; /* Total FW Mini Coredump size */ 1303 u32 md_capture_size; /* FW dump capture size */ 1304 u32 md_template_size; /* FW template size */ 1305 u32 md_template_ver; /* FW template version */ 1306 u64 md_timestamp; /* FW Mini dump timestamp */ 1307 void *md_template; /* FW template will be stored */ 1308 void *md_capture_buff; /* FW dump will be stored */ 1309 }; 1310 1311 1312 1313 struct netxen_minidump_template_hdr { 1314 u32 entry_type; 1315 u32 first_entry_offset; 1316 u32 size_of_template; 1317 u32 capture_mask; 1318 u32 num_of_entries; 1319 u32 version; 1320 u32 driver_timestamp; 1321 u32 checksum; 1322 u32 driver_capture_mask; 1323 u32 driver_info_word2; 1324 u32 driver_info_word3; 1325 u32 driver_info_word4; 1326 u32 saved_state_array[NX_DUMP_STATE_ARRAY_LEN]; 1327 u32 capture_size_array[NX_DUMP_CAP_SIZE_ARRAY_LEN]; 1328 u32 rsvd[0]; 1329 }; 1330 1331 /* Common Entry Header: Common to All Entry Types */ 1332 /* 1333 * Driver Code is for driver to write some info about the entry. 1334 * Currently not used. 1335 */ 1336 1337 struct netxen_common_entry_hdr { 1338 u32 entry_type; 1339 u32 entry_size; 1340 u32 entry_capture_size; 1341 union { 1342 struct { 1343 u8 entry_capture_mask; 1344 u8 entry_code; 1345 u8 driver_code; 1346 u8 driver_flags; 1347 }; 1348 u32 entry_ctrl_word; 1349 }; 1350 }; 1351 1352 1353 /* Generic Entry Including Header */ 1354 struct netxen_minidump_entry { 1355 struct netxen_common_entry_hdr hdr; 1356 u32 entry_data00; 1357 u32 entry_data01; 1358 u32 entry_data02; 1359 u32 entry_data03; 1360 u32 entry_data04; 1361 u32 entry_data05; 1362 u32 entry_data06; 1363 u32 entry_data07; 1364 }; 1365 1366 /* Read ROM Header */ 1367 struct netxen_minidump_entry_rdrom { 1368 struct netxen_common_entry_hdr h; 1369 union { 1370 struct { 1371 u32 select_addr_reg; 1372 }; 1373 u32 rsvd_0; 1374 }; 1375 union { 1376 struct { 1377 u8 addr_stride; 1378 u8 addr_cnt; 1379 u16 data_size; 1380 }; 1381 u32 rsvd_1; 1382 }; 1383 union { 1384 struct { 1385 u32 op_count; 1386 }; 1387 u32 rsvd_2; 1388 }; 1389 union { 1390 struct { 1391 u32 read_addr_reg; 1392 }; 1393 u32 rsvd_3; 1394 }; 1395 union { 1396 struct { 1397 u32 write_mask; 1398 }; 1399 u32 rsvd_4; 1400 }; 1401 union { 1402 struct { 1403 u32 read_mask; 1404 }; 1405 u32 rsvd_5; 1406 }; 1407 u32 read_addr; 1408 u32 read_data_size; 1409 }; 1410 1411 1412 /* Read CRB and Control Entry Header */ 1413 struct netxen_minidump_entry_crb { 1414 struct netxen_common_entry_hdr h; 1415 u32 addr; 1416 union { 1417 struct { 1418 u8 addr_stride; 1419 u8 state_index_a; 1420 u16 poll_timeout; 1421 }; 1422 u32 addr_cntrl; 1423 }; 1424 u32 data_size; 1425 u32 op_count; 1426 union { 1427 struct { 1428 u8 opcode; 1429 u8 state_index_v; 1430 u8 shl; 1431 u8 shr; 1432 }; 1433 u32 control_value; 1434 }; 1435 u32 value_1; 1436 u32 value_2; 1437 u32 value_3; 1438 }; 1439 1440 /* Read Memory and MN Header */ 1441 struct netxen_minidump_entry_rdmem { 1442 struct netxen_common_entry_hdr h; 1443 union { 1444 struct { 1445 u32 select_addr_reg; 1446 }; 1447 u32 rsvd_0; 1448 }; 1449 union { 1450 struct { 1451 u8 addr_stride; 1452 u8 addr_cnt; 1453 u16 data_size; 1454 }; 1455 u32 rsvd_1; 1456 }; 1457 union { 1458 struct { 1459 u32 op_count; 1460 }; 1461 u32 rsvd_2; 1462 }; 1463 union { 1464 struct { 1465 u32 read_addr_reg; 1466 }; 1467 u32 rsvd_3; 1468 }; 1469 union { 1470 struct { 1471 u32 cntrl_addr_reg; 1472 }; 1473 u32 rsvd_4; 1474 }; 1475 union { 1476 struct { 1477 u8 wr_byte0; 1478 u8 wr_byte1; 1479 u8 poll_mask; 1480 u8 poll_cnt; 1481 }; 1482 u32 rsvd_5; 1483 }; 1484 u32 read_addr; 1485 u32 read_data_size; 1486 }; 1487 1488 /* Read Cache L1 and L2 Header */ 1489 struct netxen_minidump_entry_cache { 1490 struct netxen_common_entry_hdr h; 1491 u32 tag_reg_addr; 1492 union { 1493 struct { 1494 u16 tag_value_stride; 1495 u16 init_tag_value; 1496 }; 1497 u32 select_addr_cntrl; 1498 }; 1499 u32 data_size; 1500 u32 op_count; 1501 u32 control_addr; 1502 union { 1503 struct { 1504 u16 write_value; 1505 u8 poll_mask; 1506 u8 poll_wait; 1507 }; 1508 u32 control_value; 1509 }; 1510 u32 read_addr; 1511 union { 1512 struct { 1513 u8 read_addr_stride; 1514 u8 read_addr_cnt; 1515 u16 rsvd_1; 1516 }; 1517 u32 read_addr_cntrl; 1518 }; 1519 }; 1520 1521 /* Read OCM Header */ 1522 struct netxen_minidump_entry_rdocm { 1523 struct netxen_common_entry_hdr h; 1524 u32 rsvd_0; 1525 union { 1526 struct { 1527 u32 rsvd_1; 1528 }; 1529 u32 select_addr_cntrl; 1530 }; 1531 u32 data_size; 1532 u32 op_count; 1533 u32 rsvd_2; 1534 u32 rsvd_3; 1535 u32 read_addr; 1536 union { 1537 struct { 1538 u32 read_addr_stride; 1539 }; 1540 u32 read_addr_cntrl; 1541 }; 1542 }; 1543 1544 /* Read MUX Header */ 1545 struct netxen_minidump_entry_mux { 1546 struct netxen_common_entry_hdr h; 1547 u32 select_addr; 1548 union { 1549 struct { 1550 u32 rsvd_0; 1551 }; 1552 u32 select_addr_cntrl; 1553 }; 1554 u32 data_size; 1555 u32 op_count; 1556 u32 select_value; 1557 u32 select_value_stride; 1558 u32 read_addr; 1559 u32 rsvd_1; 1560 }; 1561 1562 /* Read Queue Header */ 1563 struct netxen_minidump_entry_queue { 1564 struct netxen_common_entry_hdr h; 1565 u32 select_addr; 1566 union { 1567 struct { 1568 u16 queue_id_stride; 1569 u16 rsvd_0; 1570 }; 1571 u32 select_addr_cntrl; 1572 }; 1573 u32 data_size; 1574 u32 op_count; 1575 u32 rsvd_1; 1576 u32 rsvd_2; 1577 u32 read_addr; 1578 union { 1579 struct { 1580 u8 read_addr_stride; 1581 u8 read_addr_cnt; 1582 u16 rsvd_3; 1583 }; 1584 u32 read_addr_cntrl; 1585 }; 1586 }; 1587 1588 struct netxen_dummy_dma { 1589 void *addr; 1590 dma_addr_t phys_addr; 1591 }; 1592 1593 struct netxen_adapter { 1594 struct netxen_hardware_context ahw; 1595 1596 struct net_device *netdev; 1597 struct pci_dev *pdev; 1598 struct list_head mac_list; 1599 struct list_head vlan_ip_list; 1600 1601 spinlock_t tx_clean_lock; 1602 1603 u16 num_txd; 1604 u16 num_rxd; 1605 u16 num_jumbo_rxd; 1606 u16 num_lro_rxd; 1607 1608 u8 max_rds_rings; 1609 u8 max_sds_rings; 1610 u8 driver_mismatch; 1611 u8 msix_supported; 1612 u8 __pad; 1613 u8 pci_using_dac; 1614 u8 portnum; 1615 u8 physical_port; 1616 1617 u8 mc_enabled; 1618 u8 max_mc_count; 1619 u8 rss_supported; 1620 u8 link_changed; 1621 u8 fw_wait_cnt; 1622 u8 fw_fail_cnt; 1623 u8 tx_timeo_cnt; 1624 u8 need_fw_reset; 1625 1626 u8 has_link_events; 1627 u8 fw_type; 1628 u16 tx_context_id; 1629 u16 mtu; 1630 u16 is_up; 1631 1632 u16 link_speed; 1633 u16 link_duplex; 1634 u16 link_autoneg; 1635 u16 module_type; 1636 1637 u32 capabilities; 1638 u32 flags; 1639 u32 irq; 1640 u32 temp; 1641 1642 u32 int_vec_bit; 1643 u32 heartbit; 1644 1645 u8 mac_addr[ETH_ALEN]; 1646 1647 struct netxen_adapter_stats stats; 1648 1649 struct netxen_recv_context recv_ctx; 1650 struct nx_host_tx_ring *tx_ring; 1651 1652 int (*macaddr_set) (struct netxen_adapter *, u8 *); 1653 int (*set_mtu) (struct netxen_adapter *, int); 1654 int (*set_promisc) (struct netxen_adapter *, u32); 1655 void (*set_multi) (struct net_device *); 1656 int (*phy_read) (struct netxen_adapter *, u32 reg, u32 *); 1657 int (*phy_write) (struct netxen_adapter *, u32 reg, u32 val); 1658 int (*init_port) (struct netxen_adapter *, int); 1659 int (*stop_port) (struct netxen_adapter *); 1660 1661 u32 (*crb_read)(struct netxen_adapter *, ulong); 1662 int (*crb_write)(struct netxen_adapter *, ulong, u32); 1663 1664 int (*pci_mem_read)(struct netxen_adapter *, u64, u64 *); 1665 int (*pci_mem_write)(struct netxen_adapter *, u64, u64); 1666 1667 int (*pci_set_window)(struct netxen_adapter *, u64, u32 *); 1668 1669 u32 (*io_read)(struct netxen_adapter *, void __iomem *); 1670 void (*io_write)(struct netxen_adapter *, void __iomem *, u32); 1671 1672 void __iomem *tgt_mask_reg; 1673 void __iomem *pci_int_reg; 1674 void __iomem *tgt_status_reg; 1675 void __iomem *crb_int_state_reg; 1676 void __iomem *isr_int_vec; 1677 1678 struct msix_entry msix_entries[MSIX_ENTRIES_PER_ADAPTER]; 1679 1680 struct netxen_dummy_dma dummy_dma; 1681 1682 struct delayed_work fw_work; 1683 1684 struct work_struct tx_timeout_task; 1685 1686 nx_nic_intr_coalesce_t coal; 1687 1688 unsigned long state; 1689 __le32 file_prd_off; /*File fw product offset*/ 1690 u32 fw_version; 1691 const struct firmware *fw; 1692 struct netxen_minidump mdump; /* mdump ptr */ 1693 int fw_mdump_rdy; /* for mdump ready */ 1694 }; 1695 1696 int nx_fw_cmd_query_phy(struct netxen_adapter *adapter, u32 reg, u32 *val); 1697 int nx_fw_cmd_set_phy(struct netxen_adapter *adapter, u32 reg, u32 val); 1698 1699 #define NXRD32(adapter, off) \ 1700 (adapter->crb_read(adapter, off)) 1701 #define NXWR32(adapter, off, val) \ 1702 (adapter->crb_write(adapter, off, val)) 1703 #define NXRDIO(adapter, addr) \ 1704 (adapter->io_read(adapter, addr)) 1705 #define NXWRIO(adapter, addr, val) \ 1706 (adapter->io_write(adapter, addr, val)) 1707 1708 int netxen_pcie_sem_lock(struct netxen_adapter *, int, u32); 1709 void netxen_pcie_sem_unlock(struct netxen_adapter *, int); 1710 1711 #define netxen_rom_lock(a) \ 1712 netxen_pcie_sem_lock((a), 2, NETXEN_ROM_LOCK_ID) 1713 #define netxen_rom_unlock(a) \ 1714 netxen_pcie_sem_unlock((a), 2) 1715 #define netxen_phy_lock(a) \ 1716 netxen_pcie_sem_lock((a), 3, NETXEN_PHY_LOCK_ID) 1717 #define netxen_phy_unlock(a) \ 1718 netxen_pcie_sem_unlock((a), 3) 1719 #define netxen_api_lock(a) \ 1720 netxen_pcie_sem_lock((a), 5, 0) 1721 #define netxen_api_unlock(a) \ 1722 netxen_pcie_sem_unlock((a), 5) 1723 #define netxen_sw_lock(a) \ 1724 netxen_pcie_sem_lock((a), 6, 0) 1725 #define netxen_sw_unlock(a) \ 1726 netxen_pcie_sem_unlock((a), 6) 1727 #define crb_win_lock(a) \ 1728 netxen_pcie_sem_lock((a), 7, NETXEN_CRB_WIN_LOCK_ID) 1729 #define crb_win_unlock(a) \ 1730 netxen_pcie_sem_unlock((a), 7) 1731 1732 int netxen_nic_get_board_info(struct netxen_adapter *adapter); 1733 int netxen_nic_wol_supported(struct netxen_adapter *adapter); 1734 1735 /* Functions from netxen_nic_init.c */ 1736 int netxen_init_dummy_dma(struct netxen_adapter *adapter); 1737 void netxen_free_dummy_dma(struct netxen_adapter *adapter); 1738 1739 int netxen_check_flash_fw_compatibility(struct netxen_adapter *adapter); 1740 int netxen_phantom_init(struct netxen_adapter *adapter, int pegtune_val); 1741 int netxen_load_firmware(struct netxen_adapter *adapter); 1742 int netxen_need_fw_reset(struct netxen_adapter *adapter); 1743 void netxen_request_firmware(struct netxen_adapter *adapter); 1744 void netxen_release_firmware(struct netxen_adapter *adapter); 1745 int netxen_pinit_from_rom(struct netxen_adapter *adapter); 1746 1747 int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, int *valp); 1748 int netxen_rom_fast_read_words(struct netxen_adapter *adapter, int addr, 1749 u8 *bytes, size_t size); 1750 int netxen_rom_fast_write_words(struct netxen_adapter *adapter, int addr, 1751 u8 *bytes, size_t size); 1752 int netxen_flash_unlock(struct netxen_adapter *adapter); 1753 int netxen_backup_crbinit(struct netxen_adapter *adapter); 1754 int netxen_flash_erase_secondary(struct netxen_adapter *adapter); 1755 int netxen_flash_erase_primary(struct netxen_adapter *adapter); 1756 void netxen_halt_pegs(struct netxen_adapter *adapter); 1757 1758 int netxen_rom_se(struct netxen_adapter *adapter, int addr); 1759 1760 int netxen_alloc_sw_resources(struct netxen_adapter *adapter); 1761 void netxen_free_sw_resources(struct netxen_adapter *adapter); 1762 1763 void netxen_setup_hwops(struct netxen_adapter *adapter); 1764 void __iomem *netxen_get_ioaddr(struct netxen_adapter *, u32); 1765 1766 int netxen_alloc_hw_resources(struct netxen_adapter *adapter); 1767 void netxen_free_hw_resources(struct netxen_adapter *adapter); 1768 1769 void netxen_release_rx_buffers(struct netxen_adapter *adapter); 1770 void netxen_release_tx_buffers(struct netxen_adapter *adapter); 1771 1772 int netxen_init_firmware(struct netxen_adapter *adapter); 1773 void netxen_nic_clear_stats(struct netxen_adapter *adapter); 1774 void netxen_watchdog_task(struct work_struct *work); 1775 void netxen_post_rx_buffers(struct netxen_adapter *adapter, u32 ringid, 1776 struct nx_host_rds_ring *rds_ring); 1777 int netxen_process_cmd_ring(struct netxen_adapter *adapter); 1778 int netxen_process_rcv_ring(struct nx_host_sds_ring *sds_ring, int max); 1779 1780 void netxen_p3_free_mac_list(struct netxen_adapter *adapter); 1781 int netxen_config_intr_coalesce(struct netxen_adapter *adapter); 1782 int netxen_config_rss(struct netxen_adapter *adapter, int enable); 1783 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd); 1784 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable); 1785 void netxen_advert_link_change(struct netxen_adapter *adapter, int linkup); 1786 void netxen_pci_camqm_read_2M(struct netxen_adapter *, u64, u64 *); 1787 void netxen_pci_camqm_write_2M(struct netxen_adapter *, u64, u64); 1788 1789 int nx_fw_cmd_set_gbe_port(struct netxen_adapter *adapter, 1790 u32 speed, u32 duplex, u32 autoneg); 1791 int nx_fw_cmd_set_mtu(struct netxen_adapter *adapter, int mtu); 1792 int netxen_nic_change_mtu(struct net_device *netdev, int new_mtu); 1793 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable); 1794 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable); 1795 int netxen_send_lro_cleanup(struct netxen_adapter *adapter); 1796 int netxen_setup_minidump(struct netxen_adapter *adapter); 1797 void netxen_dump_fw(struct netxen_adapter *adapter); 1798 void netxen_nic_update_cmd_producer(struct netxen_adapter *adapter, 1799 struct nx_host_tx_ring *tx_ring); 1800 1801 /* Functions from netxen_nic_main.c */ 1802 int netxen_nic_reset_context(struct netxen_adapter *); 1803 1804 int nx_dev_request_reset(struct netxen_adapter *adapter); 1805 1806 /* 1807 * NetXen Board information 1808 */ 1809 1810 #define NETXEN_MAX_SHORT_NAME 32 1811 struct netxen_brdinfo { 1812 int brdtype; /* type of board */ 1813 long ports; /* max no of physical ports */ 1814 char short_name[NETXEN_MAX_SHORT_NAME]; 1815 }; 1816 1817 static const struct netxen_brdinfo netxen_boards[] = { 1818 {NETXEN_BRDTYPE_P2_SB31_10G_CX4, 1, "XGb CX4"}, 1819 {NETXEN_BRDTYPE_P2_SB31_10G_HMEZ, 1, "XGb HMEZ"}, 1820 {NETXEN_BRDTYPE_P2_SB31_10G_IMEZ, 2, "XGb IMEZ"}, 1821 {NETXEN_BRDTYPE_P2_SB31_10G, 1, "XGb XFP"}, 1822 {NETXEN_BRDTYPE_P2_SB35_4G, 4, "Quad Gb"}, 1823 {NETXEN_BRDTYPE_P2_SB31_2G, 2, "Dual Gb"}, 1824 {NETXEN_BRDTYPE_P3_REF_QG, 4, "Reference Quad Gig "}, 1825 {NETXEN_BRDTYPE_P3_HMEZ, 2, "Dual XGb HMEZ"}, 1826 {NETXEN_BRDTYPE_P3_10G_CX4_LP, 2, "Dual XGb CX4 LP"}, 1827 {NETXEN_BRDTYPE_P3_4_GB, 4, "Quad Gig LP"}, 1828 {NETXEN_BRDTYPE_P3_IMEZ, 2, "Dual XGb IMEZ"}, 1829 {NETXEN_BRDTYPE_P3_10G_SFP_PLUS, 2, "Dual XGb SFP+ LP"}, 1830 {NETXEN_BRDTYPE_P3_10000_BASE_T, 1, "XGB 10G BaseT LP"}, 1831 {NETXEN_BRDTYPE_P3_XG_LOM, 2, "Dual XGb LOM"}, 1832 {NETXEN_BRDTYPE_P3_4_GB_MM, 4, "NX3031 Gigabit Ethernet"}, 1833 {NETXEN_BRDTYPE_P3_10G_SFP_CT, 2, "NX3031 10 Gigabit Ethernet"}, 1834 {NETXEN_BRDTYPE_P3_10G_SFP_QT, 2, "Quanta Dual XGb SFP+"}, 1835 {NETXEN_BRDTYPE_P3_10G_CX4, 2, "Reference Dual CX4 Option"}, 1836 {NETXEN_BRDTYPE_P3_10G_XFP, 1, "Reference Single XFP Option"} 1837 }; 1838 1839 #define NUM_SUPPORTED_BOARDS ARRAY_SIZE(netxen_boards) 1840 1841 static inline void get_brd_name_by_type(u32 type, char *name) 1842 { 1843 int i, found = 0; 1844 for (i = 0; i < NUM_SUPPORTED_BOARDS; ++i) { 1845 if (netxen_boards[i].brdtype == type) { 1846 strcpy(name, netxen_boards[i].short_name); 1847 found = 1; 1848 break; 1849 } 1850 1851 } 1852 if (!found) 1853 name = "Unknown"; 1854 } 1855 1856 static inline u32 netxen_tx_avail(struct nx_host_tx_ring *tx_ring) 1857 { 1858 smp_mb(); 1859 return find_diff_among(tx_ring->producer, 1860 tx_ring->sw_consumer, tx_ring->num_desc); 1861 1862 } 1863 1864 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac); 1865 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac); 1866 extern void netxen_change_ringparam(struct netxen_adapter *adapter); 1867 extern int netxen_rom_fast_read(struct netxen_adapter *adapter, int addr, 1868 int *valp); 1869 1870 extern const struct ethtool_ops netxen_nic_ethtool_ops; 1871 1872 #endif /* __NETXEN_NIC_H_ */ 1873