1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ip.h> 5 #include <linux/ipv6.h> 6 #include <linux/if_vlan.h> 7 #include <net/ip6_checksum.h> 8 9 #include "ionic.h" 10 #include "ionic_lif.h" 11 #include "ionic_txrx.h" 12 13 static void ionic_rx_clean(struct ionic_queue *q, 14 struct ionic_desc_info *desc_info, 15 struct ionic_cq_info *cq_info, 16 void *cb_arg); 17 18 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 19 20 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 21 22 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell, 23 ionic_desc_cb cb_func, void *cb_arg) 24 { 25 DEBUG_STATS_TXQ_POST(q_to_qcq(q), q->head->desc, ring_dbell); 26 27 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 28 } 29 30 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell, 31 ionic_desc_cb cb_func, void *cb_arg) 32 { 33 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 34 35 DEBUG_STATS_RX_BUFF_CNT(q_to_qcq(q)); 36 } 37 38 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q) 39 { 40 return netdev_get_tx_queue(q->lif->netdev, q->index); 41 } 42 43 static struct sk_buff *ionic_rx_skb_alloc(struct ionic_queue *q, 44 unsigned int len, bool frags) 45 { 46 struct ionic_lif *lif = q->lif; 47 struct ionic_rx_stats *stats; 48 struct net_device *netdev; 49 struct sk_buff *skb; 50 51 netdev = lif->netdev; 52 stats = q_to_rx_stats(q); 53 54 if (frags) 55 skb = napi_get_frags(&q_to_qcq(q)->napi); 56 else 57 skb = netdev_alloc_skb_ip_align(netdev, len); 58 59 if (unlikely(!skb)) { 60 net_warn_ratelimited("%s: SKB alloc failed on %s!\n", 61 netdev->name, q->name); 62 stats->alloc_err++; 63 return NULL; 64 } 65 66 return skb; 67 } 68 69 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q, 70 struct ionic_desc_info *desc_info, 71 struct ionic_cq_info *cq_info) 72 { 73 struct ionic_rxq_comp *comp = cq_info->cq_desc; 74 struct device *dev = q->lif->ionic->dev; 75 struct ionic_page_info *page_info; 76 struct sk_buff *skb; 77 unsigned int i; 78 u16 frag_len; 79 u16 len; 80 81 page_info = &desc_info->pages[0]; 82 len = le16_to_cpu(comp->len); 83 84 prefetch(page_address(page_info->page) + NET_IP_ALIGN); 85 86 skb = ionic_rx_skb_alloc(q, len, true); 87 if (unlikely(!skb)) 88 return NULL; 89 90 i = comp->num_sg_elems + 1; 91 do { 92 if (unlikely(!page_info->page)) { 93 struct napi_struct *napi = &q_to_qcq(q)->napi; 94 95 napi->skb = NULL; 96 dev_kfree_skb(skb); 97 return NULL; 98 } 99 100 frag_len = min(len, (u16)PAGE_SIZE); 101 len -= frag_len; 102 103 dma_unmap_page(dev, dma_unmap_addr(page_info, dma_addr), 104 PAGE_SIZE, DMA_FROM_DEVICE); 105 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 106 page_info->page, 0, frag_len, PAGE_SIZE); 107 page_info->page = NULL; 108 page_info++; 109 i--; 110 } while (i > 0); 111 112 return skb; 113 } 114 115 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q, 116 struct ionic_desc_info *desc_info, 117 struct ionic_cq_info *cq_info) 118 { 119 struct ionic_rxq_comp *comp = cq_info->cq_desc; 120 struct device *dev = q->lif->ionic->dev; 121 struct ionic_page_info *page_info; 122 struct sk_buff *skb; 123 u16 len; 124 125 page_info = &desc_info->pages[0]; 126 len = le16_to_cpu(comp->len); 127 128 skb = ionic_rx_skb_alloc(q, len, false); 129 if (unlikely(!skb)) 130 return NULL; 131 132 if (unlikely(!page_info->page)) { 133 dev_kfree_skb(skb); 134 return NULL; 135 } 136 137 dma_sync_single_for_cpu(dev, dma_unmap_addr(page_info, dma_addr), 138 len, DMA_FROM_DEVICE); 139 skb_copy_to_linear_data(skb, page_address(page_info->page), len); 140 dma_sync_single_for_device(dev, dma_unmap_addr(page_info, dma_addr), 141 len, DMA_FROM_DEVICE); 142 143 skb_put(skb, len); 144 skb->protocol = eth_type_trans(skb, q->lif->netdev); 145 146 return skb; 147 } 148 149 static void ionic_rx_clean(struct ionic_queue *q, 150 struct ionic_desc_info *desc_info, 151 struct ionic_cq_info *cq_info, 152 void *cb_arg) 153 { 154 struct ionic_rxq_comp *comp = cq_info->cq_desc; 155 struct ionic_qcq *qcq = q_to_qcq(q); 156 struct ionic_rx_stats *stats; 157 struct net_device *netdev; 158 struct sk_buff *skb; 159 160 stats = q_to_rx_stats(q); 161 netdev = q->lif->netdev; 162 163 if (comp->status) { 164 stats->dropped++; 165 return; 166 } 167 168 stats->pkts++; 169 stats->bytes += le16_to_cpu(comp->len); 170 171 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 172 skb = ionic_rx_copybreak(q, desc_info, cq_info); 173 else 174 skb = ionic_rx_frags(q, desc_info, cq_info); 175 176 if (unlikely(!skb)) { 177 stats->dropped++; 178 return; 179 } 180 181 skb_record_rx_queue(skb, q->index); 182 183 if (likely(netdev->features & NETIF_F_RXHASH)) { 184 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) { 185 case IONIC_PKT_TYPE_IPV4: 186 case IONIC_PKT_TYPE_IPV6: 187 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 188 PKT_HASH_TYPE_L3); 189 break; 190 case IONIC_PKT_TYPE_IPV4_TCP: 191 case IONIC_PKT_TYPE_IPV6_TCP: 192 case IONIC_PKT_TYPE_IPV4_UDP: 193 case IONIC_PKT_TYPE_IPV6_UDP: 194 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 195 PKT_HASH_TYPE_L4); 196 break; 197 } 198 } 199 200 if (likely(netdev->features & NETIF_F_RXCSUM)) { 201 if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 202 skb->ip_summed = CHECKSUM_COMPLETE; 203 skb->csum = (__wsum)le16_to_cpu(comp->csum); 204 stats->csum_complete++; 205 } 206 } else { 207 stats->csum_none++; 208 } 209 210 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) || 211 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) || 212 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))) 213 stats->csum_error++; 214 215 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 216 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) { 217 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 218 le16_to_cpu(comp->vlan_tci)); 219 stats->vlan_stripped++; 220 } 221 222 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 223 napi_gro_receive(&qcq->napi, skb); 224 else 225 napi_gro_frags(&qcq->napi); 226 } 227 228 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 229 { 230 struct ionic_rxq_comp *comp = cq_info->cq_desc; 231 struct ionic_queue *q = cq->bound_q; 232 struct ionic_desc_info *desc_info; 233 234 if (!color_match(comp->pkt_type_color, cq->done_color)) 235 return false; 236 237 /* check for empty queue */ 238 if (q->tail->index == q->head->index) 239 return false; 240 241 desc_info = q->tail; 242 if (desc_info->index != le16_to_cpu(comp->comp_index)) 243 return false; 244 245 q->tail = desc_info->next; 246 247 /* clean the related q entry, only one per qc completion */ 248 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg); 249 250 desc_info->cb = NULL; 251 desc_info->cb_arg = NULL; 252 253 return true; 254 } 255 256 void ionic_rx_flush(struct ionic_cq *cq) 257 { 258 struct ionic_dev *idev = &cq->lif->ionic->idev; 259 u32 work_done; 260 261 work_done = ionic_cq_service(cq, cq->num_descs, 262 ionic_rx_service, NULL, NULL); 263 264 if (work_done) 265 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 266 work_done, IONIC_INTR_CRED_RESET_COALESCE); 267 } 268 269 static struct page *ionic_rx_page_alloc(struct ionic_queue *q, 270 dma_addr_t *dma_addr) 271 { 272 struct ionic_lif *lif = q->lif; 273 struct ionic_rx_stats *stats; 274 struct net_device *netdev; 275 struct device *dev; 276 struct page *page; 277 278 netdev = lif->netdev; 279 dev = lif->ionic->dev; 280 stats = q_to_rx_stats(q); 281 page = alloc_page(GFP_ATOMIC); 282 if (unlikely(!page)) { 283 net_err_ratelimited("%s: Page alloc failed on %s!\n", 284 netdev->name, q->name); 285 stats->alloc_err++; 286 return NULL; 287 } 288 289 *dma_addr = dma_map_page(dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE); 290 if (unlikely(dma_mapping_error(dev, *dma_addr))) { 291 __free_page(page); 292 net_err_ratelimited("%s: DMA single map failed on %s!\n", 293 netdev->name, q->name); 294 stats->dma_map_err++; 295 return NULL; 296 } 297 298 return page; 299 } 300 301 static void ionic_rx_page_free(struct ionic_queue *q, struct page *page, 302 dma_addr_t dma_addr) 303 { 304 struct ionic_lif *lif = q->lif; 305 struct net_device *netdev; 306 struct device *dev; 307 308 netdev = lif->netdev; 309 dev = lif->ionic->dev; 310 311 if (unlikely(!page)) { 312 net_err_ratelimited("%s: Trying to free unallocated buffer on %s!\n", 313 netdev->name, q->name); 314 return; 315 } 316 317 dma_unmap_page(dev, dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 318 319 __free_page(page); 320 } 321 322 void ionic_rx_fill(struct ionic_queue *q) 323 { 324 struct net_device *netdev = q->lif->netdev; 325 struct ionic_desc_info *desc_info; 326 struct ionic_page_info *page_info; 327 struct ionic_rxq_sg_desc *sg_desc; 328 struct ionic_rxq_sg_elem *sg_elem; 329 struct ionic_rxq_desc *desc; 330 unsigned int remain_len; 331 unsigned int seg_len; 332 unsigned int nfrags; 333 unsigned int i, j; 334 unsigned int len; 335 336 len = netdev->mtu + ETH_HLEN; 337 nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE; 338 339 for (i = ionic_q_space_avail(q); i; i--) { 340 remain_len = len; 341 desc_info = q->head; 342 desc = desc_info->desc; 343 sg_desc = desc_info->sg_desc; 344 page_info = &desc_info->pages[0]; 345 346 if (page_info->page) { /* recycle the buffer */ 347 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 348 continue; 349 } 350 351 /* fill main descriptor - pages[0] */ 352 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG : 353 IONIC_RXQ_DESC_OPCODE_SIMPLE; 354 desc_info->npages = nfrags; 355 page_info->page = ionic_rx_page_alloc(q, &page_info->dma_addr); 356 if (unlikely(!page_info->page)) { 357 desc->addr = 0; 358 desc->len = 0; 359 return; 360 } 361 desc->addr = cpu_to_le64(page_info->dma_addr); 362 seg_len = min_t(unsigned int, PAGE_SIZE, len); 363 desc->len = cpu_to_le16(seg_len); 364 remain_len -= seg_len; 365 page_info++; 366 367 /* fill sg descriptors - pages[1..n] */ 368 for (j = 0; j < nfrags - 1; j++) { 369 if (page_info->page) /* recycle the sg buffer */ 370 continue; 371 372 sg_elem = &sg_desc->elems[j]; 373 page_info->page = ionic_rx_page_alloc(q, &page_info->dma_addr); 374 if (unlikely(!page_info->page)) { 375 sg_elem->addr = 0; 376 sg_elem->len = 0; 377 return; 378 } 379 sg_elem->addr = cpu_to_le64(page_info->dma_addr); 380 seg_len = min_t(unsigned int, PAGE_SIZE, remain_len); 381 sg_elem->len = cpu_to_le16(seg_len); 382 remain_len -= seg_len; 383 page_info++; 384 } 385 386 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 387 } 388 389 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type, 390 q->dbval | q->head->index); 391 } 392 393 static void ionic_rx_fill_cb(void *arg) 394 { 395 ionic_rx_fill(arg); 396 } 397 398 void ionic_rx_empty(struct ionic_queue *q) 399 { 400 struct ionic_desc_info *cur; 401 struct ionic_rxq_desc *desc; 402 unsigned int i; 403 404 for (cur = q->tail; cur != q->head; cur = cur->next) { 405 desc = cur->desc; 406 desc->addr = 0; 407 desc->len = 0; 408 409 for (i = 0; i < cur->npages; i++) { 410 if (likely(cur->pages[i].page)) { 411 ionic_rx_page_free(q, cur->pages[i].page, 412 cur->pages[i].dma_addr); 413 cur->pages[i].page = NULL; 414 cur->pages[i].dma_addr = 0; 415 } 416 } 417 418 cur->cb_arg = NULL; 419 } 420 } 421 422 int ionic_tx_napi(struct napi_struct *napi, int budget) 423 { 424 struct ionic_qcq *qcq = napi_to_qcq(napi); 425 struct ionic_cq *cq = napi_to_cq(napi); 426 struct ionic_dev *idev; 427 struct ionic_lif *lif; 428 u32 work_done = 0; 429 u32 flags = 0; 430 431 lif = cq->bound_q->lif; 432 idev = &lif->ionic->idev; 433 434 work_done = ionic_cq_service(cq, budget, 435 ionic_tx_service, NULL, NULL); 436 437 if (work_done < budget && napi_complete_done(napi, work_done)) { 438 flags |= IONIC_INTR_CRED_UNMASK; 439 DEBUG_STATS_INTR_REARM(cq->bound_intr); 440 } 441 442 if (work_done || flags) { 443 flags |= IONIC_INTR_CRED_RESET_COALESCE; 444 ionic_intr_credits(idev->intr_ctrl, 445 cq->bound_intr->index, 446 work_done, flags); 447 } 448 449 DEBUG_STATS_NAPI_POLL(qcq, work_done); 450 451 return work_done; 452 } 453 454 int ionic_rx_napi(struct napi_struct *napi, int budget) 455 { 456 struct ionic_qcq *qcq = napi_to_qcq(napi); 457 struct ionic_cq *cq = napi_to_cq(napi); 458 struct ionic_dev *idev; 459 struct ionic_lif *lif; 460 u32 work_done = 0; 461 u32 flags = 0; 462 463 lif = cq->bound_q->lif; 464 idev = &lif->ionic->idev; 465 466 work_done = ionic_cq_service(cq, budget, 467 ionic_rx_service, NULL, NULL); 468 469 if (work_done) 470 ionic_rx_fill(cq->bound_q); 471 472 if (work_done < budget && napi_complete_done(napi, work_done)) { 473 flags |= IONIC_INTR_CRED_UNMASK; 474 DEBUG_STATS_INTR_REARM(cq->bound_intr); 475 } 476 477 if (work_done || flags) { 478 flags |= IONIC_INTR_CRED_RESET_COALESCE; 479 ionic_intr_credits(idev->intr_ctrl, 480 cq->bound_intr->index, 481 work_done, flags); 482 } 483 484 DEBUG_STATS_NAPI_POLL(qcq, work_done); 485 486 return work_done; 487 } 488 489 int ionic_txrx_napi(struct napi_struct *napi, int budget) 490 { 491 struct ionic_qcq *qcq = napi_to_qcq(napi); 492 struct ionic_cq *rxcq = napi_to_cq(napi); 493 unsigned int qi = rxcq->bound_q->index; 494 struct ionic_dev *idev; 495 struct ionic_lif *lif; 496 struct ionic_cq *txcq; 497 u32 rx_work_done = 0; 498 u32 tx_work_done = 0; 499 u32 flags = 0; 500 501 lif = rxcq->bound_q->lif; 502 idev = &lif->ionic->idev; 503 txcq = &lif->txqcqs[qi].qcq->cq; 504 505 tx_work_done = ionic_cq_service(txcq, lif->tx_budget, 506 ionic_tx_service, NULL, NULL); 507 508 rx_work_done = ionic_cq_service(rxcq, budget, 509 ionic_rx_service, NULL, NULL); 510 if (rx_work_done) 511 ionic_rx_fill_cb(rxcq->bound_q); 512 513 if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) { 514 flags |= IONIC_INTR_CRED_UNMASK; 515 DEBUG_STATS_INTR_REARM(rxcq->bound_intr); 516 } 517 518 if (rx_work_done || flags) { 519 flags |= IONIC_INTR_CRED_RESET_COALESCE; 520 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index, 521 tx_work_done + rx_work_done, flags); 522 } 523 524 DEBUG_STATS_NAPI_POLL(qcq, rx_work_done); 525 DEBUG_STATS_NAPI_POLL(qcq, tx_work_done); 526 527 return rx_work_done; 528 } 529 530 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, 531 void *data, size_t len) 532 { 533 struct ionic_tx_stats *stats = q_to_tx_stats(q); 534 struct device *dev = q->lif->ionic->dev; 535 dma_addr_t dma_addr; 536 537 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE); 538 if (dma_mapping_error(dev, dma_addr)) { 539 net_warn_ratelimited("%s: DMA single map failed on %s!\n", 540 q->lif->netdev->name, q->name); 541 stats->dma_map_err++; 542 return 0; 543 } 544 return dma_addr; 545 } 546 547 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, 548 const skb_frag_t *frag, 549 size_t offset, size_t len) 550 { 551 struct ionic_tx_stats *stats = q_to_tx_stats(q); 552 struct device *dev = q->lif->ionic->dev; 553 dma_addr_t dma_addr; 554 555 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE); 556 if (dma_mapping_error(dev, dma_addr)) { 557 net_warn_ratelimited("%s: DMA frag map failed on %s!\n", 558 q->lif->netdev->name, q->name); 559 stats->dma_map_err++; 560 } 561 return dma_addr; 562 } 563 564 static void ionic_tx_clean(struct ionic_queue *q, 565 struct ionic_desc_info *desc_info, 566 struct ionic_cq_info *cq_info, 567 void *cb_arg) 568 { 569 struct ionic_txq_sg_desc *sg_desc = desc_info->sg_desc; 570 struct ionic_txq_sg_elem *elem = sg_desc->elems; 571 struct ionic_tx_stats *stats = q_to_tx_stats(q); 572 struct ionic_txq_desc *desc = desc_info->desc; 573 struct device *dev = q->lif->ionic->dev; 574 u8 opcode, flags, nsge; 575 u16 queue_index; 576 unsigned int i; 577 u64 addr; 578 579 decode_txq_desc_cmd(le64_to_cpu(desc->cmd), 580 &opcode, &flags, &nsge, &addr); 581 582 /* use unmap_single only if either this is not TSO, 583 * or this is first descriptor of a TSO 584 */ 585 if (opcode != IONIC_TXQ_DESC_OPCODE_TSO || 586 flags & IONIC_TXQ_DESC_FLAG_TSO_SOT) 587 dma_unmap_single(dev, (dma_addr_t)addr, 588 le16_to_cpu(desc->len), DMA_TO_DEVICE); 589 else 590 dma_unmap_page(dev, (dma_addr_t)addr, 591 le16_to_cpu(desc->len), DMA_TO_DEVICE); 592 593 for (i = 0; i < nsge; i++, elem++) 594 dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem->addr), 595 le16_to_cpu(elem->len), DMA_TO_DEVICE); 596 597 if (cb_arg) { 598 struct sk_buff *skb = cb_arg; 599 u32 len = skb->len; 600 601 queue_index = skb_get_queue_mapping(skb); 602 if (unlikely(__netif_subqueue_stopped(q->lif->netdev, 603 queue_index))) { 604 netif_wake_subqueue(q->lif->netdev, queue_index); 605 q->wake++; 606 } 607 dev_kfree_skb_any(skb); 608 stats->clean++; 609 netdev_tx_completed_queue(q_to_ndq(q), 1, len); 610 } 611 } 612 613 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 614 { 615 struct ionic_txq_comp *comp = cq_info->cq_desc; 616 struct ionic_queue *q = cq->bound_q; 617 struct ionic_desc_info *desc_info; 618 619 if (!color_match(comp->color, cq->done_color)) 620 return false; 621 622 /* clean the related q entries, there could be 623 * several q entries completed for each cq completion 624 */ 625 do { 626 desc_info = q->tail; 627 q->tail = desc_info->next; 628 ionic_tx_clean(q, desc_info, cq->tail, desc_info->cb_arg); 629 desc_info->cb = NULL; 630 desc_info->cb_arg = NULL; 631 } while (desc_info->index != le16_to_cpu(comp->comp_index)); 632 633 return true; 634 } 635 636 void ionic_tx_flush(struct ionic_cq *cq) 637 { 638 struct ionic_dev *idev = &cq->lif->ionic->idev; 639 u32 work_done; 640 641 work_done = ionic_cq_service(cq, cq->num_descs, 642 ionic_tx_service, NULL, NULL); 643 if (work_done) 644 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 645 work_done, IONIC_INTR_CRED_RESET_COALESCE); 646 } 647 648 void ionic_tx_empty(struct ionic_queue *q) 649 { 650 struct ionic_desc_info *desc_info; 651 int done = 0; 652 653 /* walk the not completed tx entries, if any */ 654 while (q->head != q->tail) { 655 desc_info = q->tail; 656 q->tail = desc_info->next; 657 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg); 658 desc_info->cb = NULL; 659 desc_info->cb_arg = NULL; 660 done++; 661 } 662 } 663 664 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb) 665 { 666 int err; 667 668 err = skb_cow_head(skb, 0); 669 if (err) 670 return err; 671 672 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 673 inner_ip_hdr(skb)->check = 0; 674 inner_tcp_hdr(skb)->check = 675 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr, 676 inner_ip_hdr(skb)->daddr, 677 0, IPPROTO_TCP, 0); 678 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 679 inner_tcp_hdr(skb)->check = 680 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr, 681 &inner_ipv6_hdr(skb)->daddr, 682 0, IPPROTO_TCP, 0); 683 } 684 685 return 0; 686 } 687 688 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb) 689 { 690 int err; 691 692 err = skb_cow_head(skb, 0); 693 if (err) 694 return err; 695 696 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 697 ip_hdr(skb)->check = 0; 698 tcp_hdr(skb)->check = 699 ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 700 ip_hdr(skb)->daddr, 701 0, IPPROTO_TCP, 0); 702 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 703 tcp_v6_gso_csum_prep(skb); 704 } 705 706 return 0; 707 } 708 709 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, 710 struct sk_buff *skb, 711 dma_addr_t addr, u8 nsge, u16 len, 712 unsigned int hdrlen, unsigned int mss, 713 bool outer_csum, 714 u16 vlan_tci, bool has_vlan, 715 bool start, bool done) 716 { 717 u8 flags = 0; 718 u64 cmd; 719 720 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 721 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 722 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; 723 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; 724 725 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr); 726 desc->cmd = cpu_to_le64(cmd); 727 desc->len = cpu_to_le16(len); 728 desc->vlan_tci = cpu_to_le16(vlan_tci); 729 desc->hdr_len = cpu_to_le16(hdrlen); 730 desc->mss = cpu_to_le16(mss); 731 732 if (done) { 733 skb_tx_timestamp(skb); 734 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 735 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 736 } else { 737 ionic_txq_post(q, false, ionic_tx_clean, NULL); 738 } 739 } 740 741 static struct ionic_txq_desc *ionic_tx_tso_next(struct ionic_queue *q, 742 struct ionic_txq_sg_elem **elem) 743 { 744 struct ionic_txq_sg_desc *sg_desc = q->head->sg_desc; 745 struct ionic_txq_desc *desc = q->head->desc; 746 747 *elem = sg_desc->elems; 748 return desc; 749 } 750 751 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb) 752 { 753 struct ionic_tx_stats *stats = q_to_tx_stats(q); 754 struct ionic_desc_info *abort = q->head; 755 struct device *dev = q->lif->ionic->dev; 756 struct ionic_desc_info *rewind = abort; 757 struct ionic_txq_sg_elem *elem; 758 struct ionic_txq_desc *desc; 759 unsigned int frag_left = 0; 760 unsigned int offset = 0; 761 unsigned int len_left; 762 dma_addr_t desc_addr; 763 unsigned int hdrlen; 764 unsigned int nfrags; 765 unsigned int seglen; 766 u64 total_bytes = 0; 767 u64 total_pkts = 0; 768 unsigned int left; 769 unsigned int len; 770 unsigned int mss; 771 skb_frag_t *frag; 772 bool start, done; 773 bool outer_csum; 774 bool has_vlan; 775 u16 desc_len; 776 u8 desc_nsge; 777 u16 vlan_tci; 778 bool encap; 779 int err; 780 781 mss = skb_shinfo(skb)->gso_size; 782 nfrags = skb_shinfo(skb)->nr_frags; 783 len_left = skb->len - skb_headlen(skb); 784 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) || 785 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM); 786 has_vlan = !!skb_vlan_tag_present(skb); 787 vlan_tci = skb_vlan_tag_get(skb); 788 encap = skb->encapsulation; 789 790 /* Preload inner-most TCP csum field with IP pseudo hdr 791 * calculated with IP length set to zero. HW will later 792 * add in length to each TCP segment resulting from the TSO. 793 */ 794 795 if (encap) 796 err = ionic_tx_tcp_inner_pseudo_csum(skb); 797 else 798 err = ionic_tx_tcp_pseudo_csum(skb); 799 if (err) 800 return err; 801 802 if (encap) 803 hdrlen = skb_inner_transport_header(skb) - skb->data + 804 inner_tcp_hdrlen(skb); 805 else 806 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); 807 808 seglen = hdrlen + mss; 809 left = skb_headlen(skb); 810 811 desc = ionic_tx_tso_next(q, &elem); 812 start = true; 813 814 /* Chop skb->data up into desc segments */ 815 816 while (left > 0) { 817 len = min(seglen, left); 818 frag_left = seglen - len; 819 desc_addr = ionic_tx_map_single(q, skb->data + offset, len); 820 if (dma_mapping_error(dev, desc_addr)) 821 goto err_out_abort; 822 desc_len = len; 823 desc_nsge = 0; 824 left -= len; 825 offset += len; 826 if (nfrags > 0 && frag_left > 0) 827 continue; 828 done = (nfrags == 0 && left == 0); 829 ionic_tx_tso_post(q, desc, skb, 830 desc_addr, desc_nsge, desc_len, 831 hdrlen, mss, 832 outer_csum, 833 vlan_tci, has_vlan, 834 start, done); 835 total_pkts++; 836 total_bytes += start ? len : len + hdrlen; 837 desc = ionic_tx_tso_next(q, &elem); 838 start = false; 839 seglen = mss; 840 } 841 842 /* Chop skb frags into desc segments */ 843 844 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 845 offset = 0; 846 left = skb_frag_size(frag); 847 len_left -= left; 848 nfrags--; 849 stats->frags++; 850 851 while (left > 0) { 852 if (frag_left > 0) { 853 len = min(frag_left, left); 854 frag_left -= len; 855 elem->addr = 856 cpu_to_le64(ionic_tx_map_frag(q, frag, 857 offset, len)); 858 if (dma_mapping_error(dev, elem->addr)) 859 goto err_out_abort; 860 elem->len = cpu_to_le16(len); 861 elem++; 862 desc_nsge++; 863 left -= len; 864 offset += len; 865 if (nfrags > 0 && frag_left > 0) 866 continue; 867 done = (nfrags == 0 && left == 0); 868 ionic_tx_tso_post(q, desc, skb, desc_addr, 869 desc_nsge, desc_len, 870 hdrlen, mss, outer_csum, 871 vlan_tci, has_vlan, 872 start, done); 873 total_pkts++; 874 total_bytes += start ? len : len + hdrlen; 875 desc = ionic_tx_tso_next(q, &elem); 876 start = false; 877 } else { 878 len = min(mss, left); 879 frag_left = mss - len; 880 desc_addr = ionic_tx_map_frag(q, frag, 881 offset, len); 882 if (dma_mapping_error(dev, desc_addr)) 883 goto err_out_abort; 884 desc_len = len; 885 desc_nsge = 0; 886 left -= len; 887 offset += len; 888 if (nfrags > 0 && frag_left > 0) 889 continue; 890 done = (nfrags == 0 && left == 0); 891 ionic_tx_tso_post(q, desc, skb, desc_addr, 892 desc_nsge, desc_len, 893 hdrlen, mss, outer_csum, 894 vlan_tci, has_vlan, 895 start, done); 896 total_pkts++; 897 total_bytes += start ? len : len + hdrlen; 898 desc = ionic_tx_tso_next(q, &elem); 899 start = false; 900 } 901 } 902 } 903 904 stats->pkts += total_pkts; 905 stats->bytes += total_bytes; 906 stats->tso++; 907 stats->tso_bytes += total_bytes; 908 909 return 0; 910 911 err_out_abort: 912 while (rewind->desc != q->head->desc) { 913 ionic_tx_clean(q, rewind, NULL, NULL); 914 rewind = rewind->next; 915 } 916 q->head = abort; 917 918 return -ENOMEM; 919 } 920 921 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb) 922 { 923 struct ionic_tx_stats *stats = q_to_tx_stats(q); 924 struct ionic_txq_desc *desc = q->head->desc; 925 struct device *dev = q->lif->ionic->dev; 926 dma_addr_t dma_addr; 927 bool has_vlan; 928 u8 flags = 0; 929 bool encap; 930 u64 cmd; 931 932 has_vlan = !!skb_vlan_tag_present(skb); 933 encap = skb->encapsulation; 934 935 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 936 if (dma_mapping_error(dev, dma_addr)) 937 return -ENOMEM; 938 939 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 940 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 941 942 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL, 943 flags, skb_shinfo(skb)->nr_frags, dma_addr); 944 desc->cmd = cpu_to_le64(cmd); 945 desc->len = cpu_to_le16(skb_headlen(skb)); 946 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb)); 947 desc->csum_offset = cpu_to_le16(skb->csum_offset); 948 if (has_vlan) { 949 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 950 stats->vlan_inserted++; 951 } 952 953 if (skb->csum_not_inet) 954 stats->crc32_csum++; 955 else 956 stats->csum++; 957 958 return 0; 959 } 960 961 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb) 962 { 963 struct ionic_tx_stats *stats = q_to_tx_stats(q); 964 struct ionic_txq_desc *desc = q->head->desc; 965 struct device *dev = q->lif->ionic->dev; 966 dma_addr_t dma_addr; 967 bool has_vlan; 968 u8 flags = 0; 969 bool encap; 970 u64 cmd; 971 972 has_vlan = !!skb_vlan_tag_present(skb); 973 encap = skb->encapsulation; 974 975 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 976 if (dma_mapping_error(dev, dma_addr)) 977 return -ENOMEM; 978 979 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 980 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 981 982 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE, 983 flags, skb_shinfo(skb)->nr_frags, dma_addr); 984 desc->cmd = cpu_to_le64(cmd); 985 desc->len = cpu_to_le16(skb_headlen(skb)); 986 if (has_vlan) { 987 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 988 stats->vlan_inserted++; 989 } 990 991 stats->csum_none++; 992 993 return 0; 994 } 995 996 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb) 997 { 998 struct ionic_txq_sg_desc *sg_desc = q->head->sg_desc; 999 unsigned int len_left = skb->len - skb_headlen(skb); 1000 struct ionic_txq_sg_elem *elem = sg_desc->elems; 1001 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1002 struct device *dev = q->lif->ionic->dev; 1003 dma_addr_t dma_addr; 1004 skb_frag_t *frag; 1005 u16 len; 1006 1007 for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) { 1008 len = skb_frag_size(frag); 1009 elem->len = cpu_to_le16(len); 1010 dma_addr = ionic_tx_map_frag(q, frag, 0, len); 1011 if (dma_mapping_error(dev, dma_addr)) 1012 return -ENOMEM; 1013 elem->addr = cpu_to_le64(dma_addr); 1014 len_left -= len; 1015 stats->frags++; 1016 } 1017 1018 return 0; 1019 } 1020 1021 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb) 1022 { 1023 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1024 int err; 1025 1026 /* set up the initial descriptor */ 1027 if (skb->ip_summed == CHECKSUM_PARTIAL) 1028 err = ionic_tx_calc_csum(q, skb); 1029 else 1030 err = ionic_tx_calc_no_csum(q, skb); 1031 if (err) 1032 return err; 1033 1034 /* add frags */ 1035 err = ionic_tx_skb_frags(q, skb); 1036 if (err) 1037 return err; 1038 1039 skb_tx_timestamp(skb); 1040 stats->pkts++; 1041 stats->bytes += skb->len; 1042 1043 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 1044 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 1045 1046 return 0; 1047 } 1048 1049 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) 1050 { 1051 int sg_elems = q->lif->qtype_info[IONIC_QTYPE_TXQ].max_sg_elems; 1052 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1053 int err; 1054 1055 /* If TSO, need roundup(skb->len/mss) descs */ 1056 if (skb_is_gso(skb)) 1057 return (skb->len / skb_shinfo(skb)->gso_size) + 1; 1058 1059 /* If non-TSO, just need 1 desc and nr_frags sg elems */ 1060 if (skb_shinfo(skb)->nr_frags <= sg_elems) 1061 return 1; 1062 1063 /* Too many frags, so linearize */ 1064 err = skb_linearize(skb); 1065 if (err) 1066 return err; 1067 1068 stats->linearize++; 1069 1070 /* Need 1 desc and zero sg elems */ 1071 return 1; 1072 } 1073 1074 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs) 1075 { 1076 int stopped = 0; 1077 1078 if (unlikely(!ionic_q_has_space(q, ndescs))) { 1079 netif_stop_subqueue(q->lif->netdev, q->index); 1080 q->stop++; 1081 stopped = 1; 1082 1083 /* Might race with ionic_tx_clean, check again */ 1084 smp_rmb(); 1085 if (ionic_q_has_space(q, ndescs)) { 1086 netif_wake_subqueue(q->lif->netdev, q->index); 1087 stopped = 0; 1088 } 1089 } 1090 1091 return stopped; 1092 } 1093 1094 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev) 1095 { 1096 u16 queue_index = skb_get_queue_mapping(skb); 1097 struct ionic_lif *lif = netdev_priv(netdev); 1098 struct ionic_queue *q; 1099 int ndescs; 1100 int err; 1101 1102 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) { 1103 dev_kfree_skb(skb); 1104 return NETDEV_TX_OK; 1105 } 1106 1107 if (unlikely(!lif_to_txqcq(lif, queue_index))) 1108 queue_index = 0; 1109 q = lif_to_txq(lif, queue_index); 1110 1111 ndescs = ionic_tx_descs_needed(q, skb); 1112 if (ndescs < 0) 1113 goto err_out_drop; 1114 1115 if (unlikely(ionic_maybe_stop_tx(q, ndescs))) 1116 return NETDEV_TX_BUSY; 1117 1118 if (skb_is_gso(skb)) 1119 err = ionic_tx_tso(q, skb); 1120 else 1121 err = ionic_tx(q, skb); 1122 1123 if (err) 1124 goto err_out_drop; 1125 1126 /* Stop the queue if there aren't descriptors for the next packet. 1127 * Since our SG lists per descriptor take care of most of the possible 1128 * fragmentation, we don't need to have many descriptors available. 1129 */ 1130 ionic_maybe_stop_tx(q, 4); 1131 1132 return NETDEV_TX_OK; 1133 1134 err_out_drop: 1135 q->stop++; 1136 q->drop++; 1137 dev_kfree_skb(skb); 1138 return NETDEV_TX_OK; 1139 } 1140