1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ip.h> 5 #include <linux/ipv6.h> 6 #include <linux/if_vlan.h> 7 #include <net/ip6_checksum.h> 8 9 #include "ionic.h" 10 #include "ionic_lif.h" 11 #include "ionic_txrx.h" 12 13 14 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 15 16 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell, 17 ionic_desc_cb cb_func, void *cb_arg) 18 { 19 DEBUG_STATS_TXQ_POST(q, ring_dbell); 20 21 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 22 } 23 24 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell, 25 ionic_desc_cb cb_func, void *cb_arg) 26 { 27 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 28 29 DEBUG_STATS_RX_BUFF_CNT(q); 30 } 31 32 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q) 33 { 34 return netdev_get_tx_queue(q->lif->netdev, q->index); 35 } 36 37 static void ionic_rx_buf_reset(struct ionic_buf_info *buf_info) 38 { 39 buf_info->page = NULL; 40 buf_info->page_offset = 0; 41 buf_info->dma_addr = 0; 42 } 43 44 static int ionic_rx_page_alloc(struct ionic_queue *q, 45 struct ionic_buf_info *buf_info) 46 { 47 struct net_device *netdev = q->lif->netdev; 48 struct ionic_rx_stats *stats; 49 struct device *dev; 50 51 dev = q->dev; 52 stats = q_to_rx_stats(q); 53 54 if (unlikely(!buf_info)) { 55 net_err_ratelimited("%s: %s invalid buf_info in alloc\n", 56 netdev->name, q->name); 57 return -EINVAL; 58 } 59 60 buf_info->page = alloc_pages(IONIC_PAGE_GFP_MASK, 0); 61 if (unlikely(!buf_info->page)) { 62 net_err_ratelimited("%s: %s page alloc failed\n", 63 netdev->name, q->name); 64 stats->alloc_err++; 65 return -ENOMEM; 66 } 67 buf_info->page_offset = 0; 68 69 buf_info->dma_addr = dma_map_page(dev, buf_info->page, buf_info->page_offset, 70 IONIC_PAGE_SIZE, DMA_FROM_DEVICE); 71 if (unlikely(dma_mapping_error(dev, buf_info->dma_addr))) { 72 __free_pages(buf_info->page, 0); 73 ionic_rx_buf_reset(buf_info); 74 net_err_ratelimited("%s: %s dma map failed\n", 75 netdev->name, q->name); 76 stats->dma_map_err++; 77 return -EIO; 78 } 79 80 return 0; 81 } 82 83 static void ionic_rx_page_free(struct ionic_queue *q, 84 struct ionic_buf_info *buf_info) 85 { 86 struct net_device *netdev = q->lif->netdev; 87 struct device *dev = q->dev; 88 89 if (unlikely(!buf_info)) { 90 net_err_ratelimited("%s: %s invalid buf_info in free\n", 91 netdev->name, q->name); 92 return; 93 } 94 95 if (!buf_info->page) 96 return; 97 98 dma_unmap_page(dev, buf_info->dma_addr, IONIC_PAGE_SIZE, DMA_FROM_DEVICE); 99 __free_pages(buf_info->page, 0); 100 ionic_rx_buf_reset(buf_info); 101 } 102 103 static bool ionic_rx_buf_recycle(struct ionic_queue *q, 104 struct ionic_buf_info *buf_info, u32 used) 105 { 106 u32 size; 107 108 /* don't re-use pages allocated in low-mem condition */ 109 if (page_is_pfmemalloc(buf_info->page)) 110 return false; 111 112 /* don't re-use buffers from non-local numa nodes */ 113 if (page_to_nid(buf_info->page) != numa_mem_id()) 114 return false; 115 116 size = ALIGN(used, IONIC_PAGE_SPLIT_SZ); 117 buf_info->page_offset += size; 118 if (buf_info->page_offset >= IONIC_PAGE_SIZE) 119 return false; 120 121 get_page(buf_info->page); 122 123 return true; 124 } 125 126 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q, 127 struct ionic_desc_info *desc_info, 128 struct ionic_rxq_comp *comp) 129 { 130 struct net_device *netdev = q->lif->netdev; 131 struct ionic_buf_info *buf_info; 132 struct ionic_rx_stats *stats; 133 struct device *dev = q->dev; 134 struct sk_buff *skb; 135 unsigned int i; 136 u16 frag_len; 137 u16 len; 138 139 stats = q_to_rx_stats(q); 140 141 buf_info = &desc_info->bufs[0]; 142 len = le16_to_cpu(comp->len); 143 144 prefetch(buf_info->page); 145 146 skb = napi_get_frags(&q_to_qcq(q)->napi); 147 if (unlikely(!skb)) { 148 net_warn_ratelimited("%s: SKB alloc failed on %s!\n", 149 netdev->name, q->name); 150 stats->alloc_err++; 151 return NULL; 152 } 153 154 i = comp->num_sg_elems + 1; 155 do { 156 if (unlikely(!buf_info->page)) { 157 dev_kfree_skb(skb); 158 return NULL; 159 } 160 161 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset); 162 len -= frag_len; 163 164 dma_sync_single_for_cpu(dev, 165 buf_info->dma_addr + buf_info->page_offset, 166 frag_len, DMA_FROM_DEVICE); 167 168 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 169 buf_info->page, buf_info->page_offset, frag_len, 170 IONIC_PAGE_SIZE); 171 172 if (!ionic_rx_buf_recycle(q, buf_info, frag_len)) { 173 dma_unmap_page(dev, buf_info->dma_addr, 174 IONIC_PAGE_SIZE, DMA_FROM_DEVICE); 175 ionic_rx_buf_reset(buf_info); 176 } 177 178 buf_info++; 179 180 i--; 181 } while (i > 0); 182 183 return skb; 184 } 185 186 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q, 187 struct ionic_desc_info *desc_info, 188 struct ionic_rxq_comp *comp) 189 { 190 struct net_device *netdev = q->lif->netdev; 191 struct ionic_buf_info *buf_info; 192 struct ionic_rx_stats *stats; 193 struct device *dev = q->dev; 194 struct sk_buff *skb; 195 u16 len; 196 197 stats = q_to_rx_stats(q); 198 199 buf_info = &desc_info->bufs[0]; 200 len = le16_to_cpu(comp->len); 201 202 skb = napi_alloc_skb(&q_to_qcq(q)->napi, len); 203 if (unlikely(!skb)) { 204 net_warn_ratelimited("%s: SKB alloc failed on %s!\n", 205 netdev->name, q->name); 206 stats->alloc_err++; 207 return NULL; 208 } 209 210 if (unlikely(!buf_info->page)) { 211 dev_kfree_skb(skb); 212 return NULL; 213 } 214 215 dma_sync_single_for_cpu(dev, buf_info->dma_addr + buf_info->page_offset, 216 len, DMA_FROM_DEVICE); 217 skb_copy_to_linear_data(skb, page_address(buf_info->page) + buf_info->page_offset, len); 218 dma_sync_single_for_device(dev, buf_info->dma_addr + buf_info->page_offset, 219 len, DMA_FROM_DEVICE); 220 221 skb_put(skb, len); 222 skb->protocol = eth_type_trans(skb, q->lif->netdev); 223 224 return skb; 225 } 226 227 static void ionic_rx_clean(struct ionic_queue *q, 228 struct ionic_desc_info *desc_info, 229 struct ionic_cq_info *cq_info, 230 void *cb_arg) 231 { 232 struct ionic_rxq_comp *comp = cq_info->rxcq; 233 struct net_device *netdev = q->lif->netdev; 234 struct ionic_qcq *qcq = q_to_qcq(q); 235 struct ionic_rx_stats *stats; 236 struct sk_buff *skb; 237 238 stats = q_to_rx_stats(q); 239 240 if (comp->status) { 241 stats->dropped++; 242 return; 243 } 244 245 stats->pkts++; 246 stats->bytes += le16_to_cpu(comp->len); 247 248 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 249 skb = ionic_rx_copybreak(q, desc_info, comp); 250 else 251 skb = ionic_rx_frags(q, desc_info, comp); 252 253 if (unlikely(!skb)) { 254 stats->dropped++; 255 return; 256 } 257 258 skb_record_rx_queue(skb, q->index); 259 260 if (likely(netdev->features & NETIF_F_RXHASH)) { 261 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) { 262 case IONIC_PKT_TYPE_IPV4: 263 case IONIC_PKT_TYPE_IPV6: 264 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 265 PKT_HASH_TYPE_L3); 266 break; 267 case IONIC_PKT_TYPE_IPV4_TCP: 268 case IONIC_PKT_TYPE_IPV6_TCP: 269 case IONIC_PKT_TYPE_IPV4_UDP: 270 case IONIC_PKT_TYPE_IPV6_UDP: 271 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 272 PKT_HASH_TYPE_L4); 273 break; 274 } 275 } 276 277 if (likely(netdev->features & NETIF_F_RXCSUM)) { 278 if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 279 skb->ip_summed = CHECKSUM_COMPLETE; 280 skb->csum = (__force __wsum)le16_to_cpu(comp->csum); 281 stats->csum_complete++; 282 } 283 } else { 284 stats->csum_none++; 285 } 286 287 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) || 288 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) || 289 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))) 290 stats->csum_error++; 291 292 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 293 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) { 294 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 295 le16_to_cpu(comp->vlan_tci)); 296 stats->vlan_stripped++; 297 } 298 299 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 300 napi_gro_receive(&qcq->napi, skb); 301 else 302 napi_gro_frags(&qcq->napi); 303 } 304 305 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 306 { 307 struct ionic_rxq_comp *comp = cq_info->rxcq; 308 struct ionic_queue *q = cq->bound_q; 309 struct ionic_desc_info *desc_info; 310 311 if (!color_match(comp->pkt_type_color, cq->done_color)) 312 return false; 313 314 /* check for empty queue */ 315 if (q->tail_idx == q->head_idx) 316 return false; 317 318 if (q->tail_idx != le16_to_cpu(comp->comp_index)) 319 return false; 320 321 desc_info = &q->info[q->tail_idx]; 322 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 323 324 /* clean the related q entry, only one per qc completion */ 325 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg); 326 327 desc_info->cb = NULL; 328 desc_info->cb_arg = NULL; 329 330 return true; 331 } 332 333 void ionic_rx_fill(struct ionic_queue *q) 334 { 335 struct net_device *netdev = q->lif->netdev; 336 struct ionic_desc_info *desc_info; 337 struct ionic_rxq_sg_desc *sg_desc; 338 struct ionic_rxq_sg_elem *sg_elem; 339 struct ionic_buf_info *buf_info; 340 struct ionic_rxq_desc *desc; 341 unsigned int remain_len; 342 unsigned int frag_len; 343 unsigned int nfrags; 344 unsigned int i, j; 345 unsigned int len; 346 347 len = netdev->mtu + ETH_HLEN + VLAN_HLEN; 348 349 for (i = ionic_q_space_avail(q); i; i--) { 350 nfrags = 0; 351 remain_len = len; 352 desc_info = &q->info[q->head_idx]; 353 desc = desc_info->desc; 354 buf_info = &desc_info->bufs[0]; 355 356 if (!buf_info->page) { /* alloc a new buffer? */ 357 if (unlikely(ionic_rx_page_alloc(q, buf_info))) { 358 desc->addr = 0; 359 desc->len = 0; 360 return; 361 } 362 } 363 364 /* fill main descriptor - buf[0] */ 365 desc->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset); 366 frag_len = min_t(u16, len, IONIC_PAGE_SIZE - buf_info->page_offset); 367 desc->len = cpu_to_le16(frag_len); 368 remain_len -= frag_len; 369 buf_info++; 370 nfrags++; 371 372 /* fill sg descriptors - buf[1..n] */ 373 sg_desc = desc_info->sg_desc; 374 for (j = 0; remain_len > 0 && j < q->max_sg_elems; j++) { 375 sg_elem = &sg_desc->elems[j]; 376 if (!buf_info->page) { /* alloc a new sg buffer? */ 377 if (unlikely(ionic_rx_page_alloc(q, buf_info))) { 378 sg_elem->addr = 0; 379 sg_elem->len = 0; 380 return; 381 } 382 } 383 384 sg_elem->addr = cpu_to_le64(buf_info->dma_addr + buf_info->page_offset); 385 frag_len = min_t(u16, remain_len, IONIC_PAGE_SIZE - buf_info->page_offset); 386 sg_elem->len = cpu_to_le16(frag_len); 387 remain_len -= frag_len; 388 buf_info++; 389 nfrags++; 390 } 391 392 /* clear end sg element as a sentinel */ 393 if (j < q->max_sg_elems) { 394 sg_elem = &sg_desc->elems[j]; 395 memset(sg_elem, 0, sizeof(*sg_elem)); 396 } 397 398 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG : 399 IONIC_RXQ_DESC_OPCODE_SIMPLE; 400 desc_info->nbufs = nfrags; 401 402 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 403 } 404 405 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type, 406 q->dbval | q->head_idx); 407 } 408 409 void ionic_rx_empty(struct ionic_queue *q) 410 { 411 struct ionic_desc_info *desc_info; 412 struct ionic_buf_info *buf_info; 413 unsigned int i, j; 414 415 for (i = 0; i < q->num_descs; i++) { 416 desc_info = &q->info[i]; 417 for (j = 0; j < IONIC_RX_MAX_SG_ELEMS + 1; j++) { 418 buf_info = &desc_info->bufs[j]; 419 if (buf_info->page) 420 ionic_rx_page_free(q, buf_info); 421 } 422 423 desc_info->nbufs = 0; 424 desc_info->cb = NULL; 425 desc_info->cb_arg = NULL; 426 } 427 428 q->head_idx = 0; 429 q->tail_idx = 0; 430 } 431 432 static void ionic_dim_update(struct ionic_qcq *qcq) 433 { 434 struct dim_sample dim_sample; 435 struct ionic_lif *lif; 436 unsigned int qi; 437 438 if (!qcq->intr.dim_coal_hw) 439 return; 440 441 lif = qcq->q.lif; 442 qi = qcq->cq.bound_q->index; 443 444 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 445 lif->rxqcqs[qi]->intr.index, 446 qcq->intr.dim_coal_hw); 447 448 dim_update_sample(qcq->cq.bound_intr->rearm_count, 449 lif->txqstats[qi].pkts, 450 lif->txqstats[qi].bytes, 451 &dim_sample); 452 453 net_dim(&qcq->dim, dim_sample); 454 } 455 456 int ionic_tx_napi(struct napi_struct *napi, int budget) 457 { 458 struct ionic_qcq *qcq = napi_to_qcq(napi); 459 struct ionic_cq *cq = napi_to_cq(napi); 460 struct ionic_dev *idev; 461 struct ionic_lif *lif; 462 u32 work_done = 0; 463 u32 flags = 0; 464 465 lif = cq->bound_q->lif; 466 idev = &lif->ionic->idev; 467 468 work_done = ionic_cq_service(cq, budget, 469 ionic_tx_service, NULL, NULL); 470 471 if (work_done < budget && napi_complete_done(napi, work_done)) { 472 ionic_dim_update(qcq); 473 flags |= IONIC_INTR_CRED_UNMASK; 474 cq->bound_intr->rearm_count++; 475 } 476 477 if (work_done || flags) { 478 flags |= IONIC_INTR_CRED_RESET_COALESCE; 479 ionic_intr_credits(idev->intr_ctrl, 480 cq->bound_intr->index, 481 work_done, flags); 482 } 483 484 DEBUG_STATS_NAPI_POLL(qcq, work_done); 485 486 return work_done; 487 } 488 489 int ionic_rx_napi(struct napi_struct *napi, int budget) 490 { 491 struct ionic_qcq *qcq = napi_to_qcq(napi); 492 struct ionic_cq *cq = napi_to_cq(napi); 493 struct ionic_dev *idev; 494 struct ionic_lif *lif; 495 u16 rx_fill_threshold; 496 u32 work_done = 0; 497 u32 flags = 0; 498 499 lif = cq->bound_q->lif; 500 idev = &lif->ionic->idev; 501 502 work_done = ionic_cq_service(cq, budget, 503 ionic_rx_service, NULL, NULL); 504 505 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD, 506 cq->num_descs / IONIC_RX_FILL_DIV); 507 if (work_done && ionic_q_space_avail(cq->bound_q) >= rx_fill_threshold) 508 ionic_rx_fill(cq->bound_q); 509 510 if (work_done < budget && napi_complete_done(napi, work_done)) { 511 ionic_dim_update(qcq); 512 flags |= IONIC_INTR_CRED_UNMASK; 513 cq->bound_intr->rearm_count++; 514 } 515 516 if (work_done || flags) { 517 flags |= IONIC_INTR_CRED_RESET_COALESCE; 518 ionic_intr_credits(idev->intr_ctrl, 519 cq->bound_intr->index, 520 work_done, flags); 521 } 522 523 DEBUG_STATS_NAPI_POLL(qcq, work_done); 524 525 return work_done; 526 } 527 528 int ionic_txrx_napi(struct napi_struct *napi, int budget) 529 { 530 struct ionic_qcq *qcq = napi_to_qcq(napi); 531 struct ionic_cq *rxcq = napi_to_cq(napi); 532 unsigned int qi = rxcq->bound_q->index; 533 struct ionic_dev *idev; 534 struct ionic_lif *lif; 535 struct ionic_cq *txcq; 536 u16 rx_fill_threshold; 537 u32 rx_work_done = 0; 538 u32 tx_work_done = 0; 539 u32 flags = 0; 540 541 lif = rxcq->bound_q->lif; 542 idev = &lif->ionic->idev; 543 txcq = &lif->txqcqs[qi]->cq; 544 545 tx_work_done = ionic_cq_service(txcq, IONIC_TX_BUDGET_DEFAULT, 546 ionic_tx_service, NULL, NULL); 547 548 rx_work_done = ionic_cq_service(rxcq, budget, 549 ionic_rx_service, NULL, NULL); 550 551 rx_fill_threshold = min_t(u16, IONIC_RX_FILL_THRESHOLD, 552 rxcq->num_descs / IONIC_RX_FILL_DIV); 553 if (rx_work_done && ionic_q_space_avail(rxcq->bound_q) >= rx_fill_threshold) 554 ionic_rx_fill(rxcq->bound_q); 555 556 if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) { 557 ionic_dim_update(qcq); 558 flags |= IONIC_INTR_CRED_UNMASK; 559 rxcq->bound_intr->rearm_count++; 560 } 561 562 if (rx_work_done || flags) { 563 flags |= IONIC_INTR_CRED_RESET_COALESCE; 564 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index, 565 tx_work_done + rx_work_done, flags); 566 } 567 568 DEBUG_STATS_NAPI_POLL(qcq, rx_work_done); 569 DEBUG_STATS_NAPI_POLL(qcq, tx_work_done); 570 571 return rx_work_done; 572 } 573 574 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, 575 void *data, size_t len) 576 { 577 struct ionic_tx_stats *stats = q_to_tx_stats(q); 578 struct device *dev = q->dev; 579 dma_addr_t dma_addr; 580 581 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE); 582 if (dma_mapping_error(dev, dma_addr)) { 583 net_warn_ratelimited("%s: DMA single map failed on %s!\n", 584 q->lif->netdev->name, q->name); 585 stats->dma_map_err++; 586 return 0; 587 } 588 return dma_addr; 589 } 590 591 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, 592 const skb_frag_t *frag, 593 size_t offset, size_t len) 594 { 595 struct ionic_tx_stats *stats = q_to_tx_stats(q); 596 struct device *dev = q->dev; 597 dma_addr_t dma_addr; 598 599 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE); 600 if (dma_mapping_error(dev, dma_addr)) { 601 net_warn_ratelimited("%s: DMA frag map failed on %s!\n", 602 q->lif->netdev->name, q->name); 603 stats->dma_map_err++; 604 } 605 return dma_addr; 606 } 607 608 static int ionic_tx_map_skb(struct ionic_queue *q, struct sk_buff *skb, 609 struct ionic_desc_info *desc_info) 610 { 611 struct ionic_buf_info *buf_info = desc_info->bufs; 612 struct device *dev = q->dev; 613 dma_addr_t dma_addr; 614 unsigned int nfrags; 615 skb_frag_t *frag; 616 int frag_idx; 617 618 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 619 if (dma_mapping_error(dev, dma_addr)) 620 return -EIO; 621 buf_info->dma_addr = dma_addr; 622 buf_info->len = skb_headlen(skb); 623 buf_info++; 624 625 frag = skb_shinfo(skb)->frags; 626 nfrags = skb_shinfo(skb)->nr_frags; 627 for (frag_idx = 0; frag_idx < nfrags; frag_idx++, frag++) { 628 dma_addr = ionic_tx_map_frag(q, frag, 0, skb_frag_size(frag)); 629 if (dma_mapping_error(dev, dma_addr)) 630 goto dma_fail; 631 buf_info->dma_addr = dma_addr; 632 buf_info->len = skb_frag_size(frag); 633 buf_info++; 634 } 635 636 desc_info->nbufs = 1 + nfrags; 637 638 return 0; 639 640 dma_fail: 641 /* unwind the frag mappings and the head mapping */ 642 while (frag_idx > 0) { 643 frag_idx--; 644 buf_info--; 645 dma_unmap_page(dev, buf_info->dma_addr, 646 buf_info->len, DMA_TO_DEVICE); 647 } 648 dma_unmap_single(dev, buf_info->dma_addr, buf_info->len, DMA_TO_DEVICE); 649 return -EIO; 650 } 651 652 static void ionic_tx_clean(struct ionic_queue *q, 653 struct ionic_desc_info *desc_info, 654 struct ionic_cq_info *cq_info, 655 void *cb_arg) 656 { 657 struct ionic_buf_info *buf_info = desc_info->bufs; 658 struct ionic_tx_stats *stats = q_to_tx_stats(q); 659 struct device *dev = q->dev; 660 u16 queue_index; 661 unsigned int i; 662 663 if (desc_info->nbufs) { 664 dma_unmap_single(dev, (dma_addr_t)buf_info->dma_addr, 665 buf_info->len, DMA_TO_DEVICE); 666 buf_info++; 667 for (i = 1; i < desc_info->nbufs; i++, buf_info++) 668 dma_unmap_page(dev, (dma_addr_t)buf_info->dma_addr, 669 buf_info->len, DMA_TO_DEVICE); 670 } 671 672 if (cb_arg) { 673 struct sk_buff *skb = cb_arg; 674 675 queue_index = skb_get_queue_mapping(skb); 676 if (unlikely(__netif_subqueue_stopped(q->lif->netdev, 677 queue_index))) { 678 netif_wake_subqueue(q->lif->netdev, queue_index); 679 q->wake++; 680 } 681 682 desc_info->bytes = skb->len; 683 stats->clean++; 684 685 dev_consume_skb_any(skb); 686 } 687 } 688 689 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 690 { 691 struct ionic_txq_comp *comp = cq_info->txcq; 692 struct ionic_queue *q = cq->bound_q; 693 struct ionic_desc_info *desc_info; 694 int bytes = 0; 695 int pkts = 0; 696 u16 index; 697 698 if (!color_match(comp->color, cq->done_color)) 699 return false; 700 701 /* clean the related q entries, there could be 702 * several q entries completed for each cq completion 703 */ 704 do { 705 desc_info = &q->info[q->tail_idx]; 706 desc_info->bytes = 0; 707 index = q->tail_idx; 708 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 709 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg); 710 if (desc_info->cb_arg) { 711 pkts++; 712 bytes += desc_info->bytes; 713 } 714 desc_info->cb = NULL; 715 desc_info->cb_arg = NULL; 716 } while (index != le16_to_cpu(comp->comp_index)); 717 718 if (pkts && bytes) 719 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes); 720 721 return true; 722 } 723 724 void ionic_tx_flush(struct ionic_cq *cq) 725 { 726 struct ionic_dev *idev = &cq->lif->ionic->idev; 727 u32 work_done; 728 729 work_done = ionic_cq_service(cq, cq->num_descs, 730 ionic_tx_service, NULL, NULL); 731 if (work_done) 732 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 733 work_done, IONIC_INTR_CRED_RESET_COALESCE); 734 } 735 736 void ionic_tx_empty(struct ionic_queue *q) 737 { 738 struct ionic_desc_info *desc_info; 739 int bytes = 0; 740 int pkts = 0; 741 742 /* walk the not completed tx entries, if any */ 743 while (q->head_idx != q->tail_idx) { 744 desc_info = &q->info[q->tail_idx]; 745 desc_info->bytes = 0; 746 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 747 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg); 748 if (desc_info->cb_arg) { 749 pkts++; 750 bytes += desc_info->bytes; 751 } 752 desc_info->cb = NULL; 753 desc_info->cb_arg = NULL; 754 } 755 756 if (pkts && bytes) 757 netdev_tx_completed_queue(q_to_ndq(q), pkts, bytes); 758 } 759 760 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb) 761 { 762 int err; 763 764 err = skb_cow_head(skb, 0); 765 if (err) 766 return err; 767 768 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 769 inner_ip_hdr(skb)->check = 0; 770 inner_tcp_hdr(skb)->check = 771 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr, 772 inner_ip_hdr(skb)->daddr, 773 0, IPPROTO_TCP, 0); 774 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 775 inner_tcp_hdr(skb)->check = 776 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr, 777 &inner_ipv6_hdr(skb)->daddr, 778 0, IPPROTO_TCP, 0); 779 } 780 781 return 0; 782 } 783 784 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb) 785 { 786 int err; 787 788 err = skb_cow_head(skb, 0); 789 if (err) 790 return err; 791 792 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 793 ip_hdr(skb)->check = 0; 794 tcp_hdr(skb)->check = 795 ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 796 ip_hdr(skb)->daddr, 797 0, IPPROTO_TCP, 0); 798 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 799 tcp_v6_gso_csum_prep(skb); 800 } 801 802 return 0; 803 } 804 805 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, 806 struct sk_buff *skb, 807 dma_addr_t addr, u8 nsge, u16 len, 808 unsigned int hdrlen, unsigned int mss, 809 bool outer_csum, 810 u16 vlan_tci, bool has_vlan, 811 bool start, bool done) 812 { 813 u8 flags = 0; 814 u64 cmd; 815 816 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 817 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 818 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; 819 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; 820 821 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr); 822 desc->cmd = cpu_to_le64(cmd); 823 desc->len = cpu_to_le16(len); 824 desc->vlan_tci = cpu_to_le16(vlan_tci); 825 desc->hdr_len = cpu_to_le16(hdrlen); 826 desc->mss = cpu_to_le16(mss); 827 828 if (start) { 829 skb_tx_timestamp(skb); 830 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 831 ionic_txq_post(q, false, ionic_tx_clean, skb); 832 } else { 833 ionic_txq_post(q, done, NULL, NULL); 834 } 835 } 836 837 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb) 838 { 839 struct ionic_tx_stats *stats = q_to_tx_stats(q); 840 struct ionic_desc_info *desc_info; 841 struct ionic_buf_info *buf_info; 842 struct ionic_txq_sg_elem *elem; 843 struct ionic_txq_desc *desc; 844 unsigned int chunk_len; 845 unsigned int frag_rem; 846 unsigned int tso_rem; 847 unsigned int seg_rem; 848 dma_addr_t desc_addr; 849 dma_addr_t frag_addr; 850 unsigned int hdrlen; 851 unsigned int len; 852 unsigned int mss; 853 bool start, done; 854 bool outer_csum; 855 bool has_vlan; 856 u16 desc_len; 857 u8 desc_nsge; 858 u16 vlan_tci; 859 bool encap; 860 int err; 861 862 desc_info = &q->info[q->head_idx]; 863 buf_info = desc_info->bufs; 864 865 if (unlikely(ionic_tx_map_skb(q, skb, desc_info))) 866 return -EIO; 867 868 len = skb->len; 869 mss = skb_shinfo(skb)->gso_size; 870 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) || 871 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM); 872 has_vlan = !!skb_vlan_tag_present(skb); 873 vlan_tci = skb_vlan_tag_get(skb); 874 encap = skb->encapsulation; 875 876 /* Preload inner-most TCP csum field with IP pseudo hdr 877 * calculated with IP length set to zero. HW will later 878 * add in length to each TCP segment resulting from the TSO. 879 */ 880 881 if (encap) 882 err = ionic_tx_tcp_inner_pseudo_csum(skb); 883 else 884 err = ionic_tx_tcp_pseudo_csum(skb); 885 if (err) 886 return err; 887 888 if (encap) 889 hdrlen = skb_inner_transport_header(skb) - skb->data + 890 inner_tcp_hdrlen(skb); 891 else 892 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); 893 894 tso_rem = len; 895 seg_rem = min(tso_rem, hdrlen + mss); 896 897 frag_addr = 0; 898 frag_rem = 0; 899 900 start = true; 901 902 while (tso_rem > 0) { 903 desc = NULL; 904 elem = NULL; 905 desc_addr = 0; 906 desc_len = 0; 907 desc_nsge = 0; 908 /* use fragments until we have enough to post a single descriptor */ 909 while (seg_rem > 0) { 910 /* if the fragment is exhausted then move to the next one */ 911 if (frag_rem == 0) { 912 /* grab the next fragment */ 913 frag_addr = buf_info->dma_addr; 914 frag_rem = buf_info->len; 915 buf_info++; 916 } 917 chunk_len = min(frag_rem, seg_rem); 918 if (!desc) { 919 /* fill main descriptor */ 920 desc = desc_info->txq_desc; 921 elem = desc_info->txq_sg_desc->elems; 922 desc_addr = frag_addr; 923 desc_len = chunk_len; 924 } else { 925 /* fill sg descriptor */ 926 elem->addr = cpu_to_le64(frag_addr); 927 elem->len = cpu_to_le16(chunk_len); 928 elem++; 929 desc_nsge++; 930 } 931 frag_addr += chunk_len; 932 frag_rem -= chunk_len; 933 tso_rem -= chunk_len; 934 seg_rem -= chunk_len; 935 } 936 seg_rem = min(tso_rem, mss); 937 done = (tso_rem == 0); 938 /* post descriptor */ 939 ionic_tx_tso_post(q, desc, skb, 940 desc_addr, desc_nsge, desc_len, 941 hdrlen, mss, outer_csum, vlan_tci, has_vlan, 942 start, done); 943 start = false; 944 /* Buffer information is stored with the first tso descriptor */ 945 desc_info = &q->info[q->head_idx]; 946 desc_info->nbufs = 0; 947 } 948 949 stats->pkts += DIV_ROUND_UP(len - hdrlen, mss); 950 stats->bytes += len; 951 stats->tso++; 952 stats->tso_bytes = len; 953 954 return 0; 955 } 956 957 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb, 958 struct ionic_desc_info *desc_info) 959 { 960 struct ionic_txq_desc *desc = desc_info->txq_desc; 961 struct ionic_buf_info *buf_info = desc_info->bufs; 962 struct ionic_tx_stats *stats = q_to_tx_stats(q); 963 bool has_vlan; 964 u8 flags = 0; 965 bool encap; 966 u64 cmd; 967 968 has_vlan = !!skb_vlan_tag_present(skb); 969 encap = skb->encapsulation; 970 971 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 972 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 973 974 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL, 975 flags, skb_shinfo(skb)->nr_frags, 976 buf_info->dma_addr); 977 desc->cmd = cpu_to_le64(cmd); 978 desc->len = cpu_to_le16(buf_info->len); 979 if (has_vlan) { 980 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 981 stats->vlan_inserted++; 982 } else { 983 desc->vlan_tci = 0; 984 } 985 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb)); 986 desc->csum_offset = cpu_to_le16(skb->csum_offset); 987 988 if (skb_csum_is_sctp(skb)) 989 stats->crc32_csum++; 990 else 991 stats->csum++; 992 993 return 0; 994 } 995 996 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb, 997 struct ionic_desc_info *desc_info) 998 { 999 struct ionic_txq_desc *desc = desc_info->txq_desc; 1000 struct ionic_buf_info *buf_info = desc_info->bufs; 1001 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1002 bool has_vlan; 1003 u8 flags = 0; 1004 bool encap; 1005 u64 cmd; 1006 1007 has_vlan = !!skb_vlan_tag_present(skb); 1008 encap = skb->encapsulation; 1009 1010 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 1011 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 1012 1013 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE, 1014 flags, skb_shinfo(skb)->nr_frags, 1015 buf_info->dma_addr); 1016 desc->cmd = cpu_to_le64(cmd); 1017 desc->len = cpu_to_le16(buf_info->len); 1018 if (has_vlan) { 1019 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 1020 stats->vlan_inserted++; 1021 } else { 1022 desc->vlan_tci = 0; 1023 } 1024 desc->csum_start = 0; 1025 desc->csum_offset = 0; 1026 1027 stats->csum_none++; 1028 1029 return 0; 1030 } 1031 1032 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb, 1033 struct ionic_desc_info *desc_info) 1034 { 1035 struct ionic_txq_sg_desc *sg_desc = desc_info->txq_sg_desc; 1036 struct ionic_buf_info *buf_info = &desc_info->bufs[1]; 1037 struct ionic_txq_sg_elem *elem = sg_desc->elems; 1038 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1039 unsigned int i; 1040 1041 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++, buf_info++, elem++) { 1042 elem->addr = cpu_to_le64(buf_info->dma_addr); 1043 elem->len = cpu_to_le16(buf_info->len); 1044 } 1045 1046 stats->frags += skb_shinfo(skb)->nr_frags; 1047 1048 return 0; 1049 } 1050 1051 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb) 1052 { 1053 struct ionic_desc_info *desc_info = &q->info[q->head_idx]; 1054 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1055 int err; 1056 1057 if (unlikely(ionic_tx_map_skb(q, skb, desc_info))) 1058 return -EIO; 1059 1060 /* set up the initial descriptor */ 1061 if (skb->ip_summed == CHECKSUM_PARTIAL) 1062 err = ionic_tx_calc_csum(q, skb, desc_info); 1063 else 1064 err = ionic_tx_calc_no_csum(q, skb, desc_info); 1065 if (err) 1066 return err; 1067 1068 /* add frags */ 1069 err = ionic_tx_skb_frags(q, skb, desc_info); 1070 if (err) 1071 return err; 1072 1073 skb_tx_timestamp(skb); 1074 stats->pkts++; 1075 stats->bytes += skb->len; 1076 1077 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 1078 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 1079 1080 return 0; 1081 } 1082 1083 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) 1084 { 1085 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1086 int err; 1087 1088 /* If TSO, need roundup(skb->len/mss) descs */ 1089 if (skb_is_gso(skb)) 1090 return (skb->len / skb_shinfo(skb)->gso_size) + 1; 1091 1092 /* If non-TSO, just need 1 desc and nr_frags sg elems */ 1093 if (skb_shinfo(skb)->nr_frags <= q->max_sg_elems) 1094 return 1; 1095 1096 /* Too many frags, so linearize */ 1097 err = skb_linearize(skb); 1098 if (err) 1099 return err; 1100 1101 stats->linearize++; 1102 1103 /* Need 1 desc and zero sg elems */ 1104 return 1; 1105 } 1106 1107 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs) 1108 { 1109 int stopped = 0; 1110 1111 if (unlikely(!ionic_q_has_space(q, ndescs))) { 1112 netif_stop_subqueue(q->lif->netdev, q->index); 1113 q->stop++; 1114 stopped = 1; 1115 1116 /* Might race with ionic_tx_clean, check again */ 1117 smp_rmb(); 1118 if (ionic_q_has_space(q, ndescs)) { 1119 netif_wake_subqueue(q->lif->netdev, q->index); 1120 stopped = 0; 1121 } 1122 } 1123 1124 return stopped; 1125 } 1126 1127 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev) 1128 { 1129 u16 queue_index = skb_get_queue_mapping(skb); 1130 struct ionic_lif *lif = netdev_priv(netdev); 1131 struct ionic_queue *q; 1132 int ndescs; 1133 int err; 1134 1135 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) { 1136 dev_kfree_skb(skb); 1137 return NETDEV_TX_OK; 1138 } 1139 1140 if (unlikely(queue_index >= lif->nxqs)) 1141 queue_index = 0; 1142 q = &lif->txqcqs[queue_index]->q; 1143 1144 ndescs = ionic_tx_descs_needed(q, skb); 1145 if (ndescs < 0) 1146 goto err_out_drop; 1147 1148 if (unlikely(ionic_maybe_stop_tx(q, ndescs))) 1149 return NETDEV_TX_BUSY; 1150 1151 if (skb_is_gso(skb)) 1152 err = ionic_tx_tso(q, skb); 1153 else 1154 err = ionic_tx(q, skb); 1155 1156 if (err) 1157 goto err_out_drop; 1158 1159 /* Stop the queue if there aren't descriptors for the next packet. 1160 * Since our SG lists per descriptor take care of most of the possible 1161 * fragmentation, we don't need to have many descriptors available. 1162 */ 1163 ionic_maybe_stop_tx(q, 4); 1164 1165 return NETDEV_TX_OK; 1166 1167 err_out_drop: 1168 q->stop++; 1169 q->drop++; 1170 dev_kfree_skb(skb); 1171 return NETDEV_TX_OK; 1172 } 1173