1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ip.h> 5 #include <linux/ipv6.h> 6 #include <linux/if_vlan.h> 7 #include <net/ip6_checksum.h> 8 9 #include "ionic.h" 10 #include "ionic_lif.h" 11 #include "ionic_txrx.h" 12 13 static void ionic_rx_clean(struct ionic_queue *q, 14 struct ionic_desc_info *desc_info, 15 struct ionic_cq_info *cq_info, 16 void *cb_arg); 17 18 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 19 20 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info); 21 22 static inline void ionic_txq_post(struct ionic_queue *q, bool ring_dbell, 23 ionic_desc_cb cb_func, void *cb_arg) 24 { 25 DEBUG_STATS_TXQ_POST(q, ring_dbell); 26 27 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 28 } 29 30 static inline void ionic_rxq_post(struct ionic_queue *q, bool ring_dbell, 31 ionic_desc_cb cb_func, void *cb_arg) 32 { 33 ionic_q_post(q, ring_dbell, cb_func, cb_arg); 34 35 DEBUG_STATS_RX_BUFF_CNT(q); 36 } 37 38 static inline struct netdev_queue *q_to_ndq(struct ionic_queue *q) 39 { 40 return netdev_get_tx_queue(q->lif->netdev, q->index); 41 } 42 43 static struct sk_buff *ionic_rx_skb_alloc(struct ionic_queue *q, 44 unsigned int len, bool frags) 45 { 46 struct ionic_lif *lif = q->lif; 47 struct ionic_rx_stats *stats; 48 struct net_device *netdev; 49 struct sk_buff *skb; 50 51 netdev = lif->netdev; 52 stats = &q->lif->rxqstats[q->index]; 53 54 if (frags) 55 skb = napi_get_frags(&q_to_qcq(q)->napi); 56 else 57 skb = netdev_alloc_skb_ip_align(netdev, len); 58 59 if (unlikely(!skb)) { 60 net_warn_ratelimited("%s: SKB alloc failed on %s!\n", 61 netdev->name, q->name); 62 stats->alloc_err++; 63 return NULL; 64 } 65 66 return skb; 67 } 68 69 static struct sk_buff *ionic_rx_frags(struct ionic_queue *q, 70 struct ionic_desc_info *desc_info, 71 struct ionic_cq_info *cq_info) 72 { 73 struct ionic_rxq_comp *comp = cq_info->cq_desc; 74 struct device *dev = q->lif->ionic->dev; 75 struct ionic_page_info *page_info; 76 struct sk_buff *skb; 77 unsigned int i; 78 u16 frag_len; 79 u16 len; 80 81 page_info = &desc_info->pages[0]; 82 len = le16_to_cpu(comp->len); 83 84 prefetch(page_address(page_info->page) + NET_IP_ALIGN); 85 86 skb = ionic_rx_skb_alloc(q, len, true); 87 if (unlikely(!skb)) 88 return NULL; 89 90 i = comp->num_sg_elems + 1; 91 do { 92 if (unlikely(!page_info->page)) { 93 struct napi_struct *napi = &q_to_qcq(q)->napi; 94 95 napi->skb = NULL; 96 dev_kfree_skb(skb); 97 return NULL; 98 } 99 100 frag_len = min(len, (u16)PAGE_SIZE); 101 len -= frag_len; 102 103 dma_unmap_page(dev, dma_unmap_addr(page_info, dma_addr), 104 PAGE_SIZE, DMA_FROM_DEVICE); 105 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 106 page_info->page, 0, frag_len, PAGE_SIZE); 107 page_info->page = NULL; 108 page_info++; 109 i--; 110 } while (i > 0); 111 112 return skb; 113 } 114 115 static struct sk_buff *ionic_rx_copybreak(struct ionic_queue *q, 116 struct ionic_desc_info *desc_info, 117 struct ionic_cq_info *cq_info) 118 { 119 struct ionic_rxq_comp *comp = cq_info->cq_desc; 120 struct device *dev = q->lif->ionic->dev; 121 struct ionic_page_info *page_info; 122 struct sk_buff *skb; 123 u16 len; 124 125 page_info = &desc_info->pages[0]; 126 len = le16_to_cpu(comp->len); 127 128 skb = ionic_rx_skb_alloc(q, len, false); 129 if (unlikely(!skb)) 130 return NULL; 131 132 if (unlikely(!page_info->page)) { 133 dev_kfree_skb(skb); 134 return NULL; 135 } 136 137 dma_sync_single_for_cpu(dev, dma_unmap_addr(page_info, dma_addr), 138 len, DMA_FROM_DEVICE); 139 skb_copy_to_linear_data(skb, page_address(page_info->page), len); 140 dma_sync_single_for_device(dev, dma_unmap_addr(page_info, dma_addr), 141 len, DMA_FROM_DEVICE); 142 143 skb_put(skb, len); 144 skb->protocol = eth_type_trans(skb, q->lif->netdev); 145 146 return skb; 147 } 148 149 static void ionic_rx_clean(struct ionic_queue *q, 150 struct ionic_desc_info *desc_info, 151 struct ionic_cq_info *cq_info, 152 void *cb_arg) 153 { 154 struct ionic_rxq_comp *comp = cq_info->cq_desc; 155 struct ionic_qcq *qcq = q_to_qcq(q); 156 struct ionic_rx_stats *stats; 157 struct net_device *netdev; 158 struct sk_buff *skb; 159 160 stats = q_to_rx_stats(q); 161 netdev = q->lif->netdev; 162 163 if (comp->status) { 164 stats->dropped++; 165 return; 166 } 167 168 stats->pkts++; 169 stats->bytes += le16_to_cpu(comp->len); 170 171 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 172 skb = ionic_rx_copybreak(q, desc_info, cq_info); 173 else 174 skb = ionic_rx_frags(q, desc_info, cq_info); 175 176 if (unlikely(!skb)) { 177 stats->dropped++; 178 return; 179 } 180 181 skb_record_rx_queue(skb, q->index); 182 183 if (likely(netdev->features & NETIF_F_RXHASH)) { 184 switch (comp->pkt_type_color & IONIC_RXQ_COMP_PKT_TYPE_MASK) { 185 case IONIC_PKT_TYPE_IPV4: 186 case IONIC_PKT_TYPE_IPV6: 187 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 188 PKT_HASH_TYPE_L3); 189 break; 190 case IONIC_PKT_TYPE_IPV4_TCP: 191 case IONIC_PKT_TYPE_IPV6_TCP: 192 case IONIC_PKT_TYPE_IPV4_UDP: 193 case IONIC_PKT_TYPE_IPV6_UDP: 194 skb_set_hash(skb, le32_to_cpu(comp->rss_hash), 195 PKT_HASH_TYPE_L4); 196 break; 197 } 198 } 199 200 if (likely(netdev->features & NETIF_F_RXCSUM)) { 201 if (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_CALC) { 202 skb->ip_summed = CHECKSUM_COMPLETE; 203 skb->csum = (__wsum)le16_to_cpu(comp->csum); 204 stats->csum_complete++; 205 } 206 } else { 207 stats->csum_none++; 208 } 209 210 if (unlikely((comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_TCP_BAD) || 211 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_UDP_BAD) || 212 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_IP_BAD))) 213 stats->csum_error++; 214 215 if (likely(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) && 216 (comp->csum_flags & IONIC_RXQ_COMP_CSUM_F_VLAN)) { 217 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 218 le16_to_cpu(comp->vlan_tci)); 219 stats->vlan_stripped++; 220 } 221 222 if (le16_to_cpu(comp->len) <= q->lif->rx_copybreak) 223 napi_gro_receive(&qcq->napi, skb); 224 else 225 napi_gro_frags(&qcq->napi); 226 } 227 228 static bool ionic_rx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 229 { 230 struct ionic_rxq_comp *comp = cq_info->cq_desc; 231 struct ionic_queue *q = cq->bound_q; 232 struct ionic_desc_info *desc_info; 233 234 if (!color_match(comp->pkt_type_color, cq->done_color)) 235 return false; 236 237 /* check for empty queue */ 238 if (q->tail_idx == q->head_idx) 239 return false; 240 241 if (q->tail_idx != le16_to_cpu(comp->comp_index)) 242 return false; 243 244 desc_info = &q->info[q->tail_idx]; 245 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 246 247 /* clean the related q entry, only one per qc completion */ 248 ionic_rx_clean(q, desc_info, cq_info, desc_info->cb_arg); 249 250 desc_info->cb = NULL; 251 desc_info->cb_arg = NULL; 252 253 return true; 254 } 255 256 void ionic_rx_flush(struct ionic_cq *cq) 257 { 258 struct ionic_dev *idev = &cq->lif->ionic->idev; 259 u32 work_done; 260 261 work_done = ionic_cq_service(cq, cq->num_descs, 262 ionic_rx_service, NULL, NULL); 263 264 if (work_done) 265 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 266 work_done, IONIC_INTR_CRED_RESET_COALESCE); 267 } 268 269 static int ionic_rx_page_alloc(struct ionic_queue *q, 270 struct ionic_page_info *page_info) 271 { 272 struct ionic_lif *lif = q->lif; 273 struct ionic_rx_stats *stats; 274 struct net_device *netdev; 275 struct device *dev; 276 277 netdev = lif->netdev; 278 dev = lif->ionic->dev; 279 stats = q_to_rx_stats(q); 280 281 if (unlikely(!page_info)) { 282 net_err_ratelimited("%s: %s invalid page_info in alloc\n", 283 netdev->name, q->name); 284 return -EINVAL; 285 } 286 287 page_info->page = dev_alloc_page(); 288 if (unlikely(!page_info->page)) { 289 net_err_ratelimited("%s: %s page alloc failed\n", 290 netdev->name, q->name); 291 stats->alloc_err++; 292 return -ENOMEM; 293 } 294 295 page_info->dma_addr = dma_map_page(dev, page_info->page, 0, PAGE_SIZE, 296 DMA_FROM_DEVICE); 297 if (unlikely(dma_mapping_error(dev, page_info->dma_addr))) { 298 put_page(page_info->page); 299 page_info->dma_addr = 0; 300 page_info->page = NULL; 301 net_err_ratelimited("%s: %s dma map failed\n", 302 netdev->name, q->name); 303 stats->dma_map_err++; 304 return -EIO; 305 } 306 307 return 0; 308 } 309 310 static void ionic_rx_page_free(struct ionic_queue *q, 311 struct ionic_page_info *page_info) 312 { 313 struct ionic_lif *lif = q->lif; 314 struct net_device *netdev; 315 struct device *dev; 316 317 netdev = lif->netdev; 318 dev = lif->ionic->dev; 319 320 if (unlikely(!page_info)) { 321 net_err_ratelimited("%s: %s invalid page_info in free\n", 322 netdev->name, q->name); 323 return; 324 } 325 326 if (unlikely(!page_info->page)) { 327 net_err_ratelimited("%s: %s invalid page in free\n", 328 netdev->name, q->name); 329 return; 330 } 331 332 dma_unmap_page(dev, page_info->dma_addr, PAGE_SIZE, DMA_FROM_DEVICE); 333 334 put_page(page_info->page); 335 page_info->dma_addr = 0; 336 page_info->page = NULL; 337 } 338 339 void ionic_rx_fill(struct ionic_queue *q) 340 { 341 struct net_device *netdev = q->lif->netdev; 342 struct ionic_desc_info *desc_info; 343 struct ionic_page_info *page_info; 344 struct ionic_rxq_sg_desc *sg_desc; 345 struct ionic_rxq_sg_elem *sg_elem; 346 struct ionic_rxq_desc *desc; 347 unsigned int remain_len; 348 unsigned int seg_len; 349 unsigned int nfrags; 350 unsigned int i, j; 351 unsigned int len; 352 353 len = netdev->mtu + ETH_HLEN; 354 nfrags = round_up(len, PAGE_SIZE) / PAGE_SIZE; 355 356 for (i = ionic_q_space_avail(q); i; i--) { 357 remain_len = len; 358 desc_info = &q->info[q->head_idx]; 359 desc = desc_info->desc; 360 sg_desc = desc_info->sg_desc; 361 page_info = &desc_info->pages[0]; 362 363 if (page_info->page) { /* recycle the buffer */ 364 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 365 continue; 366 } 367 368 /* fill main descriptor - pages[0] */ 369 desc->opcode = (nfrags > 1) ? IONIC_RXQ_DESC_OPCODE_SG : 370 IONIC_RXQ_DESC_OPCODE_SIMPLE; 371 desc_info->npages = nfrags; 372 if (unlikely(ionic_rx_page_alloc(q, page_info))) { 373 desc->addr = 0; 374 desc->len = 0; 375 return; 376 } 377 desc->addr = cpu_to_le64(page_info->dma_addr); 378 seg_len = min_t(unsigned int, PAGE_SIZE, len); 379 desc->len = cpu_to_le16(seg_len); 380 remain_len -= seg_len; 381 page_info++; 382 383 /* fill sg descriptors - pages[1..n] */ 384 for (j = 0; j < nfrags - 1; j++) { 385 if (page_info->page) /* recycle the sg buffer */ 386 continue; 387 388 sg_elem = &sg_desc->elems[j]; 389 if (unlikely(ionic_rx_page_alloc(q, page_info))) { 390 sg_elem->addr = 0; 391 sg_elem->len = 0; 392 return; 393 } 394 sg_elem->addr = cpu_to_le64(page_info->dma_addr); 395 seg_len = min_t(unsigned int, PAGE_SIZE, remain_len); 396 sg_elem->len = cpu_to_le16(seg_len); 397 remain_len -= seg_len; 398 page_info++; 399 } 400 401 ionic_rxq_post(q, false, ionic_rx_clean, NULL); 402 } 403 404 ionic_dbell_ring(q->lif->kern_dbpage, q->hw_type, 405 q->dbval | q->head_idx); 406 } 407 408 static void ionic_rx_fill_cb(void *arg) 409 { 410 ionic_rx_fill(arg); 411 } 412 413 void ionic_rx_empty(struct ionic_queue *q) 414 { 415 struct ionic_desc_info *desc_info; 416 struct ionic_rxq_desc *desc; 417 unsigned int i; 418 u16 idx; 419 420 idx = q->tail_idx; 421 while (idx != q->head_idx) { 422 desc_info = &q->info[idx]; 423 desc = desc_info->desc; 424 desc->addr = 0; 425 desc->len = 0; 426 427 for (i = 0; i < desc_info->npages; i++) 428 ionic_rx_page_free(q, &desc_info->pages[i]); 429 430 desc_info->cb_arg = NULL; 431 idx = (idx + 1) & (q->num_descs - 1); 432 } 433 } 434 435 int ionic_tx_napi(struct napi_struct *napi, int budget) 436 { 437 struct ionic_qcq *qcq = napi_to_qcq(napi); 438 struct ionic_cq *cq = napi_to_cq(napi); 439 struct ionic_dev *idev; 440 struct ionic_lif *lif; 441 u32 work_done = 0; 442 u32 flags = 0; 443 444 lif = cq->bound_q->lif; 445 idev = &lif->ionic->idev; 446 447 work_done = ionic_cq_service(cq, budget, 448 ionic_tx_service, NULL, NULL); 449 450 if (work_done < budget && napi_complete_done(napi, work_done)) { 451 flags |= IONIC_INTR_CRED_UNMASK; 452 DEBUG_STATS_INTR_REARM(cq->bound_intr); 453 } 454 455 if (work_done || flags) { 456 flags |= IONIC_INTR_CRED_RESET_COALESCE; 457 ionic_intr_credits(idev->intr_ctrl, 458 cq->bound_intr->index, 459 work_done, flags); 460 } 461 462 DEBUG_STATS_NAPI_POLL(qcq, work_done); 463 464 return work_done; 465 } 466 467 int ionic_rx_napi(struct napi_struct *napi, int budget) 468 { 469 struct ionic_qcq *qcq = napi_to_qcq(napi); 470 struct ionic_cq *cq = napi_to_cq(napi); 471 struct ionic_dev *idev; 472 struct ionic_lif *lif; 473 u32 work_done = 0; 474 u32 flags = 0; 475 476 lif = cq->bound_q->lif; 477 idev = &lif->ionic->idev; 478 479 work_done = ionic_cq_service(cq, budget, 480 ionic_rx_service, NULL, NULL); 481 482 if (work_done) 483 ionic_rx_fill(cq->bound_q); 484 485 if (work_done < budget && napi_complete_done(napi, work_done)) { 486 flags |= IONIC_INTR_CRED_UNMASK; 487 DEBUG_STATS_INTR_REARM(cq->bound_intr); 488 } 489 490 if (work_done || flags) { 491 flags |= IONIC_INTR_CRED_RESET_COALESCE; 492 ionic_intr_credits(idev->intr_ctrl, 493 cq->bound_intr->index, 494 work_done, flags); 495 } 496 497 DEBUG_STATS_NAPI_POLL(qcq, work_done); 498 499 return work_done; 500 } 501 502 int ionic_txrx_napi(struct napi_struct *napi, int budget) 503 { 504 struct ionic_qcq *qcq = napi_to_qcq(napi); 505 struct ionic_cq *rxcq = napi_to_cq(napi); 506 unsigned int qi = rxcq->bound_q->index; 507 struct ionic_dev *idev; 508 struct ionic_lif *lif; 509 struct ionic_cq *txcq; 510 u32 rx_work_done = 0; 511 u32 tx_work_done = 0; 512 u32 flags = 0; 513 514 lif = rxcq->bound_q->lif; 515 idev = &lif->ionic->idev; 516 txcq = &lif->txqcqs[qi]->cq; 517 518 tx_work_done = ionic_cq_service(txcq, lif->tx_budget, 519 ionic_tx_service, NULL, NULL); 520 521 rx_work_done = ionic_cq_service(rxcq, budget, 522 ionic_rx_service, NULL, NULL); 523 if (rx_work_done) 524 ionic_rx_fill_cb(rxcq->bound_q); 525 526 if (rx_work_done < budget && napi_complete_done(napi, rx_work_done)) { 527 flags |= IONIC_INTR_CRED_UNMASK; 528 DEBUG_STATS_INTR_REARM(rxcq->bound_intr); 529 } 530 531 if (rx_work_done || flags) { 532 flags |= IONIC_INTR_CRED_RESET_COALESCE; 533 ionic_intr_credits(idev->intr_ctrl, rxcq->bound_intr->index, 534 tx_work_done + rx_work_done, flags); 535 } 536 537 DEBUG_STATS_NAPI_POLL(qcq, rx_work_done); 538 DEBUG_STATS_NAPI_POLL(qcq, tx_work_done); 539 540 return rx_work_done; 541 } 542 543 static dma_addr_t ionic_tx_map_single(struct ionic_queue *q, 544 void *data, size_t len) 545 { 546 struct ionic_tx_stats *stats = q_to_tx_stats(q); 547 struct device *dev = q->lif->ionic->dev; 548 dma_addr_t dma_addr; 549 550 dma_addr = dma_map_single(dev, data, len, DMA_TO_DEVICE); 551 if (dma_mapping_error(dev, dma_addr)) { 552 net_warn_ratelimited("%s: DMA single map failed on %s!\n", 553 q->lif->netdev->name, q->name); 554 stats->dma_map_err++; 555 return 0; 556 } 557 return dma_addr; 558 } 559 560 static dma_addr_t ionic_tx_map_frag(struct ionic_queue *q, 561 const skb_frag_t *frag, 562 size_t offset, size_t len) 563 { 564 struct ionic_tx_stats *stats = q_to_tx_stats(q); 565 struct device *dev = q->lif->ionic->dev; 566 dma_addr_t dma_addr; 567 568 dma_addr = skb_frag_dma_map(dev, frag, offset, len, DMA_TO_DEVICE); 569 if (dma_mapping_error(dev, dma_addr)) { 570 net_warn_ratelimited("%s: DMA frag map failed on %s!\n", 571 q->lif->netdev->name, q->name); 572 stats->dma_map_err++; 573 } 574 return dma_addr; 575 } 576 577 static void ionic_tx_clean(struct ionic_queue *q, 578 struct ionic_desc_info *desc_info, 579 struct ionic_cq_info *cq_info, 580 void *cb_arg) 581 { 582 struct ionic_txq_sg_desc *sg_desc = desc_info->sg_desc; 583 struct ionic_txq_sg_elem *elem = sg_desc->elems; 584 struct ionic_tx_stats *stats = q_to_tx_stats(q); 585 struct ionic_txq_desc *desc = desc_info->desc; 586 struct device *dev = q->lif->ionic->dev; 587 u8 opcode, flags, nsge; 588 u16 queue_index; 589 unsigned int i; 590 u64 addr; 591 592 decode_txq_desc_cmd(le64_to_cpu(desc->cmd), 593 &opcode, &flags, &nsge, &addr); 594 595 /* use unmap_single only if either this is not TSO, 596 * or this is first descriptor of a TSO 597 */ 598 if (opcode != IONIC_TXQ_DESC_OPCODE_TSO || 599 flags & IONIC_TXQ_DESC_FLAG_TSO_SOT) 600 dma_unmap_single(dev, (dma_addr_t)addr, 601 le16_to_cpu(desc->len), DMA_TO_DEVICE); 602 else 603 dma_unmap_page(dev, (dma_addr_t)addr, 604 le16_to_cpu(desc->len), DMA_TO_DEVICE); 605 606 for (i = 0; i < nsge; i++, elem++) 607 dma_unmap_page(dev, (dma_addr_t)le64_to_cpu(elem->addr), 608 le16_to_cpu(elem->len), DMA_TO_DEVICE); 609 610 if (cb_arg) { 611 struct sk_buff *skb = cb_arg; 612 u32 len = skb->len; 613 614 queue_index = skb_get_queue_mapping(skb); 615 if (unlikely(__netif_subqueue_stopped(q->lif->netdev, 616 queue_index))) { 617 netif_wake_subqueue(q->lif->netdev, queue_index); 618 q->wake++; 619 } 620 dev_kfree_skb_any(skb); 621 stats->clean++; 622 netdev_tx_completed_queue(q_to_ndq(q), 1, len); 623 } 624 } 625 626 static bool ionic_tx_service(struct ionic_cq *cq, struct ionic_cq_info *cq_info) 627 { 628 struct ionic_txq_comp *comp = cq_info->cq_desc; 629 struct ionic_queue *q = cq->bound_q; 630 struct ionic_desc_info *desc_info; 631 u16 index; 632 633 if (!color_match(comp->color, cq->done_color)) 634 return false; 635 636 /* clean the related q entries, there could be 637 * several q entries completed for each cq completion 638 */ 639 do { 640 desc_info = &q->info[q->tail_idx]; 641 index = q->tail_idx; 642 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 643 ionic_tx_clean(q, desc_info, cq_info, desc_info->cb_arg); 644 desc_info->cb = NULL; 645 desc_info->cb_arg = NULL; 646 } while (index != le16_to_cpu(comp->comp_index)); 647 648 return true; 649 } 650 651 void ionic_tx_flush(struct ionic_cq *cq) 652 { 653 struct ionic_dev *idev = &cq->lif->ionic->idev; 654 u32 work_done; 655 656 work_done = ionic_cq_service(cq, cq->num_descs, 657 ionic_tx_service, NULL, NULL); 658 if (work_done) 659 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 660 work_done, IONIC_INTR_CRED_RESET_COALESCE); 661 } 662 663 void ionic_tx_empty(struct ionic_queue *q) 664 { 665 struct ionic_desc_info *desc_info; 666 667 /* walk the not completed tx entries, if any */ 668 while (q->head_idx != q->tail_idx) { 669 desc_info = &q->info[q->tail_idx]; 670 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 671 ionic_tx_clean(q, desc_info, NULL, desc_info->cb_arg); 672 desc_info->cb = NULL; 673 desc_info->cb_arg = NULL; 674 } 675 } 676 677 static int ionic_tx_tcp_inner_pseudo_csum(struct sk_buff *skb) 678 { 679 int err; 680 681 err = skb_cow_head(skb, 0); 682 if (err) 683 return err; 684 685 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 686 inner_ip_hdr(skb)->check = 0; 687 inner_tcp_hdr(skb)->check = 688 ~csum_tcpudp_magic(inner_ip_hdr(skb)->saddr, 689 inner_ip_hdr(skb)->daddr, 690 0, IPPROTO_TCP, 0); 691 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 692 inner_tcp_hdr(skb)->check = 693 ~csum_ipv6_magic(&inner_ipv6_hdr(skb)->saddr, 694 &inner_ipv6_hdr(skb)->daddr, 695 0, IPPROTO_TCP, 0); 696 } 697 698 return 0; 699 } 700 701 static int ionic_tx_tcp_pseudo_csum(struct sk_buff *skb) 702 { 703 int err; 704 705 err = skb_cow_head(skb, 0); 706 if (err) 707 return err; 708 709 if (skb->protocol == cpu_to_be16(ETH_P_IP)) { 710 ip_hdr(skb)->check = 0; 711 tcp_hdr(skb)->check = 712 ~csum_tcpudp_magic(ip_hdr(skb)->saddr, 713 ip_hdr(skb)->daddr, 714 0, IPPROTO_TCP, 0); 715 } else if (skb->protocol == cpu_to_be16(ETH_P_IPV6)) { 716 tcp_v6_gso_csum_prep(skb); 717 } 718 719 return 0; 720 } 721 722 static void ionic_tx_tso_post(struct ionic_queue *q, struct ionic_txq_desc *desc, 723 struct sk_buff *skb, 724 dma_addr_t addr, u8 nsge, u16 len, 725 unsigned int hdrlen, unsigned int mss, 726 bool outer_csum, 727 u16 vlan_tci, bool has_vlan, 728 bool start, bool done) 729 { 730 u8 flags = 0; 731 u64 cmd; 732 733 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 734 flags |= outer_csum ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 735 flags |= start ? IONIC_TXQ_DESC_FLAG_TSO_SOT : 0; 736 flags |= done ? IONIC_TXQ_DESC_FLAG_TSO_EOT : 0; 737 738 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_TSO, flags, nsge, addr); 739 desc->cmd = cpu_to_le64(cmd); 740 desc->len = cpu_to_le16(len); 741 desc->vlan_tci = cpu_to_le16(vlan_tci); 742 desc->hdr_len = cpu_to_le16(hdrlen); 743 desc->mss = cpu_to_le16(mss); 744 745 if (done) { 746 skb_tx_timestamp(skb); 747 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 748 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 749 } else { 750 ionic_txq_post(q, false, ionic_tx_clean, NULL); 751 } 752 } 753 754 static struct ionic_txq_desc *ionic_tx_tso_next(struct ionic_queue *q, 755 struct ionic_txq_sg_elem **elem) 756 { 757 struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc; 758 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 759 760 *elem = sg_desc->elems; 761 return desc; 762 } 763 764 static int ionic_tx_tso(struct ionic_queue *q, struct sk_buff *skb) 765 { 766 struct ionic_tx_stats *stats = q_to_tx_stats(q); 767 struct ionic_desc_info *rewind_desc_info; 768 struct device *dev = q->lif->ionic->dev; 769 struct ionic_txq_sg_elem *elem; 770 struct ionic_txq_desc *desc; 771 unsigned int frag_left = 0; 772 unsigned int offset = 0; 773 u16 abort = q->head_idx; 774 unsigned int len_left; 775 dma_addr_t desc_addr; 776 unsigned int hdrlen; 777 unsigned int nfrags; 778 unsigned int seglen; 779 u64 total_bytes = 0; 780 u64 total_pkts = 0; 781 u16 rewind = abort; 782 unsigned int left; 783 unsigned int len; 784 unsigned int mss; 785 skb_frag_t *frag; 786 bool start, done; 787 bool outer_csum; 788 bool has_vlan; 789 u16 desc_len; 790 u8 desc_nsge; 791 u16 vlan_tci; 792 bool encap; 793 int err; 794 795 mss = skb_shinfo(skb)->gso_size; 796 nfrags = skb_shinfo(skb)->nr_frags; 797 len_left = skb->len - skb_headlen(skb); 798 outer_csum = (skb_shinfo(skb)->gso_type & SKB_GSO_GRE_CSUM) || 799 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM); 800 has_vlan = !!skb_vlan_tag_present(skb); 801 vlan_tci = skb_vlan_tag_get(skb); 802 encap = skb->encapsulation; 803 804 /* Preload inner-most TCP csum field with IP pseudo hdr 805 * calculated with IP length set to zero. HW will later 806 * add in length to each TCP segment resulting from the TSO. 807 */ 808 809 if (encap) 810 err = ionic_tx_tcp_inner_pseudo_csum(skb); 811 else 812 err = ionic_tx_tcp_pseudo_csum(skb); 813 if (err) 814 return err; 815 816 if (encap) 817 hdrlen = skb_inner_transport_header(skb) - skb->data + 818 inner_tcp_hdrlen(skb); 819 else 820 hdrlen = skb_transport_offset(skb) + tcp_hdrlen(skb); 821 822 seglen = hdrlen + mss; 823 left = skb_headlen(skb); 824 825 desc = ionic_tx_tso_next(q, &elem); 826 start = true; 827 828 /* Chop skb->data up into desc segments */ 829 830 while (left > 0) { 831 len = min(seglen, left); 832 frag_left = seglen - len; 833 desc_addr = ionic_tx_map_single(q, skb->data + offset, len); 834 if (dma_mapping_error(dev, desc_addr)) 835 goto err_out_abort; 836 desc_len = len; 837 desc_nsge = 0; 838 left -= len; 839 offset += len; 840 if (nfrags > 0 && frag_left > 0) 841 continue; 842 done = (nfrags == 0 && left == 0); 843 ionic_tx_tso_post(q, desc, skb, 844 desc_addr, desc_nsge, desc_len, 845 hdrlen, mss, 846 outer_csum, 847 vlan_tci, has_vlan, 848 start, done); 849 total_pkts++; 850 total_bytes += start ? len : len + hdrlen; 851 desc = ionic_tx_tso_next(q, &elem); 852 start = false; 853 seglen = mss; 854 } 855 856 /* Chop skb frags into desc segments */ 857 858 for (frag = skb_shinfo(skb)->frags; len_left; frag++) { 859 offset = 0; 860 left = skb_frag_size(frag); 861 len_left -= left; 862 nfrags--; 863 stats->frags++; 864 865 while (left > 0) { 866 if (frag_left > 0) { 867 len = min(frag_left, left); 868 frag_left -= len; 869 elem->addr = 870 cpu_to_le64(ionic_tx_map_frag(q, frag, 871 offset, len)); 872 if (dma_mapping_error(dev, elem->addr)) 873 goto err_out_abort; 874 elem->len = cpu_to_le16(len); 875 elem++; 876 desc_nsge++; 877 left -= len; 878 offset += len; 879 if (nfrags > 0 && frag_left > 0) 880 continue; 881 done = (nfrags == 0 && left == 0); 882 ionic_tx_tso_post(q, desc, skb, desc_addr, 883 desc_nsge, desc_len, 884 hdrlen, mss, outer_csum, 885 vlan_tci, has_vlan, 886 start, done); 887 total_pkts++; 888 total_bytes += start ? len : len + hdrlen; 889 desc = ionic_tx_tso_next(q, &elem); 890 start = false; 891 } else { 892 len = min(mss, left); 893 frag_left = mss - len; 894 desc_addr = ionic_tx_map_frag(q, frag, 895 offset, len); 896 if (dma_mapping_error(dev, desc_addr)) 897 goto err_out_abort; 898 desc_len = len; 899 desc_nsge = 0; 900 left -= len; 901 offset += len; 902 if (nfrags > 0 && frag_left > 0) 903 continue; 904 done = (nfrags == 0 && left == 0); 905 ionic_tx_tso_post(q, desc, skb, desc_addr, 906 desc_nsge, desc_len, 907 hdrlen, mss, outer_csum, 908 vlan_tci, has_vlan, 909 start, done); 910 total_pkts++; 911 total_bytes += start ? len : len + hdrlen; 912 desc = ionic_tx_tso_next(q, &elem); 913 start = false; 914 } 915 } 916 } 917 918 stats->pkts += total_pkts; 919 stats->bytes += total_bytes; 920 stats->tso++; 921 stats->tso_bytes += total_bytes; 922 923 return 0; 924 925 err_out_abort: 926 while (rewind != q->head_idx) { 927 rewind_desc_info = &q->info[rewind]; 928 ionic_tx_clean(q, rewind_desc_info, NULL, NULL); 929 rewind = (rewind + 1) & (q->num_descs - 1); 930 } 931 q->head_idx = abort; 932 933 return -ENOMEM; 934 } 935 936 static int ionic_tx_calc_csum(struct ionic_queue *q, struct sk_buff *skb) 937 { 938 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 939 struct ionic_tx_stats *stats = q_to_tx_stats(q); 940 struct device *dev = q->lif->ionic->dev; 941 dma_addr_t dma_addr; 942 bool has_vlan; 943 u8 flags = 0; 944 bool encap; 945 u64 cmd; 946 947 has_vlan = !!skb_vlan_tag_present(skb); 948 encap = skb->encapsulation; 949 950 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 951 if (dma_mapping_error(dev, dma_addr)) 952 return -ENOMEM; 953 954 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 955 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 956 957 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL, 958 flags, skb_shinfo(skb)->nr_frags, dma_addr); 959 desc->cmd = cpu_to_le64(cmd); 960 desc->len = cpu_to_le16(skb_headlen(skb)); 961 desc->csum_start = cpu_to_le16(skb_checksum_start_offset(skb)); 962 desc->csum_offset = cpu_to_le16(skb->csum_offset); 963 if (has_vlan) { 964 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 965 stats->vlan_inserted++; 966 } 967 968 if (skb->csum_not_inet) 969 stats->crc32_csum++; 970 else 971 stats->csum++; 972 973 return 0; 974 } 975 976 static int ionic_tx_calc_no_csum(struct ionic_queue *q, struct sk_buff *skb) 977 { 978 struct ionic_txq_desc *desc = q->info[q->head_idx].txq_desc; 979 struct ionic_tx_stats *stats = q_to_tx_stats(q); 980 struct device *dev = q->lif->ionic->dev; 981 dma_addr_t dma_addr; 982 bool has_vlan; 983 u8 flags = 0; 984 bool encap; 985 u64 cmd; 986 987 has_vlan = !!skb_vlan_tag_present(skb); 988 encap = skb->encapsulation; 989 990 dma_addr = ionic_tx_map_single(q, skb->data, skb_headlen(skb)); 991 if (dma_mapping_error(dev, dma_addr)) 992 return -ENOMEM; 993 994 flags |= has_vlan ? IONIC_TXQ_DESC_FLAG_VLAN : 0; 995 flags |= encap ? IONIC_TXQ_DESC_FLAG_ENCAP : 0; 996 997 cmd = encode_txq_desc_cmd(IONIC_TXQ_DESC_OPCODE_CSUM_NONE, 998 flags, skb_shinfo(skb)->nr_frags, dma_addr); 999 desc->cmd = cpu_to_le64(cmd); 1000 desc->len = cpu_to_le16(skb_headlen(skb)); 1001 if (has_vlan) { 1002 desc->vlan_tci = cpu_to_le16(skb_vlan_tag_get(skb)); 1003 stats->vlan_inserted++; 1004 } 1005 1006 stats->csum_none++; 1007 1008 return 0; 1009 } 1010 1011 static int ionic_tx_skb_frags(struct ionic_queue *q, struct sk_buff *skb) 1012 { 1013 struct ionic_txq_sg_desc *sg_desc = q->info[q->head_idx].txq_sg_desc; 1014 unsigned int len_left = skb->len - skb_headlen(skb); 1015 struct ionic_txq_sg_elem *elem = sg_desc->elems; 1016 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1017 struct device *dev = q->lif->ionic->dev; 1018 dma_addr_t dma_addr; 1019 skb_frag_t *frag; 1020 u16 len; 1021 1022 for (frag = skb_shinfo(skb)->frags; len_left; frag++, elem++) { 1023 len = skb_frag_size(frag); 1024 elem->len = cpu_to_le16(len); 1025 dma_addr = ionic_tx_map_frag(q, frag, 0, len); 1026 if (dma_mapping_error(dev, dma_addr)) 1027 return -ENOMEM; 1028 elem->addr = cpu_to_le64(dma_addr); 1029 len_left -= len; 1030 stats->frags++; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static int ionic_tx(struct ionic_queue *q, struct sk_buff *skb) 1037 { 1038 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1039 int err; 1040 1041 /* set up the initial descriptor */ 1042 if (skb->ip_summed == CHECKSUM_PARTIAL) 1043 err = ionic_tx_calc_csum(q, skb); 1044 else 1045 err = ionic_tx_calc_no_csum(q, skb); 1046 if (err) 1047 return err; 1048 1049 /* add frags */ 1050 err = ionic_tx_skb_frags(q, skb); 1051 if (err) 1052 return err; 1053 1054 skb_tx_timestamp(skb); 1055 stats->pkts++; 1056 stats->bytes += skb->len; 1057 1058 netdev_tx_sent_queue(q_to_ndq(q), skb->len); 1059 ionic_txq_post(q, !netdev_xmit_more(), ionic_tx_clean, skb); 1060 1061 return 0; 1062 } 1063 1064 static int ionic_tx_descs_needed(struct ionic_queue *q, struct sk_buff *skb) 1065 { 1066 int sg_elems = q->lif->qtype_info[IONIC_QTYPE_TXQ].max_sg_elems; 1067 struct ionic_tx_stats *stats = q_to_tx_stats(q); 1068 int err; 1069 1070 /* If TSO, need roundup(skb->len/mss) descs */ 1071 if (skb_is_gso(skb)) 1072 return (skb->len / skb_shinfo(skb)->gso_size) + 1; 1073 1074 /* If non-TSO, just need 1 desc and nr_frags sg elems */ 1075 if (skb_shinfo(skb)->nr_frags <= sg_elems) 1076 return 1; 1077 1078 /* Too many frags, so linearize */ 1079 err = skb_linearize(skb); 1080 if (err) 1081 return err; 1082 1083 stats->linearize++; 1084 1085 /* Need 1 desc and zero sg elems */ 1086 return 1; 1087 } 1088 1089 static int ionic_maybe_stop_tx(struct ionic_queue *q, int ndescs) 1090 { 1091 int stopped = 0; 1092 1093 if (unlikely(!ionic_q_has_space(q, ndescs))) { 1094 netif_stop_subqueue(q->lif->netdev, q->index); 1095 q->stop++; 1096 stopped = 1; 1097 1098 /* Might race with ionic_tx_clean, check again */ 1099 smp_rmb(); 1100 if (ionic_q_has_space(q, ndescs)) { 1101 netif_wake_subqueue(q->lif->netdev, q->index); 1102 stopped = 0; 1103 } 1104 } 1105 1106 return stopped; 1107 } 1108 1109 netdev_tx_t ionic_start_xmit(struct sk_buff *skb, struct net_device *netdev) 1110 { 1111 u16 queue_index = skb_get_queue_mapping(skb); 1112 struct ionic_lif *lif = netdev_priv(netdev); 1113 struct ionic_queue *q; 1114 int ndescs; 1115 int err; 1116 1117 if (unlikely(!test_bit(IONIC_LIF_F_UP, lif->state))) { 1118 dev_kfree_skb(skb); 1119 return NETDEV_TX_OK; 1120 } 1121 1122 if (unlikely(queue_index >= lif->nxqs)) 1123 queue_index = 0; 1124 q = &lif->txqcqs[queue_index]->q; 1125 1126 ndescs = ionic_tx_descs_needed(q, skb); 1127 if (ndescs < 0) 1128 goto err_out_drop; 1129 1130 if (unlikely(ionic_maybe_stop_tx(q, ndescs))) 1131 return NETDEV_TX_BUSY; 1132 1133 if (skb_is_gso(skb)) 1134 err = ionic_tx_tso(q, skb); 1135 else 1136 err = ionic_tx(q, skb); 1137 1138 if (err) 1139 goto err_out_drop; 1140 1141 /* Stop the queue if there aren't descriptors for the next packet. 1142 * Since our SG lists per descriptor take care of most of the possible 1143 * fragmentation, we don't need to have many descriptors available. 1144 */ 1145 ionic_maybe_stop_tx(q, 4); 1146 1147 return NETDEV_TX_OK; 1148 1149 err_out_drop: 1150 q->stop++; 1151 q->drop++; 1152 dev_kfree_skb(skb); 1153 return NETDEV_TX_OK; 1154 } 1155