1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/module.h> 7 #include <linux/netdevice.h> 8 #include <linux/utsname.h> 9 #include <generated/utsrelease.h> 10 11 #include "ionic.h" 12 #include "ionic_bus.h" 13 #include "ionic_lif.h" 14 #include "ionic_debugfs.h" 15 16 MODULE_DESCRIPTION(IONIC_DRV_DESCRIPTION); 17 MODULE_AUTHOR("Pensando Systems, Inc"); 18 MODULE_LICENSE("GPL"); 19 20 static const char *ionic_error_to_str(enum ionic_status_code code) 21 { 22 switch (code) { 23 case IONIC_RC_SUCCESS: 24 return "IONIC_RC_SUCCESS"; 25 case IONIC_RC_EVERSION: 26 return "IONIC_RC_EVERSION"; 27 case IONIC_RC_EOPCODE: 28 return "IONIC_RC_EOPCODE"; 29 case IONIC_RC_EIO: 30 return "IONIC_RC_EIO"; 31 case IONIC_RC_EPERM: 32 return "IONIC_RC_EPERM"; 33 case IONIC_RC_EQID: 34 return "IONIC_RC_EQID"; 35 case IONIC_RC_EQTYPE: 36 return "IONIC_RC_EQTYPE"; 37 case IONIC_RC_ENOENT: 38 return "IONIC_RC_ENOENT"; 39 case IONIC_RC_EINTR: 40 return "IONIC_RC_EINTR"; 41 case IONIC_RC_EAGAIN: 42 return "IONIC_RC_EAGAIN"; 43 case IONIC_RC_ENOMEM: 44 return "IONIC_RC_ENOMEM"; 45 case IONIC_RC_EFAULT: 46 return "IONIC_RC_EFAULT"; 47 case IONIC_RC_EBUSY: 48 return "IONIC_RC_EBUSY"; 49 case IONIC_RC_EEXIST: 50 return "IONIC_RC_EEXIST"; 51 case IONIC_RC_EINVAL: 52 return "IONIC_RC_EINVAL"; 53 case IONIC_RC_ENOSPC: 54 return "IONIC_RC_ENOSPC"; 55 case IONIC_RC_ERANGE: 56 return "IONIC_RC_ERANGE"; 57 case IONIC_RC_BAD_ADDR: 58 return "IONIC_RC_BAD_ADDR"; 59 case IONIC_RC_DEV_CMD: 60 return "IONIC_RC_DEV_CMD"; 61 case IONIC_RC_ENOSUPP: 62 return "IONIC_RC_ENOSUPP"; 63 case IONIC_RC_ERROR: 64 return "IONIC_RC_ERROR"; 65 case IONIC_RC_ERDMA: 66 return "IONIC_RC_ERDMA"; 67 case IONIC_RC_EBAD_FW: 68 return "IONIC_RC_EBAD_FW"; 69 default: 70 return "IONIC_RC_UNKNOWN"; 71 } 72 } 73 74 static int ionic_error_to_errno(enum ionic_status_code code) 75 { 76 switch (code) { 77 case IONIC_RC_SUCCESS: 78 return 0; 79 case IONIC_RC_EVERSION: 80 case IONIC_RC_EQTYPE: 81 case IONIC_RC_EQID: 82 case IONIC_RC_EINVAL: 83 case IONIC_RC_ENOSUPP: 84 return -EINVAL; 85 case IONIC_RC_EPERM: 86 return -EPERM; 87 case IONIC_RC_ENOENT: 88 return -ENOENT; 89 case IONIC_RC_EAGAIN: 90 return -EAGAIN; 91 case IONIC_RC_ENOMEM: 92 return -ENOMEM; 93 case IONIC_RC_EFAULT: 94 return -EFAULT; 95 case IONIC_RC_EBUSY: 96 return -EBUSY; 97 case IONIC_RC_EEXIST: 98 return -EEXIST; 99 case IONIC_RC_ENOSPC: 100 return -ENOSPC; 101 case IONIC_RC_ERANGE: 102 return -ERANGE; 103 case IONIC_RC_BAD_ADDR: 104 return -EFAULT; 105 case IONIC_RC_EOPCODE: 106 case IONIC_RC_EINTR: 107 case IONIC_RC_DEV_CMD: 108 case IONIC_RC_ERROR: 109 case IONIC_RC_ERDMA: 110 case IONIC_RC_EIO: 111 default: 112 return -EIO; 113 } 114 } 115 116 static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode) 117 { 118 switch (opcode) { 119 case IONIC_CMD_NOP: 120 return "IONIC_CMD_NOP"; 121 case IONIC_CMD_INIT: 122 return "IONIC_CMD_INIT"; 123 case IONIC_CMD_RESET: 124 return "IONIC_CMD_RESET"; 125 case IONIC_CMD_IDENTIFY: 126 return "IONIC_CMD_IDENTIFY"; 127 case IONIC_CMD_GETATTR: 128 return "IONIC_CMD_GETATTR"; 129 case IONIC_CMD_SETATTR: 130 return "IONIC_CMD_SETATTR"; 131 case IONIC_CMD_PORT_IDENTIFY: 132 return "IONIC_CMD_PORT_IDENTIFY"; 133 case IONIC_CMD_PORT_INIT: 134 return "IONIC_CMD_PORT_INIT"; 135 case IONIC_CMD_PORT_RESET: 136 return "IONIC_CMD_PORT_RESET"; 137 case IONIC_CMD_PORT_GETATTR: 138 return "IONIC_CMD_PORT_GETATTR"; 139 case IONIC_CMD_PORT_SETATTR: 140 return "IONIC_CMD_PORT_SETATTR"; 141 case IONIC_CMD_LIF_INIT: 142 return "IONIC_CMD_LIF_INIT"; 143 case IONIC_CMD_LIF_RESET: 144 return "IONIC_CMD_LIF_RESET"; 145 case IONIC_CMD_LIF_IDENTIFY: 146 return "IONIC_CMD_LIF_IDENTIFY"; 147 case IONIC_CMD_LIF_SETATTR: 148 return "IONIC_CMD_LIF_SETATTR"; 149 case IONIC_CMD_LIF_GETATTR: 150 return "IONIC_CMD_LIF_GETATTR"; 151 case IONIC_CMD_RX_MODE_SET: 152 return "IONIC_CMD_RX_MODE_SET"; 153 case IONIC_CMD_RX_FILTER_ADD: 154 return "IONIC_CMD_RX_FILTER_ADD"; 155 case IONIC_CMD_RX_FILTER_DEL: 156 return "IONIC_CMD_RX_FILTER_DEL"; 157 case IONIC_CMD_Q_IDENTIFY: 158 return "IONIC_CMD_Q_IDENTIFY"; 159 case IONIC_CMD_Q_INIT: 160 return "IONIC_CMD_Q_INIT"; 161 case IONIC_CMD_Q_CONTROL: 162 return "IONIC_CMD_Q_CONTROL"; 163 case IONIC_CMD_RDMA_RESET_LIF: 164 return "IONIC_CMD_RDMA_RESET_LIF"; 165 case IONIC_CMD_RDMA_CREATE_EQ: 166 return "IONIC_CMD_RDMA_CREATE_EQ"; 167 case IONIC_CMD_RDMA_CREATE_CQ: 168 return "IONIC_CMD_RDMA_CREATE_CQ"; 169 case IONIC_CMD_RDMA_CREATE_ADMINQ: 170 return "IONIC_CMD_RDMA_CREATE_ADMINQ"; 171 case IONIC_CMD_FW_DOWNLOAD: 172 return "IONIC_CMD_FW_DOWNLOAD"; 173 case IONIC_CMD_FW_CONTROL: 174 return "IONIC_CMD_FW_CONTROL"; 175 case IONIC_CMD_FW_DOWNLOAD_V1: 176 return "IONIC_CMD_FW_DOWNLOAD_V1"; 177 case IONIC_CMD_FW_CONTROL_V1: 178 return "IONIC_CMD_FW_CONTROL_V1"; 179 case IONIC_CMD_VF_GETATTR: 180 return "IONIC_CMD_VF_GETATTR"; 181 case IONIC_CMD_VF_SETATTR: 182 return "IONIC_CMD_VF_SETATTR"; 183 default: 184 return "DEVCMD_UNKNOWN"; 185 } 186 } 187 188 static void ionic_adminq_flush(struct ionic_lif *lif) 189 { 190 struct ionic_queue *q = &lif->adminqcq->q; 191 struct ionic_desc_info *desc_info; 192 193 spin_lock(&lif->adminq_lock); 194 195 while (q->tail_idx != q->head_idx) { 196 desc_info = &q->info[q->tail_idx]; 197 memset(desc_info->desc, 0, sizeof(union ionic_adminq_cmd)); 198 desc_info->cb = NULL; 199 desc_info->cb_arg = NULL; 200 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 201 } 202 spin_unlock(&lif->adminq_lock); 203 } 204 205 static int ionic_adminq_check_err(struct ionic_lif *lif, 206 struct ionic_admin_ctx *ctx, 207 bool timeout) 208 { 209 struct net_device *netdev = lif->netdev; 210 const char *opcode_str; 211 const char *status_str; 212 int err = 0; 213 214 if (ctx->comp.comp.status || timeout) { 215 opcode_str = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 216 status_str = ionic_error_to_str(ctx->comp.comp.status); 217 err = timeout ? -ETIMEDOUT : 218 ionic_error_to_errno(ctx->comp.comp.status); 219 220 netdev_err(netdev, "%s (%d) failed: %s (%d)\n", 221 opcode_str, ctx->cmd.cmd.opcode, 222 timeout ? "TIMEOUT" : status_str, err); 223 224 if (timeout) 225 ionic_adminq_flush(lif); 226 } 227 228 return err; 229 } 230 231 static void ionic_adminq_cb(struct ionic_queue *q, 232 struct ionic_desc_info *desc_info, 233 struct ionic_cq_info *cq_info, void *cb_arg) 234 { 235 struct ionic_admin_ctx *ctx = cb_arg; 236 struct ionic_admin_comp *comp; 237 struct device *dev; 238 239 if (!ctx) 240 return; 241 242 comp = cq_info->cq_desc; 243 dev = &q->lif->netdev->dev; 244 245 memcpy(&ctx->comp, comp, sizeof(*comp)); 246 247 dev_dbg(dev, "comp admin queue command:\n"); 248 dynamic_hex_dump("comp ", DUMP_PREFIX_OFFSET, 16, 1, 249 &ctx->comp, sizeof(ctx->comp), true); 250 251 complete_all(&ctx->work); 252 } 253 254 static int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 255 { 256 struct ionic_desc_info *desc_info; 257 struct ionic_queue *q; 258 int err = 0; 259 260 if (!lif->adminqcq) 261 return -EIO; 262 263 q = &lif->adminqcq->q; 264 265 spin_lock(&lif->adminq_lock); 266 if (!ionic_q_has_space(q, 1)) { 267 err = -ENOSPC; 268 goto err_out; 269 } 270 271 err = ionic_heartbeat_check(lif->ionic); 272 if (err) 273 goto err_out; 274 275 desc_info = &q->info[q->head_idx]; 276 memcpy(desc_info->desc, &ctx->cmd, sizeof(ctx->cmd)); 277 278 dev_dbg(&lif->netdev->dev, "post admin queue command:\n"); 279 dynamic_hex_dump("cmd ", DUMP_PREFIX_OFFSET, 16, 1, 280 &ctx->cmd, sizeof(ctx->cmd), true); 281 282 ionic_q_post(q, true, ionic_adminq_cb, ctx); 283 284 err_out: 285 spin_unlock(&lif->adminq_lock); 286 287 return err; 288 } 289 290 int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 291 { 292 struct net_device *netdev = lif->netdev; 293 unsigned long remaining; 294 const char *name; 295 int err; 296 297 err = ionic_adminq_post(lif, ctx); 298 if (err) { 299 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 300 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 301 netdev_err(netdev, "Posting of %s (%d) failed: %d\n", 302 name, ctx->cmd.cmd.opcode, err); 303 } 304 return err; 305 } 306 307 remaining = wait_for_completion_timeout(&ctx->work, 308 HZ * (ulong)DEVCMD_TIMEOUT); 309 return ionic_adminq_check_err(lif, ctx, (remaining == 0)); 310 } 311 312 static void ionic_dev_cmd_clean(struct ionic *ionic) 313 { 314 union __iomem ionic_dev_cmd_regs *regs = ionic->idev.dev_cmd_regs; 315 316 iowrite32(0, ®s->doorbell); 317 memset_io(®s->cmd, 0, sizeof(regs->cmd)); 318 } 319 320 int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds) 321 { 322 struct ionic_dev *idev = &ionic->idev; 323 unsigned long start_time; 324 unsigned long max_wait; 325 unsigned long duration; 326 int opcode; 327 int hb = 0; 328 int done; 329 int err; 330 331 /* Wait for dev cmd to complete, retrying if we get EAGAIN, 332 * but don't wait any longer than max_seconds. 333 */ 334 max_wait = jiffies + (max_seconds * HZ); 335 try_again: 336 opcode = readb(&idev->dev_cmd_regs->cmd.cmd.opcode); 337 start_time = jiffies; 338 do { 339 done = ionic_dev_cmd_done(idev); 340 if (done) 341 break; 342 usleep_range(100, 200); 343 344 /* Don't check the heartbeat on FW_CONTROL commands as they are 345 * notorious for interrupting the firmware's heartbeat update. 346 */ 347 if (opcode != IONIC_CMD_FW_CONTROL) 348 hb = ionic_heartbeat_check(ionic); 349 } while (!done && !hb && time_before(jiffies, max_wait)); 350 duration = jiffies - start_time; 351 352 dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n", 353 ionic_opcode_to_str(opcode), opcode, 354 done, duration / HZ, duration); 355 356 if (!done && hb) { 357 /* It is possible (but unlikely) that FW was busy and missed a 358 * heartbeat check but is still alive and will process this 359 * request, so don't clean the dev_cmd in this case. 360 */ 361 dev_warn(ionic->dev, "DEVCMD %s (%d) failed - FW halted\n", 362 ionic_opcode_to_str(opcode), opcode); 363 return -ENXIO; 364 } 365 366 if (!done && !time_before(jiffies, max_wait)) { 367 ionic_dev_cmd_clean(ionic); 368 dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n", 369 ionic_opcode_to_str(opcode), opcode, max_seconds); 370 return -ETIMEDOUT; 371 } 372 373 err = ionic_dev_cmd_status(&ionic->idev); 374 if (err) { 375 if (err == IONIC_RC_EAGAIN && 376 time_before(jiffies, (max_wait - HZ))) { 377 dev_dbg(ionic->dev, "DEV_CMD %s (%d), %s (%d) retrying...\n", 378 ionic_opcode_to_str(opcode), opcode, 379 ionic_error_to_str(err), err); 380 381 msleep(1000); 382 iowrite32(0, &idev->dev_cmd_regs->done); 383 iowrite32(1, &idev->dev_cmd_regs->doorbell); 384 goto try_again; 385 } 386 387 if (!(opcode == IONIC_CMD_FW_CONTROL && err == IONIC_RC_EAGAIN)) 388 dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n", 389 ionic_opcode_to_str(opcode), opcode, 390 ionic_error_to_str(err), err); 391 392 return ionic_error_to_errno(err); 393 } 394 395 return 0; 396 } 397 398 int ionic_setup(struct ionic *ionic) 399 { 400 int err; 401 402 err = ionic_dev_setup(ionic); 403 if (err) 404 return err; 405 ionic_reset(ionic); 406 407 return 0; 408 } 409 410 int ionic_identify(struct ionic *ionic) 411 { 412 struct ionic_identity *ident = &ionic->ident; 413 struct ionic_dev *idev = &ionic->idev; 414 size_t sz; 415 int err; 416 417 memset(ident, 0, sizeof(*ident)); 418 419 ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX); 420 strncpy(ident->drv.driver_ver_str, UTS_RELEASE, 421 sizeof(ident->drv.driver_ver_str) - 1); 422 423 mutex_lock(&ionic->dev_cmd_lock); 424 425 sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data)); 426 memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz); 427 428 ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1); 429 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 430 if (!err) { 431 sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data)); 432 memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz); 433 } 434 mutex_unlock(&ionic->dev_cmd_lock); 435 436 if (err) { 437 dev_err(ionic->dev, "Cannot identify ionic: %dn", err); 438 goto err_out; 439 } 440 441 err = ionic_lif_identify(ionic, IONIC_LIF_TYPE_CLASSIC, 442 &ionic->ident.lif); 443 if (err) { 444 dev_err(ionic->dev, "Cannot identify LIFs: %d\n", err); 445 goto err_out; 446 } 447 448 return 0; 449 450 err_out: 451 return err; 452 } 453 454 int ionic_init(struct ionic *ionic) 455 { 456 struct ionic_dev *idev = &ionic->idev; 457 int err; 458 459 mutex_lock(&ionic->dev_cmd_lock); 460 ionic_dev_cmd_init(idev); 461 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 462 mutex_unlock(&ionic->dev_cmd_lock); 463 464 return err; 465 } 466 467 int ionic_reset(struct ionic *ionic) 468 { 469 struct ionic_dev *idev = &ionic->idev; 470 int err; 471 472 mutex_lock(&ionic->dev_cmd_lock); 473 ionic_dev_cmd_reset(idev); 474 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 475 mutex_unlock(&ionic->dev_cmd_lock); 476 477 return err; 478 } 479 480 int ionic_port_identify(struct ionic *ionic) 481 { 482 struct ionic_identity *ident = &ionic->ident; 483 struct ionic_dev *idev = &ionic->idev; 484 size_t sz; 485 int err; 486 487 mutex_lock(&ionic->dev_cmd_lock); 488 489 ionic_dev_cmd_port_identify(idev); 490 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 491 if (!err) { 492 sz = min(sizeof(ident->port), sizeof(idev->dev_cmd_regs->data)); 493 memcpy_fromio(&ident->port, &idev->dev_cmd_regs->data, sz); 494 } 495 496 mutex_unlock(&ionic->dev_cmd_lock); 497 498 return err; 499 } 500 501 int ionic_port_init(struct ionic *ionic) 502 { 503 struct ionic_identity *ident = &ionic->ident; 504 struct ionic_dev *idev = &ionic->idev; 505 size_t sz; 506 int err; 507 508 if (!idev->port_info) { 509 idev->port_info_sz = ALIGN(sizeof(*idev->port_info), PAGE_SIZE); 510 idev->port_info = dma_alloc_coherent(ionic->dev, 511 idev->port_info_sz, 512 &idev->port_info_pa, 513 GFP_KERNEL); 514 if (!idev->port_info) { 515 dev_err(ionic->dev, "Failed to allocate port info\n"); 516 return -ENOMEM; 517 } 518 } 519 520 sz = min(sizeof(ident->port.config), sizeof(idev->dev_cmd_regs->data)); 521 522 mutex_lock(&ionic->dev_cmd_lock); 523 524 memcpy_toio(&idev->dev_cmd_regs->data, &ident->port.config, sz); 525 ionic_dev_cmd_port_init(idev); 526 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 527 528 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 529 (void)ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 530 531 mutex_unlock(&ionic->dev_cmd_lock); 532 if (err) { 533 dev_err(ionic->dev, "Failed to init port\n"); 534 dma_free_coherent(ionic->dev, idev->port_info_sz, 535 idev->port_info, idev->port_info_pa); 536 idev->port_info = NULL; 537 idev->port_info_pa = 0; 538 } 539 540 return err; 541 } 542 543 int ionic_port_reset(struct ionic *ionic) 544 { 545 struct ionic_dev *idev = &ionic->idev; 546 int err; 547 548 if (!idev->port_info) 549 return 0; 550 551 mutex_lock(&ionic->dev_cmd_lock); 552 ionic_dev_cmd_port_reset(idev); 553 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 554 mutex_unlock(&ionic->dev_cmd_lock); 555 556 dma_free_coherent(ionic->dev, idev->port_info_sz, 557 idev->port_info, idev->port_info_pa); 558 559 idev->port_info = NULL; 560 idev->port_info_pa = 0; 561 562 if (err) 563 dev_err(ionic->dev, "Failed to reset port\n"); 564 565 return err; 566 } 567 568 static int __init ionic_init_module(void) 569 { 570 ionic_debugfs_create(); 571 return ionic_bus_register_driver(); 572 } 573 574 static void __exit ionic_cleanup_module(void) 575 { 576 ionic_bus_unregister_driver(); 577 ionic_debugfs_destroy(); 578 579 pr_info("%s removed\n", IONIC_DRV_NAME); 580 } 581 582 module_init(ionic_init_module); 583 module_exit(ionic_cleanup_module); 584