1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/module.h> 7 #include <linux/netdevice.h> 8 #include <linux/utsname.h> 9 #include <generated/utsrelease.h> 10 11 #include "ionic.h" 12 #include "ionic_bus.h" 13 #include "ionic_lif.h" 14 #include "ionic_debugfs.h" 15 16 MODULE_DESCRIPTION(IONIC_DRV_DESCRIPTION); 17 MODULE_AUTHOR("Pensando Systems, Inc"); 18 MODULE_LICENSE("GPL"); 19 20 static const char *ionic_error_to_str(enum ionic_status_code code) 21 { 22 switch (code) { 23 case IONIC_RC_SUCCESS: 24 return "IONIC_RC_SUCCESS"; 25 case IONIC_RC_EVERSION: 26 return "IONIC_RC_EVERSION"; 27 case IONIC_RC_EOPCODE: 28 return "IONIC_RC_EOPCODE"; 29 case IONIC_RC_EIO: 30 return "IONIC_RC_EIO"; 31 case IONIC_RC_EPERM: 32 return "IONIC_RC_EPERM"; 33 case IONIC_RC_EQID: 34 return "IONIC_RC_EQID"; 35 case IONIC_RC_EQTYPE: 36 return "IONIC_RC_EQTYPE"; 37 case IONIC_RC_ENOENT: 38 return "IONIC_RC_ENOENT"; 39 case IONIC_RC_EINTR: 40 return "IONIC_RC_EINTR"; 41 case IONIC_RC_EAGAIN: 42 return "IONIC_RC_EAGAIN"; 43 case IONIC_RC_ENOMEM: 44 return "IONIC_RC_ENOMEM"; 45 case IONIC_RC_EFAULT: 46 return "IONIC_RC_EFAULT"; 47 case IONIC_RC_EBUSY: 48 return "IONIC_RC_EBUSY"; 49 case IONIC_RC_EEXIST: 50 return "IONIC_RC_EEXIST"; 51 case IONIC_RC_EINVAL: 52 return "IONIC_RC_EINVAL"; 53 case IONIC_RC_ENOSPC: 54 return "IONIC_RC_ENOSPC"; 55 case IONIC_RC_ERANGE: 56 return "IONIC_RC_ERANGE"; 57 case IONIC_RC_BAD_ADDR: 58 return "IONIC_RC_BAD_ADDR"; 59 case IONIC_RC_DEV_CMD: 60 return "IONIC_RC_DEV_CMD"; 61 case IONIC_RC_ENOSUPP: 62 return "IONIC_RC_ENOSUPP"; 63 case IONIC_RC_ERROR: 64 return "IONIC_RC_ERROR"; 65 case IONIC_RC_ERDMA: 66 return "IONIC_RC_ERDMA"; 67 case IONIC_RC_EBAD_FW: 68 return "IONIC_RC_EBAD_FW"; 69 default: 70 return "IONIC_RC_UNKNOWN"; 71 } 72 } 73 74 static int ionic_error_to_errno(enum ionic_status_code code) 75 { 76 switch (code) { 77 case IONIC_RC_SUCCESS: 78 return 0; 79 case IONIC_RC_EVERSION: 80 case IONIC_RC_EQTYPE: 81 case IONIC_RC_EQID: 82 case IONIC_RC_EINVAL: 83 case IONIC_RC_ENOSUPP: 84 return -EINVAL; 85 case IONIC_RC_EPERM: 86 return -EPERM; 87 case IONIC_RC_ENOENT: 88 return -ENOENT; 89 case IONIC_RC_EAGAIN: 90 return -EAGAIN; 91 case IONIC_RC_ENOMEM: 92 return -ENOMEM; 93 case IONIC_RC_EFAULT: 94 return -EFAULT; 95 case IONIC_RC_EBUSY: 96 return -EBUSY; 97 case IONIC_RC_EEXIST: 98 return -EEXIST; 99 case IONIC_RC_ENOSPC: 100 return -ENOSPC; 101 case IONIC_RC_ERANGE: 102 return -ERANGE; 103 case IONIC_RC_BAD_ADDR: 104 return -EFAULT; 105 case IONIC_RC_EOPCODE: 106 case IONIC_RC_EINTR: 107 case IONIC_RC_DEV_CMD: 108 case IONIC_RC_ERROR: 109 case IONIC_RC_ERDMA: 110 case IONIC_RC_EIO: 111 default: 112 return -EIO; 113 } 114 } 115 116 static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode) 117 { 118 switch (opcode) { 119 case IONIC_CMD_NOP: 120 return "IONIC_CMD_NOP"; 121 case IONIC_CMD_INIT: 122 return "IONIC_CMD_INIT"; 123 case IONIC_CMD_RESET: 124 return "IONIC_CMD_RESET"; 125 case IONIC_CMD_IDENTIFY: 126 return "IONIC_CMD_IDENTIFY"; 127 case IONIC_CMD_GETATTR: 128 return "IONIC_CMD_GETATTR"; 129 case IONIC_CMD_SETATTR: 130 return "IONIC_CMD_SETATTR"; 131 case IONIC_CMD_PORT_IDENTIFY: 132 return "IONIC_CMD_PORT_IDENTIFY"; 133 case IONIC_CMD_PORT_INIT: 134 return "IONIC_CMD_PORT_INIT"; 135 case IONIC_CMD_PORT_RESET: 136 return "IONIC_CMD_PORT_RESET"; 137 case IONIC_CMD_PORT_GETATTR: 138 return "IONIC_CMD_PORT_GETATTR"; 139 case IONIC_CMD_PORT_SETATTR: 140 return "IONIC_CMD_PORT_SETATTR"; 141 case IONIC_CMD_LIF_INIT: 142 return "IONIC_CMD_LIF_INIT"; 143 case IONIC_CMD_LIF_RESET: 144 return "IONIC_CMD_LIF_RESET"; 145 case IONIC_CMD_LIF_IDENTIFY: 146 return "IONIC_CMD_LIF_IDENTIFY"; 147 case IONIC_CMD_LIF_SETATTR: 148 return "IONIC_CMD_LIF_SETATTR"; 149 case IONIC_CMD_LIF_GETATTR: 150 return "IONIC_CMD_LIF_GETATTR"; 151 case IONIC_CMD_RX_MODE_SET: 152 return "IONIC_CMD_RX_MODE_SET"; 153 case IONIC_CMD_RX_FILTER_ADD: 154 return "IONIC_CMD_RX_FILTER_ADD"; 155 case IONIC_CMD_RX_FILTER_DEL: 156 return "IONIC_CMD_RX_FILTER_DEL"; 157 case IONIC_CMD_Q_IDENTIFY: 158 return "IONIC_CMD_Q_IDENTIFY"; 159 case IONIC_CMD_Q_INIT: 160 return "IONIC_CMD_Q_INIT"; 161 case IONIC_CMD_Q_CONTROL: 162 return "IONIC_CMD_Q_CONTROL"; 163 case IONIC_CMD_RDMA_RESET_LIF: 164 return "IONIC_CMD_RDMA_RESET_LIF"; 165 case IONIC_CMD_RDMA_CREATE_EQ: 166 return "IONIC_CMD_RDMA_CREATE_EQ"; 167 case IONIC_CMD_RDMA_CREATE_CQ: 168 return "IONIC_CMD_RDMA_CREATE_CQ"; 169 case IONIC_CMD_RDMA_CREATE_ADMINQ: 170 return "IONIC_CMD_RDMA_CREATE_ADMINQ"; 171 case IONIC_CMD_FW_DOWNLOAD: 172 return "IONIC_CMD_FW_DOWNLOAD"; 173 case IONIC_CMD_FW_CONTROL: 174 return "IONIC_CMD_FW_CONTROL"; 175 case IONIC_CMD_FW_DOWNLOAD_V1: 176 return "IONIC_CMD_FW_DOWNLOAD_V1"; 177 case IONIC_CMD_FW_CONTROL_V1: 178 return "IONIC_CMD_FW_CONTROL_V1"; 179 case IONIC_CMD_VF_GETATTR: 180 return "IONIC_CMD_VF_GETATTR"; 181 case IONIC_CMD_VF_SETATTR: 182 return "IONIC_CMD_VF_SETATTR"; 183 default: 184 return "DEVCMD_UNKNOWN"; 185 } 186 } 187 188 static void ionic_adminq_flush(struct ionic_lif *lif) 189 { 190 struct ionic_queue *q = &lif->adminqcq->q; 191 struct ionic_desc_info *desc_info; 192 193 spin_lock(&lif->adminq_lock); 194 195 while (q->tail_idx != q->head_idx) { 196 desc_info = &q->info[q->tail_idx]; 197 memset(desc_info->desc, 0, sizeof(union ionic_adminq_cmd)); 198 desc_info->cb = NULL; 199 desc_info->cb_arg = NULL; 200 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 201 } 202 spin_unlock(&lif->adminq_lock); 203 } 204 205 static int ionic_adminq_check_err(struct ionic_lif *lif, 206 struct ionic_admin_ctx *ctx, 207 bool timeout) 208 { 209 struct net_device *netdev = lif->netdev; 210 const char *opcode_str; 211 const char *status_str; 212 int err = 0; 213 214 if (ctx->comp.comp.status || timeout) { 215 opcode_str = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 216 status_str = ionic_error_to_str(ctx->comp.comp.status); 217 err = timeout ? -ETIMEDOUT : 218 ionic_error_to_errno(ctx->comp.comp.status); 219 220 netdev_err(netdev, "%s (%d) failed: %s (%d)\n", 221 opcode_str, ctx->cmd.cmd.opcode, 222 timeout ? "TIMEOUT" : status_str, err); 223 224 if (timeout) 225 ionic_adminq_flush(lif); 226 } 227 228 return err; 229 } 230 231 static void ionic_adminq_cb(struct ionic_queue *q, 232 struct ionic_desc_info *desc_info, 233 struct ionic_cq_info *cq_info, void *cb_arg) 234 { 235 struct ionic_admin_ctx *ctx = cb_arg; 236 struct ionic_admin_comp *comp; 237 238 if (!ctx) 239 return; 240 241 comp = cq_info->cq_desc; 242 243 memcpy(&ctx->comp, comp, sizeof(*comp)); 244 245 dev_dbg(q->dev, "comp admin queue command:\n"); 246 dynamic_hex_dump("comp ", DUMP_PREFIX_OFFSET, 16, 1, 247 &ctx->comp, sizeof(ctx->comp), true); 248 249 complete_all(&ctx->work); 250 } 251 252 static int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 253 { 254 struct ionic_desc_info *desc_info; 255 struct ionic_queue *q; 256 int err = 0; 257 258 if (!lif->adminqcq) 259 return -EIO; 260 261 q = &lif->adminqcq->q; 262 263 spin_lock(&lif->adminq_lock); 264 if (!ionic_q_has_space(q, 1)) { 265 err = -ENOSPC; 266 goto err_out; 267 } 268 269 err = ionic_heartbeat_check(lif->ionic); 270 if (err) 271 goto err_out; 272 273 desc_info = &q->info[q->head_idx]; 274 memcpy(desc_info->desc, &ctx->cmd, sizeof(ctx->cmd)); 275 276 dev_dbg(&lif->netdev->dev, "post admin queue command:\n"); 277 dynamic_hex_dump("cmd ", DUMP_PREFIX_OFFSET, 16, 1, 278 &ctx->cmd, sizeof(ctx->cmd), true); 279 280 ionic_q_post(q, true, ionic_adminq_cb, ctx); 281 282 err_out: 283 spin_unlock(&lif->adminq_lock); 284 285 return err; 286 } 287 288 int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 289 { 290 struct net_device *netdev = lif->netdev; 291 unsigned long remaining; 292 const char *name; 293 int err; 294 295 err = ionic_adminq_post(lif, ctx); 296 if (err) { 297 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 298 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 299 netdev_err(netdev, "Posting of %s (%d) failed: %d\n", 300 name, ctx->cmd.cmd.opcode, err); 301 } 302 return err; 303 } 304 305 remaining = wait_for_completion_timeout(&ctx->work, 306 HZ * (ulong)DEVCMD_TIMEOUT); 307 return ionic_adminq_check_err(lif, ctx, (remaining == 0)); 308 } 309 310 static void ionic_dev_cmd_clean(struct ionic *ionic) 311 { 312 union __iomem ionic_dev_cmd_regs *regs = ionic->idev.dev_cmd_regs; 313 314 iowrite32(0, ®s->doorbell); 315 memset_io(®s->cmd, 0, sizeof(regs->cmd)); 316 } 317 318 int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds) 319 { 320 struct ionic_dev *idev = &ionic->idev; 321 unsigned long start_time; 322 unsigned long max_wait; 323 unsigned long duration; 324 int opcode; 325 int hb = 0; 326 int done; 327 int err; 328 329 /* Wait for dev cmd to complete, retrying if we get EAGAIN, 330 * but don't wait any longer than max_seconds. 331 */ 332 max_wait = jiffies + (max_seconds * HZ); 333 try_again: 334 opcode = readb(&idev->dev_cmd_regs->cmd.cmd.opcode); 335 start_time = jiffies; 336 do { 337 done = ionic_dev_cmd_done(idev); 338 if (done) 339 break; 340 usleep_range(100, 200); 341 342 /* Don't check the heartbeat on FW_CONTROL commands as they are 343 * notorious for interrupting the firmware's heartbeat update. 344 */ 345 if (opcode != IONIC_CMD_FW_CONTROL) 346 hb = ionic_heartbeat_check(ionic); 347 } while (!done && !hb && time_before(jiffies, max_wait)); 348 duration = jiffies - start_time; 349 350 dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n", 351 ionic_opcode_to_str(opcode), opcode, 352 done, duration / HZ, duration); 353 354 if (!done && hb) { 355 /* It is possible (but unlikely) that FW was busy and missed a 356 * heartbeat check but is still alive and will process this 357 * request, so don't clean the dev_cmd in this case. 358 */ 359 dev_warn(ionic->dev, "DEVCMD %s (%d) failed - FW halted\n", 360 ionic_opcode_to_str(opcode), opcode); 361 return -ENXIO; 362 } 363 364 if (!done && !time_before(jiffies, max_wait)) { 365 ionic_dev_cmd_clean(ionic); 366 dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n", 367 ionic_opcode_to_str(opcode), opcode, max_seconds); 368 return -ETIMEDOUT; 369 } 370 371 err = ionic_dev_cmd_status(&ionic->idev); 372 if (err) { 373 if (err == IONIC_RC_EAGAIN && 374 time_before(jiffies, (max_wait - HZ))) { 375 dev_dbg(ionic->dev, "DEV_CMD %s (%d), %s (%d) retrying...\n", 376 ionic_opcode_to_str(opcode), opcode, 377 ionic_error_to_str(err), err); 378 379 msleep(1000); 380 iowrite32(0, &idev->dev_cmd_regs->done); 381 iowrite32(1, &idev->dev_cmd_regs->doorbell); 382 goto try_again; 383 } 384 385 if (!(opcode == IONIC_CMD_FW_CONTROL && err == IONIC_RC_EAGAIN)) 386 dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n", 387 ionic_opcode_to_str(opcode), opcode, 388 ionic_error_to_str(err), err); 389 390 return ionic_error_to_errno(err); 391 } 392 393 return 0; 394 } 395 396 int ionic_setup(struct ionic *ionic) 397 { 398 int err; 399 400 err = ionic_dev_setup(ionic); 401 if (err) 402 return err; 403 ionic_reset(ionic); 404 405 return 0; 406 } 407 408 int ionic_identify(struct ionic *ionic) 409 { 410 struct ionic_identity *ident = &ionic->ident; 411 struct ionic_dev *idev = &ionic->idev; 412 size_t sz; 413 int err; 414 415 memset(ident, 0, sizeof(*ident)); 416 417 ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX); 418 strncpy(ident->drv.driver_ver_str, UTS_RELEASE, 419 sizeof(ident->drv.driver_ver_str) - 1); 420 421 mutex_lock(&ionic->dev_cmd_lock); 422 423 sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data)); 424 memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz); 425 426 ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1); 427 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 428 if (!err) { 429 sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data)); 430 memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz); 431 } 432 mutex_unlock(&ionic->dev_cmd_lock); 433 434 if (err) { 435 dev_err(ionic->dev, "Cannot identify ionic: %dn", err); 436 goto err_out; 437 } 438 439 err = ionic_lif_identify(ionic, IONIC_LIF_TYPE_CLASSIC, 440 &ionic->ident.lif); 441 if (err) { 442 dev_err(ionic->dev, "Cannot identify LIFs: %d\n", err); 443 goto err_out; 444 } 445 446 return 0; 447 448 err_out: 449 return err; 450 } 451 452 int ionic_init(struct ionic *ionic) 453 { 454 struct ionic_dev *idev = &ionic->idev; 455 int err; 456 457 mutex_lock(&ionic->dev_cmd_lock); 458 ionic_dev_cmd_init(idev); 459 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 460 mutex_unlock(&ionic->dev_cmd_lock); 461 462 return err; 463 } 464 465 int ionic_reset(struct ionic *ionic) 466 { 467 struct ionic_dev *idev = &ionic->idev; 468 int err; 469 470 mutex_lock(&ionic->dev_cmd_lock); 471 ionic_dev_cmd_reset(idev); 472 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 473 mutex_unlock(&ionic->dev_cmd_lock); 474 475 return err; 476 } 477 478 int ionic_port_identify(struct ionic *ionic) 479 { 480 struct ionic_identity *ident = &ionic->ident; 481 struct ionic_dev *idev = &ionic->idev; 482 size_t sz; 483 int err; 484 485 mutex_lock(&ionic->dev_cmd_lock); 486 487 ionic_dev_cmd_port_identify(idev); 488 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 489 if (!err) { 490 sz = min(sizeof(ident->port), sizeof(idev->dev_cmd_regs->data)); 491 memcpy_fromio(&ident->port, &idev->dev_cmd_regs->data, sz); 492 } 493 494 mutex_unlock(&ionic->dev_cmd_lock); 495 496 return err; 497 } 498 499 int ionic_port_init(struct ionic *ionic) 500 { 501 struct ionic_identity *ident = &ionic->ident; 502 struct ionic_dev *idev = &ionic->idev; 503 size_t sz; 504 int err; 505 506 if (!idev->port_info) { 507 idev->port_info_sz = ALIGN(sizeof(*idev->port_info), PAGE_SIZE); 508 idev->port_info = dma_alloc_coherent(ionic->dev, 509 idev->port_info_sz, 510 &idev->port_info_pa, 511 GFP_KERNEL); 512 if (!idev->port_info) 513 return -ENOMEM; 514 } 515 516 sz = min(sizeof(ident->port.config), sizeof(idev->dev_cmd_regs->data)); 517 518 mutex_lock(&ionic->dev_cmd_lock); 519 520 memcpy_toio(&idev->dev_cmd_regs->data, &ident->port.config, sz); 521 ionic_dev_cmd_port_init(idev); 522 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 523 524 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 525 (void)ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 526 527 mutex_unlock(&ionic->dev_cmd_lock); 528 if (err) { 529 dev_err(ionic->dev, "Failed to init port\n"); 530 dma_free_coherent(ionic->dev, idev->port_info_sz, 531 idev->port_info, idev->port_info_pa); 532 idev->port_info = NULL; 533 idev->port_info_pa = 0; 534 } 535 536 return err; 537 } 538 539 int ionic_port_reset(struct ionic *ionic) 540 { 541 struct ionic_dev *idev = &ionic->idev; 542 int err; 543 544 if (!idev->port_info) 545 return 0; 546 547 mutex_lock(&ionic->dev_cmd_lock); 548 ionic_dev_cmd_port_reset(idev); 549 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 550 mutex_unlock(&ionic->dev_cmd_lock); 551 552 dma_free_coherent(ionic->dev, idev->port_info_sz, 553 idev->port_info, idev->port_info_pa); 554 555 idev->port_info = NULL; 556 idev->port_info_pa = 0; 557 558 if (err) 559 dev_err(ionic->dev, "Failed to reset port\n"); 560 561 return err; 562 } 563 564 static int __init ionic_init_module(void) 565 { 566 ionic_debugfs_create(); 567 return ionic_bus_register_driver(); 568 } 569 570 static void __exit ionic_cleanup_module(void) 571 { 572 ionic_bus_unregister_driver(); 573 ionic_debugfs_destroy(); 574 575 pr_info("%s removed\n", IONIC_DRV_NAME); 576 } 577 578 module_init(ionic_init_module); 579 module_exit(ionic_cleanup_module); 580