1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/module.h> 7 #include <linux/netdevice.h> 8 #include <linux/utsname.h> 9 #include <generated/utsrelease.h> 10 11 #include "ionic.h" 12 #include "ionic_bus.h" 13 #include "ionic_lif.h" 14 #include "ionic_debugfs.h" 15 16 MODULE_DESCRIPTION(IONIC_DRV_DESCRIPTION); 17 MODULE_AUTHOR("Pensando Systems, Inc"); 18 MODULE_LICENSE("GPL"); 19 20 static const char *ionic_error_to_str(enum ionic_status_code code) 21 { 22 switch (code) { 23 case IONIC_RC_SUCCESS: 24 return "IONIC_RC_SUCCESS"; 25 case IONIC_RC_EVERSION: 26 return "IONIC_RC_EVERSION"; 27 case IONIC_RC_EOPCODE: 28 return "IONIC_RC_EOPCODE"; 29 case IONIC_RC_EIO: 30 return "IONIC_RC_EIO"; 31 case IONIC_RC_EPERM: 32 return "IONIC_RC_EPERM"; 33 case IONIC_RC_EQID: 34 return "IONIC_RC_EQID"; 35 case IONIC_RC_EQTYPE: 36 return "IONIC_RC_EQTYPE"; 37 case IONIC_RC_ENOENT: 38 return "IONIC_RC_ENOENT"; 39 case IONIC_RC_EINTR: 40 return "IONIC_RC_EINTR"; 41 case IONIC_RC_EAGAIN: 42 return "IONIC_RC_EAGAIN"; 43 case IONIC_RC_ENOMEM: 44 return "IONIC_RC_ENOMEM"; 45 case IONIC_RC_EFAULT: 46 return "IONIC_RC_EFAULT"; 47 case IONIC_RC_EBUSY: 48 return "IONIC_RC_EBUSY"; 49 case IONIC_RC_EEXIST: 50 return "IONIC_RC_EEXIST"; 51 case IONIC_RC_EINVAL: 52 return "IONIC_RC_EINVAL"; 53 case IONIC_RC_ENOSPC: 54 return "IONIC_RC_ENOSPC"; 55 case IONIC_RC_ERANGE: 56 return "IONIC_RC_ERANGE"; 57 case IONIC_RC_BAD_ADDR: 58 return "IONIC_RC_BAD_ADDR"; 59 case IONIC_RC_DEV_CMD: 60 return "IONIC_RC_DEV_CMD"; 61 case IONIC_RC_ENOSUPP: 62 return "IONIC_RC_ENOSUPP"; 63 case IONIC_RC_ERROR: 64 return "IONIC_RC_ERROR"; 65 case IONIC_RC_ERDMA: 66 return "IONIC_RC_ERDMA"; 67 default: 68 return "IONIC_RC_UNKNOWN"; 69 } 70 } 71 72 static int ionic_error_to_errno(enum ionic_status_code code) 73 { 74 switch (code) { 75 case IONIC_RC_SUCCESS: 76 return 0; 77 case IONIC_RC_EVERSION: 78 case IONIC_RC_EQTYPE: 79 case IONIC_RC_EQID: 80 case IONIC_RC_EINVAL: 81 case IONIC_RC_ENOSUPP: 82 return -EINVAL; 83 case IONIC_RC_EPERM: 84 return -EPERM; 85 case IONIC_RC_ENOENT: 86 return -ENOENT; 87 case IONIC_RC_EAGAIN: 88 return -EAGAIN; 89 case IONIC_RC_ENOMEM: 90 return -ENOMEM; 91 case IONIC_RC_EFAULT: 92 return -EFAULT; 93 case IONIC_RC_EBUSY: 94 return -EBUSY; 95 case IONIC_RC_EEXIST: 96 return -EEXIST; 97 case IONIC_RC_ENOSPC: 98 return -ENOSPC; 99 case IONIC_RC_ERANGE: 100 return -ERANGE; 101 case IONIC_RC_BAD_ADDR: 102 return -EFAULT; 103 case IONIC_RC_EOPCODE: 104 case IONIC_RC_EINTR: 105 case IONIC_RC_DEV_CMD: 106 case IONIC_RC_ERROR: 107 case IONIC_RC_ERDMA: 108 case IONIC_RC_EIO: 109 default: 110 return -EIO; 111 } 112 } 113 114 static const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode) 115 { 116 switch (opcode) { 117 case IONIC_CMD_NOP: 118 return "IONIC_CMD_NOP"; 119 case IONIC_CMD_INIT: 120 return "IONIC_CMD_INIT"; 121 case IONIC_CMD_RESET: 122 return "IONIC_CMD_RESET"; 123 case IONIC_CMD_IDENTIFY: 124 return "IONIC_CMD_IDENTIFY"; 125 case IONIC_CMD_GETATTR: 126 return "IONIC_CMD_GETATTR"; 127 case IONIC_CMD_SETATTR: 128 return "IONIC_CMD_SETATTR"; 129 case IONIC_CMD_PORT_IDENTIFY: 130 return "IONIC_CMD_PORT_IDENTIFY"; 131 case IONIC_CMD_PORT_INIT: 132 return "IONIC_CMD_PORT_INIT"; 133 case IONIC_CMD_PORT_RESET: 134 return "IONIC_CMD_PORT_RESET"; 135 case IONIC_CMD_PORT_GETATTR: 136 return "IONIC_CMD_PORT_GETATTR"; 137 case IONIC_CMD_PORT_SETATTR: 138 return "IONIC_CMD_PORT_SETATTR"; 139 case IONIC_CMD_LIF_INIT: 140 return "IONIC_CMD_LIF_INIT"; 141 case IONIC_CMD_LIF_RESET: 142 return "IONIC_CMD_LIF_RESET"; 143 case IONIC_CMD_LIF_IDENTIFY: 144 return "IONIC_CMD_LIF_IDENTIFY"; 145 case IONIC_CMD_LIF_SETATTR: 146 return "IONIC_CMD_LIF_SETATTR"; 147 case IONIC_CMD_LIF_GETATTR: 148 return "IONIC_CMD_LIF_GETATTR"; 149 case IONIC_CMD_RX_MODE_SET: 150 return "IONIC_CMD_RX_MODE_SET"; 151 case IONIC_CMD_RX_FILTER_ADD: 152 return "IONIC_CMD_RX_FILTER_ADD"; 153 case IONIC_CMD_RX_FILTER_DEL: 154 return "IONIC_CMD_RX_FILTER_DEL"; 155 case IONIC_CMD_Q_IDENTIFY: 156 return "IONIC_CMD_Q_IDENTIFY"; 157 case IONIC_CMD_Q_INIT: 158 return "IONIC_CMD_Q_INIT"; 159 case IONIC_CMD_Q_CONTROL: 160 return "IONIC_CMD_Q_CONTROL"; 161 case IONIC_CMD_RDMA_RESET_LIF: 162 return "IONIC_CMD_RDMA_RESET_LIF"; 163 case IONIC_CMD_RDMA_CREATE_EQ: 164 return "IONIC_CMD_RDMA_CREATE_EQ"; 165 case IONIC_CMD_RDMA_CREATE_CQ: 166 return "IONIC_CMD_RDMA_CREATE_CQ"; 167 case IONIC_CMD_RDMA_CREATE_ADMINQ: 168 return "IONIC_CMD_RDMA_CREATE_ADMINQ"; 169 case IONIC_CMD_FW_DOWNLOAD: 170 return "IONIC_CMD_FW_DOWNLOAD"; 171 case IONIC_CMD_FW_CONTROL: 172 return "IONIC_CMD_FW_CONTROL"; 173 case IONIC_CMD_FW_DOWNLOAD_V1: 174 return "IONIC_CMD_FW_DOWNLOAD_V1"; 175 case IONIC_CMD_FW_CONTROL_V1: 176 return "IONIC_CMD_FW_CONTROL_V1"; 177 case IONIC_CMD_VF_GETATTR: 178 return "IONIC_CMD_VF_GETATTR"; 179 case IONIC_CMD_VF_SETATTR: 180 return "IONIC_CMD_VF_SETATTR"; 181 default: 182 return "DEVCMD_UNKNOWN"; 183 } 184 } 185 186 static void ionic_adminq_flush(struct ionic_lif *lif) 187 { 188 struct ionic_queue *q = &lif->adminqcq->q; 189 struct ionic_desc_info *desc_info; 190 191 spin_lock(&lif->adminq_lock); 192 193 while (q->tail_idx != q->head_idx) { 194 desc_info = &q->info[q->tail_idx]; 195 memset(desc_info->desc, 0, sizeof(union ionic_adminq_cmd)); 196 desc_info->cb = NULL; 197 desc_info->cb_arg = NULL; 198 q->tail_idx = (q->tail_idx + 1) & (q->num_descs - 1); 199 } 200 spin_unlock(&lif->adminq_lock); 201 } 202 203 static int ionic_adminq_check_err(struct ionic_lif *lif, 204 struct ionic_admin_ctx *ctx, 205 bool timeout) 206 { 207 struct net_device *netdev = lif->netdev; 208 const char *opcode_str; 209 const char *status_str; 210 int err = 0; 211 212 if (ctx->comp.comp.status || timeout) { 213 opcode_str = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 214 status_str = ionic_error_to_str(ctx->comp.comp.status); 215 err = timeout ? -ETIMEDOUT : 216 ionic_error_to_errno(ctx->comp.comp.status); 217 218 netdev_err(netdev, "%s (%d) failed: %s (%d)\n", 219 opcode_str, ctx->cmd.cmd.opcode, 220 timeout ? "TIMEOUT" : status_str, err); 221 222 if (timeout) 223 ionic_adminq_flush(lif); 224 } 225 226 return err; 227 } 228 229 static void ionic_adminq_cb(struct ionic_queue *q, 230 struct ionic_desc_info *desc_info, 231 struct ionic_cq_info *cq_info, void *cb_arg) 232 { 233 struct ionic_admin_ctx *ctx = cb_arg; 234 struct ionic_admin_comp *comp; 235 struct device *dev; 236 237 if (!ctx) 238 return; 239 240 comp = cq_info->cq_desc; 241 dev = &q->lif->netdev->dev; 242 243 memcpy(&ctx->comp, comp, sizeof(*comp)); 244 245 dev_dbg(dev, "comp admin queue command:\n"); 246 dynamic_hex_dump("comp ", DUMP_PREFIX_OFFSET, 16, 1, 247 &ctx->comp, sizeof(ctx->comp), true); 248 249 complete_all(&ctx->work); 250 } 251 252 static int ionic_adminq_post(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 253 { 254 struct ionic_desc_info *desc_info; 255 struct ionic_queue *q; 256 int err = 0; 257 258 WARN_ON(in_interrupt()); 259 260 if (!lif->adminqcq) 261 return -EIO; 262 263 q = &lif->adminqcq->q; 264 265 spin_lock(&lif->adminq_lock); 266 if (!ionic_q_has_space(q, 1)) { 267 err = -ENOSPC; 268 goto err_out; 269 } 270 271 err = ionic_heartbeat_check(lif->ionic); 272 if (err) 273 goto err_out; 274 275 desc_info = &q->info[q->head_idx]; 276 memcpy(desc_info->desc, &ctx->cmd, sizeof(ctx->cmd)); 277 278 dev_dbg(&lif->netdev->dev, "post admin queue command:\n"); 279 dynamic_hex_dump("cmd ", DUMP_PREFIX_OFFSET, 16, 1, 280 &ctx->cmd, sizeof(ctx->cmd), true); 281 282 ionic_q_post(q, true, ionic_adminq_cb, ctx); 283 284 err_out: 285 spin_unlock(&lif->adminq_lock); 286 287 return err; 288 } 289 290 int ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx) 291 { 292 struct net_device *netdev = lif->netdev; 293 unsigned long remaining; 294 const char *name; 295 int err; 296 297 err = ionic_adminq_post(lif, ctx); 298 if (err) { 299 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 300 name = ionic_opcode_to_str(ctx->cmd.cmd.opcode); 301 netdev_err(netdev, "Posting of %s (%d) failed: %d\n", 302 name, ctx->cmd.cmd.opcode, err); 303 } 304 return err; 305 } 306 307 remaining = wait_for_completion_timeout(&ctx->work, 308 HZ * (ulong)DEVCMD_TIMEOUT); 309 return ionic_adminq_check_err(lif, ctx, (remaining == 0)); 310 } 311 312 static void ionic_dev_cmd_clean(struct ionic *ionic) 313 { 314 union ionic_dev_cmd_regs *regs = ionic->idev.dev_cmd_regs; 315 316 iowrite32(0, ®s->doorbell); 317 memset_io(®s->cmd, 0, sizeof(regs->cmd)); 318 } 319 320 int ionic_dev_cmd_wait(struct ionic *ionic, unsigned long max_seconds) 321 { 322 struct ionic_dev *idev = &ionic->idev; 323 unsigned long start_time; 324 unsigned long max_wait; 325 unsigned long duration; 326 int opcode; 327 int hb = 0; 328 int done; 329 int err; 330 331 WARN_ON(in_interrupt()); 332 333 /* Wait for dev cmd to complete, retrying if we get EAGAIN, 334 * but don't wait any longer than max_seconds. 335 */ 336 max_wait = jiffies + (max_seconds * HZ); 337 try_again: 338 opcode = idev->dev_cmd_regs->cmd.cmd.opcode; 339 start_time = jiffies; 340 do { 341 done = ionic_dev_cmd_done(idev); 342 if (done) 343 break; 344 usleep_range(100, 200); 345 346 /* Don't check the heartbeat on FW_CONTROL commands as they are 347 * notorious for interrupting the firmware's heartbeat update. 348 */ 349 if (opcode != IONIC_CMD_FW_CONTROL) 350 hb = ionic_heartbeat_check(ionic); 351 } while (!done && !hb && time_before(jiffies, max_wait)); 352 duration = jiffies - start_time; 353 354 dev_dbg(ionic->dev, "DEVCMD %s (%d) done=%d took %ld secs (%ld jiffies)\n", 355 ionic_opcode_to_str(opcode), opcode, 356 done, duration / HZ, duration); 357 358 if (!done && hb) { 359 /* It is possible (but unlikely) that FW was busy and missed a 360 * heartbeat check but is still alive and will process this 361 * request, so don't clean the dev_cmd in this case. 362 */ 363 dev_warn(ionic->dev, "DEVCMD %s (%d) failed - FW halted\n", 364 ionic_opcode_to_str(opcode), opcode); 365 return -ENXIO; 366 } 367 368 if (!done && !time_before(jiffies, max_wait)) { 369 ionic_dev_cmd_clean(ionic); 370 dev_warn(ionic->dev, "DEVCMD %s (%d) timeout after %ld secs\n", 371 ionic_opcode_to_str(opcode), opcode, max_seconds); 372 return -ETIMEDOUT; 373 } 374 375 err = ionic_dev_cmd_status(&ionic->idev); 376 if (err) { 377 if (err == IONIC_RC_EAGAIN && 378 time_before(jiffies, (max_wait - HZ))) { 379 dev_dbg(ionic->dev, "DEV_CMD %s (%d), %s (%d) retrying...\n", 380 ionic_opcode_to_str(opcode), opcode, 381 ionic_error_to_str(err), err); 382 383 msleep(1000); 384 iowrite32(0, &idev->dev_cmd_regs->done); 385 iowrite32(1, &idev->dev_cmd_regs->doorbell); 386 goto try_again; 387 } 388 389 if (!(opcode == IONIC_CMD_FW_CONTROL && err == IONIC_RC_EAGAIN)) 390 dev_err(ionic->dev, "DEV_CMD %s (%d) error, %s (%d) failed\n", 391 ionic_opcode_to_str(opcode), opcode, 392 ionic_error_to_str(err), err); 393 394 return ionic_error_to_errno(err); 395 } 396 397 return 0; 398 } 399 400 int ionic_setup(struct ionic *ionic) 401 { 402 int err; 403 404 err = ionic_dev_setup(ionic); 405 if (err) 406 return err; 407 ionic_reset(ionic); 408 409 return 0; 410 } 411 412 int ionic_identify(struct ionic *ionic) 413 { 414 struct ionic_identity *ident = &ionic->ident; 415 struct ionic_dev *idev = &ionic->idev; 416 size_t sz; 417 int err; 418 419 memset(ident, 0, sizeof(*ident)); 420 421 ident->drv.os_type = cpu_to_le32(IONIC_OS_TYPE_LINUX); 422 strncpy(ident->drv.driver_ver_str, UTS_RELEASE, 423 sizeof(ident->drv.driver_ver_str) - 1); 424 425 mutex_lock(&ionic->dev_cmd_lock); 426 427 sz = min(sizeof(ident->drv), sizeof(idev->dev_cmd_regs->data)); 428 memcpy_toio(&idev->dev_cmd_regs->data, &ident->drv, sz); 429 430 ionic_dev_cmd_identify(idev, IONIC_IDENTITY_VERSION_1); 431 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 432 if (!err) { 433 sz = min(sizeof(ident->dev), sizeof(idev->dev_cmd_regs->data)); 434 memcpy_fromio(&ident->dev, &idev->dev_cmd_regs->data, sz); 435 } 436 437 mutex_unlock(&ionic->dev_cmd_lock); 438 439 if (err) 440 goto err_out_unmap; 441 442 ionic_debugfs_add_ident(ionic); 443 444 return 0; 445 446 err_out_unmap: 447 return err; 448 } 449 450 int ionic_init(struct ionic *ionic) 451 { 452 struct ionic_dev *idev = &ionic->idev; 453 int err; 454 455 mutex_lock(&ionic->dev_cmd_lock); 456 ionic_dev_cmd_init(idev); 457 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 458 mutex_unlock(&ionic->dev_cmd_lock); 459 460 return err; 461 } 462 463 int ionic_reset(struct ionic *ionic) 464 { 465 struct ionic_dev *idev = &ionic->idev; 466 int err; 467 468 mutex_lock(&ionic->dev_cmd_lock); 469 ionic_dev_cmd_reset(idev); 470 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 471 mutex_unlock(&ionic->dev_cmd_lock); 472 473 return err; 474 } 475 476 int ionic_port_identify(struct ionic *ionic) 477 { 478 struct ionic_identity *ident = &ionic->ident; 479 struct ionic_dev *idev = &ionic->idev; 480 size_t sz; 481 int err; 482 483 mutex_lock(&ionic->dev_cmd_lock); 484 485 ionic_dev_cmd_port_identify(idev); 486 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 487 if (!err) { 488 sz = min(sizeof(ident->port), sizeof(idev->dev_cmd_regs->data)); 489 memcpy_fromio(&ident->port, &idev->dev_cmd_regs->data, sz); 490 } 491 492 mutex_unlock(&ionic->dev_cmd_lock); 493 494 return err; 495 } 496 497 int ionic_port_init(struct ionic *ionic) 498 { 499 struct ionic_identity *ident = &ionic->ident; 500 struct ionic_dev *idev = &ionic->idev; 501 size_t sz; 502 int err; 503 504 if (!idev->port_info) { 505 idev->port_info_sz = ALIGN(sizeof(*idev->port_info), PAGE_SIZE); 506 idev->port_info = dma_alloc_coherent(ionic->dev, 507 idev->port_info_sz, 508 &idev->port_info_pa, 509 GFP_KERNEL); 510 if (!idev->port_info) { 511 dev_err(ionic->dev, "Failed to allocate port info\n"); 512 return -ENOMEM; 513 } 514 } 515 516 sz = min(sizeof(ident->port.config), sizeof(idev->dev_cmd_regs->data)); 517 518 mutex_lock(&ionic->dev_cmd_lock); 519 520 memcpy_toio(&idev->dev_cmd_regs->data, &ident->port.config, sz); 521 ionic_dev_cmd_port_init(idev); 522 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 523 524 ionic_dev_cmd_port_state(&ionic->idev, IONIC_PORT_ADMIN_STATE_UP); 525 (void)ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 526 527 mutex_unlock(&ionic->dev_cmd_lock); 528 if (err) { 529 dev_err(ionic->dev, "Failed to init port\n"); 530 dma_free_coherent(ionic->dev, idev->port_info_sz, 531 idev->port_info, idev->port_info_pa); 532 idev->port_info = NULL; 533 idev->port_info_pa = 0; 534 } 535 536 return err; 537 } 538 539 int ionic_port_reset(struct ionic *ionic) 540 { 541 struct ionic_dev *idev = &ionic->idev; 542 int err; 543 544 if (!idev->port_info) 545 return 0; 546 547 mutex_lock(&ionic->dev_cmd_lock); 548 ionic_dev_cmd_port_reset(idev); 549 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 550 mutex_unlock(&ionic->dev_cmd_lock); 551 552 dma_free_coherent(ionic->dev, idev->port_info_sz, 553 idev->port_info, idev->port_info_pa); 554 555 idev->port_info = NULL; 556 idev->port_info_pa = 0; 557 558 if (err) 559 dev_err(ionic->dev, "Failed to reset port\n"); 560 561 return err; 562 } 563 564 static int __init ionic_init_module(void) 565 { 566 ionic_debugfs_create(); 567 return ionic_bus_register_driver(); 568 } 569 570 static void __exit ionic_cleanup_module(void) 571 { 572 ionic_bus_unregister_driver(); 573 ionic_debugfs_destroy(); 574 575 pr_info("%s removed\n", IONIC_DRV_NAME); 576 } 577 578 module_init(ionic_init_module); 579 module_exit(ionic_cleanup_module); 580