1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_LIF_H_ 5 #define _IONIC_LIF_H_ 6 7 #include <linux/pci.h> 8 #include "ionic_rx_filter.h" 9 10 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 11 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 12 13 #define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) 14 #define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) 15 #define IONIC_RX_COPYBREAK_DEFAULT 256 16 17 struct ionic_tx_stats { 18 u64 dma_map_err; 19 u64 pkts; 20 u64 bytes; 21 u64 clean; 22 u64 linearize; 23 u64 csum_none; 24 u64 csum; 25 u64 crc32_csum; 26 u64 tso; 27 u64 tso_bytes; 28 u64 frags; 29 u64 vlan_inserted; 30 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; 31 }; 32 33 struct ionic_rx_stats { 34 u64 dma_map_err; 35 u64 alloc_err; 36 u64 pkts; 37 u64 bytes; 38 u64 csum_none; 39 u64 csum_complete; 40 u64 csum_error; 41 u64 buffers_posted; 42 u64 dropped; 43 u64 vlan_stripped; 44 }; 45 46 #define IONIC_QCQ_F_INITED BIT(0) 47 #define IONIC_QCQ_F_SG BIT(1) 48 #define IONIC_QCQ_F_INTR BIT(2) 49 #define IONIC_QCQ_F_TX_STATS BIT(3) 50 #define IONIC_QCQ_F_RX_STATS BIT(4) 51 #define IONIC_QCQ_F_NOTIFYQ BIT(5) 52 53 struct ionic_napi_stats { 54 u64 poll_count; 55 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; 56 }; 57 58 struct ionic_q_stats { 59 union { 60 struct ionic_tx_stats tx; 61 struct ionic_rx_stats rx; 62 }; 63 }; 64 65 struct ionic_qcq { 66 void *base; 67 dma_addr_t base_pa; 68 unsigned int total_size; 69 struct ionic_queue q; 70 struct ionic_cq cq; 71 struct ionic_intr_info intr; 72 struct napi_struct napi; 73 struct ionic_napi_stats napi_stats; 74 struct ionic_q_stats *stats; 75 unsigned int flags; 76 struct dentry *dentry; 77 }; 78 79 struct ionic_qcqst { 80 struct ionic_qcq *qcq; 81 struct ionic_q_stats *stats; 82 }; 83 84 #define q_to_qcq(q) container_of(q, struct ionic_qcq, q) 85 #define q_to_tx_stats(q) (&q_to_qcq(q)->stats->tx) 86 #define q_to_rx_stats(q) (&q_to_qcq(q)->stats->rx) 87 #define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) 88 #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) 89 90 enum ionic_deferred_work_type { 91 IONIC_DW_TYPE_RX_MODE, 92 IONIC_DW_TYPE_RX_ADDR_ADD, 93 IONIC_DW_TYPE_RX_ADDR_DEL, 94 IONIC_DW_TYPE_LINK_STATUS, 95 IONIC_DW_TYPE_LIF_RESET, 96 }; 97 98 struct ionic_deferred_work { 99 struct list_head list; 100 enum ionic_deferred_work_type type; 101 union { 102 unsigned int rx_mode; 103 u8 addr[ETH_ALEN]; 104 u8 fw_status; 105 }; 106 }; 107 108 struct ionic_deferred { 109 spinlock_t lock; /* lock for deferred work list */ 110 struct list_head list; 111 struct work_struct work; 112 }; 113 114 struct ionic_lif_sw_stats { 115 u64 tx_packets; 116 u64 tx_bytes; 117 u64 rx_packets; 118 u64 rx_bytes; 119 u64 tx_tso; 120 u64 tx_tso_bytes; 121 u64 tx_csum_none; 122 u64 tx_csum; 123 u64 rx_csum_none; 124 u64 rx_csum_complete; 125 u64 rx_csum_error; 126 u64 hw_tx_dropped; 127 u64 hw_rx_dropped; 128 u64 hw_rx_over_errors; 129 u64 hw_rx_missed_errors; 130 u64 hw_tx_aborted_errors; 131 }; 132 133 enum ionic_lif_state_flags { 134 IONIC_LIF_F_INITED, 135 IONIC_LIF_F_SW_DEBUG_STATS, 136 IONIC_LIF_F_UP, 137 IONIC_LIF_F_LINK_CHECK_REQUESTED, 138 IONIC_LIF_F_FW_RESET, 139 140 /* leave this as last */ 141 IONIC_LIF_F_STATE_SIZE 142 }; 143 144 struct ionic_qtype_info { 145 u8 version; 146 u8 supported; 147 u64 features; 148 u16 desc_sz; 149 u16 comp_sz; 150 u16 sg_desc_sz; 151 u16 max_sg_elems; 152 u16 sg_desc_stride; 153 }; 154 155 #define IONIC_LIF_NAME_MAX_SZ 32 156 struct ionic_lif { 157 char name[IONIC_LIF_NAME_MAX_SZ]; 158 struct list_head list; 159 struct net_device *netdev; 160 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE); 161 struct ionic *ionic; 162 bool registered; 163 unsigned int index; 164 unsigned int hw_index; 165 unsigned int kern_pid; 166 u64 __iomem *kern_dbpage; 167 struct mutex queue_lock; /* lock for queue structures */ 168 spinlock_t adminq_lock; /* lock for AdminQ operations */ 169 struct ionic_qcq *adminqcq; 170 struct ionic_qcq *notifyqcq; 171 struct ionic_qcqst *txqcqs; 172 struct ionic_qcqst *rxqcqs; 173 u64 last_eid; 174 unsigned int neqs; 175 unsigned int nxqs; 176 unsigned int ntxq_descs; 177 unsigned int nrxq_descs; 178 u32 rx_copybreak; 179 unsigned int rx_mode; 180 u64 hw_features; 181 bool mc_overflow; 182 unsigned int nmcast; 183 bool uc_overflow; 184 u16 lif_type; 185 unsigned int nucast; 186 187 union ionic_lif_identity *identity; 188 struct ionic_lif_info *info; 189 dma_addr_t info_pa; 190 u32 info_sz; 191 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 192 193 u16 rss_types; 194 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 195 u8 *rss_ind_tbl; 196 dma_addr_t rss_ind_tbl_pa; 197 u32 rss_ind_tbl_sz; 198 199 struct ionic_rx_filters rx_filters; 200 struct ionic_deferred deferred; 201 unsigned long *dbid_inuse; 202 unsigned int dbid_count; 203 struct dentry *dentry; 204 u32 rx_coalesce_usecs; /* what the user asked for */ 205 u32 rx_coalesce_hw; /* what the hw is using */ 206 207 struct work_struct tx_timeout_work; 208 }; 209 210 #define lif_to_txqcq(lif, i) ((lif)->txqcqs[i].qcq) 211 #define lif_to_rxqcq(lif, i) ((lif)->rxqcqs[i].qcq) 212 #define lif_to_txstats(lif, i) ((lif)->txqcqs[i].stats->tx) 213 #define lif_to_rxstats(lif, i) ((lif)->rxqcqs[i].stats->rx) 214 #define lif_to_txq(lif, i) (&lif_to_txqcq((lif), i)->q) 215 #define lif_to_rxq(lif, i) (&lif_to_txqcq((lif), i)->q) 216 217 static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) 218 { 219 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 220 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 221 222 /* Div-by-zero should never be an issue, but check anyway */ 223 if (!div || !mult) 224 return 0; 225 226 /* Round up in case usecs is close to the next hw unit */ 227 usecs += (div / mult) >> 1; 228 229 /* Convert from usecs to device units */ 230 return (usecs * mult) / div; 231 } 232 233 typedef void (*ionic_reset_cb)(struct ionic_lif *lif, void *arg); 234 235 void ionic_link_status_check_request(struct ionic_lif *lif); 236 void ionic_get_stats64(struct net_device *netdev, 237 struct rtnl_link_stats64 *ns); 238 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 239 struct ionic_deferred_work *work); 240 int ionic_lifs_alloc(struct ionic *ionic); 241 void ionic_lifs_free(struct ionic *ionic); 242 void ionic_lifs_deinit(struct ionic *ionic); 243 int ionic_lifs_init(struct ionic *ionic); 244 int ionic_lifs_register(struct ionic *ionic); 245 void ionic_lifs_unregister(struct ionic *ionic); 246 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 247 union ionic_lif_identity *lif_ident); 248 int ionic_lifs_size(struct ionic *ionic); 249 int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, 250 const u8 *key, const u32 *indir); 251 252 int ionic_open(struct net_device *netdev); 253 int ionic_stop(struct net_device *netdev); 254 int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg); 255 256 static inline void debug_stats_txq_post(struct ionic_qcq *qcq, 257 struct ionic_txq_desc *desc, bool dbell) 258 { 259 u8 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) 260 & IONIC_TXQ_DESC_NSGE_MASK); 261 262 qcq->q.dbell_count += dbell; 263 264 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) 265 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; 266 267 qcq->stats->tx.sg_cntr[num_sg_elems]++; 268 } 269 270 static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, 271 unsigned int work_done) 272 { 273 qcq->napi_stats.poll_count++; 274 275 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) 276 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; 277 278 qcq->napi_stats.work_done_cntr[work_done]++; 279 } 280 281 #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) 282 #define DEBUG_STATS_RX_BUFF_CNT(qcq) ((qcq)->stats->rx.buffers_posted++) 283 #define DEBUG_STATS_INTR_REARM(intr) ((intr)->rearm_count++) 284 #define DEBUG_STATS_TXQ_POST(qcq, txdesc, dbell) \ 285 debug_stats_txq_post(qcq, txdesc, dbell) 286 #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ 287 debug_stats_napi_poll(qcq, work_done) 288 289 #endif /* _IONIC_LIF_H_ */ 290