1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #ifndef _IONIC_LIF_H_ 5 #define _IONIC_LIF_H_ 6 7 #include <linux/dim.h> 8 #include <linux/pci.h> 9 #include "ionic_rx_filter.h" 10 11 #define IONIC_ADMINQ_LENGTH 16 /* must be a power of two */ 12 #define IONIC_NOTIFYQ_LENGTH 64 /* must be a power of two */ 13 14 #define IONIC_MAX_NUM_NAPI_CNTR (NAPI_POLL_WEIGHT + 1) 15 #define IONIC_MAX_NUM_SG_CNTR (IONIC_TX_MAX_SG_ELEMS + 1) 16 17 #define ADD_ADDR true 18 #define DEL_ADDR false 19 #define CAN_SLEEP true 20 #define CAN_NOT_SLEEP false 21 22 #define IONIC_RX_COPYBREAK_DEFAULT 256 23 #define IONIC_TX_BUDGET_DEFAULT 256 24 25 struct ionic_tx_stats { 26 u64 pkts; 27 u64 bytes; 28 u64 csum_none; 29 u64 csum; 30 u64 tso; 31 u64 tso_bytes; 32 u64 frags; 33 u64 vlan_inserted; 34 u64 clean; 35 u64 linearize; 36 u64 crc32_csum; 37 u64 sg_cntr[IONIC_MAX_NUM_SG_CNTR]; 38 u64 dma_map_err; 39 }; 40 41 struct ionic_rx_stats { 42 u64 pkts; 43 u64 bytes; 44 u64 csum_none; 45 u64 csum_complete; 46 u64 buffers_posted; 47 u64 dropped; 48 u64 vlan_stripped; 49 u64 csum_error; 50 u64 dma_map_err; 51 u64 alloc_err; 52 }; 53 54 #define IONIC_QCQ_F_INITED BIT(0) 55 #define IONIC_QCQ_F_SG BIT(1) 56 #define IONIC_QCQ_F_INTR BIT(2) 57 #define IONIC_QCQ_F_TX_STATS BIT(3) 58 #define IONIC_QCQ_F_RX_STATS BIT(4) 59 #define IONIC_QCQ_F_NOTIFYQ BIT(5) 60 61 struct ionic_napi_stats { 62 u64 poll_count; 63 u64 work_done_cntr[IONIC_MAX_NUM_NAPI_CNTR]; 64 }; 65 66 struct ionic_qcq { 67 void *q_base; 68 dma_addr_t q_base_pa; 69 u32 q_size; 70 void *cq_base; 71 dma_addr_t cq_base_pa; 72 u32 cq_size; 73 void *sg_base; 74 dma_addr_t sg_base_pa; 75 u32 sg_size; 76 struct dim dim; 77 struct ionic_queue q; 78 struct ionic_cq cq; 79 struct ionic_intr_info intr; 80 struct napi_struct napi; 81 struct ionic_napi_stats napi_stats; 82 unsigned int flags; 83 struct dentry *dentry; 84 }; 85 86 #define q_to_qcq(q) container_of(q, struct ionic_qcq, q) 87 #define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index]) 88 #define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index]) 89 #define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi) 90 #define napi_to_cq(napi) (&napi_to_qcq(napi)->cq) 91 92 enum ionic_deferred_work_type { 93 IONIC_DW_TYPE_RX_MODE, 94 IONIC_DW_TYPE_RX_ADDR_ADD, 95 IONIC_DW_TYPE_RX_ADDR_DEL, 96 IONIC_DW_TYPE_LINK_STATUS, 97 IONIC_DW_TYPE_LIF_RESET, 98 }; 99 100 struct ionic_deferred_work { 101 struct list_head list; 102 enum ionic_deferred_work_type type; 103 union { 104 unsigned int rx_mode; 105 u8 addr[ETH_ALEN]; 106 u8 fw_status; 107 }; 108 }; 109 110 struct ionic_deferred { 111 spinlock_t lock; /* lock for deferred work list */ 112 struct list_head list; 113 struct work_struct work; 114 }; 115 116 struct ionic_lif_sw_stats { 117 u64 tx_packets; 118 u64 tx_bytes; 119 u64 rx_packets; 120 u64 rx_bytes; 121 u64 tx_tso; 122 u64 tx_tso_bytes; 123 u64 tx_csum_none; 124 u64 tx_csum; 125 u64 rx_csum_none; 126 u64 rx_csum_complete; 127 u64 rx_csum_error; 128 u64 hw_tx_dropped; 129 u64 hw_rx_dropped; 130 u64 hw_rx_over_errors; 131 u64 hw_rx_missed_errors; 132 u64 hw_tx_aborted_errors; 133 }; 134 135 enum ionic_lif_state_flags { 136 IONIC_LIF_F_INITED, 137 IONIC_LIF_F_SW_DEBUG_STATS, 138 IONIC_LIF_F_UP, 139 IONIC_LIF_F_LINK_CHECK_REQUESTED, 140 IONIC_LIF_F_FW_RESET, 141 IONIC_LIF_F_SPLIT_INTR, 142 IONIC_LIF_F_TX_DIM_INTR, 143 IONIC_LIF_F_RX_DIM_INTR, 144 145 /* leave this as last */ 146 IONIC_LIF_F_STATE_SIZE 147 }; 148 149 struct ionic_qtype_info { 150 u8 version; 151 u8 supported; 152 u64 features; 153 u16 desc_sz; 154 u16 comp_sz; 155 u16 sg_desc_sz; 156 u16 max_sg_elems; 157 u16 sg_desc_stride; 158 }; 159 160 #define IONIC_LIF_NAME_MAX_SZ 32 161 struct ionic_lif { 162 char name[IONIC_LIF_NAME_MAX_SZ]; 163 struct list_head list; 164 struct net_device *netdev; 165 DECLARE_BITMAP(state, IONIC_LIF_F_STATE_SIZE); 166 struct ionic *ionic; 167 bool registered; 168 unsigned int index; 169 unsigned int hw_index; 170 unsigned int kern_pid; 171 u64 __iomem *kern_dbpage; 172 struct mutex queue_lock; /* lock for queue structures */ 173 spinlock_t adminq_lock; /* lock for AdminQ operations */ 174 struct ionic_qcq *adminqcq; 175 struct ionic_qcq *notifyqcq; 176 struct ionic_qcq **txqcqs; 177 struct ionic_tx_stats *txqstats; 178 struct ionic_qcq **rxqcqs; 179 struct ionic_rx_stats *rxqstats; 180 u64 last_eid; 181 unsigned int neqs; 182 unsigned int nxqs; 183 unsigned int ntxq_descs; 184 unsigned int nrxq_descs; 185 u32 rx_copybreak; 186 u32 tx_budget; 187 unsigned int rx_mode; 188 u64 hw_features; 189 bool mc_overflow; 190 unsigned int nmcast; 191 bool uc_overflow; 192 u16 lif_type; 193 unsigned int nucast; 194 195 union ionic_lif_identity *identity; 196 struct ionic_lif_info *info; 197 dma_addr_t info_pa; 198 u32 info_sz; 199 struct ionic_qtype_info qtype_info[IONIC_QTYPE_MAX]; 200 201 u16 rss_types; 202 u8 rss_hash_key[IONIC_RSS_HASH_KEY_SIZE]; 203 u8 *rss_ind_tbl; 204 dma_addr_t rss_ind_tbl_pa; 205 u32 rss_ind_tbl_sz; 206 207 struct ionic_rx_filters rx_filters; 208 struct ionic_deferred deferred; 209 unsigned long *dbid_inuse; 210 unsigned int dbid_count; 211 struct dentry *dentry; 212 u32 rx_coalesce_usecs; /* what the user asked for */ 213 u32 rx_coalesce_hw; /* what the hw is using */ 214 u32 tx_coalesce_usecs; /* what the user asked for */ 215 u32 tx_coalesce_hw; /* what the hw is using */ 216 217 struct work_struct tx_timeout_work; 218 }; 219 220 struct ionic_queue_params { 221 unsigned int nxqs; 222 unsigned int ntxq_descs; 223 unsigned int nrxq_descs; 224 unsigned int intr_split; 225 }; 226 227 static inline void ionic_init_queue_params(struct ionic_lif *lif, 228 struct ionic_queue_params *qparam) 229 { 230 qparam->nxqs = lif->nxqs; 231 qparam->ntxq_descs = lif->ntxq_descs; 232 qparam->nrxq_descs = lif->nrxq_descs; 233 qparam->intr_split = test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 234 } 235 236 static inline u32 ionic_coal_usec_to_hw(struct ionic *ionic, u32 usecs) 237 { 238 u32 mult = le32_to_cpu(ionic->ident.dev.intr_coal_mult); 239 u32 div = le32_to_cpu(ionic->ident.dev.intr_coal_div); 240 241 /* Div-by-zero should never be an issue, but check anyway */ 242 if (!div || !mult) 243 return 0; 244 245 /* Round up in case usecs is close to the next hw unit */ 246 usecs += (div / mult) >> 1; 247 248 /* Convert from usecs to device units */ 249 return (usecs * mult) / div; 250 } 251 252 typedef void (*ionic_reset_cb)(struct ionic_lif *lif, void *arg); 253 254 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep); 255 void ionic_get_stats64(struct net_device *netdev, 256 struct rtnl_link_stats64 *ns); 257 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 258 struct ionic_deferred_work *work); 259 int ionic_lif_alloc(struct ionic *ionic); 260 int ionic_lif_init(struct ionic_lif *lif); 261 void ionic_lif_free(struct ionic_lif *lif); 262 void ionic_lif_deinit(struct ionic_lif *lif); 263 int ionic_lif_register(struct ionic_lif *lif); 264 void ionic_lif_unregister(struct ionic_lif *lif); 265 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 266 union ionic_lif_identity *lif_ident); 267 int ionic_lif_size(struct ionic *ionic); 268 int ionic_lif_rss_config(struct ionic_lif *lif, u16 types, 269 const u8 *key, const u32 *indir); 270 int ionic_reconfigure_queues(struct ionic_lif *lif, 271 struct ionic_queue_params *qparam); 272 273 static inline void debug_stats_txq_post(struct ionic_queue *q, bool dbell) 274 { 275 struct ionic_txq_desc *desc = &q->txq[q->head_idx]; 276 u8 num_sg_elems; 277 278 q->dbell_count += dbell; 279 280 num_sg_elems = ((le64_to_cpu(desc->cmd) >> IONIC_TXQ_DESC_NSGE_SHIFT) 281 & IONIC_TXQ_DESC_NSGE_MASK); 282 if (num_sg_elems > (IONIC_MAX_NUM_SG_CNTR - 1)) 283 num_sg_elems = IONIC_MAX_NUM_SG_CNTR - 1; 284 285 q->lif->txqstats[q->index].sg_cntr[num_sg_elems]++; 286 } 287 288 static inline void debug_stats_napi_poll(struct ionic_qcq *qcq, 289 unsigned int work_done) 290 { 291 qcq->napi_stats.poll_count++; 292 293 if (work_done > (IONIC_MAX_NUM_NAPI_CNTR - 1)) 294 work_done = IONIC_MAX_NUM_NAPI_CNTR - 1; 295 296 qcq->napi_stats.work_done_cntr[work_done]++; 297 } 298 299 #define DEBUG_STATS_CQE_CNT(cq) ((cq)->compl_count++) 300 #define DEBUG_STATS_RX_BUFF_CNT(q) ((q)->lif->rxqstats[q->index].buffers_posted++) 301 #define DEBUG_STATS_TXQ_POST(q, dbell) debug_stats_txq_post(q, dbell) 302 #define DEBUG_STATS_NAPI_POLL(qcq, work_done) \ 303 debug_stats_napi_poll(qcq, work_done) 304 305 #endif /* _IONIC_LIF_H_ */ 306