1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/if_vlan.h> 9 #include <linux/rtnetlink.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/cpumask.h> 13 14 #include "ionic.h" 15 #include "ionic_bus.h" 16 #include "ionic_lif.h" 17 #include "ionic_txrx.h" 18 #include "ionic_ethtool.h" 19 #include "ionic_debugfs.h" 20 21 /* queuetype support level */ 22 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 23 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 24 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 25 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 26 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 27 * 1 = ... with Tx SG version 1 28 */ 29 }; 30 31 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 32 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 33 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static int ionic_start_queues(struct ionic_lif *lif); 40 static void ionic_stop_queues(struct ionic_lif *lif); 41 static void ionic_lif_queue_identify(struct ionic_lif *lif); 42 43 static void ionic_lif_deferred_work(struct work_struct *work) 44 { 45 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 46 struct ionic_deferred *def = &lif->deferred; 47 struct ionic_deferred_work *w = NULL; 48 49 spin_lock_bh(&def->lock); 50 if (!list_empty(&def->list)) { 51 w = list_first_entry(&def->list, 52 struct ionic_deferred_work, list); 53 list_del(&w->list); 54 } 55 spin_unlock_bh(&def->lock); 56 57 if (w) { 58 switch (w->type) { 59 case IONIC_DW_TYPE_RX_MODE: 60 ionic_lif_rx_mode(lif, w->rx_mode); 61 break; 62 case IONIC_DW_TYPE_RX_ADDR_ADD: 63 ionic_lif_addr_add(lif, w->addr); 64 break; 65 case IONIC_DW_TYPE_RX_ADDR_DEL: 66 ionic_lif_addr_del(lif, w->addr); 67 break; 68 case IONIC_DW_TYPE_LINK_STATUS: 69 ionic_link_status_check(lif); 70 break; 71 case IONIC_DW_TYPE_LIF_RESET: 72 if (w->fw_status) 73 ionic_lif_handle_fw_up(lif); 74 else 75 ionic_lif_handle_fw_down(lif); 76 break; 77 default: 78 break; 79 } 80 kfree(w); 81 schedule_work(&def->work); 82 } 83 } 84 85 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 86 struct ionic_deferred_work *work) 87 { 88 spin_lock_bh(&def->lock); 89 list_add_tail(&work->list, &def->list); 90 spin_unlock_bh(&def->lock); 91 schedule_work(&def->work); 92 } 93 94 static void ionic_link_status_check(struct ionic_lif *lif) 95 { 96 struct net_device *netdev = lif->netdev; 97 u16 link_status; 98 bool link_up; 99 100 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state) || 101 test_bit(IONIC_LIF_F_QUEUE_RESET, lif->state)) 102 return; 103 104 link_status = le16_to_cpu(lif->info->status.link_status); 105 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 106 107 if (link_up) { 108 if (!netif_carrier_ok(netdev)) { 109 u32 link_speed; 110 111 ionic_port_identify(lif->ionic); 112 link_speed = le32_to_cpu(lif->info->status.link_speed); 113 netdev_info(netdev, "Link up - %d Gbps\n", 114 link_speed / 1000); 115 netif_carrier_on(netdev); 116 } 117 118 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) 119 ionic_start_queues(lif); 120 } else { 121 if (netif_carrier_ok(netdev)) { 122 netdev_info(netdev, "Link down\n"); 123 netif_carrier_off(netdev); 124 } 125 126 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) 127 ionic_stop_queues(lif); 128 } 129 130 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 131 } 132 133 void ionic_link_status_check_request(struct ionic_lif *lif) 134 { 135 struct ionic_deferred_work *work; 136 137 /* we only need one request outstanding at a time */ 138 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 139 return; 140 141 if (in_interrupt()) { 142 work = kzalloc(sizeof(*work), GFP_ATOMIC); 143 if (!work) 144 return; 145 146 work->type = IONIC_DW_TYPE_LINK_STATUS; 147 ionic_lif_deferred_enqueue(&lif->deferred, work); 148 } else { 149 ionic_link_status_check(lif); 150 } 151 } 152 153 static irqreturn_t ionic_isr(int irq, void *data) 154 { 155 struct napi_struct *napi = data; 156 157 napi_schedule_irqoff(napi); 158 159 return IRQ_HANDLED; 160 } 161 162 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 163 { 164 struct ionic_intr_info *intr = &qcq->intr; 165 struct device *dev = lif->ionic->dev; 166 struct ionic_queue *q = &qcq->q; 167 const char *name; 168 169 if (lif->registered) 170 name = lif->netdev->name; 171 else 172 name = dev_name(dev); 173 174 snprintf(intr->name, sizeof(intr->name), 175 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 176 177 return devm_request_irq(dev, intr->vector, ionic_isr, 178 0, intr->name, &qcq->napi); 179 } 180 181 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 182 { 183 struct ionic *ionic = lif->ionic; 184 int index; 185 186 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 187 if (index == ionic->nintrs) { 188 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 189 __func__, index, ionic->nintrs); 190 return -ENOSPC; 191 } 192 193 set_bit(index, ionic->intrs); 194 ionic_intr_init(&ionic->idev, intr, index); 195 196 return 0; 197 } 198 199 static void ionic_intr_free(struct ionic *ionic, int index) 200 { 201 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 202 clear_bit(index, ionic->intrs); 203 } 204 205 static int ionic_qcq_enable(struct ionic_qcq *qcq) 206 { 207 struct ionic_queue *q = &qcq->q; 208 struct ionic_lif *lif = q->lif; 209 struct ionic_dev *idev; 210 struct device *dev; 211 212 struct ionic_admin_ctx ctx = { 213 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 214 .cmd.q_control = { 215 .opcode = IONIC_CMD_Q_CONTROL, 216 .lif_index = cpu_to_le16(lif->index), 217 .type = q->type, 218 .index = cpu_to_le32(q->index), 219 .oper = IONIC_Q_ENABLE, 220 }, 221 }; 222 223 idev = &lif->ionic->idev; 224 dev = lif->ionic->dev; 225 226 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 227 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 228 229 if (qcq->flags & IONIC_QCQ_F_INTR) { 230 irq_set_affinity_hint(qcq->intr.vector, 231 &qcq->intr.affinity_mask); 232 napi_enable(&qcq->napi); 233 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 234 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 235 IONIC_INTR_MASK_CLEAR); 236 } 237 238 return ionic_adminq_post_wait(lif, &ctx); 239 } 240 241 static int ionic_qcq_disable(struct ionic_qcq *qcq) 242 { 243 struct ionic_queue *q = &qcq->q; 244 struct ionic_lif *lif = q->lif; 245 struct ionic_dev *idev; 246 struct device *dev; 247 248 struct ionic_admin_ctx ctx = { 249 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 250 .cmd.q_control = { 251 .opcode = IONIC_CMD_Q_CONTROL, 252 .lif_index = cpu_to_le16(lif->index), 253 .type = q->type, 254 .index = cpu_to_le32(q->index), 255 .oper = IONIC_Q_DISABLE, 256 }, 257 }; 258 259 idev = &lif->ionic->idev; 260 dev = lif->ionic->dev; 261 262 dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n", 263 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 264 265 if (qcq->flags & IONIC_QCQ_F_INTR) { 266 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 267 IONIC_INTR_MASK_SET); 268 synchronize_irq(qcq->intr.vector); 269 irq_set_affinity_hint(qcq->intr.vector, NULL); 270 napi_disable(&qcq->napi); 271 } 272 273 return ionic_adminq_post_wait(lif, &ctx); 274 } 275 276 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 277 { 278 struct ionic_dev *idev = &lif->ionic->idev; 279 280 if (!qcq) 281 return; 282 283 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 284 return; 285 286 if (qcq->flags & IONIC_QCQ_F_INTR) { 287 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 288 IONIC_INTR_MASK_SET); 289 netif_napi_del(&qcq->napi); 290 } 291 292 qcq->flags &= ~IONIC_QCQ_F_INITED; 293 } 294 295 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 296 { 297 struct device *dev = lif->ionic->dev; 298 299 if (!qcq) 300 return; 301 302 ionic_debugfs_del_qcq(qcq); 303 304 dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa); 305 qcq->base = NULL; 306 qcq->base_pa = 0; 307 308 if (qcq->flags & IONIC_QCQ_F_INTR) { 309 irq_set_affinity_hint(qcq->intr.vector, NULL); 310 devm_free_irq(dev, qcq->intr.vector, &qcq->napi); 311 qcq->intr.vector = 0; 312 ionic_intr_free(lif->ionic, qcq->intr.index); 313 } 314 315 devm_kfree(dev, qcq->cq.info); 316 qcq->cq.info = NULL; 317 devm_kfree(dev, qcq->q.info); 318 qcq->q.info = NULL; 319 devm_kfree(dev, qcq); 320 } 321 322 static void ionic_qcqs_free(struct ionic_lif *lif) 323 { 324 struct device *dev = lif->ionic->dev; 325 unsigned int i; 326 327 if (lif->notifyqcq) { 328 ionic_qcq_free(lif, lif->notifyqcq); 329 lif->notifyqcq = NULL; 330 } 331 332 if (lif->adminqcq) { 333 ionic_qcq_free(lif, lif->adminqcq); 334 lif->adminqcq = NULL; 335 } 336 337 if (lif->rxqcqs) { 338 for (i = 0; i < lif->nxqs; i++) 339 if (lif->rxqcqs[i].stats) 340 devm_kfree(dev, lif->rxqcqs[i].stats); 341 devm_kfree(dev, lif->rxqcqs); 342 lif->rxqcqs = NULL; 343 } 344 345 if (lif->txqcqs) { 346 for (i = 0; i < lif->nxqs; i++) 347 if (lif->txqcqs[i].stats) 348 devm_kfree(dev, lif->txqcqs[i].stats); 349 devm_kfree(dev, lif->txqcqs); 350 lif->txqcqs = NULL; 351 } 352 } 353 354 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 355 struct ionic_qcq *n_qcq) 356 { 357 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 358 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 359 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 360 } 361 362 n_qcq->intr.vector = src_qcq->intr.vector; 363 n_qcq->intr.index = src_qcq->intr.index; 364 } 365 366 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 367 unsigned int index, 368 const char *name, unsigned int flags, 369 unsigned int num_descs, unsigned int desc_size, 370 unsigned int cq_desc_size, 371 unsigned int sg_desc_size, 372 unsigned int pid, struct ionic_qcq **qcq) 373 { 374 struct ionic_dev *idev = &lif->ionic->idev; 375 u32 q_size, cq_size, sg_size, total_size; 376 struct device *dev = lif->ionic->dev; 377 void *q_base, *cq_base, *sg_base; 378 dma_addr_t cq_base_pa = 0; 379 dma_addr_t sg_base_pa = 0; 380 dma_addr_t q_base_pa = 0; 381 struct ionic_qcq *new; 382 int err; 383 384 *qcq = NULL; 385 386 q_size = num_descs * desc_size; 387 cq_size = num_descs * cq_desc_size; 388 sg_size = num_descs * sg_desc_size; 389 390 total_size = ALIGN(q_size, PAGE_SIZE) + ALIGN(cq_size, PAGE_SIZE); 391 /* Note: aligning q_size/cq_size is not enough due to cq_base 392 * address aligning as q_base could be not aligned to the page. 393 * Adding PAGE_SIZE. 394 */ 395 total_size += PAGE_SIZE; 396 if (flags & IONIC_QCQ_F_SG) { 397 total_size += ALIGN(sg_size, PAGE_SIZE); 398 total_size += PAGE_SIZE; 399 } 400 401 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 402 if (!new) { 403 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 404 err = -ENOMEM; 405 goto err_out; 406 } 407 408 new->flags = flags; 409 410 new->q.info = devm_kzalloc(dev, sizeof(*new->q.info) * num_descs, 411 GFP_KERNEL); 412 if (!new->q.info) { 413 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 414 err = -ENOMEM; 415 goto err_out; 416 } 417 418 new->q.type = type; 419 420 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 421 desc_size, sg_desc_size, pid); 422 if (err) { 423 netdev_err(lif->netdev, "Cannot initialize queue\n"); 424 goto err_out; 425 } 426 427 if (flags & IONIC_QCQ_F_INTR) { 428 err = ionic_intr_alloc(lif, &new->intr); 429 if (err) { 430 netdev_warn(lif->netdev, "no intr for %s: %d\n", 431 name, err); 432 goto err_out; 433 } 434 435 err = ionic_bus_get_irq(lif->ionic, new->intr.index); 436 if (err < 0) { 437 netdev_warn(lif->netdev, "no vector for %s: %d\n", 438 name, err); 439 goto err_out_free_intr; 440 } 441 new->intr.vector = err; 442 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index, 443 IONIC_INTR_MASK_SET); 444 445 err = ionic_request_irq(lif, new); 446 if (err) { 447 netdev_warn(lif->netdev, "irq request failed %d\n", err); 448 goto err_out_free_intr; 449 } 450 451 new->intr.cpu = cpumask_local_spread(new->intr.index, 452 dev_to_node(dev)); 453 if (new->intr.cpu != -1) 454 cpumask_set_cpu(new->intr.cpu, 455 &new->intr.affinity_mask); 456 } else { 457 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 458 } 459 460 new->cq.info = devm_kzalloc(dev, sizeof(*new->cq.info) * num_descs, 461 GFP_KERNEL); 462 if (!new->cq.info) { 463 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 464 err = -ENOMEM; 465 goto err_out_free_irq; 466 } 467 468 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 469 if (err) { 470 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 471 goto err_out_free_irq; 472 } 473 474 new->base = dma_alloc_coherent(dev, total_size, &new->base_pa, 475 GFP_KERNEL); 476 if (!new->base) { 477 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 478 err = -ENOMEM; 479 goto err_out_free_irq; 480 } 481 482 new->total_size = total_size; 483 484 q_base = new->base; 485 q_base_pa = new->base_pa; 486 487 cq_base = (void *)ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 488 cq_base_pa = ALIGN(q_base_pa + q_size, PAGE_SIZE); 489 490 if (flags & IONIC_QCQ_F_SG) { 491 sg_base = (void *)ALIGN((uintptr_t)cq_base + cq_size, 492 PAGE_SIZE); 493 sg_base_pa = ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 494 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 495 } 496 497 ionic_q_map(&new->q, q_base, q_base_pa); 498 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 499 ionic_cq_bind(&new->cq, &new->q); 500 501 *qcq = new; 502 503 return 0; 504 505 err_out_free_irq: 506 if (flags & IONIC_QCQ_F_INTR) 507 devm_free_irq(dev, new->intr.vector, &new->napi); 508 err_out_free_intr: 509 if (flags & IONIC_QCQ_F_INTR) 510 ionic_intr_free(lif->ionic, new->intr.index); 511 err_out: 512 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 513 return err; 514 } 515 516 static int ionic_qcqs_alloc(struct ionic_lif *lif) 517 { 518 struct device *dev = lif->ionic->dev; 519 unsigned int q_list_size; 520 unsigned int flags; 521 int err; 522 int i; 523 524 flags = IONIC_QCQ_F_INTR; 525 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 526 IONIC_ADMINQ_LENGTH, 527 sizeof(struct ionic_admin_cmd), 528 sizeof(struct ionic_admin_comp), 529 0, lif->kern_pid, &lif->adminqcq); 530 if (err) 531 return err; 532 ionic_debugfs_add_qcq(lif, lif->adminqcq); 533 534 if (lif->ionic->nnqs_per_lif) { 535 flags = IONIC_QCQ_F_NOTIFYQ; 536 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 537 flags, IONIC_NOTIFYQ_LENGTH, 538 sizeof(struct ionic_notifyq_cmd), 539 sizeof(union ionic_notifyq_comp), 540 0, lif->kern_pid, &lif->notifyqcq); 541 if (err) 542 goto err_out_free_adminqcq; 543 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 544 545 /* Let the notifyq ride on the adminq interrupt */ 546 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 547 } 548 549 q_list_size = sizeof(*lif->txqcqs) * lif->nxqs; 550 err = -ENOMEM; 551 lif->txqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 552 if (!lif->txqcqs) 553 goto err_out_free_notifyqcq; 554 for (i = 0; i < lif->nxqs; i++) { 555 lif->txqcqs[i].stats = devm_kzalloc(dev, 556 sizeof(struct ionic_q_stats), 557 GFP_KERNEL); 558 if (!lif->txqcqs[i].stats) 559 goto err_out_free_tx_stats; 560 } 561 562 lif->rxqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 563 if (!lif->rxqcqs) 564 goto err_out_free_tx_stats; 565 for (i = 0; i < lif->nxqs; i++) { 566 lif->rxqcqs[i].stats = devm_kzalloc(dev, 567 sizeof(struct ionic_q_stats), 568 GFP_KERNEL); 569 if (!lif->rxqcqs[i].stats) 570 goto err_out_free_rx_stats; 571 } 572 573 return 0; 574 575 err_out_free_rx_stats: 576 for (i = 0; i < lif->nxqs; i++) 577 if (lif->rxqcqs[i].stats) 578 devm_kfree(dev, lif->rxqcqs[i].stats); 579 devm_kfree(dev, lif->rxqcqs); 580 lif->rxqcqs = NULL; 581 err_out_free_tx_stats: 582 for (i = 0; i < lif->nxqs; i++) 583 if (lif->txqcqs[i].stats) 584 devm_kfree(dev, lif->txqcqs[i].stats); 585 devm_kfree(dev, lif->txqcqs); 586 lif->txqcqs = NULL; 587 err_out_free_notifyqcq: 588 if (lif->notifyqcq) { 589 ionic_qcq_free(lif, lif->notifyqcq); 590 lif->notifyqcq = NULL; 591 } 592 err_out_free_adminqcq: 593 ionic_qcq_free(lif, lif->adminqcq); 594 lif->adminqcq = NULL; 595 596 return err; 597 } 598 599 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 600 { 601 struct device *dev = lif->ionic->dev; 602 struct ionic_queue *q = &qcq->q; 603 struct ionic_cq *cq = &qcq->cq; 604 struct ionic_admin_ctx ctx = { 605 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 606 .cmd.q_init = { 607 .opcode = IONIC_CMD_Q_INIT, 608 .lif_index = cpu_to_le16(lif->index), 609 .type = q->type, 610 .ver = lif->qtype_info[q->type].version, 611 .index = cpu_to_le32(q->index), 612 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 613 IONIC_QINIT_F_SG), 614 .intr_index = cpu_to_le16(lif->rxqcqs[q->index].qcq->intr.index), 615 .pid = cpu_to_le16(q->pid), 616 .ring_size = ilog2(q->num_descs), 617 .ring_base = cpu_to_le64(q->base_pa), 618 .cq_ring_base = cpu_to_le64(cq->base_pa), 619 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 620 }, 621 }; 622 int err; 623 624 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 625 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 626 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 627 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 628 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 629 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 630 631 q->tail = q->info; 632 q->head = q->tail; 633 cq->tail = cq->info; 634 635 err = ionic_adminq_post_wait(lif, &ctx); 636 if (err) 637 return err; 638 639 q->hw_type = ctx.comp.q_init.hw_type; 640 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 641 q->dbval = IONIC_DBELL_QID(q->hw_index); 642 643 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 644 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 645 646 qcq->flags |= IONIC_QCQ_F_INITED; 647 648 return 0; 649 } 650 651 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 652 { 653 struct device *dev = lif->ionic->dev; 654 struct ionic_queue *q = &qcq->q; 655 struct ionic_cq *cq = &qcq->cq; 656 struct ionic_admin_ctx ctx = { 657 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 658 .cmd.q_init = { 659 .opcode = IONIC_CMD_Q_INIT, 660 .lif_index = cpu_to_le16(lif->index), 661 .type = q->type, 662 .ver = lif->qtype_info[q->type].version, 663 .index = cpu_to_le32(q->index), 664 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 665 IONIC_QINIT_F_SG), 666 .intr_index = cpu_to_le16(cq->bound_intr->index), 667 .pid = cpu_to_le16(q->pid), 668 .ring_size = ilog2(q->num_descs), 669 .ring_base = cpu_to_le64(q->base_pa), 670 .cq_ring_base = cpu_to_le64(cq->base_pa), 671 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 672 }, 673 }; 674 int err; 675 676 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 677 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 678 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 679 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 680 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 681 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 682 683 q->tail = q->info; 684 q->head = q->tail; 685 cq->tail = cq->info; 686 687 err = ionic_adminq_post_wait(lif, &ctx); 688 if (err) 689 return err; 690 691 q->hw_type = ctx.comp.q_init.hw_type; 692 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 693 q->dbval = IONIC_DBELL_QID(q->hw_index); 694 695 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 696 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 697 698 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 699 NAPI_POLL_WEIGHT); 700 701 qcq->flags |= IONIC_QCQ_F_INITED; 702 703 return 0; 704 } 705 706 static bool ionic_notifyq_service(struct ionic_cq *cq, 707 struct ionic_cq_info *cq_info) 708 { 709 union ionic_notifyq_comp *comp = cq_info->cq_desc; 710 struct ionic_deferred_work *work; 711 struct net_device *netdev; 712 struct ionic_queue *q; 713 struct ionic_lif *lif; 714 u64 eid; 715 716 q = cq->bound_q; 717 lif = q->info[0].cb_arg; 718 netdev = lif->netdev; 719 eid = le64_to_cpu(comp->event.eid); 720 721 /* Have we run out of new completions to process? */ 722 if ((s64)(eid - lif->last_eid) <= 0) 723 return false; 724 725 lif->last_eid = eid; 726 727 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 728 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 729 comp, sizeof(*comp), true); 730 731 switch (le16_to_cpu(comp->event.ecode)) { 732 case IONIC_EVENT_LINK_CHANGE: 733 ionic_link_status_check_request(lif); 734 break; 735 case IONIC_EVENT_RESET: 736 work = kzalloc(sizeof(*work), GFP_ATOMIC); 737 if (!work) { 738 netdev_err(lif->netdev, "%s OOM\n", __func__); 739 } else { 740 work->type = IONIC_DW_TYPE_LIF_RESET; 741 ionic_lif_deferred_enqueue(&lif->deferred, work); 742 } 743 break; 744 default: 745 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 746 comp->event.ecode, eid); 747 break; 748 } 749 750 return true; 751 } 752 753 static int ionic_notifyq_clean(struct ionic_lif *lif, int budget) 754 { 755 struct ionic_dev *idev = &lif->ionic->idev; 756 struct ionic_cq *cq = &lif->notifyqcq->cq; 757 u32 work_done; 758 759 work_done = ionic_cq_service(cq, budget, ionic_notifyq_service, 760 NULL, NULL); 761 if (work_done) 762 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 763 work_done, IONIC_INTR_CRED_RESET_COALESCE); 764 765 return work_done; 766 } 767 768 static bool ionic_adminq_service(struct ionic_cq *cq, 769 struct ionic_cq_info *cq_info) 770 { 771 struct ionic_admin_comp *comp = cq_info->cq_desc; 772 773 if (!color_match(comp->color, cq->done_color)) 774 return false; 775 776 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 777 778 return true; 779 } 780 781 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 782 { 783 struct ionic_lif *lif = napi_to_cq(napi)->lif; 784 int n_work = 0; 785 int a_work = 0; 786 787 if (likely(lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)) 788 n_work = ionic_notifyq_clean(lif, budget); 789 a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL); 790 791 return max(n_work, a_work); 792 } 793 794 void ionic_get_stats64(struct net_device *netdev, 795 struct rtnl_link_stats64 *ns) 796 { 797 struct ionic_lif *lif = netdev_priv(netdev); 798 struct ionic_lif_stats *ls; 799 800 memset(ns, 0, sizeof(*ns)); 801 ls = &lif->info->stats; 802 803 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 804 le64_to_cpu(ls->rx_mcast_packets) + 805 le64_to_cpu(ls->rx_bcast_packets); 806 807 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 808 le64_to_cpu(ls->tx_mcast_packets) + 809 le64_to_cpu(ls->tx_bcast_packets); 810 811 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 812 le64_to_cpu(ls->rx_mcast_bytes) + 813 le64_to_cpu(ls->rx_bcast_bytes); 814 815 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 816 le64_to_cpu(ls->tx_mcast_bytes) + 817 le64_to_cpu(ls->tx_bcast_bytes); 818 819 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 820 le64_to_cpu(ls->rx_mcast_drop_packets) + 821 le64_to_cpu(ls->rx_bcast_drop_packets); 822 823 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 824 le64_to_cpu(ls->tx_mcast_drop_packets) + 825 le64_to_cpu(ls->tx_bcast_drop_packets); 826 827 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 828 829 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 830 831 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 832 le64_to_cpu(ls->rx_queue_disabled) + 833 le64_to_cpu(ls->rx_desc_fetch_error) + 834 le64_to_cpu(ls->rx_desc_data_error); 835 836 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 837 le64_to_cpu(ls->tx_queue_disabled) + 838 le64_to_cpu(ls->tx_desc_fetch_error) + 839 le64_to_cpu(ls->tx_desc_data_error); 840 841 ns->rx_errors = ns->rx_over_errors + 842 ns->rx_missed_errors; 843 844 ns->tx_errors = ns->tx_aborted_errors; 845 } 846 847 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 848 { 849 struct ionic_admin_ctx ctx = { 850 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 851 .cmd.rx_filter_add = { 852 .opcode = IONIC_CMD_RX_FILTER_ADD, 853 .lif_index = cpu_to_le16(lif->index), 854 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 855 }, 856 }; 857 struct ionic_rx_filter *f; 858 int err; 859 860 /* don't bother if we already have it */ 861 spin_lock_bh(&lif->rx_filters.lock); 862 f = ionic_rx_filter_by_addr(lif, addr); 863 spin_unlock_bh(&lif->rx_filters.lock); 864 if (f) 865 return 0; 866 867 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM (id %d)\n", addr, 868 ctx.comp.rx_filter_add.filter_id); 869 870 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 871 err = ionic_adminq_post_wait(lif, &ctx); 872 if (err && err != -EEXIST) 873 return err; 874 875 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 876 } 877 878 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 879 { 880 struct ionic_admin_ctx ctx = { 881 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 882 .cmd.rx_filter_del = { 883 .opcode = IONIC_CMD_RX_FILTER_DEL, 884 .lif_index = cpu_to_le16(lif->index), 885 }, 886 }; 887 struct ionic_rx_filter *f; 888 int err; 889 890 spin_lock_bh(&lif->rx_filters.lock); 891 f = ionic_rx_filter_by_addr(lif, addr); 892 if (!f) { 893 spin_unlock_bh(&lif->rx_filters.lock); 894 return -ENOENT; 895 } 896 897 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 898 ionic_rx_filter_free(lif, f); 899 spin_unlock_bh(&lif->rx_filters.lock); 900 901 err = ionic_adminq_post_wait(lif, &ctx); 902 if (err && err != -EEXIST) 903 return err; 904 905 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", addr, 906 ctx.cmd.rx_filter_del.filter_id); 907 908 return 0; 909 } 910 911 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add) 912 { 913 struct ionic *ionic = lif->ionic; 914 struct ionic_deferred_work *work; 915 unsigned int nmfilters; 916 unsigned int nufilters; 917 918 if (add) { 919 /* Do we have space for this filter? We test the counters 920 * here before checking the need for deferral so that we 921 * can return an overflow error to the stack. 922 */ 923 nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters); 924 nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters); 925 926 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 927 lif->nmcast++; 928 else if (!is_multicast_ether_addr(addr) && 929 lif->nucast < nufilters) 930 lif->nucast++; 931 else 932 return -ENOSPC; 933 } else { 934 if (is_multicast_ether_addr(addr) && lif->nmcast) 935 lif->nmcast--; 936 else if (!is_multicast_ether_addr(addr) && lif->nucast) 937 lif->nucast--; 938 } 939 940 if (in_interrupt()) { 941 work = kzalloc(sizeof(*work), GFP_ATOMIC); 942 if (!work) { 943 netdev_err(lif->netdev, "%s OOM\n", __func__); 944 return -ENOMEM; 945 } 946 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 947 IONIC_DW_TYPE_RX_ADDR_DEL; 948 memcpy(work->addr, addr, ETH_ALEN); 949 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 950 add ? "add" : "del", addr); 951 ionic_lif_deferred_enqueue(&lif->deferred, work); 952 } else { 953 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 954 add ? "add" : "del", addr); 955 if (add) 956 return ionic_lif_addr_add(lif, addr); 957 else 958 return ionic_lif_addr_del(lif, addr); 959 } 960 961 return 0; 962 } 963 964 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 965 { 966 return ionic_lif_addr(netdev_priv(netdev), addr, true); 967 } 968 969 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 970 { 971 return ionic_lif_addr(netdev_priv(netdev), addr, false); 972 } 973 974 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 975 { 976 struct ionic_admin_ctx ctx = { 977 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 978 .cmd.rx_mode_set = { 979 .opcode = IONIC_CMD_RX_MODE_SET, 980 .lif_index = cpu_to_le16(lif->index), 981 .rx_mode = cpu_to_le16(rx_mode), 982 }, 983 }; 984 char buf[128]; 985 int err; 986 int i; 987 #define REMAIN(__x) (sizeof(buf) - (__x)) 988 989 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 990 lif->rx_mode, rx_mode); 991 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 992 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 993 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 994 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 995 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 996 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 997 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 998 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 999 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1000 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1001 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1002 1003 err = ionic_adminq_post_wait(lif, &ctx); 1004 if (err) 1005 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1006 rx_mode, err); 1007 else 1008 lif->rx_mode = rx_mode; 1009 } 1010 1011 static void _ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1012 { 1013 struct ionic_deferred_work *work; 1014 1015 if (in_interrupt()) { 1016 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1017 if (!work) { 1018 netdev_err(lif->netdev, "%s OOM\n", __func__); 1019 return; 1020 } 1021 work->type = IONIC_DW_TYPE_RX_MODE; 1022 work->rx_mode = rx_mode; 1023 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1024 ionic_lif_deferred_enqueue(&lif->deferred, work); 1025 } else { 1026 ionic_lif_rx_mode(lif, rx_mode); 1027 } 1028 } 1029 1030 static void ionic_set_rx_mode(struct net_device *netdev) 1031 { 1032 struct ionic_lif *lif = netdev_priv(netdev); 1033 struct ionic_identity *ident; 1034 unsigned int nfilters; 1035 unsigned int rx_mode; 1036 1037 ident = &lif->ionic->ident; 1038 1039 rx_mode = IONIC_RX_MODE_F_UNICAST; 1040 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1041 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1042 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1043 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1044 1045 /* sync unicast addresses 1046 * next check to see if we're in an overflow state 1047 * if so, we track that we overflowed and enable NIC PROMISC 1048 * else if the overflow is set and not needed 1049 * we remove our overflow flag and check the netdev flags 1050 * to see if we can disable NIC PROMISC 1051 */ 1052 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1053 nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters); 1054 if (netdev_uc_count(netdev) + 1 > nfilters) { 1055 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1056 lif->uc_overflow = true; 1057 } else if (lif->uc_overflow) { 1058 lif->uc_overflow = false; 1059 if (!(netdev->flags & IFF_PROMISC)) 1060 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1061 } 1062 1063 /* same for multicast */ 1064 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1065 nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters); 1066 if (netdev_mc_count(netdev) > nfilters) { 1067 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1068 lif->mc_overflow = true; 1069 } else if (lif->mc_overflow) { 1070 lif->mc_overflow = false; 1071 if (!(netdev->flags & IFF_ALLMULTI)) 1072 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1073 } 1074 1075 if (lif->rx_mode != rx_mode) 1076 _ionic_lif_rx_mode(lif, rx_mode); 1077 } 1078 1079 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1080 { 1081 u64 wanted = 0; 1082 1083 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1084 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1085 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1086 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1087 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1088 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1089 if (features & NETIF_F_RXHASH) 1090 wanted |= IONIC_ETH_HW_RX_HASH; 1091 if (features & NETIF_F_RXCSUM) 1092 wanted |= IONIC_ETH_HW_RX_CSUM; 1093 if (features & NETIF_F_SG) 1094 wanted |= IONIC_ETH_HW_TX_SG; 1095 if (features & NETIF_F_HW_CSUM) 1096 wanted |= IONIC_ETH_HW_TX_CSUM; 1097 if (features & NETIF_F_TSO) 1098 wanted |= IONIC_ETH_HW_TSO; 1099 if (features & NETIF_F_TSO6) 1100 wanted |= IONIC_ETH_HW_TSO_IPV6; 1101 if (features & NETIF_F_TSO_ECN) 1102 wanted |= IONIC_ETH_HW_TSO_ECN; 1103 if (features & NETIF_F_GSO_GRE) 1104 wanted |= IONIC_ETH_HW_TSO_GRE; 1105 if (features & NETIF_F_GSO_GRE_CSUM) 1106 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1107 if (features & NETIF_F_GSO_IPXIP4) 1108 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1109 if (features & NETIF_F_GSO_IPXIP6) 1110 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1111 if (features & NETIF_F_GSO_UDP_TUNNEL) 1112 wanted |= IONIC_ETH_HW_TSO_UDP; 1113 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1114 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1115 1116 return cpu_to_le64(wanted); 1117 } 1118 1119 static int ionic_set_nic_features(struct ionic_lif *lif, 1120 netdev_features_t features) 1121 { 1122 struct device *dev = lif->ionic->dev; 1123 struct ionic_admin_ctx ctx = { 1124 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1125 .cmd.lif_setattr = { 1126 .opcode = IONIC_CMD_LIF_SETATTR, 1127 .index = cpu_to_le16(lif->index), 1128 .attr = IONIC_LIF_ATTR_FEATURES, 1129 }, 1130 }; 1131 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1132 IONIC_ETH_HW_VLAN_RX_STRIP | 1133 IONIC_ETH_HW_VLAN_RX_FILTER; 1134 u64 old_hw_features; 1135 int err; 1136 1137 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1138 err = ionic_adminq_post_wait(lif, &ctx); 1139 if (err) 1140 return err; 1141 1142 old_hw_features = lif->hw_features; 1143 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1144 ctx.comp.lif_setattr.features); 1145 1146 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1147 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1148 1149 if ((vlan_flags & features) && 1150 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1151 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1152 1153 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1154 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1155 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1156 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1157 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1158 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1159 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1160 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1161 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1162 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1163 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1164 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1165 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1166 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1167 if (lif->hw_features & IONIC_ETH_HW_TSO) 1168 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1169 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1170 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1171 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1172 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1173 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1174 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1175 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1176 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1177 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1178 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1179 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1180 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1181 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1182 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1183 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1184 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1185 1186 return 0; 1187 } 1188 1189 static int ionic_init_nic_features(struct ionic_lif *lif) 1190 { 1191 struct net_device *netdev = lif->netdev; 1192 netdev_features_t features; 1193 int err; 1194 1195 /* set up what we expect to support by default */ 1196 features = NETIF_F_HW_VLAN_CTAG_TX | 1197 NETIF_F_HW_VLAN_CTAG_RX | 1198 NETIF_F_HW_VLAN_CTAG_FILTER | 1199 NETIF_F_RXHASH | 1200 NETIF_F_SG | 1201 NETIF_F_HW_CSUM | 1202 NETIF_F_RXCSUM | 1203 NETIF_F_TSO | 1204 NETIF_F_TSO6 | 1205 NETIF_F_TSO_ECN; 1206 1207 err = ionic_set_nic_features(lif, features); 1208 if (err) 1209 return err; 1210 1211 /* tell the netdev what we actually can support */ 1212 netdev->features |= NETIF_F_HIGHDMA; 1213 1214 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1215 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1216 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1217 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1218 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1219 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1220 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1221 netdev->hw_features |= NETIF_F_RXHASH; 1222 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1223 netdev->hw_features |= NETIF_F_SG; 1224 1225 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1226 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1227 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1228 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1229 if (lif->hw_features & IONIC_ETH_HW_TSO) 1230 netdev->hw_enc_features |= NETIF_F_TSO; 1231 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1232 netdev->hw_enc_features |= NETIF_F_TSO6; 1233 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1234 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1235 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1236 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1237 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1238 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1239 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1240 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1241 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1242 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1243 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1244 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1245 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1246 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1247 1248 netdev->hw_features |= netdev->hw_enc_features; 1249 netdev->features |= netdev->hw_features; 1250 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1251 1252 netdev->priv_flags |= IFF_UNICAST_FLT | 1253 IFF_LIVE_ADDR_CHANGE; 1254 1255 return 0; 1256 } 1257 1258 static int ionic_set_features(struct net_device *netdev, 1259 netdev_features_t features) 1260 { 1261 struct ionic_lif *lif = netdev_priv(netdev); 1262 int err; 1263 1264 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1265 __func__, (u64)lif->netdev->features, (u64)features); 1266 1267 err = ionic_set_nic_features(lif, features); 1268 1269 return err; 1270 } 1271 1272 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1273 { 1274 struct sockaddr *addr = sa; 1275 u8 *mac; 1276 int err; 1277 1278 mac = (u8 *)addr->sa_data; 1279 if (ether_addr_equal(netdev->dev_addr, mac)) 1280 return 0; 1281 1282 err = eth_prepare_mac_addr_change(netdev, addr); 1283 if (err) 1284 return err; 1285 1286 if (!is_zero_ether_addr(netdev->dev_addr)) { 1287 netdev_info(netdev, "deleting mac addr %pM\n", 1288 netdev->dev_addr); 1289 ionic_addr_del(netdev, netdev->dev_addr); 1290 } 1291 1292 eth_commit_mac_addr_change(netdev, addr); 1293 netdev_info(netdev, "updating mac addr %pM\n", mac); 1294 1295 return ionic_addr_add(netdev, mac); 1296 } 1297 1298 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1299 { 1300 struct ionic_lif *lif = netdev_priv(netdev); 1301 struct ionic_admin_ctx ctx = { 1302 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1303 .cmd.lif_setattr = { 1304 .opcode = IONIC_CMD_LIF_SETATTR, 1305 .index = cpu_to_le16(lif->index), 1306 .attr = IONIC_LIF_ATTR_MTU, 1307 .mtu = cpu_to_le32(new_mtu), 1308 }, 1309 }; 1310 int err; 1311 1312 err = ionic_adminq_post_wait(lif, &ctx); 1313 if (err) 1314 return err; 1315 1316 netdev->mtu = new_mtu; 1317 err = ionic_reset_queues(lif, NULL, NULL); 1318 1319 return err; 1320 } 1321 1322 static void ionic_tx_timeout_work(struct work_struct *ws) 1323 { 1324 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1325 1326 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1327 1328 rtnl_lock(); 1329 ionic_reset_queues(lif, NULL, NULL); 1330 rtnl_unlock(); 1331 } 1332 1333 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1334 { 1335 struct ionic_lif *lif = netdev_priv(netdev); 1336 1337 schedule_work(&lif->tx_timeout_work); 1338 } 1339 1340 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1341 u16 vid) 1342 { 1343 struct ionic_lif *lif = netdev_priv(netdev); 1344 struct ionic_admin_ctx ctx = { 1345 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1346 .cmd.rx_filter_add = { 1347 .opcode = IONIC_CMD_RX_FILTER_ADD, 1348 .lif_index = cpu_to_le16(lif->index), 1349 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1350 .vlan.vlan = cpu_to_le16(vid), 1351 }, 1352 }; 1353 int err; 1354 1355 err = ionic_adminq_post_wait(lif, &ctx); 1356 if (err) 1357 return err; 1358 1359 netdev_dbg(netdev, "rx_filter add VLAN %d (id %d)\n", vid, 1360 ctx.comp.rx_filter_add.filter_id); 1361 1362 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1363 } 1364 1365 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1366 u16 vid) 1367 { 1368 struct ionic_lif *lif = netdev_priv(netdev); 1369 struct ionic_admin_ctx ctx = { 1370 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1371 .cmd.rx_filter_del = { 1372 .opcode = IONIC_CMD_RX_FILTER_DEL, 1373 .lif_index = cpu_to_le16(lif->index), 1374 }, 1375 }; 1376 struct ionic_rx_filter *f; 1377 1378 spin_lock_bh(&lif->rx_filters.lock); 1379 1380 f = ionic_rx_filter_by_vlan(lif, vid); 1381 if (!f) { 1382 spin_unlock_bh(&lif->rx_filters.lock); 1383 return -ENOENT; 1384 } 1385 1386 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", vid, 1387 le32_to_cpu(ctx.cmd.rx_filter_del.filter_id)); 1388 1389 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1390 ionic_rx_filter_free(lif, f); 1391 spin_unlock_bh(&lif->rx_filters.lock); 1392 1393 return ionic_adminq_post_wait(lif, &ctx); 1394 } 1395 1396 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1397 const u8 *key, const u32 *indir) 1398 { 1399 struct ionic_admin_ctx ctx = { 1400 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1401 .cmd.lif_setattr = { 1402 .opcode = IONIC_CMD_LIF_SETATTR, 1403 .attr = IONIC_LIF_ATTR_RSS, 1404 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1405 }, 1406 }; 1407 unsigned int i, tbl_sz; 1408 1409 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1410 lif->rss_types = types; 1411 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1412 } 1413 1414 if (key) 1415 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1416 1417 if (indir) { 1418 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1419 for (i = 0; i < tbl_sz; i++) 1420 lif->rss_ind_tbl[i] = indir[i]; 1421 } 1422 1423 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1424 IONIC_RSS_HASH_KEY_SIZE); 1425 1426 return ionic_adminq_post_wait(lif, &ctx); 1427 } 1428 1429 static int ionic_lif_rss_init(struct ionic_lif *lif) 1430 { 1431 unsigned int tbl_sz; 1432 unsigned int i; 1433 1434 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1435 IONIC_RSS_TYPE_IPV4_TCP | 1436 IONIC_RSS_TYPE_IPV4_UDP | 1437 IONIC_RSS_TYPE_IPV6 | 1438 IONIC_RSS_TYPE_IPV6_TCP | 1439 IONIC_RSS_TYPE_IPV6_UDP; 1440 1441 /* Fill indirection table with 'default' values */ 1442 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1443 for (i = 0; i < tbl_sz; i++) 1444 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1445 1446 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1447 } 1448 1449 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1450 { 1451 int tbl_sz; 1452 1453 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1454 memset(lif->rss_ind_tbl, 0, tbl_sz); 1455 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1456 1457 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1458 } 1459 1460 static void ionic_txrx_disable(struct ionic_lif *lif) 1461 { 1462 unsigned int i; 1463 int err; 1464 1465 if (lif->txqcqs) { 1466 for (i = 0; i < lif->nxqs; i++) { 1467 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1468 if (err == -ETIMEDOUT) 1469 break; 1470 } 1471 } 1472 1473 if (lif->rxqcqs) { 1474 for (i = 0; i < lif->nxqs; i++) { 1475 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1476 if (err == -ETIMEDOUT) 1477 break; 1478 } 1479 } 1480 } 1481 1482 static void ionic_txrx_deinit(struct ionic_lif *lif) 1483 { 1484 unsigned int i; 1485 1486 if (lif->txqcqs) { 1487 for (i = 0; i < lif->nxqs; i++) { 1488 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1489 ionic_tx_flush(&lif->txqcqs[i].qcq->cq); 1490 ionic_tx_empty(&lif->txqcqs[i].qcq->q); 1491 } 1492 } 1493 1494 if (lif->rxqcqs) { 1495 for (i = 0; i < lif->nxqs; i++) { 1496 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1497 ionic_rx_flush(&lif->rxqcqs[i].qcq->cq); 1498 ionic_rx_empty(&lif->rxqcqs[i].qcq->q); 1499 } 1500 } 1501 lif->rx_mode = 0; 1502 } 1503 1504 static void ionic_txrx_free(struct ionic_lif *lif) 1505 { 1506 unsigned int i; 1507 1508 if (lif->txqcqs) { 1509 for (i = 0; i < lif->nxqs; i++) { 1510 ionic_qcq_free(lif, lif->txqcqs[i].qcq); 1511 lif->txqcqs[i].qcq = NULL; 1512 } 1513 } 1514 1515 if (lif->rxqcqs) { 1516 for (i = 0; i < lif->nxqs; i++) { 1517 ionic_qcq_free(lif, lif->rxqcqs[i].qcq); 1518 lif->rxqcqs[i].qcq = NULL; 1519 } 1520 } 1521 } 1522 1523 static int ionic_txrx_alloc(struct ionic_lif *lif) 1524 { 1525 unsigned int sg_desc_sz; 1526 unsigned int flags; 1527 unsigned int i; 1528 int err = 0; 1529 1530 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1531 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1532 sizeof(struct ionic_txq_sg_desc_v1)) 1533 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1534 else 1535 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1536 1537 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1538 for (i = 0; i < lif->nxqs; i++) { 1539 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1540 lif->ntxq_descs, 1541 sizeof(struct ionic_txq_desc), 1542 sizeof(struct ionic_txq_comp), 1543 sg_desc_sz, 1544 lif->kern_pid, &lif->txqcqs[i].qcq); 1545 if (err) 1546 goto err_out; 1547 1548 lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats; 1549 ionic_debugfs_add_qcq(lif, lif->txqcqs[i].qcq); 1550 } 1551 1552 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1553 for (i = 0; i < lif->nxqs; i++) { 1554 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1555 lif->nrxq_descs, 1556 sizeof(struct ionic_rxq_desc), 1557 sizeof(struct ionic_rxq_comp), 1558 sizeof(struct ionic_rxq_sg_desc), 1559 lif->kern_pid, &lif->rxqcqs[i].qcq); 1560 if (err) 1561 goto err_out; 1562 1563 lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats; 1564 1565 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1566 lif->rxqcqs[i].qcq->intr.index, 1567 lif->rx_coalesce_hw); 1568 ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq, 1569 lif->txqcqs[i].qcq); 1570 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i].qcq); 1571 } 1572 1573 return 0; 1574 1575 err_out: 1576 ionic_txrx_free(lif); 1577 1578 return err; 1579 } 1580 1581 static int ionic_txrx_init(struct ionic_lif *lif) 1582 { 1583 unsigned int i; 1584 int err; 1585 1586 for (i = 0; i < lif->nxqs; i++) { 1587 err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq); 1588 if (err) 1589 goto err_out; 1590 1591 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq); 1592 if (err) { 1593 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1594 goto err_out; 1595 } 1596 } 1597 1598 if (lif->netdev->features & NETIF_F_RXHASH) 1599 ionic_lif_rss_init(lif); 1600 1601 ionic_set_rx_mode(lif->netdev); 1602 1603 return 0; 1604 1605 err_out: 1606 while (i--) { 1607 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1608 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1609 } 1610 1611 return err; 1612 } 1613 1614 static int ionic_txrx_enable(struct ionic_lif *lif) 1615 { 1616 int i, err; 1617 1618 for (i = 0; i < lif->nxqs; i++) { 1619 ionic_rx_fill(&lif->rxqcqs[i].qcq->q); 1620 err = ionic_qcq_enable(lif->rxqcqs[i].qcq); 1621 if (err) 1622 goto err_out; 1623 1624 err = ionic_qcq_enable(lif->txqcqs[i].qcq); 1625 if (err) { 1626 if (err != -ETIMEDOUT) 1627 ionic_qcq_disable(lif->rxqcqs[i].qcq); 1628 goto err_out; 1629 } 1630 } 1631 1632 return 0; 1633 1634 err_out: 1635 while (i--) { 1636 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1637 if (err == -ETIMEDOUT) 1638 break; 1639 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1640 if (err == -ETIMEDOUT) 1641 break; 1642 } 1643 1644 return err; 1645 } 1646 1647 static int ionic_start_queues(struct ionic_lif *lif) 1648 { 1649 int err; 1650 1651 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1652 return 0; 1653 1654 err = ionic_txrx_enable(lif); 1655 if (err) { 1656 clear_bit(IONIC_LIF_F_UP, lif->state); 1657 return err; 1658 } 1659 netif_tx_wake_all_queues(lif->netdev); 1660 1661 return 0; 1662 } 1663 1664 int ionic_open(struct net_device *netdev) 1665 { 1666 struct ionic_lif *lif = netdev_priv(netdev); 1667 int err; 1668 1669 err = ionic_txrx_alloc(lif); 1670 if (err) 1671 return err; 1672 1673 err = ionic_txrx_init(lif); 1674 if (err) 1675 goto err_out; 1676 1677 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1678 if (err) 1679 goto err_txrx_deinit; 1680 1681 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1682 if (err) 1683 goto err_txrx_deinit; 1684 1685 /* don't start the queues until we have link */ 1686 if (netif_carrier_ok(netdev)) { 1687 err = ionic_start_queues(lif); 1688 if (err) 1689 goto err_txrx_deinit; 1690 } 1691 1692 return 0; 1693 1694 err_txrx_deinit: 1695 ionic_txrx_deinit(lif); 1696 err_out: 1697 ionic_txrx_free(lif); 1698 return err; 1699 } 1700 1701 static void ionic_stop_queues(struct ionic_lif *lif) 1702 { 1703 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1704 return; 1705 1706 netif_tx_disable(lif->netdev); 1707 ionic_txrx_disable(lif); 1708 } 1709 1710 int ionic_stop(struct net_device *netdev) 1711 { 1712 struct ionic_lif *lif = netdev_priv(netdev); 1713 1714 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1715 return 0; 1716 1717 ionic_stop_queues(lif); 1718 ionic_txrx_deinit(lif); 1719 ionic_txrx_free(lif); 1720 1721 return 0; 1722 } 1723 1724 static int ionic_get_vf_config(struct net_device *netdev, 1725 int vf, struct ifla_vf_info *ivf) 1726 { 1727 struct ionic_lif *lif = netdev_priv(netdev); 1728 struct ionic *ionic = lif->ionic; 1729 int ret = 0; 1730 1731 if (!netif_device_present(netdev)) 1732 return -EBUSY; 1733 1734 down_read(&ionic->vf_op_lock); 1735 1736 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1737 ret = -EINVAL; 1738 } else { 1739 ivf->vf = vf; 1740 ivf->vlan = ionic->vfs[vf].vlanid; 1741 ivf->qos = 0; 1742 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1743 ivf->linkstate = ionic->vfs[vf].linkstate; 1744 ivf->max_tx_rate = ionic->vfs[vf].maxrate; 1745 ivf->trusted = ionic->vfs[vf].trusted; 1746 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1747 } 1748 1749 up_read(&ionic->vf_op_lock); 1750 return ret; 1751 } 1752 1753 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1754 struct ifla_vf_stats *vf_stats) 1755 { 1756 struct ionic_lif *lif = netdev_priv(netdev); 1757 struct ionic *ionic = lif->ionic; 1758 struct ionic_lif_stats *vs; 1759 int ret = 0; 1760 1761 if (!netif_device_present(netdev)) 1762 return -EBUSY; 1763 1764 down_read(&ionic->vf_op_lock); 1765 1766 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1767 ret = -EINVAL; 1768 } else { 1769 memset(vf_stats, 0, sizeof(*vf_stats)); 1770 vs = &ionic->vfs[vf].stats; 1771 1772 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1773 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1774 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1775 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1776 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1777 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1778 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1779 le64_to_cpu(vs->rx_mcast_drop_packets) + 1780 le64_to_cpu(vs->rx_bcast_drop_packets); 1781 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1782 le64_to_cpu(vs->tx_mcast_drop_packets) + 1783 le64_to_cpu(vs->tx_bcast_drop_packets); 1784 } 1785 1786 up_read(&ionic->vf_op_lock); 1787 return ret; 1788 } 1789 1790 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1791 { 1792 struct ionic_lif *lif = netdev_priv(netdev); 1793 struct ionic *ionic = lif->ionic; 1794 int ret; 1795 1796 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1797 return -EINVAL; 1798 1799 if (!netif_device_present(netdev)) 1800 return -EBUSY; 1801 1802 down_write(&ionic->vf_op_lock); 1803 1804 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1805 ret = -EINVAL; 1806 } else { 1807 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1808 if (!ret) 1809 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1810 } 1811 1812 up_write(&ionic->vf_op_lock); 1813 return ret; 1814 } 1815 1816 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1817 u8 qos, __be16 proto) 1818 { 1819 struct ionic_lif *lif = netdev_priv(netdev); 1820 struct ionic *ionic = lif->ionic; 1821 int ret; 1822 1823 /* until someday when we support qos */ 1824 if (qos) 1825 return -EINVAL; 1826 1827 if (vlan > 4095) 1828 return -EINVAL; 1829 1830 if (proto != htons(ETH_P_8021Q)) 1831 return -EPROTONOSUPPORT; 1832 1833 if (!netif_device_present(netdev)) 1834 return -EBUSY; 1835 1836 down_write(&ionic->vf_op_lock); 1837 1838 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1839 ret = -EINVAL; 1840 } else { 1841 ret = ionic_set_vf_config(ionic, vf, 1842 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 1843 if (!ret) 1844 ionic->vfs[vf].vlanid = vlan; 1845 } 1846 1847 up_write(&ionic->vf_op_lock); 1848 return ret; 1849 } 1850 1851 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 1852 int tx_min, int tx_max) 1853 { 1854 struct ionic_lif *lif = netdev_priv(netdev); 1855 struct ionic *ionic = lif->ionic; 1856 int ret; 1857 1858 /* setting the min just seems silly */ 1859 if (tx_min) 1860 return -EINVAL; 1861 1862 if (!netif_device_present(netdev)) 1863 return -EBUSY; 1864 1865 down_write(&ionic->vf_op_lock); 1866 1867 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1868 ret = -EINVAL; 1869 } else { 1870 ret = ionic_set_vf_config(ionic, vf, 1871 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 1872 if (!ret) 1873 lif->ionic->vfs[vf].maxrate = tx_max; 1874 } 1875 1876 up_write(&ionic->vf_op_lock); 1877 return ret; 1878 } 1879 1880 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 1881 { 1882 struct ionic_lif *lif = netdev_priv(netdev); 1883 struct ionic *ionic = lif->ionic; 1884 u8 data = set; /* convert to u8 for config */ 1885 int ret; 1886 1887 if (!netif_device_present(netdev)) 1888 return -EBUSY; 1889 1890 down_write(&ionic->vf_op_lock); 1891 1892 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1893 ret = -EINVAL; 1894 } else { 1895 ret = ionic_set_vf_config(ionic, vf, 1896 IONIC_VF_ATTR_SPOOFCHK, &data); 1897 if (!ret) 1898 ionic->vfs[vf].spoofchk = data; 1899 } 1900 1901 up_write(&ionic->vf_op_lock); 1902 return ret; 1903 } 1904 1905 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 1906 { 1907 struct ionic_lif *lif = netdev_priv(netdev); 1908 struct ionic *ionic = lif->ionic; 1909 u8 data = set; /* convert to u8 for config */ 1910 int ret; 1911 1912 if (!netif_device_present(netdev)) 1913 return -EBUSY; 1914 1915 down_write(&ionic->vf_op_lock); 1916 1917 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1918 ret = -EINVAL; 1919 } else { 1920 ret = ionic_set_vf_config(ionic, vf, 1921 IONIC_VF_ATTR_TRUST, &data); 1922 if (!ret) 1923 ionic->vfs[vf].trusted = data; 1924 } 1925 1926 up_write(&ionic->vf_op_lock); 1927 return ret; 1928 } 1929 1930 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 1931 { 1932 struct ionic_lif *lif = netdev_priv(netdev); 1933 struct ionic *ionic = lif->ionic; 1934 u8 data; 1935 int ret; 1936 1937 switch (set) { 1938 case IFLA_VF_LINK_STATE_ENABLE: 1939 data = IONIC_VF_LINK_STATUS_UP; 1940 break; 1941 case IFLA_VF_LINK_STATE_DISABLE: 1942 data = IONIC_VF_LINK_STATUS_DOWN; 1943 break; 1944 case IFLA_VF_LINK_STATE_AUTO: 1945 data = IONIC_VF_LINK_STATUS_AUTO; 1946 break; 1947 default: 1948 return -EINVAL; 1949 } 1950 1951 if (!netif_device_present(netdev)) 1952 return -EBUSY; 1953 1954 down_write(&ionic->vf_op_lock); 1955 1956 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1957 ret = -EINVAL; 1958 } else { 1959 ret = ionic_set_vf_config(ionic, vf, 1960 IONIC_VF_ATTR_LINKSTATE, &data); 1961 if (!ret) 1962 ionic->vfs[vf].linkstate = set; 1963 } 1964 1965 up_write(&ionic->vf_op_lock); 1966 return ret; 1967 } 1968 1969 static const struct net_device_ops ionic_netdev_ops = { 1970 .ndo_open = ionic_open, 1971 .ndo_stop = ionic_stop, 1972 .ndo_start_xmit = ionic_start_xmit, 1973 .ndo_get_stats64 = ionic_get_stats64, 1974 .ndo_set_rx_mode = ionic_set_rx_mode, 1975 .ndo_set_features = ionic_set_features, 1976 .ndo_set_mac_address = ionic_set_mac_address, 1977 .ndo_validate_addr = eth_validate_addr, 1978 .ndo_tx_timeout = ionic_tx_timeout, 1979 .ndo_change_mtu = ionic_change_mtu, 1980 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 1981 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 1982 .ndo_set_vf_vlan = ionic_set_vf_vlan, 1983 .ndo_set_vf_trust = ionic_set_vf_trust, 1984 .ndo_set_vf_mac = ionic_set_vf_mac, 1985 .ndo_set_vf_rate = ionic_set_vf_rate, 1986 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 1987 .ndo_get_vf_config = ionic_get_vf_config, 1988 .ndo_set_vf_link_state = ionic_set_vf_link_state, 1989 .ndo_get_vf_stats = ionic_get_vf_stats, 1990 }; 1991 1992 int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg) 1993 { 1994 bool running; 1995 int err = 0; 1996 1997 err = ionic_wait_for_bit(lif, IONIC_LIF_F_QUEUE_RESET); 1998 if (err) 1999 return err; 2000 2001 running = netif_running(lif->netdev); 2002 if (running) { 2003 netif_device_detach(lif->netdev); 2004 err = ionic_stop(lif->netdev); 2005 if (err) 2006 goto reset_out; 2007 } 2008 2009 if (cb) 2010 cb(lif, arg); 2011 2012 if (running) { 2013 err = ionic_open(lif->netdev); 2014 netif_device_attach(lif->netdev); 2015 } 2016 2017 reset_out: 2018 clear_bit(IONIC_LIF_F_QUEUE_RESET, lif->state); 2019 2020 return err; 2021 } 2022 2023 static struct ionic_lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index) 2024 { 2025 struct device *dev = ionic->dev; 2026 union ionic_lif_identity *lid; 2027 struct net_device *netdev; 2028 struct ionic_lif *lif; 2029 int tbl_sz; 2030 int err; 2031 2032 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2033 if (!lid) 2034 return ERR_PTR(-ENOMEM); 2035 2036 netdev = alloc_etherdev_mqs(sizeof(*lif), 2037 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2038 if (!netdev) { 2039 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2040 err = -ENOMEM; 2041 goto err_out_free_lid; 2042 } 2043 2044 SET_NETDEV_DEV(netdev, dev); 2045 2046 lif = netdev_priv(netdev); 2047 lif->netdev = netdev; 2048 ionic->master_lif = lif; 2049 netdev->netdev_ops = &ionic_netdev_ops; 2050 ionic_ethtool_set_ops(netdev); 2051 2052 netdev->watchdog_timeo = 2 * HZ; 2053 netif_carrier_off(netdev); 2054 2055 lif->identity = lid; 2056 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2057 ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2058 lif->netdev->min_mtu = le32_to_cpu(lif->identity->eth.min_frame_size); 2059 lif->netdev->max_mtu = 2060 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2061 2062 lif->neqs = ionic->neqs_per_lif; 2063 lif->nxqs = ionic->ntxqs_per_lif; 2064 2065 lif->ionic = ionic; 2066 lif->index = index; 2067 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2068 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2069 2070 /* Convert the default coalesce value to actual hw resolution */ 2071 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2072 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2073 lif->rx_coalesce_usecs); 2074 2075 snprintf(lif->name, sizeof(lif->name), "lif%u", index); 2076 2077 spin_lock_init(&lif->adminq_lock); 2078 2079 spin_lock_init(&lif->deferred.lock); 2080 INIT_LIST_HEAD(&lif->deferred.list); 2081 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2082 2083 /* allocate lif info */ 2084 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2085 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2086 &lif->info_pa, GFP_KERNEL); 2087 if (!lif->info) { 2088 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2089 err = -ENOMEM; 2090 goto err_out_free_netdev; 2091 } 2092 2093 ionic_debugfs_add_lif(lif); 2094 2095 /* allocate queues */ 2096 err = ionic_qcqs_alloc(lif); 2097 if (err) 2098 goto err_out_free_lif_info; 2099 2100 /* allocate rss indirection table */ 2101 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2102 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2103 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2104 &lif->rss_ind_tbl_pa, 2105 GFP_KERNEL); 2106 2107 if (!lif->rss_ind_tbl) { 2108 err = -ENOMEM; 2109 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2110 goto err_out_free_qcqs; 2111 } 2112 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2113 2114 list_add_tail(&lif->list, &ionic->lifs); 2115 2116 return lif; 2117 2118 err_out_free_qcqs: 2119 ionic_qcqs_free(lif); 2120 err_out_free_lif_info: 2121 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2122 lif->info = NULL; 2123 lif->info_pa = 0; 2124 err_out_free_netdev: 2125 free_netdev(lif->netdev); 2126 lif = NULL; 2127 err_out_free_lid: 2128 kfree(lid); 2129 2130 return ERR_PTR(err); 2131 } 2132 2133 int ionic_lifs_alloc(struct ionic *ionic) 2134 { 2135 struct ionic_lif *lif; 2136 2137 INIT_LIST_HEAD(&ionic->lifs); 2138 2139 /* only build the first lif, others are for later features */ 2140 set_bit(0, ionic->lifbits); 2141 2142 lif = ionic_lif_alloc(ionic, 0); 2143 if (IS_ERR_OR_NULL(lif)) { 2144 clear_bit(0, ionic->lifbits); 2145 return -ENOMEM; 2146 } 2147 2148 ionic_lif_queue_identify(lif); 2149 2150 return 0; 2151 } 2152 2153 static void ionic_lif_reset(struct ionic_lif *lif) 2154 { 2155 struct ionic_dev *idev = &lif->ionic->idev; 2156 2157 mutex_lock(&lif->ionic->dev_cmd_lock); 2158 ionic_dev_cmd_lif_reset(idev, lif->index); 2159 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2160 mutex_unlock(&lif->ionic->dev_cmd_lock); 2161 } 2162 2163 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2164 { 2165 struct ionic *ionic = lif->ionic; 2166 2167 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2168 return; 2169 2170 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2171 2172 netif_device_detach(lif->netdev); 2173 2174 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2175 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2176 ionic_stop_queues(lif); 2177 } 2178 2179 if (netif_running(lif->netdev)) { 2180 ionic_txrx_deinit(lif); 2181 ionic_txrx_free(lif); 2182 } 2183 ionic_lifs_deinit(ionic); 2184 ionic_reset(ionic); 2185 ionic_qcqs_free(lif); 2186 2187 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2188 } 2189 2190 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2191 { 2192 struct ionic *ionic = lif->ionic; 2193 int err; 2194 2195 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2196 return; 2197 2198 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2199 2200 ionic_init_devinfo(ionic); 2201 ionic_port_init(ionic); 2202 err = ionic_qcqs_alloc(lif); 2203 if (err) 2204 goto err_out; 2205 2206 err = ionic_lifs_init(ionic); 2207 if (err) 2208 goto err_qcqs_free; 2209 2210 if (lif->registered) 2211 ionic_lif_set_netdev_info(lif); 2212 2213 ionic_rx_filter_replay(lif); 2214 2215 if (netif_running(lif->netdev)) { 2216 err = ionic_txrx_alloc(lif); 2217 if (err) 2218 goto err_lifs_deinit; 2219 2220 err = ionic_txrx_init(lif); 2221 if (err) 2222 goto err_txrx_free; 2223 } 2224 2225 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2226 ionic_link_status_check_request(lif); 2227 netif_device_attach(lif->netdev); 2228 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2229 2230 return; 2231 2232 err_txrx_free: 2233 ionic_txrx_free(lif); 2234 err_lifs_deinit: 2235 ionic_lifs_deinit(ionic); 2236 err_qcqs_free: 2237 ionic_qcqs_free(lif); 2238 err_out: 2239 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2240 } 2241 2242 static void ionic_lif_free(struct ionic_lif *lif) 2243 { 2244 struct device *dev = lif->ionic->dev; 2245 2246 /* free rss indirection table */ 2247 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2248 lif->rss_ind_tbl_pa); 2249 lif->rss_ind_tbl = NULL; 2250 lif->rss_ind_tbl_pa = 0; 2251 2252 /* free queues */ 2253 ionic_qcqs_free(lif); 2254 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2255 ionic_lif_reset(lif); 2256 2257 /* free lif info */ 2258 kfree(lif->identity); 2259 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2260 lif->info = NULL; 2261 lif->info_pa = 0; 2262 2263 /* unmap doorbell page */ 2264 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2265 lif->kern_dbpage = NULL; 2266 kfree(lif->dbid_inuse); 2267 lif->dbid_inuse = NULL; 2268 2269 /* free netdev & lif */ 2270 ionic_debugfs_del_lif(lif); 2271 list_del(&lif->list); 2272 free_netdev(lif->netdev); 2273 } 2274 2275 void ionic_lifs_free(struct ionic *ionic) 2276 { 2277 struct list_head *cur, *tmp; 2278 struct ionic_lif *lif; 2279 2280 list_for_each_safe(cur, tmp, &ionic->lifs) { 2281 lif = list_entry(cur, struct ionic_lif, list); 2282 2283 ionic_lif_free(lif); 2284 } 2285 } 2286 2287 static void ionic_lif_deinit(struct ionic_lif *lif) 2288 { 2289 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2290 return; 2291 2292 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2293 cancel_work_sync(&lif->deferred.work); 2294 cancel_work_sync(&lif->tx_timeout_work); 2295 ionic_rx_filters_deinit(lif); 2296 } 2297 2298 if (lif->netdev->features & NETIF_F_RXHASH) 2299 ionic_lif_rss_deinit(lif); 2300 2301 napi_disable(&lif->adminqcq->napi); 2302 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2303 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2304 2305 ionic_lif_reset(lif); 2306 } 2307 2308 void ionic_lifs_deinit(struct ionic *ionic) 2309 { 2310 struct list_head *cur, *tmp; 2311 struct ionic_lif *lif; 2312 2313 list_for_each_safe(cur, tmp, &ionic->lifs) { 2314 lif = list_entry(cur, struct ionic_lif, list); 2315 ionic_lif_deinit(lif); 2316 } 2317 } 2318 2319 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2320 { 2321 struct device *dev = lif->ionic->dev; 2322 struct ionic_q_init_comp comp; 2323 struct ionic_dev *idev; 2324 struct ionic_qcq *qcq; 2325 struct ionic_queue *q; 2326 int err; 2327 2328 idev = &lif->ionic->idev; 2329 qcq = lif->adminqcq; 2330 q = &qcq->q; 2331 2332 mutex_lock(&lif->ionic->dev_cmd_lock); 2333 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2334 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2335 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2336 mutex_unlock(&lif->ionic->dev_cmd_lock); 2337 if (err) { 2338 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2339 return err; 2340 } 2341 2342 q->hw_type = comp.hw_type; 2343 q->hw_index = le32_to_cpu(comp.hw_index); 2344 q->dbval = IONIC_DBELL_QID(q->hw_index); 2345 2346 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2347 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2348 2349 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2350 NAPI_POLL_WEIGHT); 2351 2352 napi_enable(&qcq->napi); 2353 2354 if (qcq->flags & IONIC_QCQ_F_INTR) 2355 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2356 IONIC_INTR_MASK_CLEAR); 2357 2358 qcq->flags |= IONIC_QCQ_F_INITED; 2359 2360 return 0; 2361 } 2362 2363 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2364 { 2365 struct ionic_qcq *qcq = lif->notifyqcq; 2366 struct device *dev = lif->ionic->dev; 2367 struct ionic_queue *q = &qcq->q; 2368 int err; 2369 2370 struct ionic_admin_ctx ctx = { 2371 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2372 .cmd.q_init = { 2373 .opcode = IONIC_CMD_Q_INIT, 2374 .lif_index = cpu_to_le16(lif->index), 2375 .type = q->type, 2376 .ver = lif->qtype_info[q->type].version, 2377 .index = cpu_to_le32(q->index), 2378 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2379 IONIC_QINIT_F_ENA), 2380 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2381 .pid = cpu_to_le16(q->pid), 2382 .ring_size = ilog2(q->num_descs), 2383 .ring_base = cpu_to_le64(q->base_pa), 2384 } 2385 }; 2386 2387 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2388 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2389 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2390 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2391 2392 err = ionic_adminq_post_wait(lif, &ctx); 2393 if (err) 2394 return err; 2395 2396 lif->last_eid = 0; 2397 q->hw_type = ctx.comp.q_init.hw_type; 2398 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2399 q->dbval = IONIC_DBELL_QID(q->hw_index); 2400 2401 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2402 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2403 2404 /* preset the callback info */ 2405 q->info[0].cb_arg = lif; 2406 2407 qcq->flags |= IONIC_QCQ_F_INITED; 2408 2409 return 0; 2410 } 2411 2412 static int ionic_station_set(struct ionic_lif *lif) 2413 { 2414 struct net_device *netdev = lif->netdev; 2415 struct ionic_admin_ctx ctx = { 2416 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2417 .cmd.lif_getattr = { 2418 .opcode = IONIC_CMD_LIF_GETATTR, 2419 .index = cpu_to_le16(lif->index), 2420 .attr = IONIC_LIF_ATTR_MAC, 2421 }, 2422 }; 2423 struct sockaddr addr; 2424 int err; 2425 2426 err = ionic_adminq_post_wait(lif, &ctx); 2427 if (err) 2428 return err; 2429 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2430 ctx.comp.lif_getattr.mac); 2431 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2432 return 0; 2433 2434 if (!is_zero_ether_addr(netdev->dev_addr)) { 2435 /* If the netdev mac is non-zero and doesn't match the default 2436 * device address, it was set by something earlier and we're 2437 * likely here again after a fw-upgrade reset. We need to be 2438 * sure the netdev mac is in our filter list. 2439 */ 2440 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2441 netdev->dev_addr)) 2442 ionic_lif_addr(lif, netdev->dev_addr, true); 2443 } else { 2444 /* Update the netdev mac with the device's mac */ 2445 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2446 addr.sa_family = AF_INET; 2447 err = eth_prepare_mac_addr_change(netdev, &addr); 2448 if (err) { 2449 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2450 addr.sa_data, err); 2451 return 0; 2452 } 2453 2454 eth_commit_mac_addr_change(netdev, &addr); 2455 } 2456 2457 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2458 netdev->dev_addr); 2459 ionic_lif_addr(lif, netdev->dev_addr, true); 2460 2461 return 0; 2462 } 2463 2464 static int ionic_lif_init(struct ionic_lif *lif) 2465 { 2466 struct ionic_dev *idev = &lif->ionic->idev; 2467 struct device *dev = lif->ionic->dev; 2468 struct ionic_lif_init_comp comp; 2469 int dbpage_num; 2470 int err; 2471 2472 mutex_lock(&lif->ionic->dev_cmd_lock); 2473 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2474 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2475 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2476 mutex_unlock(&lif->ionic->dev_cmd_lock); 2477 if (err) 2478 return err; 2479 2480 lif->hw_index = le16_to_cpu(comp.hw_index); 2481 2482 /* now that we have the hw_index we can figure out our doorbell page */ 2483 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2484 if (!lif->dbid_count) { 2485 dev_err(dev, "No doorbell pages, aborting\n"); 2486 return -EINVAL; 2487 } 2488 2489 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 2490 if (!lif->dbid_inuse) { 2491 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2492 return -ENOMEM; 2493 } 2494 2495 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2496 set_bit(0, lif->dbid_inuse); 2497 lif->kern_pid = 0; 2498 2499 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2500 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2501 if (!lif->kern_dbpage) { 2502 dev_err(dev, "Cannot map dbpage, aborting\n"); 2503 err = -ENOMEM; 2504 goto err_out_free_dbid; 2505 } 2506 2507 err = ionic_lif_adminq_init(lif); 2508 if (err) 2509 goto err_out_adminq_deinit; 2510 2511 if (lif->ionic->nnqs_per_lif) { 2512 err = ionic_lif_notifyq_init(lif); 2513 if (err) 2514 goto err_out_notifyq_deinit; 2515 } 2516 2517 err = ionic_init_nic_features(lif); 2518 if (err) 2519 goto err_out_notifyq_deinit; 2520 2521 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2522 err = ionic_rx_filters_init(lif); 2523 if (err) 2524 goto err_out_notifyq_deinit; 2525 } 2526 2527 err = ionic_station_set(lif); 2528 if (err) 2529 goto err_out_notifyq_deinit; 2530 2531 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2532 2533 set_bit(IONIC_LIF_F_INITED, lif->state); 2534 2535 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2536 2537 return 0; 2538 2539 err_out_notifyq_deinit: 2540 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2541 err_out_adminq_deinit: 2542 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2543 ionic_lif_reset(lif); 2544 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2545 lif->kern_dbpage = NULL; 2546 err_out_free_dbid: 2547 kfree(lif->dbid_inuse); 2548 lif->dbid_inuse = NULL; 2549 2550 return err; 2551 } 2552 2553 int ionic_lifs_init(struct ionic *ionic) 2554 { 2555 struct list_head *cur, *tmp; 2556 struct ionic_lif *lif; 2557 int err; 2558 2559 list_for_each_safe(cur, tmp, &ionic->lifs) { 2560 lif = list_entry(cur, struct ionic_lif, list); 2561 err = ionic_lif_init(lif); 2562 if (err) 2563 return err; 2564 } 2565 2566 return 0; 2567 } 2568 2569 static void ionic_lif_notify_work(struct work_struct *ws) 2570 { 2571 } 2572 2573 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2574 { 2575 struct ionic_admin_ctx ctx = { 2576 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2577 .cmd.lif_setattr = { 2578 .opcode = IONIC_CMD_LIF_SETATTR, 2579 .index = cpu_to_le16(lif->index), 2580 .attr = IONIC_LIF_ATTR_NAME, 2581 }, 2582 }; 2583 2584 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2585 sizeof(ctx.cmd.lif_setattr.name)); 2586 2587 ionic_adminq_post_wait(lif, &ctx); 2588 } 2589 2590 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2591 { 2592 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2593 return NULL; 2594 2595 return netdev_priv(netdev); 2596 } 2597 2598 static int ionic_lif_notify(struct notifier_block *nb, 2599 unsigned long event, void *info) 2600 { 2601 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2602 struct ionic *ionic = container_of(nb, struct ionic, nb); 2603 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2604 2605 if (!lif || lif->ionic != ionic) 2606 return NOTIFY_DONE; 2607 2608 switch (event) { 2609 case NETDEV_CHANGENAME: 2610 ionic_lif_set_netdev_info(lif); 2611 break; 2612 } 2613 2614 return NOTIFY_DONE; 2615 } 2616 2617 int ionic_lifs_register(struct ionic *ionic) 2618 { 2619 int err; 2620 2621 INIT_WORK(&ionic->nb_work, ionic_lif_notify_work); 2622 2623 ionic->nb.notifier_call = ionic_lif_notify; 2624 2625 err = register_netdevice_notifier(&ionic->nb); 2626 if (err) 2627 ionic->nb.notifier_call = NULL; 2628 2629 /* only register LIF0 for now */ 2630 err = register_netdev(ionic->master_lif->netdev); 2631 if (err) { 2632 dev_err(ionic->dev, "Cannot register net device, aborting\n"); 2633 return err; 2634 } 2635 ionic->master_lif->registered = true; 2636 ionic_lif_set_netdev_info(ionic->master_lif); 2637 2638 return 0; 2639 } 2640 2641 void ionic_lifs_unregister(struct ionic *ionic) 2642 { 2643 if (ionic->nb.notifier_call) { 2644 unregister_netdevice_notifier(&ionic->nb); 2645 cancel_work_sync(&ionic->nb_work); 2646 ionic->nb.notifier_call = NULL; 2647 } 2648 2649 /* There is only one lif ever registered in the 2650 * current model, so don't bother searching the 2651 * ionic->lif for candidates to unregister 2652 */ 2653 if (ionic->master_lif && 2654 ionic->master_lif->netdev->reg_state == NETREG_REGISTERED) 2655 unregister_netdev(ionic->master_lif->netdev); 2656 } 2657 2658 static void ionic_lif_queue_identify(struct ionic_lif *lif) 2659 { 2660 struct ionic *ionic = lif->ionic; 2661 union ionic_q_identity *q_ident; 2662 struct ionic_dev *idev; 2663 int qtype; 2664 int err; 2665 2666 idev = &lif->ionic->idev; 2667 q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data; 2668 2669 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 2670 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 2671 2672 /* filter out the ones we know about */ 2673 switch (qtype) { 2674 case IONIC_QTYPE_ADMINQ: 2675 case IONIC_QTYPE_NOTIFYQ: 2676 case IONIC_QTYPE_RXQ: 2677 case IONIC_QTYPE_TXQ: 2678 break; 2679 default: 2680 continue; 2681 } 2682 2683 memset(qti, 0, sizeof(*qti)); 2684 2685 mutex_lock(&ionic->dev_cmd_lock); 2686 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 2687 ionic_qtype_versions[qtype]); 2688 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2689 if (!err) { 2690 qti->version = q_ident->version; 2691 qti->supported = q_ident->supported; 2692 qti->features = le64_to_cpu(q_ident->features); 2693 qti->desc_sz = le16_to_cpu(q_ident->desc_sz); 2694 qti->comp_sz = le16_to_cpu(q_ident->comp_sz); 2695 qti->sg_desc_sz = le16_to_cpu(q_ident->sg_desc_sz); 2696 qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems); 2697 qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride); 2698 } 2699 mutex_unlock(&ionic->dev_cmd_lock); 2700 2701 if (err == -EINVAL) { 2702 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 2703 continue; 2704 } else if (err == -EIO) { 2705 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 2706 return; 2707 } else if (err) { 2708 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 2709 qtype, err); 2710 return; 2711 } 2712 2713 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 2714 qtype, qti->version); 2715 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 2716 qtype, qti->supported); 2717 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 2718 qtype, qti->features); 2719 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 2720 qtype, qti->desc_sz); 2721 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 2722 qtype, qti->comp_sz); 2723 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 2724 qtype, qti->sg_desc_sz); 2725 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 2726 qtype, qti->max_sg_elems); 2727 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 2728 qtype, qti->sg_desc_stride); 2729 } 2730 } 2731 2732 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 2733 union ionic_lif_identity *lid) 2734 { 2735 struct ionic_dev *idev = &ionic->idev; 2736 size_t sz; 2737 int err; 2738 2739 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 2740 2741 mutex_lock(&ionic->dev_cmd_lock); 2742 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 2743 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2744 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 2745 mutex_unlock(&ionic->dev_cmd_lock); 2746 if (err) 2747 return (err); 2748 2749 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 2750 le64_to_cpu(lid->capabilities)); 2751 2752 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 2753 le32_to_cpu(lid->eth.max_ucast_filters)); 2754 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 2755 le32_to_cpu(lid->eth.max_mcast_filters)); 2756 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 2757 le64_to_cpu(lid->eth.config.features)); 2758 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 2759 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 2760 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 2761 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 2762 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 2763 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 2764 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 2765 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 2766 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 2767 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 2768 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 2769 le32_to_cpu(lid->eth.config.mtu)); 2770 2771 return 0; 2772 } 2773 2774 int ionic_lifs_size(struct ionic *ionic) 2775 { 2776 struct ionic_identity *ident = &ionic->ident; 2777 unsigned int nintrs, dev_nintrs; 2778 union ionic_lif_config *lc; 2779 unsigned int ntxqs_per_lif; 2780 unsigned int nrxqs_per_lif; 2781 unsigned int neqs_per_lif; 2782 unsigned int nnqs_per_lif; 2783 unsigned int nxqs, neqs; 2784 unsigned int min_intrs; 2785 int err; 2786 2787 lc = &ident->lif.eth.config; 2788 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 2789 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 2790 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 2791 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 2792 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 2793 2794 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 2795 nxqs = min(nxqs, num_online_cpus()); 2796 neqs = min(neqs_per_lif, num_online_cpus()); 2797 2798 try_again: 2799 /* interrupt usage: 2800 * 1 for master lif adminq/notifyq 2801 * 1 for each CPU for master lif TxRx queue pairs 2802 * whatever's left is for RDMA queues 2803 */ 2804 nintrs = 1 + nxqs + neqs; 2805 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 2806 2807 if (nintrs > dev_nintrs) 2808 goto try_fewer; 2809 2810 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 2811 if (err < 0 && err != -ENOSPC) { 2812 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 2813 return err; 2814 } 2815 if (err == -ENOSPC) 2816 goto try_fewer; 2817 2818 if (err != nintrs) { 2819 ionic_bus_free_irq_vectors(ionic); 2820 goto try_fewer; 2821 } 2822 2823 ionic->nnqs_per_lif = nnqs_per_lif; 2824 ionic->neqs_per_lif = neqs; 2825 ionic->ntxqs_per_lif = nxqs; 2826 ionic->nrxqs_per_lif = nxqs; 2827 ionic->nintrs = nintrs; 2828 2829 ionic_debugfs_add_sizes(ionic); 2830 2831 return 0; 2832 2833 try_fewer: 2834 if (nnqs_per_lif > 1) { 2835 nnqs_per_lif >>= 1; 2836 goto try_again; 2837 } 2838 if (neqs > 1) { 2839 neqs >>= 1; 2840 goto try_again; 2841 } 2842 if (nxqs > 1) { 2843 nxqs >>= 1; 2844 goto try_again; 2845 } 2846 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 2847 return -ENOSPC; 2848 } 2849