1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 #include <linux/vmalloc.h> 16 17 #include "ionic.h" 18 #include "ionic_bus.h" 19 #include "ionic_lif.h" 20 #include "ionic_txrx.h" 21 #include "ionic_ethtool.h" 22 #include "ionic_debugfs.h" 23 24 /* queuetype support level */ 25 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 26 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 27 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 28 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 29 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 30 * 1 = ... with Tx SG version 1 31 */ 32 }; 33 34 static void ionic_link_status_check(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 36 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 37 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 38 39 static void ionic_txrx_deinit(struct ionic_lif *lif); 40 static int ionic_txrx_init(struct ionic_lif *lif); 41 static int ionic_start_queues(struct ionic_lif *lif); 42 static void ionic_stop_queues(struct ionic_lif *lif); 43 static void ionic_lif_queue_identify(struct ionic_lif *lif); 44 45 static void ionic_dim_work(struct work_struct *work) 46 { 47 struct dim *dim = container_of(work, struct dim, work); 48 struct dim_cq_moder cur_moder; 49 struct ionic_qcq *qcq; 50 u32 new_coal; 51 52 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 53 qcq = container_of(dim, struct ionic_qcq, dim); 54 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 55 new_coal = new_coal ? new_coal : 1; 56 57 if (qcq->intr.dim_coal_hw != new_coal) { 58 unsigned int qi = qcq->cq.bound_q->index; 59 struct ionic_lif *lif = qcq->q.lif; 60 61 qcq->intr.dim_coal_hw = new_coal; 62 63 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 64 lif->rxqcqs[qi]->intr.index, 65 qcq->intr.dim_coal_hw); 66 } 67 68 dim->state = DIM_START_MEASURE; 69 } 70 71 static void ionic_lif_deferred_work(struct work_struct *work) 72 { 73 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 74 struct ionic_deferred *def = &lif->deferred; 75 struct ionic_deferred_work *w = NULL; 76 77 do { 78 spin_lock_bh(&def->lock); 79 if (!list_empty(&def->list)) { 80 w = list_first_entry(&def->list, 81 struct ionic_deferred_work, list); 82 list_del(&w->list); 83 } 84 spin_unlock_bh(&def->lock); 85 86 if (!w) 87 break; 88 89 switch (w->type) { 90 case IONIC_DW_TYPE_RX_MODE: 91 ionic_lif_rx_mode(lif); 92 break; 93 case IONIC_DW_TYPE_LINK_STATUS: 94 ionic_link_status_check(lif); 95 break; 96 case IONIC_DW_TYPE_LIF_RESET: 97 if (w->fw_status) { 98 ionic_lif_handle_fw_up(lif); 99 } else { 100 ionic_lif_handle_fw_down(lif); 101 102 /* Fire off another watchdog to see 103 * if the FW is already back rather than 104 * waiting another whole cycle 105 */ 106 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 107 } 108 break; 109 default: 110 break; 111 } 112 kfree(w); 113 w = NULL; 114 } while (true); 115 } 116 117 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 118 struct ionic_deferred_work *work) 119 { 120 spin_lock_bh(&def->lock); 121 list_add_tail(&work->list, &def->list); 122 spin_unlock_bh(&def->lock); 123 schedule_work(&def->work); 124 } 125 126 static void ionic_link_status_check(struct ionic_lif *lif) 127 { 128 struct net_device *netdev = lif->netdev; 129 u16 link_status; 130 bool link_up; 131 132 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 133 return; 134 135 /* Don't put carrier back up if we're in a broken state */ 136 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 137 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 138 return; 139 } 140 141 link_status = le16_to_cpu(lif->info->status.link_status); 142 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 143 144 if (link_up) { 145 int err = 0; 146 147 if (netdev->flags & IFF_UP && netif_running(netdev)) { 148 mutex_lock(&lif->queue_lock); 149 err = ionic_start_queues(lif); 150 if (err && err != -EBUSY) { 151 netdev_err(lif->netdev, 152 "Failed to start queues: %d\n", err); 153 set_bit(IONIC_LIF_F_BROKEN, lif->state); 154 netif_carrier_off(lif->netdev); 155 } 156 mutex_unlock(&lif->queue_lock); 157 } 158 159 if (!err && !netif_carrier_ok(netdev)) { 160 ionic_port_identify(lif->ionic); 161 netdev_info(netdev, "Link up - %d Gbps\n", 162 le32_to_cpu(lif->info->status.link_speed) / 1000); 163 netif_carrier_on(netdev); 164 } 165 } else { 166 if (netif_carrier_ok(netdev)) { 167 netdev_info(netdev, "Link down\n"); 168 netif_carrier_off(netdev); 169 } 170 171 if (netdev->flags & IFF_UP && netif_running(netdev)) { 172 mutex_lock(&lif->queue_lock); 173 ionic_stop_queues(lif); 174 mutex_unlock(&lif->queue_lock); 175 } 176 } 177 178 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 179 } 180 181 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 182 { 183 struct ionic_deferred_work *work; 184 185 /* we only need one request outstanding at a time */ 186 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 187 return; 188 189 if (!can_sleep) { 190 work = kzalloc(sizeof(*work), GFP_ATOMIC); 191 if (!work) { 192 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 193 return; 194 } 195 196 work->type = IONIC_DW_TYPE_LINK_STATUS; 197 ionic_lif_deferred_enqueue(&lif->deferred, work); 198 } else { 199 ionic_link_status_check(lif); 200 } 201 } 202 203 static irqreturn_t ionic_isr(int irq, void *data) 204 { 205 struct napi_struct *napi = data; 206 207 napi_schedule_irqoff(napi); 208 209 return IRQ_HANDLED; 210 } 211 212 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 213 { 214 struct ionic_intr_info *intr = &qcq->intr; 215 struct device *dev = lif->ionic->dev; 216 struct ionic_queue *q = &qcq->q; 217 const char *name; 218 219 if (lif->registered) 220 name = lif->netdev->name; 221 else 222 name = dev_name(dev); 223 224 snprintf(intr->name, sizeof(intr->name), 225 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 226 227 return devm_request_irq(dev, intr->vector, ionic_isr, 228 0, intr->name, &qcq->napi); 229 } 230 231 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 232 { 233 struct ionic *ionic = lif->ionic; 234 int index; 235 236 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 237 if (index == ionic->nintrs) { 238 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 239 __func__, index, ionic->nintrs); 240 return -ENOSPC; 241 } 242 243 set_bit(index, ionic->intrs); 244 ionic_intr_init(&ionic->idev, intr, index); 245 246 return 0; 247 } 248 249 static void ionic_intr_free(struct ionic *ionic, int index) 250 { 251 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 252 clear_bit(index, ionic->intrs); 253 } 254 255 static int ionic_qcq_enable(struct ionic_qcq *qcq) 256 { 257 struct ionic_queue *q = &qcq->q; 258 struct ionic_lif *lif = q->lif; 259 struct ionic_dev *idev; 260 struct device *dev; 261 262 struct ionic_admin_ctx ctx = { 263 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 264 .cmd.q_control = { 265 .opcode = IONIC_CMD_Q_CONTROL, 266 .lif_index = cpu_to_le16(lif->index), 267 .type = q->type, 268 .index = cpu_to_le32(q->index), 269 .oper = IONIC_Q_ENABLE, 270 }, 271 }; 272 273 idev = &lif->ionic->idev; 274 dev = lif->ionic->dev; 275 276 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 277 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 278 279 if (qcq->flags & IONIC_QCQ_F_INTR) { 280 irq_set_affinity_hint(qcq->intr.vector, 281 &qcq->intr.affinity_mask); 282 napi_enable(&qcq->napi); 283 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 284 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 285 IONIC_INTR_MASK_CLEAR); 286 } 287 288 return ionic_adminq_post_wait(lif, &ctx); 289 } 290 291 static int ionic_qcq_disable(struct ionic_lif *lif, struct ionic_qcq *qcq, int fw_err) 292 { 293 struct ionic_queue *q; 294 295 struct ionic_admin_ctx ctx = { 296 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 297 .cmd.q_control = { 298 .opcode = IONIC_CMD_Q_CONTROL, 299 .oper = IONIC_Q_DISABLE, 300 }, 301 }; 302 303 if (!qcq) { 304 netdev_err(lif->netdev, "%s: bad qcq\n", __func__); 305 return -ENXIO; 306 } 307 308 q = &qcq->q; 309 310 if (qcq->flags & IONIC_QCQ_F_INTR) { 311 struct ionic_dev *idev = &lif->ionic->idev; 312 313 cancel_work_sync(&qcq->dim.work); 314 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 315 IONIC_INTR_MASK_SET); 316 synchronize_irq(qcq->intr.vector); 317 irq_set_affinity_hint(qcq->intr.vector, NULL); 318 napi_disable(&qcq->napi); 319 } 320 321 /* If there was a previous fw communcation error, don't bother with 322 * sending the adminq command and just return the same error value. 323 */ 324 if (fw_err == -ETIMEDOUT || fw_err == -ENXIO) 325 return fw_err; 326 327 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 328 ctx.cmd.q_control.type = q->type; 329 ctx.cmd.q_control.index = cpu_to_le32(q->index); 330 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 331 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 332 333 return ionic_adminq_post_wait(lif, &ctx); 334 } 335 336 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 337 { 338 struct ionic_dev *idev = &lif->ionic->idev; 339 340 if (!qcq) 341 return; 342 343 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 344 return; 345 346 if (qcq->flags & IONIC_QCQ_F_INTR) { 347 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 348 IONIC_INTR_MASK_SET); 349 netif_napi_del(&qcq->napi); 350 } 351 352 qcq->flags &= ~IONIC_QCQ_F_INITED; 353 } 354 355 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 356 { 357 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 358 return; 359 360 irq_set_affinity_hint(qcq->intr.vector, NULL); 361 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 362 qcq->intr.vector = 0; 363 ionic_intr_free(lif->ionic, qcq->intr.index); 364 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 365 } 366 367 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 368 { 369 struct device *dev = lif->ionic->dev; 370 371 if (!qcq) 372 return; 373 374 ionic_debugfs_del_qcq(qcq); 375 376 if (qcq->q_base) { 377 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 378 qcq->q_base = NULL; 379 qcq->q_base_pa = 0; 380 } 381 382 if (qcq->cq_base) { 383 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 384 qcq->cq_base = NULL; 385 qcq->cq_base_pa = 0; 386 } 387 388 if (qcq->sg_base) { 389 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 390 qcq->sg_base = NULL; 391 qcq->sg_base_pa = 0; 392 } 393 394 ionic_qcq_intr_free(lif, qcq); 395 396 if (qcq->cq.info) { 397 vfree(qcq->cq.info); 398 qcq->cq.info = NULL; 399 } 400 if (qcq->q.info) { 401 vfree(qcq->q.info); 402 qcq->q.info = NULL; 403 } 404 } 405 406 static void ionic_qcqs_free(struct ionic_lif *lif) 407 { 408 struct device *dev = lif->ionic->dev; 409 struct ionic_qcq *adminqcq; 410 unsigned long irqflags; 411 412 if (lif->notifyqcq) { 413 ionic_qcq_free(lif, lif->notifyqcq); 414 devm_kfree(dev, lif->notifyqcq); 415 lif->notifyqcq = NULL; 416 } 417 418 if (lif->adminqcq) { 419 spin_lock_irqsave(&lif->adminq_lock, irqflags); 420 adminqcq = READ_ONCE(lif->adminqcq); 421 lif->adminqcq = NULL; 422 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 423 if (adminqcq) { 424 ionic_qcq_free(lif, adminqcq); 425 devm_kfree(dev, adminqcq); 426 } 427 } 428 429 if (lif->rxqcqs) { 430 devm_kfree(dev, lif->rxqstats); 431 lif->rxqstats = NULL; 432 devm_kfree(dev, lif->rxqcqs); 433 lif->rxqcqs = NULL; 434 } 435 436 if (lif->txqcqs) { 437 devm_kfree(dev, lif->txqstats); 438 lif->txqstats = NULL; 439 devm_kfree(dev, lif->txqcqs); 440 lif->txqcqs = NULL; 441 } 442 } 443 444 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 445 struct ionic_qcq *n_qcq) 446 { 447 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 448 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 449 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 450 } 451 452 n_qcq->intr.vector = src_qcq->intr.vector; 453 n_qcq->intr.index = src_qcq->intr.index; 454 } 455 456 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 457 { 458 int err; 459 460 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 461 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 462 return 0; 463 } 464 465 err = ionic_intr_alloc(lif, &qcq->intr); 466 if (err) { 467 netdev_warn(lif->netdev, "no intr for %s: %d\n", 468 qcq->q.name, err); 469 goto err_out; 470 } 471 472 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 473 if (err < 0) { 474 netdev_warn(lif->netdev, "no vector for %s: %d\n", 475 qcq->q.name, err); 476 goto err_out_free_intr; 477 } 478 qcq->intr.vector = err; 479 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 480 IONIC_INTR_MASK_SET); 481 482 err = ionic_request_irq(lif, qcq); 483 if (err) { 484 netdev_warn(lif->netdev, "irq request failed %d\n", err); 485 goto err_out_free_intr; 486 } 487 488 /* try to get the irq on the local numa node first */ 489 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 490 dev_to_node(lif->ionic->dev)); 491 if (qcq->intr.cpu != -1) 492 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 493 494 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 495 return 0; 496 497 err_out_free_intr: 498 ionic_intr_free(lif->ionic, qcq->intr.index); 499 err_out: 500 return err; 501 } 502 503 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 504 unsigned int index, 505 const char *name, unsigned int flags, 506 unsigned int num_descs, unsigned int desc_size, 507 unsigned int cq_desc_size, 508 unsigned int sg_desc_size, 509 unsigned int pid, struct ionic_qcq **qcq) 510 { 511 struct ionic_dev *idev = &lif->ionic->idev; 512 struct device *dev = lif->ionic->dev; 513 void *q_base, *cq_base, *sg_base; 514 dma_addr_t cq_base_pa = 0; 515 dma_addr_t sg_base_pa = 0; 516 dma_addr_t q_base_pa = 0; 517 struct ionic_qcq *new; 518 int err; 519 520 *qcq = NULL; 521 522 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 523 if (!new) { 524 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 525 err = -ENOMEM; 526 goto err_out; 527 } 528 529 new->q.dev = dev; 530 new->flags = flags; 531 532 new->q.info = vzalloc(num_descs * sizeof(*new->q.info)); 533 if (!new->q.info) { 534 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 535 err = -ENOMEM; 536 goto err_out_free_qcq; 537 } 538 539 new->q.type = type; 540 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 541 542 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 543 desc_size, sg_desc_size, pid); 544 if (err) { 545 netdev_err(lif->netdev, "Cannot initialize queue\n"); 546 goto err_out_free_q_info; 547 } 548 549 err = ionic_alloc_qcq_interrupt(lif, new); 550 if (err) 551 goto err_out; 552 553 new->cq.info = vzalloc(num_descs * sizeof(*new->cq.info)); 554 if (!new->cq.info) { 555 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 556 err = -ENOMEM; 557 goto err_out_free_irq; 558 } 559 560 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 561 if (err) { 562 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 563 goto err_out_free_cq_info; 564 } 565 566 if (flags & IONIC_QCQ_F_NOTIFYQ) { 567 int q_size, cq_size; 568 569 /* q & cq need to be contiguous in case of notifyq */ 570 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 571 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 572 573 new->q_size = PAGE_SIZE + q_size + cq_size; 574 new->q_base = dma_alloc_coherent(dev, new->q_size, 575 &new->q_base_pa, GFP_KERNEL); 576 if (!new->q_base) { 577 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 578 err = -ENOMEM; 579 goto err_out_free_cq_info; 580 } 581 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 582 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 583 ionic_q_map(&new->q, q_base, q_base_pa); 584 585 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 586 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 587 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 588 ionic_cq_bind(&new->cq, &new->q); 589 } else { 590 new->q_size = PAGE_SIZE + (num_descs * desc_size); 591 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 592 GFP_KERNEL); 593 if (!new->q_base) { 594 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 595 err = -ENOMEM; 596 goto err_out_free_cq_info; 597 } 598 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 599 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 600 ionic_q_map(&new->q, q_base, q_base_pa); 601 602 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 603 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 604 GFP_KERNEL); 605 if (!new->cq_base) { 606 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 607 err = -ENOMEM; 608 goto err_out_free_q; 609 } 610 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 611 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 612 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 613 ionic_cq_bind(&new->cq, &new->q); 614 } 615 616 if (flags & IONIC_QCQ_F_SG) { 617 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 618 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 619 GFP_KERNEL); 620 if (!new->sg_base) { 621 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 622 err = -ENOMEM; 623 goto err_out_free_cq; 624 } 625 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 626 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 627 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 628 } 629 630 INIT_WORK(&new->dim.work, ionic_dim_work); 631 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 632 633 *qcq = new; 634 635 return 0; 636 637 err_out_free_cq: 638 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 639 err_out_free_q: 640 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 641 err_out_free_cq_info: 642 vfree(new->cq.info); 643 err_out_free_irq: 644 if (flags & IONIC_QCQ_F_INTR) { 645 devm_free_irq(dev, new->intr.vector, &new->napi); 646 ionic_intr_free(lif->ionic, new->intr.index); 647 } 648 err_out_free_q_info: 649 vfree(new->q.info); 650 err_out_free_qcq: 651 devm_kfree(dev, new); 652 err_out: 653 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 654 return err; 655 } 656 657 static int ionic_qcqs_alloc(struct ionic_lif *lif) 658 { 659 struct device *dev = lif->ionic->dev; 660 unsigned int flags; 661 int err; 662 663 flags = IONIC_QCQ_F_INTR; 664 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 665 IONIC_ADMINQ_LENGTH, 666 sizeof(struct ionic_admin_cmd), 667 sizeof(struct ionic_admin_comp), 668 0, lif->kern_pid, &lif->adminqcq); 669 if (err) 670 return err; 671 ionic_debugfs_add_qcq(lif, lif->adminqcq); 672 673 if (lif->ionic->nnqs_per_lif) { 674 flags = IONIC_QCQ_F_NOTIFYQ; 675 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 676 flags, IONIC_NOTIFYQ_LENGTH, 677 sizeof(struct ionic_notifyq_cmd), 678 sizeof(union ionic_notifyq_comp), 679 0, lif->kern_pid, &lif->notifyqcq); 680 if (err) 681 goto err_out; 682 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 683 684 /* Let the notifyq ride on the adminq interrupt */ 685 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 686 } 687 688 err = -ENOMEM; 689 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 690 sizeof(*lif->txqcqs), GFP_KERNEL); 691 if (!lif->txqcqs) 692 goto err_out; 693 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 694 sizeof(*lif->rxqcqs), GFP_KERNEL); 695 if (!lif->rxqcqs) 696 goto err_out; 697 698 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 699 sizeof(*lif->txqstats), GFP_KERNEL); 700 if (!lif->txqstats) 701 goto err_out; 702 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 703 sizeof(*lif->rxqstats), GFP_KERNEL); 704 if (!lif->rxqstats) 705 goto err_out; 706 707 return 0; 708 709 err_out: 710 ionic_qcqs_free(lif); 711 return err; 712 } 713 714 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 715 { 716 qcq->q.tail_idx = 0; 717 qcq->q.head_idx = 0; 718 qcq->cq.tail_idx = 0; 719 qcq->cq.done_color = 1; 720 memset(qcq->q_base, 0, qcq->q_size); 721 memset(qcq->cq_base, 0, qcq->cq_size); 722 memset(qcq->sg_base, 0, qcq->sg_size); 723 } 724 725 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 726 { 727 struct device *dev = lif->ionic->dev; 728 struct ionic_queue *q = &qcq->q; 729 struct ionic_cq *cq = &qcq->cq; 730 struct ionic_admin_ctx ctx = { 731 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 732 .cmd.q_init = { 733 .opcode = IONIC_CMD_Q_INIT, 734 .lif_index = cpu_to_le16(lif->index), 735 .type = q->type, 736 .ver = lif->qtype_info[q->type].version, 737 .index = cpu_to_le32(q->index), 738 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 739 IONIC_QINIT_F_SG), 740 .pid = cpu_to_le16(q->pid), 741 .ring_size = ilog2(q->num_descs), 742 .ring_base = cpu_to_le64(q->base_pa), 743 .cq_ring_base = cpu_to_le64(cq->base_pa), 744 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 745 .features = cpu_to_le64(q->features), 746 }, 747 }; 748 unsigned int intr_index; 749 int err; 750 751 intr_index = qcq->intr.index; 752 753 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 754 755 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 756 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 757 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 758 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 759 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 760 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 761 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 762 763 ionic_qcq_sanitize(qcq); 764 765 err = ionic_adminq_post_wait(lif, &ctx); 766 if (err) 767 return err; 768 769 q->hw_type = ctx.comp.q_init.hw_type; 770 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 771 q->dbval = IONIC_DBELL_QID(q->hw_index); 772 773 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 774 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 775 776 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 777 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi); 778 779 qcq->flags |= IONIC_QCQ_F_INITED; 780 781 return 0; 782 } 783 784 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 785 { 786 struct device *dev = lif->ionic->dev; 787 struct ionic_queue *q = &qcq->q; 788 struct ionic_cq *cq = &qcq->cq; 789 struct ionic_admin_ctx ctx = { 790 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 791 .cmd.q_init = { 792 .opcode = IONIC_CMD_Q_INIT, 793 .lif_index = cpu_to_le16(lif->index), 794 .type = q->type, 795 .ver = lif->qtype_info[q->type].version, 796 .index = cpu_to_le32(q->index), 797 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 798 IONIC_QINIT_F_SG), 799 .intr_index = cpu_to_le16(cq->bound_intr->index), 800 .pid = cpu_to_le16(q->pid), 801 .ring_size = ilog2(q->num_descs), 802 .ring_base = cpu_to_le64(q->base_pa), 803 .cq_ring_base = cpu_to_le64(cq->base_pa), 804 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 805 .features = cpu_to_le64(q->features), 806 }, 807 }; 808 int err; 809 810 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 811 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 812 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 813 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 814 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 815 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 816 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 817 818 ionic_qcq_sanitize(qcq); 819 820 err = ionic_adminq_post_wait(lif, &ctx); 821 if (err) 822 return err; 823 824 q->hw_type = ctx.comp.q_init.hw_type; 825 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 826 q->dbval = IONIC_DBELL_QID(q->hw_index); 827 828 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 829 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 830 831 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 832 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi); 833 else 834 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi); 835 836 qcq->flags |= IONIC_QCQ_F_INITED; 837 838 return 0; 839 } 840 841 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 842 { 843 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 844 unsigned int txq_i, flags; 845 struct ionic_qcq *txq; 846 u64 features; 847 int err; 848 849 if (lif->hwstamp_txq) 850 return 0; 851 852 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 853 854 num_desc = IONIC_MIN_TXRX_DESC; 855 desc_sz = sizeof(struct ionic_txq_desc); 856 comp_sz = 2 * sizeof(struct ionic_txq_comp); 857 858 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 859 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 860 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 861 else 862 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 863 864 txq_i = lif->ionic->ntxqs_per_lif; 865 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 866 867 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 868 num_desc, desc_sz, comp_sz, sg_desc_sz, 869 lif->kern_pid, &txq); 870 if (err) 871 goto err_qcq_alloc; 872 873 txq->q.features = features; 874 875 ionic_link_qcq_interrupts(lif->adminqcq, txq); 876 ionic_debugfs_add_qcq(lif, txq); 877 878 lif->hwstamp_txq = txq; 879 880 if (netif_running(lif->netdev)) { 881 err = ionic_lif_txq_init(lif, txq); 882 if (err) 883 goto err_qcq_init; 884 885 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 886 err = ionic_qcq_enable(txq); 887 if (err) 888 goto err_qcq_enable; 889 } 890 } 891 892 return 0; 893 894 err_qcq_enable: 895 ionic_lif_qcq_deinit(lif, txq); 896 err_qcq_init: 897 lif->hwstamp_txq = NULL; 898 ionic_debugfs_del_qcq(txq); 899 ionic_qcq_free(lif, txq); 900 devm_kfree(lif->ionic->dev, txq); 901 err_qcq_alloc: 902 return err; 903 } 904 905 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 906 { 907 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 908 unsigned int rxq_i, flags; 909 struct ionic_qcq *rxq; 910 u64 features; 911 int err; 912 913 if (lif->hwstamp_rxq) 914 return 0; 915 916 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 917 918 num_desc = IONIC_MIN_TXRX_DESC; 919 desc_sz = sizeof(struct ionic_rxq_desc); 920 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 921 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 922 923 rxq_i = lif->ionic->nrxqs_per_lif; 924 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 925 926 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 927 num_desc, desc_sz, comp_sz, sg_desc_sz, 928 lif->kern_pid, &rxq); 929 if (err) 930 goto err_qcq_alloc; 931 932 rxq->q.features = features; 933 934 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 935 ionic_debugfs_add_qcq(lif, rxq); 936 937 lif->hwstamp_rxq = rxq; 938 939 if (netif_running(lif->netdev)) { 940 err = ionic_lif_rxq_init(lif, rxq); 941 if (err) 942 goto err_qcq_init; 943 944 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 945 ionic_rx_fill(&rxq->q); 946 err = ionic_qcq_enable(rxq); 947 if (err) 948 goto err_qcq_enable; 949 } 950 } 951 952 return 0; 953 954 err_qcq_enable: 955 ionic_lif_qcq_deinit(lif, rxq); 956 err_qcq_init: 957 lif->hwstamp_rxq = NULL; 958 ionic_debugfs_del_qcq(rxq); 959 ionic_qcq_free(lif, rxq); 960 devm_kfree(lif->ionic->dev, rxq); 961 err_qcq_alloc: 962 return err; 963 } 964 965 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 966 { 967 struct ionic_queue_params qparam; 968 969 ionic_init_queue_params(lif, &qparam); 970 971 if (rx_all) 972 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 973 else 974 qparam.rxq_features = 0; 975 976 /* if we're not running, just set the values and return */ 977 if (!netif_running(lif->netdev)) { 978 lif->rxq_features = qparam.rxq_features; 979 return 0; 980 } 981 982 return ionic_reconfigure_queues(lif, &qparam); 983 } 984 985 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 986 { 987 struct ionic_admin_ctx ctx = { 988 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 989 .cmd.lif_setattr = { 990 .opcode = IONIC_CMD_LIF_SETATTR, 991 .index = cpu_to_le16(lif->index), 992 .attr = IONIC_LIF_ATTR_TXSTAMP, 993 .txstamp_mode = cpu_to_le16(txstamp_mode), 994 }, 995 }; 996 997 return ionic_adminq_post_wait(lif, &ctx); 998 } 999 1000 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1001 { 1002 struct ionic_admin_ctx ctx = { 1003 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1004 .cmd.rx_filter_del = { 1005 .opcode = IONIC_CMD_RX_FILTER_DEL, 1006 .lif_index = cpu_to_le16(lif->index), 1007 }, 1008 }; 1009 struct ionic_rx_filter *f; 1010 u32 filter_id; 1011 int err; 1012 1013 spin_lock_bh(&lif->rx_filters.lock); 1014 1015 f = ionic_rx_filter_rxsteer(lif); 1016 if (!f) { 1017 spin_unlock_bh(&lif->rx_filters.lock); 1018 return; 1019 } 1020 1021 filter_id = f->filter_id; 1022 ionic_rx_filter_free(lif, f); 1023 1024 spin_unlock_bh(&lif->rx_filters.lock); 1025 1026 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1027 1028 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1029 1030 err = ionic_adminq_post_wait(lif, &ctx); 1031 if (err && err != -EEXIST) 1032 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1033 } 1034 1035 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1036 { 1037 struct ionic_admin_ctx ctx = { 1038 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1039 .cmd.rx_filter_add = { 1040 .opcode = IONIC_CMD_RX_FILTER_ADD, 1041 .lif_index = cpu_to_le16(lif->index), 1042 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1043 .pkt_class = cpu_to_le64(pkt_class), 1044 }, 1045 }; 1046 u8 qtype; 1047 u32 qid; 1048 int err; 1049 1050 if (!lif->hwstamp_rxq) 1051 return -EINVAL; 1052 1053 qtype = lif->hwstamp_rxq->q.type; 1054 ctx.cmd.rx_filter_add.qtype = qtype; 1055 1056 qid = lif->hwstamp_rxq->q.index; 1057 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1058 1059 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1060 err = ionic_adminq_post_wait(lif, &ctx); 1061 if (err && err != -EEXIST) 1062 return err; 1063 1064 spin_lock_bh(&lif->rx_filters.lock); 1065 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1066 spin_unlock_bh(&lif->rx_filters.lock); 1067 1068 return err; 1069 } 1070 1071 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1072 { 1073 ionic_lif_del_hwstamp_rxfilt(lif); 1074 1075 if (!pkt_class) 1076 return 0; 1077 1078 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1079 } 1080 1081 static bool ionic_notifyq_service(struct ionic_cq *cq, 1082 struct ionic_cq_info *cq_info) 1083 { 1084 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1085 struct ionic_deferred_work *work; 1086 struct net_device *netdev; 1087 struct ionic_queue *q; 1088 struct ionic_lif *lif; 1089 u64 eid; 1090 1091 q = cq->bound_q; 1092 lif = q->info[0].cb_arg; 1093 netdev = lif->netdev; 1094 eid = le64_to_cpu(comp->event.eid); 1095 1096 /* Have we run out of new completions to process? */ 1097 if ((s64)(eid - lif->last_eid) <= 0) 1098 return false; 1099 1100 lif->last_eid = eid; 1101 1102 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1103 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1104 comp, sizeof(*comp), true); 1105 1106 switch (le16_to_cpu(comp->event.ecode)) { 1107 case IONIC_EVENT_LINK_CHANGE: 1108 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1109 break; 1110 case IONIC_EVENT_RESET: 1111 if (lif->ionic->idev.fw_status_ready && 1112 !test_bit(IONIC_LIF_F_FW_RESET, lif->state) && 1113 !test_and_set_bit(IONIC_LIF_F_FW_STOPPING, lif->state)) { 1114 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1115 if (!work) { 1116 netdev_err(lif->netdev, "Reset event dropped\n"); 1117 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 1118 } else { 1119 work->type = IONIC_DW_TYPE_LIF_RESET; 1120 ionic_lif_deferred_enqueue(&lif->deferred, work); 1121 } 1122 } 1123 break; 1124 default: 1125 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1126 comp->event.ecode, eid); 1127 break; 1128 } 1129 1130 return true; 1131 } 1132 1133 static bool ionic_adminq_service(struct ionic_cq *cq, 1134 struct ionic_cq_info *cq_info) 1135 { 1136 struct ionic_admin_comp *comp = cq_info->cq_desc; 1137 1138 if (!color_match(comp->color, cq->done_color)) 1139 return false; 1140 1141 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1142 1143 return true; 1144 } 1145 1146 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1147 { 1148 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1149 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1150 struct ionic_dev *idev = &lif->ionic->idev; 1151 unsigned long irqflags; 1152 unsigned int flags = 0; 1153 int rx_work = 0; 1154 int tx_work = 0; 1155 int n_work = 0; 1156 int a_work = 0; 1157 int work_done; 1158 int credits; 1159 1160 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1161 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1162 ionic_notifyq_service, NULL, NULL); 1163 1164 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1165 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1166 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1167 ionic_adminq_service, NULL, NULL); 1168 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1169 1170 if (lif->hwstamp_rxq) 1171 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1172 ionic_rx_service, NULL, NULL); 1173 1174 if (lif->hwstamp_txq) 1175 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1176 ionic_tx_service, NULL, NULL); 1177 1178 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1179 if (work_done < budget && napi_complete_done(napi, work_done)) { 1180 flags |= IONIC_INTR_CRED_UNMASK; 1181 intr->rearm_count++; 1182 } 1183 1184 if (work_done || flags) { 1185 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1186 credits = n_work + a_work + rx_work + tx_work; 1187 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1188 } 1189 1190 return work_done; 1191 } 1192 1193 void ionic_get_stats64(struct net_device *netdev, 1194 struct rtnl_link_stats64 *ns) 1195 { 1196 struct ionic_lif *lif = netdev_priv(netdev); 1197 struct ionic_lif_stats *ls; 1198 1199 memset(ns, 0, sizeof(*ns)); 1200 ls = &lif->info->stats; 1201 1202 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1203 le64_to_cpu(ls->rx_mcast_packets) + 1204 le64_to_cpu(ls->rx_bcast_packets); 1205 1206 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1207 le64_to_cpu(ls->tx_mcast_packets) + 1208 le64_to_cpu(ls->tx_bcast_packets); 1209 1210 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1211 le64_to_cpu(ls->rx_mcast_bytes) + 1212 le64_to_cpu(ls->rx_bcast_bytes); 1213 1214 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1215 le64_to_cpu(ls->tx_mcast_bytes) + 1216 le64_to_cpu(ls->tx_bcast_bytes); 1217 1218 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1219 le64_to_cpu(ls->rx_mcast_drop_packets) + 1220 le64_to_cpu(ls->rx_bcast_drop_packets); 1221 1222 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1223 le64_to_cpu(ls->tx_mcast_drop_packets) + 1224 le64_to_cpu(ls->tx_bcast_drop_packets); 1225 1226 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1227 1228 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1229 1230 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1231 le64_to_cpu(ls->rx_queue_disabled) + 1232 le64_to_cpu(ls->rx_desc_fetch_error) + 1233 le64_to_cpu(ls->rx_desc_data_error); 1234 1235 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1236 le64_to_cpu(ls->tx_queue_disabled) + 1237 le64_to_cpu(ls->tx_desc_fetch_error) + 1238 le64_to_cpu(ls->tx_desc_data_error); 1239 1240 ns->rx_errors = ns->rx_over_errors + 1241 ns->rx_missed_errors; 1242 1243 ns->tx_errors = ns->tx_aborted_errors; 1244 } 1245 1246 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1247 { 1248 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1249 } 1250 1251 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1252 { 1253 /* Don't delete our own address from the uc list */ 1254 if (ether_addr_equal(addr, netdev->dev_addr)) 1255 return 0; 1256 1257 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1258 } 1259 1260 void ionic_lif_rx_mode(struct ionic_lif *lif) 1261 { 1262 struct net_device *netdev = lif->netdev; 1263 unsigned int nfilters; 1264 unsigned int nd_flags; 1265 char buf[128]; 1266 u16 rx_mode; 1267 int i; 1268 #define REMAIN(__x) (sizeof(buf) - (__x)) 1269 1270 mutex_lock(&lif->config_lock); 1271 1272 /* grab the flags once for local use */ 1273 nd_flags = netdev->flags; 1274 1275 rx_mode = IONIC_RX_MODE_F_UNICAST; 1276 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1277 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1278 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1279 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1280 1281 /* sync the filters */ 1282 ionic_rx_filter_sync(lif); 1283 1284 /* check for overflow state 1285 * if so, we track that we overflowed and enable NIC PROMISC 1286 * else if the overflow is set and not needed 1287 * we remove our overflow flag and check the netdev flags 1288 * to see if we can disable NIC PROMISC 1289 */ 1290 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1291 1292 if (((lif->nucast + lif->nmcast) >= nfilters) || 1293 (lif->max_vlans && lif->nvlans >= lif->max_vlans)) { 1294 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1295 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1296 } else { 1297 if (!(nd_flags & IFF_PROMISC)) 1298 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1299 if (!(nd_flags & IFF_ALLMULTI)) 1300 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1301 } 1302 1303 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1304 lif->rx_mode, rx_mode); 1305 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1306 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1307 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1308 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1309 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1310 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1311 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1312 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1313 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1314 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1315 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1316 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1317 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1318 1319 if (lif->rx_mode != rx_mode) { 1320 struct ionic_admin_ctx ctx = { 1321 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1322 .cmd.rx_mode_set = { 1323 .opcode = IONIC_CMD_RX_MODE_SET, 1324 .lif_index = cpu_to_le16(lif->index), 1325 }, 1326 }; 1327 int err; 1328 1329 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1330 err = ionic_adminq_post_wait(lif, &ctx); 1331 if (err) 1332 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1333 rx_mode, err); 1334 else 1335 lif->rx_mode = rx_mode; 1336 } 1337 1338 mutex_unlock(&lif->config_lock); 1339 } 1340 1341 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1342 { 1343 struct ionic_lif *lif = netdev_priv(netdev); 1344 struct ionic_deferred_work *work; 1345 1346 /* Sync the kernel filter list with the driver filter list */ 1347 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1348 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1349 1350 /* Shove off the rest of the rxmode work to the work task 1351 * which will include syncing the filters to the firmware. 1352 */ 1353 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1354 if (!work) { 1355 netdev_err(lif->netdev, "rxmode change dropped\n"); 1356 return; 1357 } 1358 work->type = IONIC_DW_TYPE_RX_MODE; 1359 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1360 ionic_lif_deferred_enqueue(&lif->deferred, work); 1361 } 1362 1363 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1364 { 1365 u64 wanted = 0; 1366 1367 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1368 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1369 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1370 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1371 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1372 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1373 if (features & NETIF_F_RXHASH) 1374 wanted |= IONIC_ETH_HW_RX_HASH; 1375 if (features & NETIF_F_RXCSUM) 1376 wanted |= IONIC_ETH_HW_RX_CSUM; 1377 if (features & NETIF_F_SG) 1378 wanted |= IONIC_ETH_HW_TX_SG; 1379 if (features & NETIF_F_HW_CSUM) 1380 wanted |= IONIC_ETH_HW_TX_CSUM; 1381 if (features & NETIF_F_TSO) 1382 wanted |= IONIC_ETH_HW_TSO; 1383 if (features & NETIF_F_TSO6) 1384 wanted |= IONIC_ETH_HW_TSO_IPV6; 1385 if (features & NETIF_F_TSO_ECN) 1386 wanted |= IONIC_ETH_HW_TSO_ECN; 1387 if (features & NETIF_F_GSO_GRE) 1388 wanted |= IONIC_ETH_HW_TSO_GRE; 1389 if (features & NETIF_F_GSO_GRE_CSUM) 1390 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1391 if (features & NETIF_F_GSO_IPXIP4) 1392 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1393 if (features & NETIF_F_GSO_IPXIP6) 1394 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1395 if (features & NETIF_F_GSO_UDP_TUNNEL) 1396 wanted |= IONIC_ETH_HW_TSO_UDP; 1397 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1398 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1399 1400 return cpu_to_le64(wanted); 1401 } 1402 1403 static int ionic_set_nic_features(struct ionic_lif *lif, 1404 netdev_features_t features) 1405 { 1406 struct device *dev = lif->ionic->dev; 1407 struct ionic_admin_ctx ctx = { 1408 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1409 .cmd.lif_setattr = { 1410 .opcode = IONIC_CMD_LIF_SETATTR, 1411 .index = cpu_to_le16(lif->index), 1412 .attr = IONIC_LIF_ATTR_FEATURES, 1413 }, 1414 }; 1415 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1416 IONIC_ETH_HW_VLAN_RX_STRIP | 1417 IONIC_ETH_HW_VLAN_RX_FILTER; 1418 u64 old_hw_features; 1419 int err; 1420 1421 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1422 1423 if (lif->phc) 1424 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1425 1426 err = ionic_adminq_post_wait(lif, &ctx); 1427 if (err) 1428 return err; 1429 1430 old_hw_features = lif->hw_features; 1431 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1432 ctx.comp.lif_setattr.features); 1433 1434 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1435 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1436 1437 if ((vlan_flags & le64_to_cpu(ctx.cmd.lif_setattr.features)) && 1438 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1439 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1440 1441 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1442 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1443 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1444 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1445 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1446 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1447 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1448 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1449 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1450 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1451 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1452 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1453 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1454 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1455 if (lif->hw_features & IONIC_ETH_HW_TSO) 1456 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1457 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1458 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1459 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1460 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1461 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1462 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1463 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1464 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1465 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1466 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1467 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1468 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1469 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1470 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1471 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1472 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1473 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1474 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1475 1476 return 0; 1477 } 1478 1479 static int ionic_init_nic_features(struct ionic_lif *lif) 1480 { 1481 struct net_device *netdev = lif->netdev; 1482 netdev_features_t features; 1483 int err; 1484 1485 /* set up what we expect to support by default */ 1486 features = NETIF_F_HW_VLAN_CTAG_TX | 1487 NETIF_F_HW_VLAN_CTAG_RX | 1488 NETIF_F_HW_VLAN_CTAG_FILTER | 1489 NETIF_F_SG | 1490 NETIF_F_HW_CSUM | 1491 NETIF_F_RXCSUM | 1492 NETIF_F_TSO | 1493 NETIF_F_TSO6 | 1494 NETIF_F_TSO_ECN | 1495 NETIF_F_GSO_GRE | 1496 NETIF_F_GSO_GRE_CSUM | 1497 NETIF_F_GSO_IPXIP4 | 1498 NETIF_F_GSO_IPXIP6 | 1499 NETIF_F_GSO_UDP_TUNNEL | 1500 NETIF_F_GSO_UDP_TUNNEL_CSUM; 1501 1502 if (lif->nxqs > 1) 1503 features |= NETIF_F_RXHASH; 1504 1505 err = ionic_set_nic_features(lif, features); 1506 if (err) 1507 return err; 1508 1509 /* tell the netdev what we actually can support */ 1510 netdev->features |= NETIF_F_HIGHDMA; 1511 1512 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1513 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1514 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1515 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1516 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1517 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1518 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1519 netdev->hw_features |= NETIF_F_RXHASH; 1520 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1521 netdev->hw_features |= NETIF_F_SG; 1522 1523 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1524 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1525 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1526 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1527 if (lif->hw_features & IONIC_ETH_HW_TSO) 1528 netdev->hw_enc_features |= NETIF_F_TSO; 1529 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1530 netdev->hw_enc_features |= NETIF_F_TSO6; 1531 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1532 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1533 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1534 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1535 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1536 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1537 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1538 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1539 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1540 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1541 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1542 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1543 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1544 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1545 1546 netdev->hw_features |= netdev->hw_enc_features; 1547 netdev->features |= netdev->hw_features; 1548 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1549 1550 netdev->priv_flags |= IFF_UNICAST_FLT | 1551 IFF_LIVE_ADDR_CHANGE; 1552 1553 return 0; 1554 } 1555 1556 static int ionic_set_features(struct net_device *netdev, 1557 netdev_features_t features) 1558 { 1559 struct ionic_lif *lif = netdev_priv(netdev); 1560 int err; 1561 1562 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1563 __func__, (u64)lif->netdev->features, (u64)features); 1564 1565 err = ionic_set_nic_features(lif, features); 1566 1567 return err; 1568 } 1569 1570 static int ionic_set_attr_mac(struct ionic_lif *lif, u8 *mac) 1571 { 1572 struct ionic_admin_ctx ctx = { 1573 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1574 .cmd.lif_setattr = { 1575 .opcode = IONIC_CMD_LIF_SETATTR, 1576 .index = cpu_to_le16(lif->index), 1577 .attr = IONIC_LIF_ATTR_MAC, 1578 }, 1579 }; 1580 1581 ether_addr_copy(ctx.cmd.lif_setattr.mac, mac); 1582 return ionic_adminq_post_wait(lif, &ctx); 1583 } 1584 1585 static int ionic_get_attr_mac(struct ionic_lif *lif, u8 *mac_addr) 1586 { 1587 struct ionic_admin_ctx ctx = { 1588 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1589 .cmd.lif_getattr = { 1590 .opcode = IONIC_CMD_LIF_GETATTR, 1591 .index = cpu_to_le16(lif->index), 1592 .attr = IONIC_LIF_ATTR_MAC, 1593 }, 1594 }; 1595 int err; 1596 1597 err = ionic_adminq_post_wait(lif, &ctx); 1598 if (err) 1599 return err; 1600 1601 ether_addr_copy(mac_addr, ctx.comp.lif_getattr.mac); 1602 return 0; 1603 } 1604 1605 static int ionic_program_mac(struct ionic_lif *lif, u8 *mac) 1606 { 1607 u8 get_mac[ETH_ALEN]; 1608 int err; 1609 1610 err = ionic_set_attr_mac(lif, mac); 1611 if (err) 1612 return err; 1613 1614 err = ionic_get_attr_mac(lif, get_mac); 1615 if (err) 1616 return err; 1617 1618 /* To deal with older firmware that silently ignores the set attr mac: 1619 * doesn't actually change the mac and doesn't return an error, so we 1620 * do the get attr to verify whether or not the set actually happened 1621 */ 1622 if (!ether_addr_equal(get_mac, mac)) 1623 return 1; 1624 1625 return 0; 1626 } 1627 1628 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1629 { 1630 struct ionic_lif *lif = netdev_priv(netdev); 1631 struct sockaddr *addr = sa; 1632 u8 *mac; 1633 int err; 1634 1635 mac = (u8 *)addr->sa_data; 1636 if (ether_addr_equal(netdev->dev_addr, mac)) 1637 return 0; 1638 1639 err = ionic_program_mac(lif, mac); 1640 if (err < 0) 1641 return err; 1642 1643 if (err > 0) 1644 netdev_dbg(netdev, "%s: SET and GET ATTR Mac are not equal-due to old FW running\n", 1645 __func__); 1646 1647 err = eth_prepare_mac_addr_change(netdev, addr); 1648 if (err) 1649 return err; 1650 1651 if (!is_zero_ether_addr(netdev->dev_addr)) { 1652 netdev_info(netdev, "deleting mac addr %pM\n", 1653 netdev->dev_addr); 1654 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1655 } 1656 1657 eth_commit_mac_addr_change(netdev, addr); 1658 netdev_info(netdev, "updating mac addr %pM\n", mac); 1659 1660 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1661 } 1662 1663 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1664 { 1665 /* Stop and clean the queues before reconfiguration */ 1666 netif_device_detach(lif->netdev); 1667 ionic_stop_queues(lif); 1668 ionic_txrx_deinit(lif); 1669 } 1670 1671 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1672 { 1673 int err; 1674 1675 /* Re-init the queues after reconfiguration */ 1676 1677 /* The only way txrx_init can fail here is if communication 1678 * with FW is suddenly broken. There's not much we can do 1679 * at this point - error messages have already been printed, 1680 * so we can continue on and the user can eventually do a 1681 * DOWN and UP to try to reset and clear the issue. 1682 */ 1683 err = ionic_txrx_init(lif); 1684 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1685 netif_device_attach(lif->netdev); 1686 1687 return err; 1688 } 1689 1690 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1691 { 1692 struct ionic_lif *lif = netdev_priv(netdev); 1693 struct ionic_admin_ctx ctx = { 1694 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1695 .cmd.lif_setattr = { 1696 .opcode = IONIC_CMD_LIF_SETATTR, 1697 .index = cpu_to_le16(lif->index), 1698 .attr = IONIC_LIF_ATTR_MTU, 1699 .mtu = cpu_to_le32(new_mtu), 1700 }, 1701 }; 1702 int err; 1703 1704 err = ionic_adminq_post_wait(lif, &ctx); 1705 if (err) 1706 return err; 1707 1708 /* if we're not running, nothing more to do */ 1709 if (!netif_running(netdev)) { 1710 netdev->mtu = new_mtu; 1711 return 0; 1712 } 1713 1714 mutex_lock(&lif->queue_lock); 1715 ionic_stop_queues_reconfig(lif); 1716 netdev->mtu = new_mtu; 1717 err = ionic_start_queues_reconfig(lif); 1718 mutex_unlock(&lif->queue_lock); 1719 1720 return err; 1721 } 1722 1723 static void ionic_tx_timeout_work(struct work_struct *ws) 1724 { 1725 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1726 1727 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1728 return; 1729 1730 /* if we were stopped before this scheduled job was launched, 1731 * don't bother the queues as they are already stopped. 1732 */ 1733 if (!netif_running(lif->netdev)) 1734 return; 1735 1736 mutex_lock(&lif->queue_lock); 1737 ionic_stop_queues_reconfig(lif); 1738 ionic_start_queues_reconfig(lif); 1739 mutex_unlock(&lif->queue_lock); 1740 } 1741 1742 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1743 { 1744 struct ionic_lif *lif = netdev_priv(netdev); 1745 1746 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1747 schedule_work(&lif->tx_timeout_work); 1748 } 1749 1750 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1751 u16 vid) 1752 { 1753 struct ionic_lif *lif = netdev_priv(netdev); 1754 int err; 1755 1756 err = ionic_lif_vlan_add(lif, vid); 1757 if (err) 1758 return err; 1759 1760 ionic_lif_rx_mode(lif); 1761 1762 return 0; 1763 } 1764 1765 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1766 u16 vid) 1767 { 1768 struct ionic_lif *lif = netdev_priv(netdev); 1769 int err; 1770 1771 err = ionic_lif_vlan_del(lif, vid); 1772 if (err) 1773 return err; 1774 1775 ionic_lif_rx_mode(lif); 1776 1777 return 0; 1778 } 1779 1780 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1781 const u8 *key, const u32 *indir) 1782 { 1783 struct ionic_admin_ctx ctx = { 1784 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1785 .cmd.lif_setattr = { 1786 .opcode = IONIC_CMD_LIF_SETATTR, 1787 .attr = IONIC_LIF_ATTR_RSS, 1788 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1789 }, 1790 }; 1791 unsigned int i, tbl_sz; 1792 1793 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1794 lif->rss_types = types; 1795 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1796 } 1797 1798 if (key) 1799 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1800 1801 if (indir) { 1802 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1803 for (i = 0; i < tbl_sz; i++) 1804 lif->rss_ind_tbl[i] = indir[i]; 1805 } 1806 1807 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1808 IONIC_RSS_HASH_KEY_SIZE); 1809 1810 return ionic_adminq_post_wait(lif, &ctx); 1811 } 1812 1813 static int ionic_lif_rss_init(struct ionic_lif *lif) 1814 { 1815 unsigned int tbl_sz; 1816 unsigned int i; 1817 1818 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1819 IONIC_RSS_TYPE_IPV4_TCP | 1820 IONIC_RSS_TYPE_IPV4_UDP | 1821 IONIC_RSS_TYPE_IPV6 | 1822 IONIC_RSS_TYPE_IPV6_TCP | 1823 IONIC_RSS_TYPE_IPV6_UDP; 1824 1825 /* Fill indirection table with 'default' values */ 1826 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1827 for (i = 0; i < tbl_sz; i++) 1828 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1829 1830 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1831 } 1832 1833 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1834 { 1835 int tbl_sz; 1836 1837 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1838 memset(lif->rss_ind_tbl, 0, tbl_sz); 1839 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1840 1841 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1842 } 1843 1844 static void ionic_lif_quiesce(struct ionic_lif *lif) 1845 { 1846 struct ionic_admin_ctx ctx = { 1847 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1848 .cmd.lif_setattr = { 1849 .opcode = IONIC_CMD_LIF_SETATTR, 1850 .index = cpu_to_le16(lif->index), 1851 .attr = IONIC_LIF_ATTR_STATE, 1852 .state = IONIC_LIF_QUIESCE, 1853 }, 1854 }; 1855 int err; 1856 1857 err = ionic_adminq_post_wait(lif, &ctx); 1858 if (err) 1859 netdev_dbg(lif->netdev, "lif quiesce failed %d\n", err); 1860 } 1861 1862 static void ionic_txrx_disable(struct ionic_lif *lif) 1863 { 1864 unsigned int i; 1865 int err = 0; 1866 1867 if (lif->txqcqs) { 1868 for (i = 0; i < lif->nxqs; i++) 1869 err = ionic_qcq_disable(lif, lif->txqcqs[i], err); 1870 } 1871 1872 if (lif->hwstamp_txq) 1873 err = ionic_qcq_disable(lif, lif->hwstamp_txq, err); 1874 1875 if (lif->rxqcqs) { 1876 for (i = 0; i < lif->nxqs; i++) 1877 err = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 1878 } 1879 1880 if (lif->hwstamp_rxq) 1881 err = ionic_qcq_disable(lif, lif->hwstamp_rxq, err); 1882 1883 ionic_lif_quiesce(lif); 1884 } 1885 1886 static void ionic_txrx_deinit(struct ionic_lif *lif) 1887 { 1888 unsigned int i; 1889 1890 if (lif->txqcqs) { 1891 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1892 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1893 ionic_tx_flush(&lif->txqcqs[i]->cq); 1894 ionic_tx_empty(&lif->txqcqs[i]->q); 1895 } 1896 } 1897 1898 if (lif->rxqcqs) { 1899 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1900 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1901 ionic_rx_empty(&lif->rxqcqs[i]->q); 1902 } 1903 } 1904 lif->rx_mode = 0; 1905 1906 if (lif->hwstamp_txq) { 1907 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1908 ionic_tx_flush(&lif->hwstamp_txq->cq); 1909 ionic_tx_empty(&lif->hwstamp_txq->q); 1910 } 1911 1912 if (lif->hwstamp_rxq) { 1913 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1914 ionic_rx_empty(&lif->hwstamp_rxq->q); 1915 } 1916 } 1917 1918 static void ionic_txrx_free(struct ionic_lif *lif) 1919 { 1920 unsigned int i; 1921 1922 if (lif->txqcqs) { 1923 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 1924 ionic_qcq_free(lif, lif->txqcqs[i]); 1925 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 1926 lif->txqcqs[i] = NULL; 1927 } 1928 } 1929 1930 if (lif->rxqcqs) { 1931 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 1932 ionic_qcq_free(lif, lif->rxqcqs[i]); 1933 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 1934 lif->rxqcqs[i] = NULL; 1935 } 1936 } 1937 1938 if (lif->hwstamp_txq) { 1939 ionic_qcq_free(lif, lif->hwstamp_txq); 1940 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 1941 lif->hwstamp_txq = NULL; 1942 } 1943 1944 if (lif->hwstamp_rxq) { 1945 ionic_qcq_free(lif, lif->hwstamp_rxq); 1946 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 1947 lif->hwstamp_rxq = NULL; 1948 } 1949 } 1950 1951 static int ionic_txrx_alloc(struct ionic_lif *lif) 1952 { 1953 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 1954 unsigned int flags, i; 1955 int err = 0; 1956 1957 num_desc = lif->ntxq_descs; 1958 desc_sz = sizeof(struct ionic_txq_desc); 1959 comp_sz = sizeof(struct ionic_txq_comp); 1960 1961 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1962 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1963 sizeof(struct ionic_txq_sg_desc_v1)) 1964 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1965 else 1966 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1967 1968 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1969 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 1970 flags |= IONIC_QCQ_F_INTR; 1971 for (i = 0; i < lif->nxqs; i++) { 1972 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1973 num_desc, desc_sz, comp_sz, sg_desc_sz, 1974 lif->kern_pid, &lif->txqcqs[i]); 1975 if (err) 1976 goto err_out; 1977 1978 if (flags & IONIC_QCQ_F_INTR) { 1979 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1980 lif->txqcqs[i]->intr.index, 1981 lif->tx_coalesce_hw); 1982 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 1983 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 1984 } 1985 1986 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 1987 } 1988 1989 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1990 1991 num_desc = lif->nrxq_descs; 1992 desc_sz = sizeof(struct ionic_rxq_desc); 1993 comp_sz = sizeof(struct ionic_rxq_comp); 1994 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 1995 1996 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 1997 comp_sz *= 2; 1998 1999 for (i = 0; i < lif->nxqs; i++) { 2000 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2001 num_desc, desc_sz, comp_sz, sg_desc_sz, 2002 lif->kern_pid, &lif->rxqcqs[i]); 2003 if (err) 2004 goto err_out; 2005 2006 lif->rxqcqs[i]->q.features = lif->rxq_features; 2007 2008 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2009 lif->rxqcqs[i]->intr.index, 2010 lif->rx_coalesce_hw); 2011 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2012 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2013 2014 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2015 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2016 lif->txqcqs[i]); 2017 2018 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2019 } 2020 2021 return 0; 2022 2023 err_out: 2024 ionic_txrx_free(lif); 2025 2026 return err; 2027 } 2028 2029 static int ionic_txrx_init(struct ionic_lif *lif) 2030 { 2031 unsigned int i; 2032 int err; 2033 2034 for (i = 0; i < lif->nxqs; i++) { 2035 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2036 if (err) 2037 goto err_out; 2038 2039 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2040 if (err) { 2041 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2042 goto err_out; 2043 } 2044 } 2045 2046 if (lif->netdev->features & NETIF_F_RXHASH) 2047 ionic_lif_rss_init(lif); 2048 2049 ionic_lif_rx_mode(lif); 2050 2051 return 0; 2052 2053 err_out: 2054 while (i--) { 2055 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2056 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2057 } 2058 2059 return err; 2060 } 2061 2062 static int ionic_txrx_enable(struct ionic_lif *lif) 2063 { 2064 int derr = 0; 2065 int i, err; 2066 2067 for (i = 0; i < lif->nxqs; i++) { 2068 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2069 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2070 err = -ENXIO; 2071 goto err_out; 2072 } 2073 2074 ionic_rx_fill(&lif->rxqcqs[i]->q); 2075 err = ionic_qcq_enable(lif->rxqcqs[i]); 2076 if (err) 2077 goto err_out; 2078 2079 err = ionic_qcq_enable(lif->txqcqs[i]); 2080 if (err) { 2081 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], err); 2082 goto err_out; 2083 } 2084 } 2085 2086 if (lif->hwstamp_rxq) { 2087 ionic_rx_fill(&lif->hwstamp_rxq->q); 2088 err = ionic_qcq_enable(lif->hwstamp_rxq); 2089 if (err) 2090 goto err_out_hwstamp_rx; 2091 } 2092 2093 if (lif->hwstamp_txq) { 2094 err = ionic_qcq_enable(lif->hwstamp_txq); 2095 if (err) 2096 goto err_out_hwstamp_tx; 2097 } 2098 2099 return 0; 2100 2101 err_out_hwstamp_tx: 2102 if (lif->hwstamp_rxq) 2103 derr = ionic_qcq_disable(lif, lif->hwstamp_rxq, derr); 2104 err_out_hwstamp_rx: 2105 i = lif->nxqs; 2106 err_out: 2107 while (i--) { 2108 derr = ionic_qcq_disable(lif, lif->txqcqs[i], derr); 2109 derr = ionic_qcq_disable(lif, lif->rxqcqs[i], derr); 2110 } 2111 2112 return err; 2113 } 2114 2115 static int ionic_start_queues(struct ionic_lif *lif) 2116 { 2117 int err; 2118 2119 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2120 return -EIO; 2121 2122 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2123 return -EBUSY; 2124 2125 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2126 return 0; 2127 2128 err = ionic_txrx_enable(lif); 2129 if (err) { 2130 clear_bit(IONIC_LIF_F_UP, lif->state); 2131 return err; 2132 } 2133 netif_tx_wake_all_queues(lif->netdev); 2134 2135 return 0; 2136 } 2137 2138 static int ionic_open(struct net_device *netdev) 2139 { 2140 struct ionic_lif *lif = netdev_priv(netdev); 2141 int err; 2142 2143 /* If recovering from a broken state, clear the bit and we'll try again */ 2144 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2145 netdev_info(netdev, "clearing broken state\n"); 2146 2147 mutex_lock(&lif->queue_lock); 2148 2149 err = ionic_txrx_alloc(lif); 2150 if (err) 2151 goto err_unlock; 2152 2153 err = ionic_txrx_init(lif); 2154 if (err) 2155 goto err_txrx_free; 2156 2157 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2158 if (err) 2159 goto err_txrx_deinit; 2160 2161 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2162 if (err) 2163 goto err_txrx_deinit; 2164 2165 /* don't start the queues until we have link */ 2166 if (netif_carrier_ok(netdev)) { 2167 err = ionic_start_queues(lif); 2168 if (err) 2169 goto err_txrx_deinit; 2170 } 2171 2172 /* If hardware timestamping is enabled, but the queues were freed by 2173 * ionic_stop, those need to be reallocated and initialized, too. 2174 */ 2175 ionic_lif_hwstamp_recreate_queues(lif); 2176 2177 mutex_unlock(&lif->queue_lock); 2178 2179 return 0; 2180 2181 err_txrx_deinit: 2182 ionic_txrx_deinit(lif); 2183 err_txrx_free: 2184 ionic_txrx_free(lif); 2185 err_unlock: 2186 mutex_unlock(&lif->queue_lock); 2187 return err; 2188 } 2189 2190 static void ionic_stop_queues(struct ionic_lif *lif) 2191 { 2192 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2193 return; 2194 2195 netif_tx_disable(lif->netdev); 2196 ionic_txrx_disable(lif); 2197 } 2198 2199 static int ionic_stop(struct net_device *netdev) 2200 { 2201 struct ionic_lif *lif = netdev_priv(netdev); 2202 2203 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2204 return 0; 2205 2206 mutex_lock(&lif->queue_lock); 2207 ionic_stop_queues(lif); 2208 ionic_txrx_deinit(lif); 2209 ionic_txrx_free(lif); 2210 mutex_unlock(&lif->queue_lock); 2211 2212 return 0; 2213 } 2214 2215 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2216 { 2217 struct ionic_lif *lif = netdev_priv(netdev); 2218 2219 switch (cmd) { 2220 case SIOCSHWTSTAMP: 2221 return ionic_lif_hwstamp_set(lif, ifr); 2222 case SIOCGHWTSTAMP: 2223 return ionic_lif_hwstamp_get(lif, ifr); 2224 default: 2225 return -EOPNOTSUPP; 2226 } 2227 } 2228 2229 static int ionic_get_fw_vf_config(struct ionic *ionic, int vf, struct ionic_vf *vfdata) 2230 { 2231 struct ionic_vf_getattr_comp comp = { 0 }; 2232 int err; 2233 u8 attr; 2234 2235 attr = IONIC_VF_ATTR_VLAN; 2236 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2237 if (err && comp.status != IONIC_RC_ENOSUPP) 2238 goto err_out; 2239 if (!err) 2240 vfdata->vlanid = comp.vlanid; 2241 2242 attr = IONIC_VF_ATTR_SPOOFCHK; 2243 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2244 if (err && comp.status != IONIC_RC_ENOSUPP) 2245 goto err_out; 2246 if (!err) 2247 vfdata->spoofchk = comp.spoofchk; 2248 2249 attr = IONIC_VF_ATTR_LINKSTATE; 2250 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2251 if (err && comp.status != IONIC_RC_ENOSUPP) 2252 goto err_out; 2253 if (!err) { 2254 switch (comp.linkstate) { 2255 case IONIC_VF_LINK_STATUS_UP: 2256 vfdata->linkstate = IFLA_VF_LINK_STATE_ENABLE; 2257 break; 2258 case IONIC_VF_LINK_STATUS_DOWN: 2259 vfdata->linkstate = IFLA_VF_LINK_STATE_DISABLE; 2260 break; 2261 case IONIC_VF_LINK_STATUS_AUTO: 2262 vfdata->linkstate = IFLA_VF_LINK_STATE_AUTO; 2263 break; 2264 default: 2265 dev_warn(ionic->dev, "Unexpected link state %u\n", comp.linkstate); 2266 break; 2267 } 2268 } 2269 2270 attr = IONIC_VF_ATTR_RATE; 2271 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2272 if (err && comp.status != IONIC_RC_ENOSUPP) 2273 goto err_out; 2274 if (!err) 2275 vfdata->maxrate = comp.maxrate; 2276 2277 attr = IONIC_VF_ATTR_TRUST; 2278 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2279 if (err && comp.status != IONIC_RC_ENOSUPP) 2280 goto err_out; 2281 if (!err) 2282 vfdata->trusted = comp.trust; 2283 2284 attr = IONIC_VF_ATTR_MAC; 2285 err = ionic_dev_cmd_vf_getattr(ionic, vf, attr, &comp); 2286 if (err && comp.status != IONIC_RC_ENOSUPP) 2287 goto err_out; 2288 if (!err) 2289 ether_addr_copy(vfdata->macaddr, comp.macaddr); 2290 2291 err_out: 2292 if (err) 2293 dev_err(ionic->dev, "Failed to get %s for VF %d\n", 2294 ionic_vf_attr_to_str(attr), vf); 2295 2296 return err; 2297 } 2298 2299 static int ionic_get_vf_config(struct net_device *netdev, 2300 int vf, struct ifla_vf_info *ivf) 2301 { 2302 struct ionic_lif *lif = netdev_priv(netdev); 2303 struct ionic *ionic = lif->ionic; 2304 struct ionic_vf vfdata = { 0 }; 2305 int ret = 0; 2306 2307 if (!netif_device_present(netdev)) 2308 return -EBUSY; 2309 2310 down_read(&ionic->vf_op_lock); 2311 2312 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2313 ret = -EINVAL; 2314 } else { 2315 ivf->vf = vf; 2316 ivf->qos = 0; 2317 2318 ret = ionic_get_fw_vf_config(ionic, vf, &vfdata); 2319 if (!ret) { 2320 ivf->vlan = le16_to_cpu(vfdata.vlanid); 2321 ivf->spoofchk = vfdata.spoofchk; 2322 ivf->linkstate = vfdata.linkstate; 2323 ivf->max_tx_rate = le32_to_cpu(vfdata.maxrate); 2324 ivf->trusted = vfdata.trusted; 2325 ether_addr_copy(ivf->mac, vfdata.macaddr); 2326 } 2327 } 2328 2329 up_read(&ionic->vf_op_lock); 2330 return ret; 2331 } 2332 2333 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2334 struct ifla_vf_stats *vf_stats) 2335 { 2336 struct ionic_lif *lif = netdev_priv(netdev); 2337 struct ionic *ionic = lif->ionic; 2338 struct ionic_lif_stats *vs; 2339 int ret = 0; 2340 2341 if (!netif_device_present(netdev)) 2342 return -EBUSY; 2343 2344 down_read(&ionic->vf_op_lock); 2345 2346 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2347 ret = -EINVAL; 2348 } else { 2349 memset(vf_stats, 0, sizeof(*vf_stats)); 2350 vs = &ionic->vfs[vf].stats; 2351 2352 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2353 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2354 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2355 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2356 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2357 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2358 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2359 le64_to_cpu(vs->rx_mcast_drop_packets) + 2360 le64_to_cpu(vs->rx_bcast_drop_packets); 2361 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2362 le64_to_cpu(vs->tx_mcast_drop_packets) + 2363 le64_to_cpu(vs->tx_bcast_drop_packets); 2364 } 2365 2366 up_read(&ionic->vf_op_lock); 2367 return ret; 2368 } 2369 2370 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2371 { 2372 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_MAC }; 2373 struct ionic_lif *lif = netdev_priv(netdev); 2374 struct ionic *ionic = lif->ionic; 2375 int ret; 2376 2377 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2378 return -EINVAL; 2379 2380 if (!netif_device_present(netdev)) 2381 return -EBUSY; 2382 2383 down_write(&ionic->vf_op_lock); 2384 2385 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2386 ret = -EINVAL; 2387 } else { 2388 ether_addr_copy(vfc.macaddr, mac); 2389 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 2390 __func__, vf, vfc.macaddr); 2391 2392 ret = ionic_set_vf_config(ionic, vf, &vfc); 2393 if (!ret) 2394 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2395 } 2396 2397 up_write(&ionic->vf_op_lock); 2398 return ret; 2399 } 2400 2401 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2402 u8 qos, __be16 proto) 2403 { 2404 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_VLAN }; 2405 struct ionic_lif *lif = netdev_priv(netdev); 2406 struct ionic *ionic = lif->ionic; 2407 int ret; 2408 2409 /* until someday when we support qos */ 2410 if (qos) 2411 return -EINVAL; 2412 2413 if (vlan > 4095) 2414 return -EINVAL; 2415 2416 if (proto != htons(ETH_P_8021Q)) 2417 return -EPROTONOSUPPORT; 2418 2419 if (!netif_device_present(netdev)) 2420 return -EBUSY; 2421 2422 down_write(&ionic->vf_op_lock); 2423 2424 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2425 ret = -EINVAL; 2426 } else { 2427 vfc.vlanid = cpu_to_le16(vlan); 2428 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 2429 __func__, vf, le16_to_cpu(vfc.vlanid)); 2430 2431 ret = ionic_set_vf_config(ionic, vf, &vfc); 2432 if (!ret) 2433 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2434 } 2435 2436 up_write(&ionic->vf_op_lock); 2437 return ret; 2438 } 2439 2440 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2441 int tx_min, int tx_max) 2442 { 2443 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_RATE }; 2444 struct ionic_lif *lif = netdev_priv(netdev); 2445 struct ionic *ionic = lif->ionic; 2446 int ret; 2447 2448 /* setting the min just seems silly */ 2449 if (tx_min) 2450 return -EINVAL; 2451 2452 if (!netif_device_present(netdev)) 2453 return -EBUSY; 2454 2455 down_write(&ionic->vf_op_lock); 2456 2457 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2458 ret = -EINVAL; 2459 } else { 2460 vfc.maxrate = cpu_to_le32(tx_max); 2461 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 2462 __func__, vf, le32_to_cpu(vfc.maxrate)); 2463 2464 ret = ionic_set_vf_config(ionic, vf, &vfc); 2465 if (!ret) 2466 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2467 } 2468 2469 up_write(&ionic->vf_op_lock); 2470 return ret; 2471 } 2472 2473 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2474 { 2475 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_SPOOFCHK }; 2476 struct ionic_lif *lif = netdev_priv(netdev); 2477 struct ionic *ionic = lif->ionic; 2478 int ret; 2479 2480 if (!netif_device_present(netdev)) 2481 return -EBUSY; 2482 2483 down_write(&ionic->vf_op_lock); 2484 2485 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2486 ret = -EINVAL; 2487 } else { 2488 vfc.spoofchk = set; 2489 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 2490 __func__, vf, vfc.spoofchk); 2491 2492 ret = ionic_set_vf_config(ionic, vf, &vfc); 2493 if (!ret) 2494 ionic->vfs[vf].spoofchk = set; 2495 } 2496 2497 up_write(&ionic->vf_op_lock); 2498 return ret; 2499 } 2500 2501 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2502 { 2503 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_TRUST }; 2504 struct ionic_lif *lif = netdev_priv(netdev); 2505 struct ionic *ionic = lif->ionic; 2506 int ret; 2507 2508 if (!netif_device_present(netdev)) 2509 return -EBUSY; 2510 2511 down_write(&ionic->vf_op_lock); 2512 2513 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2514 ret = -EINVAL; 2515 } else { 2516 vfc.trust = set; 2517 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 2518 __func__, vf, vfc.trust); 2519 2520 ret = ionic_set_vf_config(ionic, vf, &vfc); 2521 if (!ret) 2522 ionic->vfs[vf].trusted = set; 2523 } 2524 2525 up_write(&ionic->vf_op_lock); 2526 return ret; 2527 } 2528 2529 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2530 { 2531 struct ionic_vf_setattr_cmd vfc = { .attr = IONIC_VF_ATTR_LINKSTATE }; 2532 struct ionic_lif *lif = netdev_priv(netdev); 2533 struct ionic *ionic = lif->ionic; 2534 u8 vfls; 2535 int ret; 2536 2537 switch (set) { 2538 case IFLA_VF_LINK_STATE_ENABLE: 2539 vfls = IONIC_VF_LINK_STATUS_UP; 2540 break; 2541 case IFLA_VF_LINK_STATE_DISABLE: 2542 vfls = IONIC_VF_LINK_STATUS_DOWN; 2543 break; 2544 case IFLA_VF_LINK_STATE_AUTO: 2545 vfls = IONIC_VF_LINK_STATUS_AUTO; 2546 break; 2547 default: 2548 return -EINVAL; 2549 } 2550 2551 if (!netif_device_present(netdev)) 2552 return -EBUSY; 2553 2554 down_write(&ionic->vf_op_lock); 2555 2556 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2557 ret = -EINVAL; 2558 } else { 2559 vfc.linkstate = vfls; 2560 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 2561 __func__, vf, vfc.linkstate); 2562 2563 ret = ionic_set_vf_config(ionic, vf, &vfc); 2564 if (!ret) 2565 ionic->vfs[vf].linkstate = set; 2566 } 2567 2568 up_write(&ionic->vf_op_lock); 2569 return ret; 2570 } 2571 2572 static void ionic_vf_attr_replay(struct ionic_lif *lif) 2573 { 2574 struct ionic_vf_setattr_cmd vfc = { }; 2575 struct ionic *ionic = lif->ionic; 2576 struct ionic_vf *v; 2577 int i; 2578 2579 if (!ionic->vfs) 2580 return; 2581 2582 down_read(&ionic->vf_op_lock); 2583 2584 for (i = 0; i < ionic->num_vfs; i++) { 2585 v = &ionic->vfs[i]; 2586 2587 if (v->stats_pa) { 2588 vfc.attr = IONIC_VF_ATTR_STATSADDR; 2589 vfc.stats_pa = cpu_to_le64(v->stats_pa); 2590 ionic_set_vf_config(ionic, i, &vfc); 2591 vfc.stats_pa = 0; 2592 } 2593 2594 if (!is_zero_ether_addr(v->macaddr)) { 2595 vfc.attr = IONIC_VF_ATTR_MAC; 2596 ether_addr_copy(vfc.macaddr, v->macaddr); 2597 ionic_set_vf_config(ionic, i, &vfc); 2598 eth_zero_addr(vfc.macaddr); 2599 } 2600 2601 if (v->vlanid) { 2602 vfc.attr = IONIC_VF_ATTR_VLAN; 2603 vfc.vlanid = v->vlanid; 2604 ionic_set_vf_config(ionic, i, &vfc); 2605 vfc.vlanid = 0; 2606 } 2607 2608 if (v->maxrate) { 2609 vfc.attr = IONIC_VF_ATTR_RATE; 2610 vfc.maxrate = v->maxrate; 2611 ionic_set_vf_config(ionic, i, &vfc); 2612 vfc.maxrate = 0; 2613 } 2614 2615 if (v->spoofchk) { 2616 vfc.attr = IONIC_VF_ATTR_SPOOFCHK; 2617 vfc.spoofchk = v->spoofchk; 2618 ionic_set_vf_config(ionic, i, &vfc); 2619 vfc.spoofchk = 0; 2620 } 2621 2622 if (v->trusted) { 2623 vfc.attr = IONIC_VF_ATTR_TRUST; 2624 vfc.trust = v->trusted; 2625 ionic_set_vf_config(ionic, i, &vfc); 2626 vfc.trust = 0; 2627 } 2628 2629 if (v->linkstate) { 2630 vfc.attr = IONIC_VF_ATTR_LINKSTATE; 2631 vfc.linkstate = v->linkstate; 2632 ionic_set_vf_config(ionic, i, &vfc); 2633 vfc.linkstate = 0; 2634 } 2635 } 2636 2637 up_read(&ionic->vf_op_lock); 2638 2639 ionic_vf_start(ionic); 2640 } 2641 2642 static const struct net_device_ops ionic_netdev_ops = { 2643 .ndo_open = ionic_open, 2644 .ndo_stop = ionic_stop, 2645 .ndo_eth_ioctl = ionic_eth_ioctl, 2646 .ndo_start_xmit = ionic_start_xmit, 2647 .ndo_get_stats64 = ionic_get_stats64, 2648 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2649 .ndo_set_features = ionic_set_features, 2650 .ndo_set_mac_address = ionic_set_mac_address, 2651 .ndo_validate_addr = eth_validate_addr, 2652 .ndo_tx_timeout = ionic_tx_timeout, 2653 .ndo_change_mtu = ionic_change_mtu, 2654 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2655 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2656 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2657 .ndo_set_vf_trust = ionic_set_vf_trust, 2658 .ndo_set_vf_mac = ionic_set_vf_mac, 2659 .ndo_set_vf_rate = ionic_set_vf_rate, 2660 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2661 .ndo_get_vf_config = ionic_get_vf_config, 2662 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2663 .ndo_get_vf_stats = ionic_get_vf_stats, 2664 }; 2665 2666 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2667 { 2668 /* only swapping the queues, not the napi, flags, or other stuff */ 2669 swap(a->q.features, b->q.features); 2670 swap(a->q.num_descs, b->q.num_descs); 2671 swap(a->q.desc_size, b->q.desc_size); 2672 swap(a->q.base, b->q.base); 2673 swap(a->q.base_pa, b->q.base_pa); 2674 swap(a->q.info, b->q.info); 2675 swap(a->q_base, b->q_base); 2676 swap(a->q_base_pa, b->q_base_pa); 2677 swap(a->q_size, b->q_size); 2678 2679 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2680 swap(a->q.sg_base, b->q.sg_base); 2681 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2682 swap(a->sg_base, b->sg_base); 2683 swap(a->sg_base_pa, b->sg_base_pa); 2684 swap(a->sg_size, b->sg_size); 2685 2686 swap(a->cq.num_descs, b->cq.num_descs); 2687 swap(a->cq.desc_size, b->cq.desc_size); 2688 swap(a->cq.base, b->cq.base); 2689 swap(a->cq.base_pa, b->cq.base_pa); 2690 swap(a->cq.info, b->cq.info); 2691 swap(a->cq_base, b->cq_base); 2692 swap(a->cq_base_pa, b->cq_base_pa); 2693 swap(a->cq_size, b->cq_size); 2694 2695 ionic_debugfs_del_qcq(a); 2696 ionic_debugfs_add_qcq(a->q.lif, a); 2697 } 2698 2699 int ionic_reconfigure_queues(struct ionic_lif *lif, 2700 struct ionic_queue_params *qparam) 2701 { 2702 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2703 struct ionic_qcq **tx_qcqs = NULL; 2704 struct ionic_qcq **rx_qcqs = NULL; 2705 unsigned int flags, i; 2706 int err = 0; 2707 2708 /* allocate temporary qcq arrays to hold new queue structs */ 2709 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2710 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2711 sizeof(struct ionic_qcq *), GFP_KERNEL); 2712 if (!tx_qcqs) { 2713 err = -ENOMEM; 2714 goto err_out; 2715 } 2716 } 2717 if (qparam->nxqs != lif->nxqs || 2718 qparam->nrxq_descs != lif->nrxq_descs || 2719 qparam->rxq_features != lif->rxq_features) { 2720 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2721 sizeof(struct ionic_qcq *), GFP_KERNEL); 2722 if (!rx_qcqs) { 2723 err = -ENOMEM; 2724 goto err_out; 2725 } 2726 } 2727 2728 /* allocate new desc_info and rings, but leave the interrupt setup 2729 * until later so as to not mess with the still-running queues 2730 */ 2731 if (tx_qcqs) { 2732 num_desc = qparam->ntxq_descs; 2733 desc_sz = sizeof(struct ionic_txq_desc); 2734 comp_sz = sizeof(struct ionic_txq_comp); 2735 2736 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2737 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2738 sizeof(struct ionic_txq_sg_desc_v1)) 2739 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2740 else 2741 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2742 2743 for (i = 0; i < qparam->nxqs; i++) { 2744 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2745 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2746 num_desc, desc_sz, comp_sz, sg_desc_sz, 2747 lif->kern_pid, &tx_qcqs[i]); 2748 if (err) 2749 goto err_out; 2750 } 2751 } 2752 2753 if (rx_qcqs) { 2754 num_desc = qparam->nrxq_descs; 2755 desc_sz = sizeof(struct ionic_rxq_desc); 2756 comp_sz = sizeof(struct ionic_rxq_comp); 2757 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2758 2759 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2760 comp_sz *= 2; 2761 2762 for (i = 0; i < qparam->nxqs; i++) { 2763 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2764 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2765 num_desc, desc_sz, comp_sz, sg_desc_sz, 2766 lif->kern_pid, &rx_qcqs[i]); 2767 if (err) 2768 goto err_out; 2769 2770 rx_qcqs[i]->q.features = qparam->rxq_features; 2771 } 2772 } 2773 2774 /* stop and clean the queues */ 2775 ionic_stop_queues_reconfig(lif); 2776 2777 if (qparam->nxqs != lif->nxqs) { 2778 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2779 if (err) 2780 goto err_out_reinit_unlock; 2781 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2782 if (err) { 2783 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2784 goto err_out_reinit_unlock; 2785 } 2786 } 2787 2788 /* swap new desc_info and rings, keeping existing interrupt config */ 2789 if (tx_qcqs) { 2790 lif->ntxq_descs = qparam->ntxq_descs; 2791 for (i = 0; i < qparam->nxqs; i++) 2792 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2793 } 2794 2795 if (rx_qcqs) { 2796 lif->nrxq_descs = qparam->nrxq_descs; 2797 for (i = 0; i < qparam->nxqs; i++) 2798 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2799 } 2800 2801 /* if we need to change the interrupt layout, this is the time */ 2802 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2803 qparam->nxqs != lif->nxqs) { 2804 if (qparam->intr_split) { 2805 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2806 } else { 2807 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2808 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2809 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2810 } 2811 2812 /* clear existing interrupt assignments */ 2813 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2814 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2815 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2816 } 2817 2818 /* re-assign the interrupts */ 2819 for (i = 0; i < qparam->nxqs; i++) { 2820 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2821 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2822 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2823 lif->rxqcqs[i]->intr.index, 2824 lif->rx_coalesce_hw); 2825 2826 if (qparam->intr_split) { 2827 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2828 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2829 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2830 lif->txqcqs[i]->intr.index, 2831 lif->tx_coalesce_hw); 2832 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2833 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2834 } else { 2835 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2836 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2837 } 2838 } 2839 } 2840 2841 /* now we can rework the debugfs mappings */ 2842 if (tx_qcqs) { 2843 for (i = 0; i < qparam->nxqs; i++) { 2844 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2845 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2846 } 2847 } 2848 2849 if (rx_qcqs) { 2850 for (i = 0; i < qparam->nxqs; i++) { 2851 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2852 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2853 } 2854 } 2855 2856 swap(lif->nxqs, qparam->nxqs); 2857 swap(lif->rxq_features, qparam->rxq_features); 2858 2859 err_out_reinit_unlock: 2860 /* re-init the queues, but don't lose an error code */ 2861 if (err) 2862 ionic_start_queues_reconfig(lif); 2863 else 2864 err = ionic_start_queues_reconfig(lif); 2865 2866 err_out: 2867 /* free old allocs without cleaning intr */ 2868 for (i = 0; i < qparam->nxqs; i++) { 2869 if (tx_qcqs && tx_qcqs[i]) { 2870 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2871 ionic_qcq_free(lif, tx_qcqs[i]); 2872 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2873 tx_qcqs[i] = NULL; 2874 } 2875 if (rx_qcqs && rx_qcqs[i]) { 2876 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2877 ionic_qcq_free(lif, rx_qcqs[i]); 2878 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2879 rx_qcqs[i] = NULL; 2880 } 2881 } 2882 2883 /* free q array */ 2884 if (rx_qcqs) { 2885 devm_kfree(lif->ionic->dev, rx_qcqs); 2886 rx_qcqs = NULL; 2887 } 2888 if (tx_qcqs) { 2889 devm_kfree(lif->ionic->dev, tx_qcqs); 2890 tx_qcqs = NULL; 2891 } 2892 2893 /* clean the unused dma and info allocations when new set is smaller 2894 * than the full array, but leave the qcq shells in place 2895 */ 2896 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2897 if (lif->txqcqs && lif->txqcqs[i]) { 2898 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2899 ionic_qcq_free(lif, lif->txqcqs[i]); 2900 } 2901 2902 if (lif->rxqcqs && lif->rxqcqs[i]) { 2903 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2904 ionic_qcq_free(lif, lif->rxqcqs[i]); 2905 } 2906 } 2907 2908 if (err) 2909 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2910 2911 return err; 2912 } 2913 2914 int ionic_lif_alloc(struct ionic *ionic) 2915 { 2916 struct device *dev = ionic->dev; 2917 union ionic_lif_identity *lid; 2918 struct net_device *netdev; 2919 struct ionic_lif *lif; 2920 int tbl_sz; 2921 int err; 2922 2923 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2924 if (!lid) 2925 return -ENOMEM; 2926 2927 netdev = alloc_etherdev_mqs(sizeof(*lif), 2928 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2929 if (!netdev) { 2930 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2931 err = -ENOMEM; 2932 goto err_out_free_lid; 2933 } 2934 2935 SET_NETDEV_DEV(netdev, dev); 2936 2937 lif = netdev_priv(netdev); 2938 lif->netdev = netdev; 2939 ionic->lif = lif; 2940 netdev->netdev_ops = &ionic_netdev_ops; 2941 ionic_ethtool_set_ops(netdev); 2942 2943 netdev->watchdog_timeo = 2 * HZ; 2944 netif_carrier_off(netdev); 2945 2946 lif->identity = lid; 2947 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2948 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2949 if (err) { 2950 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2951 lif->lif_type, err); 2952 goto err_out_free_netdev; 2953 } 2954 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2955 le32_to_cpu(lif->identity->eth.min_frame_size)); 2956 lif->netdev->max_mtu = 2957 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2958 2959 lif->neqs = ionic->neqs_per_lif; 2960 lif->nxqs = ionic->ntxqs_per_lif; 2961 2962 lif->ionic = ionic; 2963 lif->index = 0; 2964 2965 if (is_kdump_kernel()) { 2966 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2967 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2968 } else { 2969 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2970 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2971 } 2972 2973 /* Convert the default coalesce value to actual hw resolution */ 2974 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2975 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2976 lif->rx_coalesce_usecs); 2977 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2978 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2979 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2980 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2981 2982 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2983 2984 mutex_init(&lif->queue_lock); 2985 mutex_init(&lif->config_lock); 2986 2987 spin_lock_init(&lif->adminq_lock); 2988 2989 spin_lock_init(&lif->deferred.lock); 2990 INIT_LIST_HEAD(&lif->deferred.list); 2991 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2992 2993 /* allocate lif info */ 2994 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2995 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2996 &lif->info_pa, GFP_KERNEL); 2997 if (!lif->info) { 2998 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2999 err = -ENOMEM; 3000 goto err_out_free_mutex; 3001 } 3002 3003 ionic_debugfs_add_lif(lif); 3004 3005 /* allocate control queues and txrx queue arrays */ 3006 ionic_lif_queue_identify(lif); 3007 err = ionic_qcqs_alloc(lif); 3008 if (err) 3009 goto err_out_free_lif_info; 3010 3011 /* allocate rss indirection table */ 3012 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 3013 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 3014 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 3015 &lif->rss_ind_tbl_pa, 3016 GFP_KERNEL); 3017 3018 if (!lif->rss_ind_tbl) { 3019 err = -ENOMEM; 3020 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 3021 goto err_out_free_qcqs; 3022 } 3023 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 3024 3025 ionic_lif_alloc_phc(lif); 3026 3027 return 0; 3028 3029 err_out_free_qcqs: 3030 ionic_qcqs_free(lif); 3031 err_out_free_lif_info: 3032 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3033 lif->info = NULL; 3034 lif->info_pa = 0; 3035 err_out_free_mutex: 3036 mutex_destroy(&lif->config_lock); 3037 mutex_destroy(&lif->queue_lock); 3038 err_out_free_netdev: 3039 free_netdev(lif->netdev); 3040 lif = NULL; 3041 err_out_free_lid: 3042 kfree(lid); 3043 3044 return err; 3045 } 3046 3047 static void ionic_lif_reset(struct ionic_lif *lif) 3048 { 3049 struct ionic_dev *idev = &lif->ionic->idev; 3050 3051 mutex_lock(&lif->ionic->dev_cmd_lock); 3052 ionic_dev_cmd_lif_reset(idev, lif->index); 3053 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3054 mutex_unlock(&lif->ionic->dev_cmd_lock); 3055 } 3056 3057 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 3058 { 3059 struct ionic *ionic = lif->ionic; 3060 3061 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3062 return; 3063 3064 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 3065 3066 netif_device_detach(lif->netdev); 3067 3068 mutex_lock(&lif->queue_lock); 3069 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 3070 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 3071 ionic_stop_queues(lif); 3072 } 3073 3074 if (netif_running(lif->netdev)) { 3075 ionic_txrx_deinit(lif); 3076 ionic_txrx_free(lif); 3077 } 3078 ionic_lif_deinit(lif); 3079 ionic_reset(ionic); 3080 ionic_qcqs_free(lif); 3081 3082 mutex_unlock(&lif->queue_lock); 3083 3084 clear_bit(IONIC_LIF_F_FW_STOPPING, lif->state); 3085 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 3086 } 3087 3088 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 3089 { 3090 struct ionic *ionic = lif->ionic; 3091 int err; 3092 3093 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3094 return; 3095 3096 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 3097 3098 ionic_init_devinfo(ionic); 3099 err = ionic_identify(ionic); 3100 if (err) 3101 goto err_out; 3102 err = ionic_port_identify(ionic); 3103 if (err) 3104 goto err_out; 3105 err = ionic_port_init(ionic); 3106 if (err) 3107 goto err_out; 3108 3109 mutex_lock(&lif->queue_lock); 3110 3111 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 3112 dev_info(ionic->dev, "FW Up: clearing broken state\n"); 3113 3114 err = ionic_qcqs_alloc(lif); 3115 if (err) 3116 goto err_unlock; 3117 3118 err = ionic_lif_init(lif); 3119 if (err) 3120 goto err_qcqs_free; 3121 3122 ionic_vf_attr_replay(lif); 3123 3124 if (lif->registered) 3125 ionic_lif_set_netdev_info(lif); 3126 3127 ionic_rx_filter_replay(lif); 3128 3129 if (netif_running(lif->netdev)) { 3130 err = ionic_txrx_alloc(lif); 3131 if (err) 3132 goto err_lifs_deinit; 3133 3134 err = ionic_txrx_init(lif); 3135 if (err) 3136 goto err_txrx_free; 3137 } 3138 3139 mutex_unlock(&lif->queue_lock); 3140 3141 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3142 ionic_link_status_check_request(lif, CAN_SLEEP); 3143 netif_device_attach(lif->netdev); 3144 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3145 3146 /* restore the hardware timestamping queues */ 3147 ionic_lif_hwstamp_replay(lif); 3148 3149 return; 3150 3151 err_txrx_free: 3152 ionic_txrx_free(lif); 3153 err_lifs_deinit: 3154 ionic_lif_deinit(lif); 3155 err_qcqs_free: 3156 ionic_qcqs_free(lif); 3157 err_unlock: 3158 mutex_unlock(&lif->queue_lock); 3159 err_out: 3160 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3161 } 3162 3163 void ionic_lif_free(struct ionic_lif *lif) 3164 { 3165 struct device *dev = lif->ionic->dev; 3166 3167 ionic_lif_free_phc(lif); 3168 3169 /* free rss indirection table */ 3170 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3171 lif->rss_ind_tbl_pa); 3172 lif->rss_ind_tbl = NULL; 3173 lif->rss_ind_tbl_pa = 0; 3174 3175 /* free queues */ 3176 ionic_qcqs_free(lif); 3177 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3178 ionic_lif_reset(lif); 3179 3180 /* free lif info */ 3181 kfree(lif->identity); 3182 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3183 lif->info = NULL; 3184 lif->info_pa = 0; 3185 3186 /* unmap doorbell page */ 3187 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3188 lif->kern_dbpage = NULL; 3189 3190 mutex_destroy(&lif->config_lock); 3191 mutex_destroy(&lif->queue_lock); 3192 3193 /* free netdev & lif */ 3194 ionic_debugfs_del_lif(lif); 3195 free_netdev(lif->netdev); 3196 } 3197 3198 void ionic_lif_deinit(struct ionic_lif *lif) 3199 { 3200 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3201 return; 3202 3203 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3204 cancel_work_sync(&lif->deferred.work); 3205 cancel_work_sync(&lif->tx_timeout_work); 3206 ionic_rx_filters_deinit(lif); 3207 if (lif->netdev->features & NETIF_F_RXHASH) 3208 ionic_lif_rss_deinit(lif); 3209 } 3210 3211 napi_disable(&lif->adminqcq->napi); 3212 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3213 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3214 3215 ionic_lif_reset(lif); 3216 } 3217 3218 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3219 { 3220 struct device *dev = lif->ionic->dev; 3221 struct ionic_q_init_comp comp; 3222 struct ionic_dev *idev; 3223 struct ionic_qcq *qcq; 3224 struct ionic_queue *q; 3225 int err; 3226 3227 idev = &lif->ionic->idev; 3228 qcq = lif->adminqcq; 3229 q = &qcq->q; 3230 3231 mutex_lock(&lif->ionic->dev_cmd_lock); 3232 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3233 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3234 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3235 mutex_unlock(&lif->ionic->dev_cmd_lock); 3236 if (err) { 3237 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3238 return err; 3239 } 3240 3241 q->hw_type = comp.hw_type; 3242 q->hw_index = le32_to_cpu(comp.hw_index); 3243 q->dbval = IONIC_DBELL_QID(q->hw_index); 3244 3245 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3246 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3247 3248 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi); 3249 3250 napi_enable(&qcq->napi); 3251 3252 if (qcq->flags & IONIC_QCQ_F_INTR) 3253 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3254 IONIC_INTR_MASK_CLEAR); 3255 3256 qcq->flags |= IONIC_QCQ_F_INITED; 3257 3258 return 0; 3259 } 3260 3261 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3262 { 3263 struct ionic_qcq *qcq = lif->notifyqcq; 3264 struct device *dev = lif->ionic->dev; 3265 struct ionic_queue *q = &qcq->q; 3266 int err; 3267 3268 struct ionic_admin_ctx ctx = { 3269 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3270 .cmd.q_init = { 3271 .opcode = IONIC_CMD_Q_INIT, 3272 .lif_index = cpu_to_le16(lif->index), 3273 .type = q->type, 3274 .ver = lif->qtype_info[q->type].version, 3275 .index = cpu_to_le32(q->index), 3276 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3277 IONIC_QINIT_F_ENA), 3278 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3279 .pid = cpu_to_le16(q->pid), 3280 .ring_size = ilog2(q->num_descs), 3281 .ring_base = cpu_to_le64(q->base_pa), 3282 } 3283 }; 3284 3285 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3286 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3287 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3288 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3289 3290 err = ionic_adminq_post_wait(lif, &ctx); 3291 if (err) 3292 return err; 3293 3294 lif->last_eid = 0; 3295 q->hw_type = ctx.comp.q_init.hw_type; 3296 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3297 q->dbval = IONIC_DBELL_QID(q->hw_index); 3298 3299 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3300 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3301 3302 /* preset the callback info */ 3303 q->info[0].cb_arg = lif; 3304 3305 qcq->flags |= IONIC_QCQ_F_INITED; 3306 3307 return 0; 3308 } 3309 3310 static int ionic_station_set(struct ionic_lif *lif) 3311 { 3312 struct net_device *netdev = lif->netdev; 3313 struct ionic_admin_ctx ctx = { 3314 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3315 .cmd.lif_getattr = { 3316 .opcode = IONIC_CMD_LIF_GETATTR, 3317 .index = cpu_to_le16(lif->index), 3318 .attr = IONIC_LIF_ATTR_MAC, 3319 }, 3320 }; 3321 u8 mac_address[ETH_ALEN]; 3322 struct sockaddr addr; 3323 int err; 3324 3325 err = ionic_adminq_post_wait(lif, &ctx); 3326 if (err) 3327 return err; 3328 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3329 ctx.comp.lif_getattr.mac); 3330 ether_addr_copy(mac_address, ctx.comp.lif_getattr.mac); 3331 3332 if (is_zero_ether_addr(mac_address)) { 3333 eth_hw_addr_random(netdev); 3334 netdev_dbg(netdev, "Random Mac generated: %pM\n", netdev->dev_addr); 3335 ether_addr_copy(mac_address, netdev->dev_addr); 3336 3337 err = ionic_program_mac(lif, mac_address); 3338 if (err < 0) 3339 return err; 3340 3341 if (err > 0) { 3342 netdev_dbg(netdev, "%s:SET/GET ATTR Mac are not same-due to old FW running\n", 3343 __func__); 3344 return 0; 3345 } 3346 } 3347 3348 if (!is_zero_ether_addr(netdev->dev_addr)) { 3349 /* If the netdev mac is non-zero and doesn't match the default 3350 * device address, it was set by something earlier and we're 3351 * likely here again after a fw-upgrade reset. We need to be 3352 * sure the netdev mac is in our filter list. 3353 */ 3354 if (!ether_addr_equal(mac_address, netdev->dev_addr)) 3355 ionic_lif_addr_add(lif, netdev->dev_addr); 3356 } else { 3357 /* Update the netdev mac with the device's mac */ 3358 ether_addr_copy(addr.sa_data, mac_address); 3359 addr.sa_family = AF_INET; 3360 err = eth_prepare_mac_addr_change(netdev, &addr); 3361 if (err) { 3362 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3363 addr.sa_data, err); 3364 return 0; 3365 } 3366 3367 eth_commit_mac_addr_change(netdev, &addr); 3368 } 3369 3370 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3371 netdev->dev_addr); 3372 ionic_lif_addr_add(lif, netdev->dev_addr); 3373 3374 return 0; 3375 } 3376 3377 int ionic_lif_init(struct ionic_lif *lif) 3378 { 3379 struct ionic_dev *idev = &lif->ionic->idev; 3380 struct device *dev = lif->ionic->dev; 3381 struct ionic_lif_init_comp comp; 3382 int dbpage_num; 3383 int err; 3384 3385 mutex_lock(&lif->ionic->dev_cmd_lock); 3386 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3387 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3388 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3389 mutex_unlock(&lif->ionic->dev_cmd_lock); 3390 if (err) 3391 return err; 3392 3393 lif->hw_index = le16_to_cpu(comp.hw_index); 3394 3395 /* now that we have the hw_index we can figure out our doorbell page */ 3396 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3397 if (!lif->dbid_count) { 3398 dev_err(dev, "No doorbell pages, aborting\n"); 3399 return -EINVAL; 3400 } 3401 3402 lif->kern_pid = 0; 3403 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3404 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3405 if (!lif->kern_dbpage) { 3406 dev_err(dev, "Cannot map dbpage, aborting\n"); 3407 return -ENOMEM; 3408 } 3409 3410 err = ionic_lif_adminq_init(lif); 3411 if (err) 3412 goto err_out_adminq_deinit; 3413 3414 if (lif->ionic->nnqs_per_lif) { 3415 err = ionic_lif_notifyq_init(lif); 3416 if (err) 3417 goto err_out_notifyq_deinit; 3418 } 3419 3420 err = ionic_init_nic_features(lif); 3421 if (err) 3422 goto err_out_notifyq_deinit; 3423 3424 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3425 err = ionic_rx_filters_init(lif); 3426 if (err) 3427 goto err_out_notifyq_deinit; 3428 } 3429 3430 err = ionic_station_set(lif); 3431 if (err) 3432 goto err_out_notifyq_deinit; 3433 3434 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3435 3436 set_bit(IONIC_LIF_F_INITED, lif->state); 3437 3438 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3439 3440 return 0; 3441 3442 err_out_notifyq_deinit: 3443 napi_disable(&lif->adminqcq->napi); 3444 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3445 err_out_adminq_deinit: 3446 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3447 ionic_lif_reset(lif); 3448 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3449 lif->kern_dbpage = NULL; 3450 3451 return err; 3452 } 3453 3454 static void ionic_lif_notify_work(struct work_struct *ws) 3455 { 3456 } 3457 3458 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3459 { 3460 struct ionic_admin_ctx ctx = { 3461 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3462 .cmd.lif_setattr = { 3463 .opcode = IONIC_CMD_LIF_SETATTR, 3464 .index = cpu_to_le16(lif->index), 3465 .attr = IONIC_LIF_ATTR_NAME, 3466 }, 3467 }; 3468 3469 strscpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3470 sizeof(ctx.cmd.lif_setattr.name)); 3471 3472 ionic_adminq_post_wait(lif, &ctx); 3473 } 3474 3475 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3476 { 3477 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3478 return NULL; 3479 3480 return netdev_priv(netdev); 3481 } 3482 3483 static int ionic_lif_notify(struct notifier_block *nb, 3484 unsigned long event, void *info) 3485 { 3486 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3487 struct ionic *ionic = container_of(nb, struct ionic, nb); 3488 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3489 3490 if (!lif || lif->ionic != ionic) 3491 return NOTIFY_DONE; 3492 3493 switch (event) { 3494 case NETDEV_CHANGENAME: 3495 ionic_lif_set_netdev_info(lif); 3496 break; 3497 } 3498 3499 return NOTIFY_DONE; 3500 } 3501 3502 int ionic_lif_register(struct ionic_lif *lif) 3503 { 3504 int err; 3505 3506 ionic_lif_register_phc(lif); 3507 3508 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3509 3510 lif->ionic->nb.notifier_call = ionic_lif_notify; 3511 3512 err = register_netdevice_notifier(&lif->ionic->nb); 3513 if (err) 3514 lif->ionic->nb.notifier_call = NULL; 3515 3516 /* only register LIF0 for now */ 3517 err = register_netdev(lif->netdev); 3518 if (err) { 3519 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3520 ionic_lif_unregister_phc(lif); 3521 return err; 3522 } 3523 3524 ionic_link_status_check_request(lif, CAN_SLEEP); 3525 lif->registered = true; 3526 ionic_lif_set_netdev_info(lif); 3527 3528 return 0; 3529 } 3530 3531 void ionic_lif_unregister(struct ionic_lif *lif) 3532 { 3533 if (lif->ionic->nb.notifier_call) { 3534 unregister_netdevice_notifier(&lif->ionic->nb); 3535 cancel_work_sync(&lif->ionic->nb_work); 3536 lif->ionic->nb.notifier_call = NULL; 3537 } 3538 3539 if (lif->netdev->reg_state == NETREG_REGISTERED) 3540 unregister_netdev(lif->netdev); 3541 3542 ionic_lif_unregister_phc(lif); 3543 3544 lif->registered = false; 3545 } 3546 3547 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3548 { 3549 union ionic_q_identity __iomem *q_ident; 3550 struct ionic *ionic = lif->ionic; 3551 struct ionic_dev *idev; 3552 int qtype; 3553 int err; 3554 3555 idev = &lif->ionic->idev; 3556 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3557 3558 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3559 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3560 3561 /* filter out the ones we know about */ 3562 switch (qtype) { 3563 case IONIC_QTYPE_ADMINQ: 3564 case IONIC_QTYPE_NOTIFYQ: 3565 case IONIC_QTYPE_RXQ: 3566 case IONIC_QTYPE_TXQ: 3567 break; 3568 default: 3569 continue; 3570 } 3571 3572 memset(qti, 0, sizeof(*qti)); 3573 3574 mutex_lock(&ionic->dev_cmd_lock); 3575 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3576 ionic_qtype_versions[qtype]); 3577 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3578 if (!err) { 3579 qti->version = readb(&q_ident->version); 3580 qti->supported = readb(&q_ident->supported); 3581 qti->features = readq(&q_ident->features); 3582 qti->desc_sz = readw(&q_ident->desc_sz); 3583 qti->comp_sz = readw(&q_ident->comp_sz); 3584 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3585 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3586 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3587 } 3588 mutex_unlock(&ionic->dev_cmd_lock); 3589 3590 if (err == -EINVAL) { 3591 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3592 continue; 3593 } else if (err == -EIO) { 3594 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3595 return; 3596 } else if (err) { 3597 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3598 qtype, err); 3599 return; 3600 } 3601 3602 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3603 qtype, qti->version); 3604 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3605 qtype, qti->supported); 3606 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3607 qtype, qti->features); 3608 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3609 qtype, qti->desc_sz); 3610 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3611 qtype, qti->comp_sz); 3612 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3613 qtype, qti->sg_desc_sz); 3614 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3615 qtype, qti->max_sg_elems); 3616 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3617 qtype, qti->sg_desc_stride); 3618 } 3619 } 3620 3621 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3622 union ionic_lif_identity *lid) 3623 { 3624 struct ionic_dev *idev = &ionic->idev; 3625 size_t sz; 3626 int err; 3627 3628 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3629 3630 mutex_lock(&ionic->dev_cmd_lock); 3631 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3632 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3633 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3634 mutex_unlock(&ionic->dev_cmd_lock); 3635 if (err) 3636 return (err); 3637 3638 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3639 le64_to_cpu(lid->capabilities)); 3640 3641 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3642 le32_to_cpu(lid->eth.max_ucast_filters)); 3643 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3644 le32_to_cpu(lid->eth.max_mcast_filters)); 3645 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3646 le64_to_cpu(lid->eth.config.features)); 3647 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3648 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3649 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3650 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3651 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3652 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3653 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3654 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3655 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3656 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3657 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3658 le32_to_cpu(lid->eth.config.mtu)); 3659 3660 return 0; 3661 } 3662 3663 int ionic_lif_size(struct ionic *ionic) 3664 { 3665 struct ionic_identity *ident = &ionic->ident; 3666 unsigned int nintrs, dev_nintrs; 3667 union ionic_lif_config *lc; 3668 unsigned int ntxqs_per_lif; 3669 unsigned int nrxqs_per_lif; 3670 unsigned int neqs_per_lif; 3671 unsigned int nnqs_per_lif; 3672 unsigned int nxqs, neqs; 3673 unsigned int min_intrs; 3674 int err; 3675 3676 /* retrieve basic values from FW */ 3677 lc = &ident->lif.eth.config; 3678 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3679 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3680 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3681 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3682 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3683 3684 /* limit values to play nice with kdump */ 3685 if (is_kdump_kernel()) { 3686 dev_nintrs = 2; 3687 neqs_per_lif = 0; 3688 nnqs_per_lif = 0; 3689 ntxqs_per_lif = 1; 3690 nrxqs_per_lif = 1; 3691 } 3692 3693 /* reserve last queue id for hardware timestamping */ 3694 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3695 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3696 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3697 } else { 3698 ntxqs_per_lif -= 1; 3699 nrxqs_per_lif -= 1; 3700 } 3701 } 3702 3703 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3704 nxqs = min(nxqs, num_online_cpus()); 3705 neqs = min(neqs_per_lif, num_online_cpus()); 3706 3707 try_again: 3708 /* interrupt usage: 3709 * 1 for master lif adminq/notifyq 3710 * 1 for each CPU for master lif TxRx queue pairs 3711 * whatever's left is for RDMA queues 3712 */ 3713 nintrs = 1 + nxqs + neqs; 3714 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3715 3716 if (nintrs > dev_nintrs) 3717 goto try_fewer; 3718 3719 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3720 if (err < 0 && err != -ENOSPC) { 3721 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3722 return err; 3723 } 3724 if (err == -ENOSPC) 3725 goto try_fewer; 3726 3727 if (err != nintrs) { 3728 ionic_bus_free_irq_vectors(ionic); 3729 goto try_fewer; 3730 } 3731 3732 ionic->nnqs_per_lif = nnqs_per_lif; 3733 ionic->neqs_per_lif = neqs; 3734 ionic->ntxqs_per_lif = nxqs; 3735 ionic->nrxqs_per_lif = nxqs; 3736 ionic->nintrs = nintrs; 3737 3738 ionic_debugfs_add_sizes(ionic); 3739 3740 return 0; 3741 3742 try_fewer: 3743 if (nnqs_per_lif > 1) { 3744 nnqs_per_lif >>= 1; 3745 goto try_again; 3746 } 3747 if (neqs > 1) { 3748 neqs >>= 1; 3749 goto try_again; 3750 } 3751 if (nxqs > 1) { 3752 nxqs >>= 1; 3753 goto try_again; 3754 } 3755 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3756 return -ENOSPC; 3757 } 3758