1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/printk.h> 5 #include <linux/dynamic_debug.h> 6 #include <linux/netdevice.h> 7 #include <linux/etherdevice.h> 8 #include <linux/rtnetlink.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/cpumask.h> 12 13 #include "ionic.h" 14 #include "ionic_bus.h" 15 #include "ionic_lif.h" 16 #include "ionic_txrx.h" 17 #include "ionic_ethtool.h" 18 #include "ionic_debugfs.h" 19 20 /* queuetype support level */ 21 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 22 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 23 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 24 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 25 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 26 * 1 = ... with Tx SG version 1 27 */ 28 }; 29 30 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode); 31 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr); 32 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr); 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static int ionic_start_queues(struct ionic_lif *lif); 39 static void ionic_stop_queues(struct ionic_lif *lif); 40 static void ionic_lif_queue_identify(struct ionic_lif *lif); 41 42 static void ionic_lif_deferred_work(struct work_struct *work) 43 { 44 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 45 struct ionic_deferred *def = &lif->deferred; 46 struct ionic_deferred_work *w = NULL; 47 48 spin_lock_bh(&def->lock); 49 if (!list_empty(&def->list)) { 50 w = list_first_entry(&def->list, 51 struct ionic_deferred_work, list); 52 list_del(&w->list); 53 } 54 spin_unlock_bh(&def->lock); 55 56 if (w) { 57 switch (w->type) { 58 case IONIC_DW_TYPE_RX_MODE: 59 ionic_lif_rx_mode(lif, w->rx_mode); 60 break; 61 case IONIC_DW_TYPE_RX_ADDR_ADD: 62 ionic_lif_addr_add(lif, w->addr); 63 break; 64 case IONIC_DW_TYPE_RX_ADDR_DEL: 65 ionic_lif_addr_del(lif, w->addr); 66 break; 67 case IONIC_DW_TYPE_LINK_STATUS: 68 ionic_link_status_check(lif); 69 break; 70 case IONIC_DW_TYPE_LIF_RESET: 71 if (w->fw_status) 72 ionic_lif_handle_fw_up(lif); 73 else 74 ionic_lif_handle_fw_down(lif); 75 break; 76 default: 77 break; 78 } 79 kfree(w); 80 schedule_work(&def->work); 81 } 82 } 83 84 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 85 struct ionic_deferred_work *work) 86 { 87 spin_lock_bh(&def->lock); 88 list_add_tail(&work->list, &def->list); 89 spin_unlock_bh(&def->lock); 90 schedule_work(&def->work); 91 } 92 93 static void ionic_link_status_check(struct ionic_lif *lif) 94 { 95 struct net_device *netdev = lif->netdev; 96 u16 link_status; 97 bool link_up; 98 99 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 100 return; 101 102 link_status = le16_to_cpu(lif->info->status.link_status); 103 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 104 105 if (link_up) { 106 if (!netif_carrier_ok(netdev)) { 107 u32 link_speed; 108 109 ionic_port_identify(lif->ionic); 110 link_speed = le32_to_cpu(lif->info->status.link_speed); 111 netdev_info(netdev, "Link up - %d Gbps\n", 112 link_speed / 1000); 113 netif_carrier_on(netdev); 114 } 115 116 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 117 mutex_lock(&lif->queue_lock); 118 ionic_start_queues(lif); 119 mutex_unlock(&lif->queue_lock); 120 } 121 } else { 122 if (netif_carrier_ok(netdev)) { 123 netdev_info(netdev, "Link down\n"); 124 netif_carrier_off(netdev); 125 } 126 127 if (lif->netdev->flags & IFF_UP && netif_running(lif->netdev)) { 128 mutex_lock(&lif->queue_lock); 129 ionic_stop_queues(lif); 130 mutex_unlock(&lif->queue_lock); 131 } 132 } 133 134 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 135 } 136 137 void ionic_link_status_check_request(struct ionic_lif *lif) 138 { 139 struct ionic_deferred_work *work; 140 141 /* we only need one request outstanding at a time */ 142 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 143 return; 144 145 if (in_interrupt()) { 146 work = kzalloc(sizeof(*work), GFP_ATOMIC); 147 if (!work) 148 return; 149 150 work->type = IONIC_DW_TYPE_LINK_STATUS; 151 ionic_lif_deferred_enqueue(&lif->deferred, work); 152 } else { 153 ionic_link_status_check(lif); 154 } 155 } 156 157 static irqreturn_t ionic_isr(int irq, void *data) 158 { 159 struct napi_struct *napi = data; 160 161 napi_schedule_irqoff(napi); 162 163 return IRQ_HANDLED; 164 } 165 166 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 167 { 168 struct ionic_intr_info *intr = &qcq->intr; 169 struct device *dev = lif->ionic->dev; 170 struct ionic_queue *q = &qcq->q; 171 const char *name; 172 173 if (lif->registered) 174 name = lif->netdev->name; 175 else 176 name = dev_name(dev); 177 178 snprintf(intr->name, sizeof(intr->name), 179 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 180 181 return devm_request_irq(dev, intr->vector, ionic_isr, 182 0, intr->name, &qcq->napi); 183 } 184 185 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 186 { 187 struct ionic *ionic = lif->ionic; 188 int index; 189 190 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 191 if (index == ionic->nintrs) { 192 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 193 __func__, index, ionic->nintrs); 194 return -ENOSPC; 195 } 196 197 set_bit(index, ionic->intrs); 198 ionic_intr_init(&ionic->idev, intr, index); 199 200 return 0; 201 } 202 203 static void ionic_intr_free(struct ionic *ionic, int index) 204 { 205 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 206 clear_bit(index, ionic->intrs); 207 } 208 209 static int ionic_qcq_enable(struct ionic_qcq *qcq) 210 { 211 struct ionic_queue *q = &qcq->q; 212 struct ionic_lif *lif = q->lif; 213 struct ionic_dev *idev; 214 struct device *dev; 215 216 struct ionic_admin_ctx ctx = { 217 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 218 .cmd.q_control = { 219 .opcode = IONIC_CMD_Q_CONTROL, 220 .lif_index = cpu_to_le16(lif->index), 221 .type = q->type, 222 .index = cpu_to_le32(q->index), 223 .oper = IONIC_Q_ENABLE, 224 }, 225 }; 226 227 idev = &lif->ionic->idev; 228 dev = lif->ionic->dev; 229 230 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 231 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 232 233 if (qcq->flags & IONIC_QCQ_F_INTR) { 234 irq_set_affinity_hint(qcq->intr.vector, 235 &qcq->intr.affinity_mask); 236 napi_enable(&qcq->napi); 237 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 238 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 239 IONIC_INTR_MASK_CLEAR); 240 } 241 242 return ionic_adminq_post_wait(lif, &ctx); 243 } 244 245 static int ionic_qcq_disable(struct ionic_qcq *qcq) 246 { 247 struct ionic_queue *q = &qcq->q; 248 struct ionic_lif *lif = q->lif; 249 struct ionic_dev *idev; 250 struct device *dev; 251 252 struct ionic_admin_ctx ctx = { 253 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 254 .cmd.q_control = { 255 .opcode = IONIC_CMD_Q_CONTROL, 256 .lif_index = cpu_to_le16(lif->index), 257 .type = q->type, 258 .index = cpu_to_le32(q->index), 259 .oper = IONIC_Q_DISABLE, 260 }, 261 }; 262 263 idev = &lif->ionic->idev; 264 dev = lif->ionic->dev; 265 266 dev_dbg(dev, "q_disable.index %d q_disable.qtype %d\n", 267 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 268 269 if (qcq->flags & IONIC_QCQ_F_INTR) { 270 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 271 IONIC_INTR_MASK_SET); 272 synchronize_irq(qcq->intr.vector); 273 irq_set_affinity_hint(qcq->intr.vector, NULL); 274 napi_disable(&qcq->napi); 275 } 276 277 return ionic_adminq_post_wait(lif, &ctx); 278 } 279 280 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 281 { 282 struct ionic_dev *idev = &lif->ionic->idev; 283 284 if (!qcq) 285 return; 286 287 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 288 return; 289 290 if (qcq->flags & IONIC_QCQ_F_INTR) { 291 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 292 IONIC_INTR_MASK_SET); 293 netif_napi_del(&qcq->napi); 294 } 295 296 qcq->flags &= ~IONIC_QCQ_F_INITED; 297 } 298 299 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 300 { 301 struct device *dev = lif->ionic->dev; 302 303 if (!qcq) 304 return; 305 306 ionic_debugfs_del_qcq(qcq); 307 308 dma_free_coherent(dev, qcq->total_size, qcq->base, qcq->base_pa); 309 qcq->base = NULL; 310 qcq->base_pa = 0; 311 312 if (qcq->flags & IONIC_QCQ_F_INTR) { 313 irq_set_affinity_hint(qcq->intr.vector, NULL); 314 devm_free_irq(dev, qcq->intr.vector, &qcq->napi); 315 qcq->intr.vector = 0; 316 ionic_intr_free(lif->ionic, qcq->intr.index); 317 } 318 319 devm_kfree(dev, qcq->cq.info); 320 qcq->cq.info = NULL; 321 devm_kfree(dev, qcq->q.info); 322 qcq->q.info = NULL; 323 devm_kfree(dev, qcq); 324 } 325 326 static void ionic_qcqs_free(struct ionic_lif *lif) 327 { 328 struct device *dev = lif->ionic->dev; 329 unsigned int i; 330 331 if (lif->notifyqcq) { 332 ionic_qcq_free(lif, lif->notifyqcq); 333 lif->notifyqcq = NULL; 334 } 335 336 if (lif->adminqcq) { 337 ionic_qcq_free(lif, lif->adminqcq); 338 lif->adminqcq = NULL; 339 } 340 341 if (lif->rxqcqs) { 342 for (i = 0; i < lif->nxqs; i++) 343 if (lif->rxqcqs[i].stats) 344 devm_kfree(dev, lif->rxqcqs[i].stats); 345 devm_kfree(dev, lif->rxqcqs); 346 lif->rxqcqs = NULL; 347 } 348 349 if (lif->txqcqs) { 350 for (i = 0; i < lif->nxqs; i++) 351 if (lif->txqcqs[i].stats) 352 devm_kfree(dev, lif->txqcqs[i].stats); 353 devm_kfree(dev, lif->txqcqs); 354 lif->txqcqs = NULL; 355 } 356 } 357 358 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 359 struct ionic_qcq *n_qcq) 360 { 361 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 362 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 363 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 364 } 365 366 n_qcq->intr.vector = src_qcq->intr.vector; 367 n_qcq->intr.index = src_qcq->intr.index; 368 } 369 370 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 371 unsigned int index, 372 const char *name, unsigned int flags, 373 unsigned int num_descs, unsigned int desc_size, 374 unsigned int cq_desc_size, 375 unsigned int sg_desc_size, 376 unsigned int pid, struct ionic_qcq **qcq) 377 { 378 struct ionic_dev *idev = &lif->ionic->idev; 379 u32 q_size, cq_size, sg_size, total_size; 380 struct device *dev = lif->ionic->dev; 381 void *q_base, *cq_base, *sg_base; 382 dma_addr_t cq_base_pa = 0; 383 dma_addr_t sg_base_pa = 0; 384 dma_addr_t q_base_pa = 0; 385 struct ionic_qcq *new; 386 int err; 387 388 *qcq = NULL; 389 390 q_size = num_descs * desc_size; 391 cq_size = num_descs * cq_desc_size; 392 sg_size = num_descs * sg_desc_size; 393 394 total_size = ALIGN(q_size, PAGE_SIZE) + ALIGN(cq_size, PAGE_SIZE); 395 /* Note: aligning q_size/cq_size is not enough due to cq_base 396 * address aligning as q_base could be not aligned to the page. 397 * Adding PAGE_SIZE. 398 */ 399 total_size += PAGE_SIZE; 400 if (flags & IONIC_QCQ_F_SG) { 401 total_size += ALIGN(sg_size, PAGE_SIZE); 402 total_size += PAGE_SIZE; 403 } 404 405 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 406 if (!new) { 407 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 408 err = -ENOMEM; 409 goto err_out; 410 } 411 412 new->flags = flags; 413 414 new->q.info = devm_kzalloc(dev, sizeof(*new->q.info) * num_descs, 415 GFP_KERNEL); 416 if (!new->q.info) { 417 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 418 err = -ENOMEM; 419 goto err_out; 420 } 421 422 new->q.type = type; 423 424 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 425 desc_size, sg_desc_size, pid); 426 if (err) { 427 netdev_err(lif->netdev, "Cannot initialize queue\n"); 428 goto err_out; 429 } 430 431 if (flags & IONIC_QCQ_F_INTR) { 432 err = ionic_intr_alloc(lif, &new->intr); 433 if (err) { 434 netdev_warn(lif->netdev, "no intr for %s: %d\n", 435 name, err); 436 goto err_out; 437 } 438 439 err = ionic_bus_get_irq(lif->ionic, new->intr.index); 440 if (err < 0) { 441 netdev_warn(lif->netdev, "no vector for %s: %d\n", 442 name, err); 443 goto err_out_free_intr; 444 } 445 new->intr.vector = err; 446 ionic_intr_mask_assert(idev->intr_ctrl, new->intr.index, 447 IONIC_INTR_MASK_SET); 448 449 err = ionic_request_irq(lif, new); 450 if (err) { 451 netdev_warn(lif->netdev, "irq request failed %d\n", err); 452 goto err_out_free_intr; 453 } 454 455 new->intr.cpu = cpumask_local_spread(new->intr.index, 456 dev_to_node(dev)); 457 if (new->intr.cpu != -1) 458 cpumask_set_cpu(new->intr.cpu, 459 &new->intr.affinity_mask); 460 } else { 461 new->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 462 } 463 464 new->cq.info = devm_kzalloc(dev, sizeof(*new->cq.info) * num_descs, 465 GFP_KERNEL); 466 if (!new->cq.info) { 467 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 468 err = -ENOMEM; 469 goto err_out_free_irq; 470 } 471 472 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 473 if (err) { 474 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 475 goto err_out_free_irq; 476 } 477 478 new->base = dma_alloc_coherent(dev, total_size, &new->base_pa, 479 GFP_KERNEL); 480 if (!new->base) { 481 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 482 err = -ENOMEM; 483 goto err_out_free_irq; 484 } 485 486 new->total_size = total_size; 487 488 q_base = new->base; 489 q_base_pa = new->base_pa; 490 491 cq_base = (void *)ALIGN((uintptr_t)q_base + q_size, PAGE_SIZE); 492 cq_base_pa = ALIGN(q_base_pa + q_size, PAGE_SIZE); 493 494 if (flags & IONIC_QCQ_F_SG) { 495 sg_base = (void *)ALIGN((uintptr_t)cq_base + cq_size, 496 PAGE_SIZE); 497 sg_base_pa = ALIGN(cq_base_pa + cq_size, PAGE_SIZE); 498 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 499 } 500 501 ionic_q_map(&new->q, q_base, q_base_pa); 502 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 503 ionic_cq_bind(&new->cq, &new->q); 504 505 *qcq = new; 506 507 return 0; 508 509 err_out_free_irq: 510 if (flags & IONIC_QCQ_F_INTR) 511 devm_free_irq(dev, new->intr.vector, &new->napi); 512 err_out_free_intr: 513 if (flags & IONIC_QCQ_F_INTR) 514 ionic_intr_free(lif->ionic, new->intr.index); 515 err_out: 516 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 517 return err; 518 } 519 520 static int ionic_qcqs_alloc(struct ionic_lif *lif) 521 { 522 struct device *dev = lif->ionic->dev; 523 unsigned int q_list_size; 524 unsigned int flags; 525 int err; 526 int i; 527 528 flags = IONIC_QCQ_F_INTR; 529 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 530 IONIC_ADMINQ_LENGTH, 531 sizeof(struct ionic_admin_cmd), 532 sizeof(struct ionic_admin_comp), 533 0, lif->kern_pid, &lif->adminqcq); 534 if (err) 535 return err; 536 ionic_debugfs_add_qcq(lif, lif->adminqcq); 537 538 if (lif->ionic->nnqs_per_lif) { 539 flags = IONIC_QCQ_F_NOTIFYQ; 540 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 541 flags, IONIC_NOTIFYQ_LENGTH, 542 sizeof(struct ionic_notifyq_cmd), 543 sizeof(union ionic_notifyq_comp), 544 0, lif->kern_pid, &lif->notifyqcq); 545 if (err) 546 goto err_out_free_adminqcq; 547 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 548 549 /* Let the notifyq ride on the adminq interrupt */ 550 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 551 } 552 553 q_list_size = sizeof(*lif->txqcqs) * lif->nxqs; 554 err = -ENOMEM; 555 lif->txqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 556 if (!lif->txqcqs) 557 goto err_out_free_notifyqcq; 558 for (i = 0; i < lif->nxqs; i++) { 559 lif->txqcqs[i].stats = devm_kzalloc(dev, 560 sizeof(struct ionic_q_stats), 561 GFP_KERNEL); 562 if (!lif->txqcqs[i].stats) 563 goto err_out_free_tx_stats; 564 } 565 566 lif->rxqcqs = devm_kzalloc(dev, q_list_size, GFP_KERNEL); 567 if (!lif->rxqcqs) 568 goto err_out_free_tx_stats; 569 for (i = 0; i < lif->nxqs; i++) { 570 lif->rxqcqs[i].stats = devm_kzalloc(dev, 571 sizeof(struct ionic_q_stats), 572 GFP_KERNEL); 573 if (!lif->rxqcqs[i].stats) 574 goto err_out_free_rx_stats; 575 } 576 577 return 0; 578 579 err_out_free_rx_stats: 580 for (i = 0; i < lif->nxqs; i++) 581 if (lif->rxqcqs[i].stats) 582 devm_kfree(dev, lif->rxqcqs[i].stats); 583 devm_kfree(dev, lif->rxqcqs); 584 lif->rxqcqs = NULL; 585 err_out_free_tx_stats: 586 for (i = 0; i < lif->nxqs; i++) 587 if (lif->txqcqs[i].stats) 588 devm_kfree(dev, lif->txqcqs[i].stats); 589 devm_kfree(dev, lif->txqcqs); 590 lif->txqcqs = NULL; 591 err_out_free_notifyqcq: 592 if (lif->notifyqcq) { 593 ionic_qcq_free(lif, lif->notifyqcq); 594 lif->notifyqcq = NULL; 595 } 596 err_out_free_adminqcq: 597 ionic_qcq_free(lif, lif->adminqcq); 598 lif->adminqcq = NULL; 599 600 return err; 601 } 602 603 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 604 { 605 struct device *dev = lif->ionic->dev; 606 struct ionic_queue *q = &qcq->q; 607 struct ionic_cq *cq = &qcq->cq; 608 struct ionic_admin_ctx ctx = { 609 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 610 .cmd.q_init = { 611 .opcode = IONIC_CMD_Q_INIT, 612 .lif_index = cpu_to_le16(lif->index), 613 .type = q->type, 614 .ver = lif->qtype_info[q->type].version, 615 .index = cpu_to_le32(q->index), 616 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 617 IONIC_QINIT_F_SG), 618 .intr_index = cpu_to_le16(lif->rxqcqs[q->index].qcq->intr.index), 619 .pid = cpu_to_le16(q->pid), 620 .ring_size = ilog2(q->num_descs), 621 .ring_base = cpu_to_le64(q->base_pa), 622 .cq_ring_base = cpu_to_le64(cq->base_pa), 623 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 624 }, 625 }; 626 int err; 627 628 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 629 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 630 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 631 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 632 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 633 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 634 635 q->tail = q->info; 636 q->head = q->tail; 637 cq->tail = cq->info; 638 639 err = ionic_adminq_post_wait(lif, &ctx); 640 if (err) 641 return err; 642 643 q->hw_type = ctx.comp.q_init.hw_type; 644 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 645 q->dbval = IONIC_DBELL_QID(q->hw_index); 646 647 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 648 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 649 650 qcq->flags |= IONIC_QCQ_F_INITED; 651 652 return 0; 653 } 654 655 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 656 { 657 struct device *dev = lif->ionic->dev; 658 struct ionic_queue *q = &qcq->q; 659 struct ionic_cq *cq = &qcq->cq; 660 struct ionic_admin_ctx ctx = { 661 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 662 .cmd.q_init = { 663 .opcode = IONIC_CMD_Q_INIT, 664 .lif_index = cpu_to_le16(lif->index), 665 .type = q->type, 666 .ver = lif->qtype_info[q->type].version, 667 .index = cpu_to_le32(q->index), 668 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 669 IONIC_QINIT_F_SG), 670 .intr_index = cpu_to_le16(cq->bound_intr->index), 671 .pid = cpu_to_le16(q->pid), 672 .ring_size = ilog2(q->num_descs), 673 .ring_base = cpu_to_le64(q->base_pa), 674 .cq_ring_base = cpu_to_le64(cq->base_pa), 675 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 676 }, 677 }; 678 int err; 679 680 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 681 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 682 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 683 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 684 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 685 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 686 687 q->tail = q->info; 688 q->head = q->tail; 689 cq->tail = cq->info; 690 691 err = ionic_adminq_post_wait(lif, &ctx); 692 if (err) 693 return err; 694 695 q->hw_type = ctx.comp.q_init.hw_type; 696 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 697 q->dbval = IONIC_DBELL_QID(q->hw_index); 698 699 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 700 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 701 702 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 703 NAPI_POLL_WEIGHT); 704 705 qcq->flags |= IONIC_QCQ_F_INITED; 706 707 return 0; 708 } 709 710 static bool ionic_notifyq_service(struct ionic_cq *cq, 711 struct ionic_cq_info *cq_info) 712 { 713 union ionic_notifyq_comp *comp = cq_info->cq_desc; 714 struct ionic_deferred_work *work; 715 struct net_device *netdev; 716 struct ionic_queue *q; 717 struct ionic_lif *lif; 718 u64 eid; 719 720 q = cq->bound_q; 721 lif = q->info[0].cb_arg; 722 netdev = lif->netdev; 723 eid = le64_to_cpu(comp->event.eid); 724 725 /* Have we run out of new completions to process? */ 726 if (eid <= lif->last_eid) 727 return false; 728 729 lif->last_eid = eid; 730 731 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 732 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 733 comp, sizeof(*comp), true); 734 735 switch (le16_to_cpu(comp->event.ecode)) { 736 case IONIC_EVENT_LINK_CHANGE: 737 ionic_link_status_check_request(lif); 738 break; 739 case IONIC_EVENT_RESET: 740 work = kzalloc(sizeof(*work), GFP_ATOMIC); 741 if (!work) { 742 netdev_err(lif->netdev, "%s OOM\n", __func__); 743 } else { 744 work->type = IONIC_DW_TYPE_LIF_RESET; 745 ionic_lif_deferred_enqueue(&lif->deferred, work); 746 } 747 break; 748 default: 749 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 750 comp->event.ecode, eid); 751 break; 752 } 753 754 return true; 755 } 756 757 static int ionic_notifyq_clean(struct ionic_lif *lif, int budget) 758 { 759 struct ionic_dev *idev = &lif->ionic->idev; 760 struct ionic_cq *cq = &lif->notifyqcq->cq; 761 u32 work_done; 762 763 work_done = ionic_cq_service(cq, budget, ionic_notifyq_service, 764 NULL, NULL); 765 if (work_done) 766 ionic_intr_credits(idev->intr_ctrl, cq->bound_intr->index, 767 work_done, IONIC_INTR_CRED_RESET_COALESCE); 768 769 return work_done; 770 } 771 772 static bool ionic_adminq_service(struct ionic_cq *cq, 773 struct ionic_cq_info *cq_info) 774 { 775 struct ionic_admin_comp *comp = cq_info->cq_desc; 776 777 if (!color_match(comp->color, cq->done_color)) 778 return false; 779 780 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 781 782 return true; 783 } 784 785 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 786 { 787 struct ionic_lif *lif = napi_to_cq(napi)->lif; 788 int n_work = 0; 789 int a_work = 0; 790 791 if (likely(lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)) 792 n_work = ionic_notifyq_clean(lif, budget); 793 a_work = ionic_napi(napi, budget, ionic_adminq_service, NULL, NULL); 794 795 return max(n_work, a_work); 796 } 797 798 void ionic_get_stats64(struct net_device *netdev, 799 struct rtnl_link_stats64 *ns) 800 { 801 struct ionic_lif *lif = netdev_priv(netdev); 802 struct ionic_lif_stats *ls; 803 804 memset(ns, 0, sizeof(*ns)); 805 ls = &lif->info->stats; 806 807 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 808 le64_to_cpu(ls->rx_mcast_packets) + 809 le64_to_cpu(ls->rx_bcast_packets); 810 811 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 812 le64_to_cpu(ls->tx_mcast_packets) + 813 le64_to_cpu(ls->tx_bcast_packets); 814 815 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 816 le64_to_cpu(ls->rx_mcast_bytes) + 817 le64_to_cpu(ls->rx_bcast_bytes); 818 819 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 820 le64_to_cpu(ls->tx_mcast_bytes) + 821 le64_to_cpu(ls->tx_bcast_bytes); 822 823 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 824 le64_to_cpu(ls->rx_mcast_drop_packets) + 825 le64_to_cpu(ls->rx_bcast_drop_packets); 826 827 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 828 le64_to_cpu(ls->tx_mcast_drop_packets) + 829 le64_to_cpu(ls->tx_bcast_drop_packets); 830 831 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 832 833 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 834 835 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 836 le64_to_cpu(ls->rx_queue_disabled) + 837 le64_to_cpu(ls->rx_desc_fetch_error) + 838 le64_to_cpu(ls->rx_desc_data_error); 839 840 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 841 le64_to_cpu(ls->tx_queue_disabled) + 842 le64_to_cpu(ls->tx_desc_fetch_error) + 843 le64_to_cpu(ls->tx_desc_data_error); 844 845 ns->rx_errors = ns->rx_over_errors + 846 ns->rx_missed_errors; 847 848 ns->tx_errors = ns->tx_aborted_errors; 849 } 850 851 static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 852 { 853 struct ionic_admin_ctx ctx = { 854 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 855 .cmd.rx_filter_add = { 856 .opcode = IONIC_CMD_RX_FILTER_ADD, 857 .lif_index = cpu_to_le16(lif->index), 858 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 859 }, 860 }; 861 struct ionic_rx_filter *f; 862 int err; 863 864 /* don't bother if we already have it */ 865 spin_lock_bh(&lif->rx_filters.lock); 866 f = ionic_rx_filter_by_addr(lif, addr); 867 spin_unlock_bh(&lif->rx_filters.lock); 868 if (f) 869 return 0; 870 871 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 872 873 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 874 err = ionic_adminq_post_wait(lif, &ctx); 875 if (err && err != -EEXIST) 876 return err; 877 878 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 879 } 880 881 static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 882 { 883 struct ionic_admin_ctx ctx = { 884 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 885 .cmd.rx_filter_del = { 886 .opcode = IONIC_CMD_RX_FILTER_DEL, 887 .lif_index = cpu_to_le16(lif->index), 888 }, 889 }; 890 struct ionic_rx_filter *f; 891 int err; 892 893 spin_lock_bh(&lif->rx_filters.lock); 894 f = ionic_rx_filter_by_addr(lif, addr); 895 if (!f) { 896 spin_unlock_bh(&lif->rx_filters.lock); 897 return -ENOENT; 898 } 899 900 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 901 addr, f->filter_id); 902 903 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 904 ionic_rx_filter_free(lif, f); 905 spin_unlock_bh(&lif->rx_filters.lock); 906 907 err = ionic_adminq_post_wait(lif, &ctx); 908 if (err && err != -EEXIST) 909 return err; 910 911 return 0; 912 } 913 914 static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add) 915 { 916 struct ionic *ionic = lif->ionic; 917 struct ionic_deferred_work *work; 918 unsigned int nmfilters; 919 unsigned int nufilters; 920 921 if (add) { 922 /* Do we have space for this filter? We test the counters 923 * here before checking the need for deferral so that we 924 * can return an overflow error to the stack. 925 */ 926 nmfilters = le32_to_cpu(ionic->ident.lif.eth.max_mcast_filters); 927 nufilters = le32_to_cpu(ionic->ident.lif.eth.max_ucast_filters); 928 929 if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters)) 930 lif->nmcast++; 931 else if (!is_multicast_ether_addr(addr) && 932 lif->nucast < nufilters) 933 lif->nucast++; 934 else 935 return -ENOSPC; 936 } else { 937 if (is_multicast_ether_addr(addr) && lif->nmcast) 938 lif->nmcast--; 939 else if (!is_multicast_ether_addr(addr) && lif->nucast) 940 lif->nucast--; 941 } 942 943 if (in_interrupt()) { 944 work = kzalloc(sizeof(*work), GFP_ATOMIC); 945 if (!work) { 946 netdev_err(lif->netdev, "%s OOM\n", __func__); 947 return -ENOMEM; 948 } 949 work->type = add ? IONIC_DW_TYPE_RX_ADDR_ADD : 950 IONIC_DW_TYPE_RX_ADDR_DEL; 951 memcpy(work->addr, addr, ETH_ALEN); 952 netdev_dbg(lif->netdev, "deferred: rx_filter %s %pM\n", 953 add ? "add" : "del", addr); 954 ionic_lif_deferred_enqueue(&lif->deferred, work); 955 } else { 956 netdev_dbg(lif->netdev, "rx_filter %s %pM\n", 957 add ? "add" : "del", addr); 958 if (add) 959 return ionic_lif_addr_add(lif, addr); 960 else 961 return ionic_lif_addr_del(lif, addr); 962 } 963 964 return 0; 965 } 966 967 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 968 { 969 return ionic_lif_addr(netdev_priv(netdev), addr, true); 970 } 971 972 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 973 { 974 return ionic_lif_addr(netdev_priv(netdev), addr, false); 975 } 976 977 static void ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 978 { 979 struct ionic_admin_ctx ctx = { 980 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 981 .cmd.rx_mode_set = { 982 .opcode = IONIC_CMD_RX_MODE_SET, 983 .lif_index = cpu_to_le16(lif->index), 984 .rx_mode = cpu_to_le16(rx_mode), 985 }, 986 }; 987 char buf[128]; 988 int err; 989 int i; 990 #define REMAIN(__x) (sizeof(buf) - (__x)) 991 992 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 993 lif->rx_mode, rx_mode); 994 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 995 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 996 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 997 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 998 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 999 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1000 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1001 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1002 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1003 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1004 netdev_dbg(lif->netdev, "lif%d %s\n", lif->index, buf); 1005 1006 err = ionic_adminq_post_wait(lif, &ctx); 1007 if (err) 1008 netdev_warn(lif->netdev, "set rx_mode 0x%04x failed: %d\n", 1009 rx_mode, err); 1010 else 1011 lif->rx_mode = rx_mode; 1012 } 1013 1014 static void _ionic_lif_rx_mode(struct ionic_lif *lif, unsigned int rx_mode) 1015 { 1016 struct ionic_deferred_work *work; 1017 1018 if (in_interrupt()) { 1019 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1020 if (!work) { 1021 netdev_err(lif->netdev, "%s OOM\n", __func__); 1022 return; 1023 } 1024 work->type = IONIC_DW_TYPE_RX_MODE; 1025 work->rx_mode = rx_mode; 1026 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1027 ionic_lif_deferred_enqueue(&lif->deferred, work); 1028 } else { 1029 ionic_lif_rx_mode(lif, rx_mode); 1030 } 1031 } 1032 1033 static void ionic_set_rx_mode(struct net_device *netdev) 1034 { 1035 struct ionic_lif *lif = netdev_priv(netdev); 1036 struct ionic_identity *ident; 1037 unsigned int nfilters; 1038 unsigned int rx_mode; 1039 1040 ident = &lif->ionic->ident; 1041 1042 rx_mode = IONIC_RX_MODE_F_UNICAST; 1043 rx_mode |= (netdev->flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1044 rx_mode |= (netdev->flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1045 rx_mode |= (netdev->flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1046 rx_mode |= (netdev->flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1047 1048 /* sync unicast addresses 1049 * next check to see if we're in an overflow state 1050 * if so, we track that we overflowed and enable NIC PROMISC 1051 * else if the overflow is set and not needed 1052 * we remove our overflow flag and check the netdev flags 1053 * to see if we can disable NIC PROMISC 1054 */ 1055 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1056 nfilters = le32_to_cpu(ident->lif.eth.max_ucast_filters); 1057 if (netdev_uc_count(netdev) + 1 > nfilters) { 1058 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1059 lif->uc_overflow = true; 1060 } else if (lif->uc_overflow) { 1061 lif->uc_overflow = false; 1062 if (!(netdev->flags & IFF_PROMISC)) 1063 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1064 } 1065 1066 /* same for multicast */ 1067 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1068 nfilters = le32_to_cpu(ident->lif.eth.max_mcast_filters); 1069 if (netdev_mc_count(netdev) > nfilters) { 1070 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1071 lif->mc_overflow = true; 1072 } else if (lif->mc_overflow) { 1073 lif->mc_overflow = false; 1074 if (!(netdev->flags & IFF_ALLMULTI)) 1075 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1076 } 1077 1078 if (lif->rx_mode != rx_mode) 1079 _ionic_lif_rx_mode(lif, rx_mode); 1080 } 1081 1082 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1083 { 1084 u64 wanted = 0; 1085 1086 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1087 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1088 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1089 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1090 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1091 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1092 if (features & NETIF_F_RXHASH) 1093 wanted |= IONIC_ETH_HW_RX_HASH; 1094 if (features & NETIF_F_RXCSUM) 1095 wanted |= IONIC_ETH_HW_RX_CSUM; 1096 if (features & NETIF_F_SG) 1097 wanted |= IONIC_ETH_HW_TX_SG; 1098 if (features & NETIF_F_HW_CSUM) 1099 wanted |= IONIC_ETH_HW_TX_CSUM; 1100 if (features & NETIF_F_TSO) 1101 wanted |= IONIC_ETH_HW_TSO; 1102 if (features & NETIF_F_TSO6) 1103 wanted |= IONIC_ETH_HW_TSO_IPV6; 1104 if (features & NETIF_F_TSO_ECN) 1105 wanted |= IONIC_ETH_HW_TSO_ECN; 1106 if (features & NETIF_F_GSO_GRE) 1107 wanted |= IONIC_ETH_HW_TSO_GRE; 1108 if (features & NETIF_F_GSO_GRE_CSUM) 1109 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1110 if (features & NETIF_F_GSO_IPXIP4) 1111 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1112 if (features & NETIF_F_GSO_IPXIP6) 1113 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1114 if (features & NETIF_F_GSO_UDP_TUNNEL) 1115 wanted |= IONIC_ETH_HW_TSO_UDP; 1116 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1117 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1118 1119 return cpu_to_le64(wanted); 1120 } 1121 1122 static int ionic_set_nic_features(struct ionic_lif *lif, 1123 netdev_features_t features) 1124 { 1125 struct device *dev = lif->ionic->dev; 1126 struct ionic_admin_ctx ctx = { 1127 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1128 .cmd.lif_setattr = { 1129 .opcode = IONIC_CMD_LIF_SETATTR, 1130 .index = cpu_to_le16(lif->index), 1131 .attr = IONIC_LIF_ATTR_FEATURES, 1132 }, 1133 }; 1134 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1135 IONIC_ETH_HW_VLAN_RX_STRIP | 1136 IONIC_ETH_HW_VLAN_RX_FILTER; 1137 u64 old_hw_features; 1138 int err; 1139 1140 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1141 err = ionic_adminq_post_wait(lif, &ctx); 1142 if (err) 1143 return err; 1144 1145 old_hw_features = lif->hw_features; 1146 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1147 ctx.comp.lif_setattr.features); 1148 1149 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1150 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1151 1152 if ((vlan_flags & features) && 1153 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1154 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1155 1156 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1157 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1158 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1159 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1160 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1161 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1162 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1163 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1164 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1165 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1166 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1167 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1168 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1169 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1170 if (lif->hw_features & IONIC_ETH_HW_TSO) 1171 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1172 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1173 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1174 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1175 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1176 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1177 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1178 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1179 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1180 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1181 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1182 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1183 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1184 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1185 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1186 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1187 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1188 1189 return 0; 1190 } 1191 1192 static int ionic_init_nic_features(struct ionic_lif *lif) 1193 { 1194 struct net_device *netdev = lif->netdev; 1195 netdev_features_t features; 1196 int err; 1197 1198 /* set up what we expect to support by default */ 1199 features = NETIF_F_HW_VLAN_CTAG_TX | 1200 NETIF_F_HW_VLAN_CTAG_RX | 1201 NETIF_F_HW_VLAN_CTAG_FILTER | 1202 NETIF_F_RXHASH | 1203 NETIF_F_SG | 1204 NETIF_F_HW_CSUM | 1205 NETIF_F_RXCSUM | 1206 NETIF_F_TSO | 1207 NETIF_F_TSO6 | 1208 NETIF_F_TSO_ECN; 1209 1210 err = ionic_set_nic_features(lif, features); 1211 if (err) 1212 return err; 1213 1214 /* tell the netdev what we actually can support */ 1215 netdev->features |= NETIF_F_HIGHDMA; 1216 1217 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1218 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1219 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1220 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1221 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1222 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1223 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1224 netdev->hw_features |= NETIF_F_RXHASH; 1225 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1226 netdev->hw_features |= NETIF_F_SG; 1227 1228 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1229 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1230 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1231 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1232 if (lif->hw_features & IONIC_ETH_HW_TSO) 1233 netdev->hw_enc_features |= NETIF_F_TSO; 1234 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1235 netdev->hw_enc_features |= NETIF_F_TSO6; 1236 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1237 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1238 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1239 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1240 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1241 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1242 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1243 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1244 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1245 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1246 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1247 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1248 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1249 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1250 1251 netdev->hw_features |= netdev->hw_enc_features; 1252 netdev->features |= netdev->hw_features; 1253 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1254 1255 netdev->priv_flags |= IFF_UNICAST_FLT | 1256 IFF_LIVE_ADDR_CHANGE; 1257 1258 return 0; 1259 } 1260 1261 static int ionic_set_features(struct net_device *netdev, 1262 netdev_features_t features) 1263 { 1264 struct ionic_lif *lif = netdev_priv(netdev); 1265 int err; 1266 1267 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1268 __func__, (u64)lif->netdev->features, (u64)features); 1269 1270 err = ionic_set_nic_features(lif, features); 1271 1272 return err; 1273 } 1274 1275 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1276 { 1277 struct sockaddr *addr = sa; 1278 u8 *mac; 1279 int err; 1280 1281 mac = (u8 *)addr->sa_data; 1282 if (ether_addr_equal(netdev->dev_addr, mac)) 1283 return 0; 1284 1285 err = eth_prepare_mac_addr_change(netdev, addr); 1286 if (err) 1287 return err; 1288 1289 if (!is_zero_ether_addr(netdev->dev_addr)) { 1290 netdev_info(netdev, "deleting mac addr %pM\n", 1291 netdev->dev_addr); 1292 ionic_addr_del(netdev, netdev->dev_addr); 1293 } 1294 1295 eth_commit_mac_addr_change(netdev, addr); 1296 netdev_info(netdev, "updating mac addr %pM\n", mac); 1297 1298 return ionic_addr_add(netdev, mac); 1299 } 1300 1301 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1302 { 1303 struct ionic_lif *lif = netdev_priv(netdev); 1304 struct ionic_admin_ctx ctx = { 1305 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1306 .cmd.lif_setattr = { 1307 .opcode = IONIC_CMD_LIF_SETATTR, 1308 .index = cpu_to_le16(lif->index), 1309 .attr = IONIC_LIF_ATTR_MTU, 1310 .mtu = cpu_to_le32(new_mtu), 1311 }, 1312 }; 1313 int err; 1314 1315 err = ionic_adminq_post_wait(lif, &ctx); 1316 if (err) 1317 return err; 1318 1319 netdev->mtu = new_mtu; 1320 err = ionic_reset_queues(lif, NULL, NULL); 1321 1322 return err; 1323 } 1324 1325 static void ionic_tx_timeout_work(struct work_struct *ws) 1326 { 1327 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1328 1329 netdev_info(lif->netdev, "Tx Timeout recovery\n"); 1330 1331 rtnl_lock(); 1332 ionic_reset_queues(lif, NULL, NULL); 1333 rtnl_unlock(); 1334 } 1335 1336 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1337 { 1338 struct ionic_lif *lif = netdev_priv(netdev); 1339 1340 schedule_work(&lif->tx_timeout_work); 1341 } 1342 1343 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1344 u16 vid) 1345 { 1346 struct ionic_lif *lif = netdev_priv(netdev); 1347 struct ionic_admin_ctx ctx = { 1348 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1349 .cmd.rx_filter_add = { 1350 .opcode = IONIC_CMD_RX_FILTER_ADD, 1351 .lif_index = cpu_to_le16(lif->index), 1352 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1353 .vlan.vlan = cpu_to_le16(vid), 1354 }, 1355 }; 1356 int err; 1357 1358 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1359 err = ionic_adminq_post_wait(lif, &ctx); 1360 if (err) 1361 return err; 1362 1363 return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx); 1364 } 1365 1366 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1367 u16 vid) 1368 { 1369 struct ionic_lif *lif = netdev_priv(netdev); 1370 struct ionic_admin_ctx ctx = { 1371 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1372 .cmd.rx_filter_del = { 1373 .opcode = IONIC_CMD_RX_FILTER_DEL, 1374 .lif_index = cpu_to_le16(lif->index), 1375 }, 1376 }; 1377 struct ionic_rx_filter *f; 1378 1379 spin_lock_bh(&lif->rx_filters.lock); 1380 1381 f = ionic_rx_filter_by_vlan(lif, vid); 1382 if (!f) { 1383 spin_unlock_bh(&lif->rx_filters.lock); 1384 return -ENOENT; 1385 } 1386 1387 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1388 vid, f->filter_id); 1389 1390 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1391 ionic_rx_filter_free(lif, f); 1392 spin_unlock_bh(&lif->rx_filters.lock); 1393 1394 return ionic_adminq_post_wait(lif, &ctx); 1395 } 1396 1397 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1398 const u8 *key, const u32 *indir) 1399 { 1400 struct ionic_admin_ctx ctx = { 1401 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1402 .cmd.lif_setattr = { 1403 .opcode = IONIC_CMD_LIF_SETATTR, 1404 .attr = IONIC_LIF_ATTR_RSS, 1405 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1406 }, 1407 }; 1408 unsigned int i, tbl_sz; 1409 1410 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1411 lif->rss_types = types; 1412 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1413 } 1414 1415 if (key) 1416 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1417 1418 if (indir) { 1419 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1420 for (i = 0; i < tbl_sz; i++) 1421 lif->rss_ind_tbl[i] = indir[i]; 1422 } 1423 1424 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1425 IONIC_RSS_HASH_KEY_SIZE); 1426 1427 return ionic_adminq_post_wait(lif, &ctx); 1428 } 1429 1430 static int ionic_lif_rss_init(struct ionic_lif *lif) 1431 { 1432 unsigned int tbl_sz; 1433 unsigned int i; 1434 1435 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1436 IONIC_RSS_TYPE_IPV4_TCP | 1437 IONIC_RSS_TYPE_IPV4_UDP | 1438 IONIC_RSS_TYPE_IPV6 | 1439 IONIC_RSS_TYPE_IPV6_TCP | 1440 IONIC_RSS_TYPE_IPV6_UDP; 1441 1442 /* Fill indirection table with 'default' values */ 1443 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1444 for (i = 0; i < tbl_sz; i++) 1445 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1446 1447 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1448 } 1449 1450 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1451 { 1452 int tbl_sz; 1453 1454 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1455 memset(lif->rss_ind_tbl, 0, tbl_sz); 1456 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1457 1458 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1459 } 1460 1461 static void ionic_txrx_disable(struct ionic_lif *lif) 1462 { 1463 unsigned int i; 1464 int err; 1465 1466 if (lif->txqcqs) { 1467 for (i = 0; i < lif->nxqs; i++) { 1468 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1469 if (err == -ETIMEDOUT) 1470 break; 1471 } 1472 } 1473 1474 if (lif->rxqcqs) { 1475 for (i = 0; i < lif->nxqs; i++) { 1476 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1477 if (err == -ETIMEDOUT) 1478 break; 1479 } 1480 } 1481 } 1482 1483 static void ionic_txrx_deinit(struct ionic_lif *lif) 1484 { 1485 unsigned int i; 1486 1487 if (lif->txqcqs) { 1488 for (i = 0; i < lif->nxqs; i++) { 1489 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1490 ionic_tx_flush(&lif->txqcqs[i].qcq->cq); 1491 ionic_tx_empty(&lif->txqcqs[i].qcq->q); 1492 } 1493 } 1494 1495 if (lif->rxqcqs) { 1496 for (i = 0; i < lif->nxqs; i++) { 1497 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1498 ionic_rx_flush(&lif->rxqcqs[i].qcq->cq); 1499 ionic_rx_empty(&lif->rxqcqs[i].qcq->q); 1500 } 1501 } 1502 lif->rx_mode = 0; 1503 } 1504 1505 static void ionic_txrx_free(struct ionic_lif *lif) 1506 { 1507 unsigned int i; 1508 1509 if (lif->txqcqs) { 1510 for (i = 0; i < lif->nxqs; i++) { 1511 ionic_qcq_free(lif, lif->txqcqs[i].qcq); 1512 lif->txqcqs[i].qcq = NULL; 1513 } 1514 } 1515 1516 if (lif->rxqcqs) { 1517 for (i = 0; i < lif->nxqs; i++) { 1518 ionic_qcq_free(lif, lif->rxqcqs[i].qcq); 1519 lif->rxqcqs[i].qcq = NULL; 1520 } 1521 } 1522 } 1523 1524 static int ionic_txrx_alloc(struct ionic_lif *lif) 1525 { 1526 unsigned int sg_desc_sz; 1527 unsigned int flags; 1528 unsigned int i; 1529 int err = 0; 1530 1531 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 1532 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 1533 sizeof(struct ionic_txq_sg_desc_v1)) 1534 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 1535 else 1536 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 1537 1538 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 1539 for (i = 0; i < lif->nxqs; i++) { 1540 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 1541 lif->ntxq_descs, 1542 sizeof(struct ionic_txq_desc), 1543 sizeof(struct ionic_txq_comp), 1544 sg_desc_sz, 1545 lif->kern_pid, &lif->txqcqs[i].qcq); 1546 if (err) 1547 goto err_out; 1548 1549 lif->txqcqs[i].qcq->stats = lif->txqcqs[i].stats; 1550 ionic_debugfs_add_qcq(lif, lif->txqcqs[i].qcq); 1551 } 1552 1553 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 1554 for (i = 0; i < lif->nxqs; i++) { 1555 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 1556 lif->nrxq_descs, 1557 sizeof(struct ionic_rxq_desc), 1558 sizeof(struct ionic_rxq_comp), 1559 sizeof(struct ionic_rxq_sg_desc), 1560 lif->kern_pid, &lif->rxqcqs[i].qcq); 1561 if (err) 1562 goto err_out; 1563 1564 lif->rxqcqs[i].qcq->stats = lif->rxqcqs[i].stats; 1565 1566 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 1567 lif->rxqcqs[i].qcq->intr.index, 1568 lif->rx_coalesce_hw); 1569 ionic_link_qcq_interrupts(lif->rxqcqs[i].qcq, 1570 lif->txqcqs[i].qcq); 1571 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i].qcq); 1572 } 1573 1574 return 0; 1575 1576 err_out: 1577 ionic_txrx_free(lif); 1578 1579 return err; 1580 } 1581 1582 static int ionic_txrx_init(struct ionic_lif *lif) 1583 { 1584 unsigned int i; 1585 int err; 1586 1587 for (i = 0; i < lif->nxqs; i++) { 1588 err = ionic_lif_txq_init(lif, lif->txqcqs[i].qcq); 1589 if (err) 1590 goto err_out; 1591 1592 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i].qcq); 1593 if (err) { 1594 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1595 goto err_out; 1596 } 1597 } 1598 1599 if (lif->netdev->features & NETIF_F_RXHASH) 1600 ionic_lif_rss_init(lif); 1601 1602 ionic_set_rx_mode(lif->netdev); 1603 1604 return 0; 1605 1606 err_out: 1607 while (i--) { 1608 ionic_lif_qcq_deinit(lif, lif->txqcqs[i].qcq); 1609 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i].qcq); 1610 } 1611 1612 return err; 1613 } 1614 1615 static int ionic_txrx_enable(struct ionic_lif *lif) 1616 { 1617 int i, err; 1618 1619 for (i = 0; i < lif->nxqs; i++) { 1620 ionic_rx_fill(&lif->rxqcqs[i].qcq->q); 1621 err = ionic_qcq_enable(lif->rxqcqs[i].qcq); 1622 if (err) 1623 goto err_out; 1624 1625 err = ionic_qcq_enable(lif->txqcqs[i].qcq); 1626 if (err) { 1627 if (err != -ETIMEDOUT) 1628 ionic_qcq_disable(lif->rxqcqs[i].qcq); 1629 goto err_out; 1630 } 1631 } 1632 1633 return 0; 1634 1635 err_out: 1636 while (i--) { 1637 err = ionic_qcq_disable(lif->txqcqs[i].qcq); 1638 if (err == -ETIMEDOUT) 1639 break; 1640 err = ionic_qcq_disable(lif->rxqcqs[i].qcq); 1641 if (err == -ETIMEDOUT) 1642 break; 1643 } 1644 1645 return err; 1646 } 1647 1648 static int ionic_start_queues(struct ionic_lif *lif) 1649 { 1650 int err; 1651 1652 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 1653 return 0; 1654 1655 err = ionic_txrx_enable(lif); 1656 if (err) { 1657 clear_bit(IONIC_LIF_F_UP, lif->state); 1658 return err; 1659 } 1660 netif_tx_wake_all_queues(lif->netdev); 1661 1662 return 0; 1663 } 1664 1665 int ionic_open(struct net_device *netdev) 1666 { 1667 struct ionic_lif *lif = netdev_priv(netdev); 1668 int err; 1669 1670 err = ionic_txrx_alloc(lif); 1671 if (err) 1672 return err; 1673 1674 err = ionic_txrx_init(lif); 1675 if (err) 1676 goto err_out; 1677 1678 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 1679 if (err) 1680 goto err_txrx_deinit; 1681 1682 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 1683 if (err) 1684 goto err_txrx_deinit; 1685 1686 /* don't start the queues until we have link */ 1687 if (netif_carrier_ok(netdev)) { 1688 err = ionic_start_queues(lif); 1689 if (err) 1690 goto err_txrx_deinit; 1691 } 1692 1693 return 0; 1694 1695 err_txrx_deinit: 1696 ionic_txrx_deinit(lif); 1697 err_out: 1698 ionic_txrx_free(lif); 1699 return err; 1700 } 1701 1702 static void ionic_stop_queues(struct ionic_lif *lif) 1703 { 1704 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 1705 return; 1706 1707 netif_tx_disable(lif->netdev); 1708 ionic_txrx_disable(lif); 1709 } 1710 1711 int ionic_stop(struct net_device *netdev) 1712 { 1713 struct ionic_lif *lif = netdev_priv(netdev); 1714 1715 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1716 return 0; 1717 1718 ionic_stop_queues(lif); 1719 ionic_txrx_deinit(lif); 1720 ionic_txrx_free(lif); 1721 1722 return 0; 1723 } 1724 1725 static int ionic_get_vf_config(struct net_device *netdev, 1726 int vf, struct ifla_vf_info *ivf) 1727 { 1728 struct ionic_lif *lif = netdev_priv(netdev); 1729 struct ionic *ionic = lif->ionic; 1730 int ret = 0; 1731 1732 if (!netif_device_present(netdev)) 1733 return -EBUSY; 1734 1735 down_read(&ionic->vf_op_lock); 1736 1737 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1738 ret = -EINVAL; 1739 } else { 1740 ivf->vf = vf; 1741 ivf->vlan = ionic->vfs[vf].vlanid; 1742 ivf->qos = 0; 1743 ivf->spoofchk = ionic->vfs[vf].spoofchk; 1744 ivf->linkstate = ionic->vfs[vf].linkstate; 1745 ivf->max_tx_rate = ionic->vfs[vf].maxrate; 1746 ivf->trusted = ionic->vfs[vf].trusted; 1747 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 1748 } 1749 1750 up_read(&ionic->vf_op_lock); 1751 return ret; 1752 } 1753 1754 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 1755 struct ifla_vf_stats *vf_stats) 1756 { 1757 struct ionic_lif *lif = netdev_priv(netdev); 1758 struct ionic *ionic = lif->ionic; 1759 struct ionic_lif_stats *vs; 1760 int ret = 0; 1761 1762 if (!netif_device_present(netdev)) 1763 return -EBUSY; 1764 1765 down_read(&ionic->vf_op_lock); 1766 1767 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1768 ret = -EINVAL; 1769 } else { 1770 memset(vf_stats, 0, sizeof(*vf_stats)); 1771 vs = &ionic->vfs[vf].stats; 1772 1773 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 1774 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 1775 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 1776 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 1777 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 1778 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 1779 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 1780 le64_to_cpu(vs->rx_mcast_drop_packets) + 1781 le64_to_cpu(vs->rx_bcast_drop_packets); 1782 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 1783 le64_to_cpu(vs->tx_mcast_drop_packets) + 1784 le64_to_cpu(vs->tx_bcast_drop_packets); 1785 } 1786 1787 up_read(&ionic->vf_op_lock); 1788 return ret; 1789 } 1790 1791 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 1792 { 1793 struct ionic_lif *lif = netdev_priv(netdev); 1794 struct ionic *ionic = lif->ionic; 1795 int ret; 1796 1797 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 1798 return -EINVAL; 1799 1800 if (!netif_device_present(netdev)) 1801 return -EBUSY; 1802 1803 down_write(&ionic->vf_op_lock); 1804 1805 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1806 ret = -EINVAL; 1807 } else { 1808 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 1809 if (!ret) 1810 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 1811 } 1812 1813 up_write(&ionic->vf_op_lock); 1814 return ret; 1815 } 1816 1817 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 1818 u8 qos, __be16 proto) 1819 { 1820 struct ionic_lif *lif = netdev_priv(netdev); 1821 struct ionic *ionic = lif->ionic; 1822 int ret; 1823 1824 /* until someday when we support qos */ 1825 if (qos) 1826 return -EINVAL; 1827 1828 if (vlan > 4095) 1829 return -EINVAL; 1830 1831 if (proto != htons(ETH_P_8021Q)) 1832 return -EPROTONOSUPPORT; 1833 1834 if (!netif_device_present(netdev)) 1835 return -EBUSY; 1836 1837 down_write(&ionic->vf_op_lock); 1838 1839 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1840 ret = -EINVAL; 1841 } else { 1842 ret = ionic_set_vf_config(ionic, vf, 1843 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 1844 if (!ret) 1845 ionic->vfs[vf].vlanid = vlan; 1846 } 1847 1848 up_write(&ionic->vf_op_lock); 1849 return ret; 1850 } 1851 1852 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 1853 int tx_min, int tx_max) 1854 { 1855 struct ionic_lif *lif = netdev_priv(netdev); 1856 struct ionic *ionic = lif->ionic; 1857 int ret; 1858 1859 /* setting the min just seems silly */ 1860 if (tx_min) 1861 return -EINVAL; 1862 1863 if (!netif_device_present(netdev)) 1864 return -EBUSY; 1865 1866 down_write(&ionic->vf_op_lock); 1867 1868 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1869 ret = -EINVAL; 1870 } else { 1871 ret = ionic_set_vf_config(ionic, vf, 1872 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 1873 if (!ret) 1874 lif->ionic->vfs[vf].maxrate = tx_max; 1875 } 1876 1877 up_write(&ionic->vf_op_lock); 1878 return ret; 1879 } 1880 1881 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 1882 { 1883 struct ionic_lif *lif = netdev_priv(netdev); 1884 struct ionic *ionic = lif->ionic; 1885 u8 data = set; /* convert to u8 for config */ 1886 int ret; 1887 1888 if (!netif_device_present(netdev)) 1889 return -EBUSY; 1890 1891 down_write(&ionic->vf_op_lock); 1892 1893 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1894 ret = -EINVAL; 1895 } else { 1896 ret = ionic_set_vf_config(ionic, vf, 1897 IONIC_VF_ATTR_SPOOFCHK, &data); 1898 if (!ret) 1899 ionic->vfs[vf].spoofchk = data; 1900 } 1901 1902 up_write(&ionic->vf_op_lock); 1903 return ret; 1904 } 1905 1906 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 1907 { 1908 struct ionic_lif *lif = netdev_priv(netdev); 1909 struct ionic *ionic = lif->ionic; 1910 u8 data = set; /* convert to u8 for config */ 1911 int ret; 1912 1913 if (!netif_device_present(netdev)) 1914 return -EBUSY; 1915 1916 down_write(&ionic->vf_op_lock); 1917 1918 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1919 ret = -EINVAL; 1920 } else { 1921 ret = ionic_set_vf_config(ionic, vf, 1922 IONIC_VF_ATTR_TRUST, &data); 1923 if (!ret) 1924 ionic->vfs[vf].trusted = data; 1925 } 1926 1927 up_write(&ionic->vf_op_lock); 1928 return ret; 1929 } 1930 1931 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 1932 { 1933 struct ionic_lif *lif = netdev_priv(netdev); 1934 struct ionic *ionic = lif->ionic; 1935 u8 data; 1936 int ret; 1937 1938 switch (set) { 1939 case IFLA_VF_LINK_STATE_ENABLE: 1940 data = IONIC_VF_LINK_STATUS_UP; 1941 break; 1942 case IFLA_VF_LINK_STATE_DISABLE: 1943 data = IONIC_VF_LINK_STATUS_DOWN; 1944 break; 1945 case IFLA_VF_LINK_STATE_AUTO: 1946 data = IONIC_VF_LINK_STATUS_AUTO; 1947 break; 1948 default: 1949 return -EINVAL; 1950 } 1951 1952 if (!netif_device_present(netdev)) 1953 return -EBUSY; 1954 1955 down_write(&ionic->vf_op_lock); 1956 1957 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 1958 ret = -EINVAL; 1959 } else { 1960 ret = ionic_set_vf_config(ionic, vf, 1961 IONIC_VF_ATTR_LINKSTATE, &data); 1962 if (!ret) 1963 ionic->vfs[vf].linkstate = set; 1964 } 1965 1966 up_write(&ionic->vf_op_lock); 1967 return ret; 1968 } 1969 1970 static const struct net_device_ops ionic_netdev_ops = { 1971 .ndo_open = ionic_open, 1972 .ndo_stop = ionic_stop, 1973 .ndo_start_xmit = ionic_start_xmit, 1974 .ndo_get_stats64 = ionic_get_stats64, 1975 .ndo_set_rx_mode = ionic_set_rx_mode, 1976 .ndo_set_features = ionic_set_features, 1977 .ndo_set_mac_address = ionic_set_mac_address, 1978 .ndo_validate_addr = eth_validate_addr, 1979 .ndo_tx_timeout = ionic_tx_timeout, 1980 .ndo_change_mtu = ionic_change_mtu, 1981 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 1982 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 1983 .ndo_set_vf_vlan = ionic_set_vf_vlan, 1984 .ndo_set_vf_trust = ionic_set_vf_trust, 1985 .ndo_set_vf_mac = ionic_set_vf_mac, 1986 .ndo_set_vf_rate = ionic_set_vf_rate, 1987 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 1988 .ndo_get_vf_config = ionic_get_vf_config, 1989 .ndo_set_vf_link_state = ionic_set_vf_link_state, 1990 .ndo_get_vf_stats = ionic_get_vf_stats, 1991 }; 1992 1993 int ionic_reset_queues(struct ionic_lif *lif, ionic_reset_cb cb, void *arg) 1994 { 1995 bool running; 1996 int err = 0; 1997 1998 mutex_lock(&lif->queue_lock); 1999 running = netif_running(lif->netdev); 2000 if (running) { 2001 netif_device_detach(lif->netdev); 2002 err = ionic_stop(lif->netdev); 2003 if (err) 2004 goto reset_out; 2005 } 2006 2007 if (cb) 2008 cb(lif, arg); 2009 2010 if (running) { 2011 err = ionic_open(lif->netdev); 2012 netif_device_attach(lif->netdev); 2013 } 2014 2015 reset_out: 2016 mutex_unlock(&lif->queue_lock); 2017 2018 return err; 2019 } 2020 2021 static struct ionic_lif *ionic_lif_alloc(struct ionic *ionic, unsigned int index) 2022 { 2023 struct device *dev = ionic->dev; 2024 struct net_device *netdev; 2025 struct ionic_lif *lif; 2026 int tbl_sz; 2027 int err; 2028 2029 netdev = alloc_etherdev_mqs(sizeof(*lif), 2030 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2031 if (!netdev) { 2032 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2033 return ERR_PTR(-ENOMEM); 2034 } 2035 2036 SET_NETDEV_DEV(netdev, dev); 2037 2038 lif = netdev_priv(netdev); 2039 lif->netdev = netdev; 2040 ionic->master_lif = lif; 2041 netdev->netdev_ops = &ionic_netdev_ops; 2042 ionic_ethtool_set_ops(netdev); 2043 2044 netdev->watchdog_timeo = 2 * HZ; 2045 netif_carrier_off(netdev); 2046 2047 netdev->min_mtu = IONIC_MIN_MTU; 2048 netdev->max_mtu = IONIC_MAX_MTU; 2049 2050 lif->neqs = ionic->neqs_per_lif; 2051 lif->nxqs = ionic->ntxqs_per_lif; 2052 2053 lif->ionic = ionic; 2054 lif->index = index; 2055 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2056 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2057 2058 /* Convert the default coalesce value to actual hw resolution */ 2059 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2060 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2061 lif->rx_coalesce_usecs); 2062 2063 snprintf(lif->name, sizeof(lif->name), "lif%u", index); 2064 2065 spin_lock_init(&lif->adminq_lock); 2066 2067 spin_lock_init(&lif->deferred.lock); 2068 INIT_LIST_HEAD(&lif->deferred.list); 2069 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2070 2071 /* allocate lif info */ 2072 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2073 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2074 &lif->info_pa, GFP_KERNEL); 2075 if (!lif->info) { 2076 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2077 err = -ENOMEM; 2078 goto err_out_free_netdev; 2079 } 2080 2081 ionic_debugfs_add_lif(lif); 2082 2083 /* allocate queues */ 2084 err = ionic_qcqs_alloc(lif); 2085 if (err) 2086 goto err_out_free_lif_info; 2087 2088 /* allocate rss indirection table */ 2089 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2090 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2091 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2092 &lif->rss_ind_tbl_pa, 2093 GFP_KERNEL); 2094 2095 if (!lif->rss_ind_tbl) { 2096 err = -ENOMEM; 2097 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2098 goto err_out_free_qcqs; 2099 } 2100 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2101 2102 list_add_tail(&lif->list, &ionic->lifs); 2103 2104 return lif; 2105 2106 err_out_free_qcqs: 2107 ionic_qcqs_free(lif); 2108 err_out_free_lif_info: 2109 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2110 lif->info = NULL; 2111 lif->info_pa = 0; 2112 err_out_free_netdev: 2113 free_netdev(lif->netdev); 2114 lif = NULL; 2115 2116 return ERR_PTR(err); 2117 } 2118 2119 int ionic_lifs_alloc(struct ionic *ionic) 2120 { 2121 struct ionic_lif *lif; 2122 2123 INIT_LIST_HEAD(&ionic->lifs); 2124 2125 /* only build the first lif, others are for later features */ 2126 set_bit(0, ionic->lifbits); 2127 2128 lif = ionic_lif_alloc(ionic, 0); 2129 if (IS_ERR_OR_NULL(lif)) { 2130 clear_bit(0, ionic->lifbits); 2131 return -ENOMEM; 2132 } 2133 2134 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2135 ionic_lif_queue_identify(lif); 2136 2137 return 0; 2138 } 2139 2140 static void ionic_lif_reset(struct ionic_lif *lif) 2141 { 2142 struct ionic_dev *idev = &lif->ionic->idev; 2143 2144 mutex_lock(&lif->ionic->dev_cmd_lock); 2145 ionic_dev_cmd_lif_reset(idev, lif->index); 2146 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2147 mutex_unlock(&lif->ionic->dev_cmd_lock); 2148 } 2149 2150 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2151 { 2152 struct ionic *ionic = lif->ionic; 2153 2154 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2155 return; 2156 2157 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2158 2159 netif_device_detach(lif->netdev); 2160 2161 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2162 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2163 mutex_lock(&lif->queue_lock); 2164 ionic_stop_queues(lif); 2165 mutex_unlock(&lif->queue_lock); 2166 } 2167 2168 if (netif_running(lif->netdev)) { 2169 ionic_txrx_deinit(lif); 2170 ionic_txrx_free(lif); 2171 } 2172 ionic_lifs_deinit(ionic); 2173 ionic_reset(ionic); 2174 ionic_qcqs_free(lif); 2175 2176 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2177 } 2178 2179 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2180 { 2181 struct ionic *ionic = lif->ionic; 2182 int err; 2183 2184 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2185 return; 2186 2187 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2188 2189 ionic_init_devinfo(ionic); 2190 ionic_port_init(ionic); 2191 err = ionic_qcqs_alloc(lif); 2192 if (err) 2193 goto err_out; 2194 2195 err = ionic_lifs_init(ionic); 2196 if (err) 2197 goto err_qcqs_free; 2198 2199 if (lif->registered) 2200 ionic_lif_set_netdev_info(lif); 2201 2202 ionic_rx_filter_replay(lif); 2203 2204 if (netif_running(lif->netdev)) { 2205 err = ionic_txrx_alloc(lif); 2206 if (err) 2207 goto err_lifs_deinit; 2208 2209 err = ionic_txrx_init(lif); 2210 if (err) 2211 goto err_txrx_free; 2212 } 2213 2214 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 2215 ionic_link_status_check_request(lif); 2216 netif_device_attach(lif->netdev); 2217 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 2218 2219 return; 2220 2221 err_txrx_free: 2222 ionic_txrx_free(lif); 2223 err_lifs_deinit: 2224 ionic_lifs_deinit(ionic); 2225 err_qcqs_free: 2226 ionic_qcqs_free(lif); 2227 err_out: 2228 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 2229 } 2230 2231 static void ionic_lif_free(struct ionic_lif *lif) 2232 { 2233 struct device *dev = lif->ionic->dev; 2234 2235 /* free rss indirection table */ 2236 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 2237 lif->rss_ind_tbl_pa); 2238 lif->rss_ind_tbl = NULL; 2239 lif->rss_ind_tbl_pa = 0; 2240 2241 /* free queues */ 2242 ionic_qcqs_free(lif); 2243 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2244 ionic_lif_reset(lif); 2245 2246 /* free lif info */ 2247 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2248 lif->info = NULL; 2249 lif->info_pa = 0; 2250 2251 /* unmap doorbell page */ 2252 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2253 lif->kern_dbpage = NULL; 2254 kfree(lif->dbid_inuse); 2255 lif->dbid_inuse = NULL; 2256 2257 /* free netdev & lif */ 2258 ionic_debugfs_del_lif(lif); 2259 list_del(&lif->list); 2260 free_netdev(lif->netdev); 2261 } 2262 2263 void ionic_lifs_free(struct ionic *ionic) 2264 { 2265 struct list_head *cur, *tmp; 2266 struct ionic_lif *lif; 2267 2268 list_for_each_safe(cur, tmp, &ionic->lifs) { 2269 lif = list_entry(cur, struct ionic_lif, list); 2270 2271 ionic_lif_free(lif); 2272 } 2273 } 2274 2275 static void ionic_lif_deinit(struct ionic_lif *lif) 2276 { 2277 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 2278 return; 2279 2280 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2281 cancel_work_sync(&lif->deferred.work); 2282 cancel_work_sync(&lif->tx_timeout_work); 2283 ionic_rx_filters_deinit(lif); 2284 if (lif->netdev->features & NETIF_F_RXHASH) 2285 ionic_lif_rss_deinit(lif); 2286 } 2287 2288 napi_disable(&lif->adminqcq->napi); 2289 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2290 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2291 2292 mutex_destroy(&lif->queue_lock); 2293 ionic_lif_reset(lif); 2294 } 2295 2296 void ionic_lifs_deinit(struct ionic *ionic) 2297 { 2298 struct list_head *cur, *tmp; 2299 struct ionic_lif *lif; 2300 2301 list_for_each_safe(cur, tmp, &ionic->lifs) { 2302 lif = list_entry(cur, struct ionic_lif, list); 2303 ionic_lif_deinit(lif); 2304 } 2305 } 2306 2307 static int ionic_lif_adminq_init(struct ionic_lif *lif) 2308 { 2309 struct device *dev = lif->ionic->dev; 2310 struct ionic_q_init_comp comp; 2311 struct ionic_dev *idev; 2312 struct ionic_qcq *qcq; 2313 struct ionic_queue *q; 2314 int err; 2315 2316 idev = &lif->ionic->idev; 2317 qcq = lif->adminqcq; 2318 q = &qcq->q; 2319 2320 mutex_lock(&lif->ionic->dev_cmd_lock); 2321 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 2322 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2323 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2324 mutex_unlock(&lif->ionic->dev_cmd_lock); 2325 if (err) { 2326 netdev_err(lif->netdev, "adminq init failed %d\n", err); 2327 return err; 2328 } 2329 2330 q->hw_type = comp.hw_type; 2331 q->hw_index = le32_to_cpu(comp.hw_index); 2332 q->dbval = IONIC_DBELL_QID(q->hw_index); 2333 2334 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 2335 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 2336 2337 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 2338 NAPI_POLL_WEIGHT); 2339 2340 napi_enable(&qcq->napi); 2341 2342 if (qcq->flags & IONIC_QCQ_F_INTR) 2343 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 2344 IONIC_INTR_MASK_CLEAR); 2345 2346 qcq->flags |= IONIC_QCQ_F_INITED; 2347 2348 return 0; 2349 } 2350 2351 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 2352 { 2353 struct ionic_qcq *qcq = lif->notifyqcq; 2354 struct device *dev = lif->ionic->dev; 2355 struct ionic_queue *q = &qcq->q; 2356 int err; 2357 2358 struct ionic_admin_ctx ctx = { 2359 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2360 .cmd.q_init = { 2361 .opcode = IONIC_CMD_Q_INIT, 2362 .lif_index = cpu_to_le16(lif->index), 2363 .type = q->type, 2364 .ver = lif->qtype_info[q->type].version, 2365 .index = cpu_to_le32(q->index), 2366 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 2367 IONIC_QINIT_F_ENA), 2368 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 2369 .pid = cpu_to_le16(q->pid), 2370 .ring_size = ilog2(q->num_descs), 2371 .ring_base = cpu_to_le64(q->base_pa), 2372 } 2373 }; 2374 2375 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 2376 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 2377 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 2378 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 2379 2380 err = ionic_adminq_post_wait(lif, &ctx); 2381 if (err) 2382 return err; 2383 2384 lif->last_eid = 0; 2385 q->hw_type = ctx.comp.q_init.hw_type; 2386 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 2387 q->dbval = IONIC_DBELL_QID(q->hw_index); 2388 2389 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 2390 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 2391 2392 /* preset the callback info */ 2393 q->info[0].cb_arg = lif; 2394 2395 qcq->flags |= IONIC_QCQ_F_INITED; 2396 2397 return 0; 2398 } 2399 2400 static int ionic_station_set(struct ionic_lif *lif) 2401 { 2402 struct net_device *netdev = lif->netdev; 2403 struct ionic_admin_ctx ctx = { 2404 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2405 .cmd.lif_getattr = { 2406 .opcode = IONIC_CMD_LIF_GETATTR, 2407 .index = cpu_to_le16(lif->index), 2408 .attr = IONIC_LIF_ATTR_MAC, 2409 }, 2410 }; 2411 struct sockaddr addr; 2412 int err; 2413 2414 err = ionic_adminq_post_wait(lif, &ctx); 2415 if (err) 2416 return err; 2417 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 2418 ctx.comp.lif_getattr.mac); 2419 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 2420 return 0; 2421 2422 if (!is_zero_ether_addr(netdev->dev_addr)) { 2423 /* If the netdev mac is non-zero and doesn't match the default 2424 * device address, it was set by something earlier and we're 2425 * likely here again after a fw-upgrade reset. We need to be 2426 * sure the netdev mac is in our filter list. 2427 */ 2428 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 2429 netdev->dev_addr)) 2430 ionic_lif_addr(lif, netdev->dev_addr, true); 2431 } else { 2432 /* Update the netdev mac with the device's mac */ 2433 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 2434 addr.sa_family = AF_INET; 2435 err = eth_prepare_mac_addr_change(netdev, &addr); 2436 if (err) { 2437 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 2438 addr.sa_data, err); 2439 return 0; 2440 } 2441 2442 eth_commit_mac_addr_change(netdev, &addr); 2443 } 2444 2445 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 2446 netdev->dev_addr); 2447 ionic_lif_addr(lif, netdev->dev_addr, true); 2448 2449 return 0; 2450 } 2451 2452 static int ionic_lif_init(struct ionic_lif *lif) 2453 { 2454 struct ionic_dev *idev = &lif->ionic->idev; 2455 struct device *dev = lif->ionic->dev; 2456 struct ionic_lif_init_comp comp; 2457 int dbpage_num; 2458 int err; 2459 2460 mutex_lock(&lif->ionic->dev_cmd_lock); 2461 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 2462 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2463 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 2464 mutex_unlock(&lif->ionic->dev_cmd_lock); 2465 if (err) 2466 return err; 2467 2468 lif->hw_index = le16_to_cpu(comp.hw_index); 2469 mutex_init(&lif->queue_lock); 2470 2471 /* now that we have the hw_index we can figure out our doorbell page */ 2472 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 2473 if (!lif->dbid_count) { 2474 dev_err(dev, "No doorbell pages, aborting\n"); 2475 return -EINVAL; 2476 } 2477 2478 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 2479 if (!lif->dbid_inuse) { 2480 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 2481 return -ENOMEM; 2482 } 2483 2484 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 2485 set_bit(0, lif->dbid_inuse); 2486 lif->kern_pid = 0; 2487 2488 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 2489 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 2490 if (!lif->kern_dbpage) { 2491 dev_err(dev, "Cannot map dbpage, aborting\n"); 2492 err = -ENOMEM; 2493 goto err_out_free_dbid; 2494 } 2495 2496 err = ionic_lif_adminq_init(lif); 2497 if (err) 2498 goto err_out_adminq_deinit; 2499 2500 if (lif->ionic->nnqs_per_lif) { 2501 err = ionic_lif_notifyq_init(lif); 2502 if (err) 2503 goto err_out_notifyq_deinit; 2504 } 2505 2506 err = ionic_init_nic_features(lif); 2507 if (err) 2508 goto err_out_notifyq_deinit; 2509 2510 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 2511 err = ionic_rx_filters_init(lif); 2512 if (err) 2513 goto err_out_notifyq_deinit; 2514 } 2515 2516 err = ionic_station_set(lif); 2517 if (err) 2518 goto err_out_notifyq_deinit; 2519 2520 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 2521 2522 set_bit(IONIC_LIF_F_INITED, lif->state); 2523 2524 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 2525 2526 return 0; 2527 2528 err_out_notifyq_deinit: 2529 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 2530 err_out_adminq_deinit: 2531 ionic_lif_qcq_deinit(lif, lif->adminqcq); 2532 ionic_lif_reset(lif); 2533 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 2534 lif->kern_dbpage = NULL; 2535 err_out_free_dbid: 2536 kfree(lif->dbid_inuse); 2537 lif->dbid_inuse = NULL; 2538 2539 return err; 2540 } 2541 2542 int ionic_lifs_init(struct ionic *ionic) 2543 { 2544 struct list_head *cur, *tmp; 2545 struct ionic_lif *lif; 2546 int err; 2547 2548 list_for_each_safe(cur, tmp, &ionic->lifs) { 2549 lif = list_entry(cur, struct ionic_lif, list); 2550 err = ionic_lif_init(lif); 2551 if (err) 2552 return err; 2553 } 2554 2555 return 0; 2556 } 2557 2558 static void ionic_lif_notify_work(struct work_struct *ws) 2559 { 2560 } 2561 2562 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 2563 { 2564 struct ionic_admin_ctx ctx = { 2565 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 2566 .cmd.lif_setattr = { 2567 .opcode = IONIC_CMD_LIF_SETATTR, 2568 .index = cpu_to_le16(lif->index), 2569 .attr = IONIC_LIF_ATTR_NAME, 2570 }, 2571 }; 2572 2573 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 2574 sizeof(ctx.cmd.lif_setattr.name)); 2575 2576 ionic_adminq_post_wait(lif, &ctx); 2577 } 2578 2579 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 2580 { 2581 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 2582 return NULL; 2583 2584 return netdev_priv(netdev); 2585 } 2586 2587 static int ionic_lif_notify(struct notifier_block *nb, 2588 unsigned long event, void *info) 2589 { 2590 struct net_device *ndev = netdev_notifier_info_to_dev(info); 2591 struct ionic *ionic = container_of(nb, struct ionic, nb); 2592 struct ionic_lif *lif = ionic_netdev_lif(ndev); 2593 2594 if (!lif || lif->ionic != ionic) 2595 return NOTIFY_DONE; 2596 2597 switch (event) { 2598 case NETDEV_CHANGENAME: 2599 ionic_lif_set_netdev_info(lif); 2600 break; 2601 } 2602 2603 return NOTIFY_DONE; 2604 } 2605 2606 int ionic_lifs_register(struct ionic *ionic) 2607 { 2608 int err; 2609 2610 INIT_WORK(&ionic->nb_work, ionic_lif_notify_work); 2611 2612 ionic->nb.notifier_call = ionic_lif_notify; 2613 2614 err = register_netdevice_notifier(&ionic->nb); 2615 if (err) 2616 ionic->nb.notifier_call = NULL; 2617 2618 /* only register LIF0 for now */ 2619 err = register_netdev(ionic->master_lif->netdev); 2620 if (err) { 2621 dev_err(ionic->dev, "Cannot register net device, aborting\n"); 2622 return err; 2623 } 2624 ionic->master_lif->registered = true; 2625 2626 return 0; 2627 } 2628 2629 void ionic_lifs_unregister(struct ionic *ionic) 2630 { 2631 if (ionic->nb.notifier_call) { 2632 unregister_netdevice_notifier(&ionic->nb); 2633 cancel_work_sync(&ionic->nb_work); 2634 ionic->nb.notifier_call = NULL; 2635 } 2636 2637 /* There is only one lif ever registered in the 2638 * current model, so don't bother searching the 2639 * ionic->lif for candidates to unregister 2640 */ 2641 if (ionic->master_lif && 2642 ionic->master_lif->netdev->reg_state == NETREG_REGISTERED) 2643 unregister_netdev(ionic->master_lif->netdev); 2644 } 2645 2646 static void ionic_lif_queue_identify(struct ionic_lif *lif) 2647 { 2648 struct ionic *ionic = lif->ionic; 2649 union ionic_q_identity *q_ident; 2650 struct ionic_dev *idev; 2651 int qtype; 2652 int err; 2653 2654 idev = &lif->ionic->idev; 2655 q_ident = (union ionic_q_identity *)&idev->dev_cmd_regs->data; 2656 2657 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 2658 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 2659 2660 /* filter out the ones we know about */ 2661 switch (qtype) { 2662 case IONIC_QTYPE_ADMINQ: 2663 case IONIC_QTYPE_NOTIFYQ: 2664 case IONIC_QTYPE_RXQ: 2665 case IONIC_QTYPE_TXQ: 2666 break; 2667 default: 2668 continue; 2669 } 2670 2671 memset(qti, 0, sizeof(*qti)); 2672 2673 mutex_lock(&ionic->dev_cmd_lock); 2674 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 2675 ionic_qtype_versions[qtype]); 2676 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2677 if (!err) { 2678 qti->version = q_ident->version; 2679 qti->supported = q_ident->supported; 2680 qti->features = le64_to_cpu(q_ident->features); 2681 qti->desc_sz = le16_to_cpu(q_ident->desc_sz); 2682 qti->comp_sz = le16_to_cpu(q_ident->comp_sz); 2683 qti->sg_desc_sz = le16_to_cpu(q_ident->sg_desc_sz); 2684 qti->max_sg_elems = le16_to_cpu(q_ident->max_sg_elems); 2685 qti->sg_desc_stride = le16_to_cpu(q_ident->sg_desc_stride); 2686 } 2687 mutex_unlock(&ionic->dev_cmd_lock); 2688 2689 if (err == -EINVAL) { 2690 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 2691 continue; 2692 } else if (err == -EIO) { 2693 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 2694 return; 2695 } else if (err) { 2696 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 2697 qtype, err); 2698 return; 2699 } 2700 2701 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 2702 qtype, qti->version); 2703 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 2704 qtype, qti->supported); 2705 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 2706 qtype, qti->features); 2707 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 2708 qtype, qti->desc_sz); 2709 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 2710 qtype, qti->comp_sz); 2711 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 2712 qtype, qti->sg_desc_sz); 2713 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 2714 qtype, qti->max_sg_elems); 2715 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 2716 qtype, qti->sg_desc_stride); 2717 } 2718 } 2719 2720 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 2721 union ionic_lif_identity *lid) 2722 { 2723 struct ionic_dev *idev = &ionic->idev; 2724 size_t sz; 2725 int err; 2726 2727 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 2728 2729 mutex_lock(&ionic->dev_cmd_lock); 2730 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 2731 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 2732 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 2733 mutex_unlock(&ionic->dev_cmd_lock); 2734 if (err) 2735 return (err); 2736 2737 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 2738 le64_to_cpu(lid->capabilities)); 2739 2740 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 2741 le32_to_cpu(lid->eth.max_ucast_filters)); 2742 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 2743 le32_to_cpu(lid->eth.max_mcast_filters)); 2744 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 2745 le64_to_cpu(lid->eth.config.features)); 2746 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 2747 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 2748 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 2749 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 2750 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 2751 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 2752 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 2753 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 2754 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 2755 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 2756 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 2757 le32_to_cpu(lid->eth.config.mtu)); 2758 2759 return 0; 2760 } 2761 2762 int ionic_lifs_size(struct ionic *ionic) 2763 { 2764 struct ionic_identity *ident = &ionic->ident; 2765 unsigned int nintrs, dev_nintrs; 2766 union ionic_lif_config *lc; 2767 unsigned int ntxqs_per_lif; 2768 unsigned int nrxqs_per_lif; 2769 unsigned int neqs_per_lif; 2770 unsigned int nnqs_per_lif; 2771 unsigned int nxqs, neqs; 2772 unsigned int min_intrs; 2773 int err; 2774 2775 lc = &ident->lif.eth.config; 2776 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 2777 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 2778 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 2779 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 2780 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 2781 2782 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 2783 nxqs = min(nxqs, num_online_cpus()); 2784 neqs = min(neqs_per_lif, num_online_cpus()); 2785 2786 try_again: 2787 /* interrupt usage: 2788 * 1 for master lif adminq/notifyq 2789 * 1 for each CPU for master lif TxRx queue pairs 2790 * whatever's left is for RDMA queues 2791 */ 2792 nintrs = 1 + nxqs + neqs; 2793 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 2794 2795 if (nintrs > dev_nintrs) 2796 goto try_fewer; 2797 2798 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 2799 if (err < 0 && err != -ENOSPC) { 2800 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 2801 return err; 2802 } 2803 if (err == -ENOSPC) 2804 goto try_fewer; 2805 2806 if (err != nintrs) { 2807 ionic_bus_free_irq_vectors(ionic); 2808 goto try_fewer; 2809 } 2810 2811 ionic->nnqs_per_lif = nnqs_per_lif; 2812 ionic->neqs_per_lif = neqs; 2813 ionic->ntxqs_per_lif = nxqs; 2814 ionic->nrxqs_per_lif = nxqs; 2815 ionic->nintrs = nintrs; 2816 2817 ionic_debugfs_add_sizes(ionic); 2818 2819 return 0; 2820 2821 try_fewer: 2822 if (nnqs_per_lif > 1) { 2823 nnqs_per_lif >>= 1; 2824 goto try_again; 2825 } 2826 if (neqs > 1) { 2827 neqs >>= 1; 2828 goto try_again; 2829 } 2830 if (nxqs > 1) { 2831 nxqs >>= 1; 2832 goto try_again; 2833 } 2834 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 2835 return -ENOSPC; 2836 } 2837