1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/ethtool.h> 5 #include <linux/printk.h> 6 #include <linux/dynamic_debug.h> 7 #include <linux/netdevice.h> 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/rtnetlink.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/cpumask.h> 14 #include <linux/crash_dump.h> 15 16 #include "ionic.h" 17 #include "ionic_bus.h" 18 #include "ionic_lif.h" 19 #include "ionic_txrx.h" 20 #include "ionic_ethtool.h" 21 #include "ionic_debugfs.h" 22 23 /* queuetype support level */ 24 static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = { 25 [IONIC_QTYPE_ADMINQ] = 0, /* 0 = Base version with CQ support */ 26 [IONIC_QTYPE_NOTIFYQ] = 0, /* 0 = Base version */ 27 [IONIC_QTYPE_RXQ] = 0, /* 0 = Base version with CQ+SG support */ 28 [IONIC_QTYPE_TXQ] = 1, /* 0 = Base version with CQ+SG support 29 * 1 = ... with Tx SG version 1 30 */ 31 }; 32 33 static void ionic_link_status_check(struct ionic_lif *lif); 34 static void ionic_lif_handle_fw_down(struct ionic_lif *lif); 35 static void ionic_lif_handle_fw_up(struct ionic_lif *lif); 36 static void ionic_lif_set_netdev_info(struct ionic_lif *lif); 37 38 static void ionic_txrx_deinit(struct ionic_lif *lif); 39 static int ionic_txrx_init(struct ionic_lif *lif); 40 static int ionic_start_queues(struct ionic_lif *lif); 41 static void ionic_stop_queues(struct ionic_lif *lif); 42 static void ionic_lif_queue_identify(struct ionic_lif *lif); 43 44 static void ionic_dim_work(struct work_struct *work) 45 { 46 struct dim *dim = container_of(work, struct dim, work); 47 struct dim_cq_moder cur_moder; 48 struct ionic_qcq *qcq; 49 u32 new_coal; 50 51 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 52 qcq = container_of(dim, struct ionic_qcq, dim); 53 new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec); 54 new_coal = new_coal ? new_coal : 1; 55 56 if (qcq->intr.dim_coal_hw != new_coal) { 57 unsigned int qi = qcq->cq.bound_q->index; 58 struct ionic_lif *lif = qcq->q.lif; 59 60 qcq->intr.dim_coal_hw = new_coal; 61 62 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 63 lif->rxqcqs[qi]->intr.index, 64 qcq->intr.dim_coal_hw); 65 } 66 67 dim->state = DIM_START_MEASURE; 68 } 69 70 static void ionic_lif_deferred_work(struct work_struct *work) 71 { 72 struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work); 73 struct ionic_deferred *def = &lif->deferred; 74 struct ionic_deferred_work *w = NULL; 75 76 do { 77 spin_lock_bh(&def->lock); 78 if (!list_empty(&def->list)) { 79 w = list_first_entry(&def->list, 80 struct ionic_deferred_work, list); 81 list_del(&w->list); 82 } 83 spin_unlock_bh(&def->lock); 84 85 if (!w) 86 break; 87 88 switch (w->type) { 89 case IONIC_DW_TYPE_RX_MODE: 90 ionic_lif_rx_mode(lif); 91 break; 92 case IONIC_DW_TYPE_LINK_STATUS: 93 ionic_link_status_check(lif); 94 break; 95 case IONIC_DW_TYPE_LIF_RESET: 96 if (w->fw_status) { 97 ionic_lif_handle_fw_up(lif); 98 } else { 99 ionic_lif_handle_fw_down(lif); 100 101 /* Fire off another watchdog to see 102 * if the FW is already back rather than 103 * waiting another whole cycle 104 */ 105 mod_timer(&lif->ionic->watchdog_timer, jiffies + 1); 106 } 107 break; 108 default: 109 break; 110 } 111 kfree(w); 112 w = NULL; 113 } while (true); 114 } 115 116 void ionic_lif_deferred_enqueue(struct ionic_deferred *def, 117 struct ionic_deferred_work *work) 118 { 119 spin_lock_bh(&def->lock); 120 list_add_tail(&work->list, &def->list); 121 spin_unlock_bh(&def->lock); 122 schedule_work(&def->work); 123 } 124 125 static void ionic_link_status_check(struct ionic_lif *lif) 126 { 127 struct net_device *netdev = lif->netdev; 128 u16 link_status; 129 bool link_up; 130 131 if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 132 return; 133 134 /* Don't put carrier back up if we're in a broken state */ 135 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) { 136 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 137 return; 138 } 139 140 link_status = le16_to_cpu(lif->info->status.link_status); 141 link_up = link_status == IONIC_PORT_OPER_STATUS_UP; 142 143 if (link_up) { 144 int err = 0; 145 146 if (netdev->flags & IFF_UP && netif_running(netdev)) { 147 mutex_lock(&lif->queue_lock); 148 err = ionic_start_queues(lif); 149 if (err && err != -EBUSY) { 150 netdev_err(lif->netdev, 151 "Failed to start queues: %d\n", err); 152 set_bit(IONIC_LIF_F_BROKEN, lif->state); 153 netif_carrier_off(lif->netdev); 154 } 155 mutex_unlock(&lif->queue_lock); 156 } 157 158 if (!err && !netif_carrier_ok(netdev)) { 159 ionic_port_identify(lif->ionic); 160 netdev_info(netdev, "Link up - %d Gbps\n", 161 le32_to_cpu(lif->info->status.link_speed) / 1000); 162 netif_carrier_on(netdev); 163 } 164 } else { 165 if (netif_carrier_ok(netdev)) { 166 netdev_info(netdev, "Link down\n"); 167 netif_carrier_off(netdev); 168 } 169 170 if (netdev->flags & IFF_UP && netif_running(netdev)) { 171 mutex_lock(&lif->queue_lock); 172 ionic_stop_queues(lif); 173 mutex_unlock(&lif->queue_lock); 174 } 175 } 176 177 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 178 } 179 180 void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep) 181 { 182 struct ionic_deferred_work *work; 183 184 /* we only need one request outstanding at a time */ 185 if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state)) 186 return; 187 188 if (!can_sleep) { 189 work = kzalloc(sizeof(*work), GFP_ATOMIC); 190 if (!work) { 191 clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state); 192 return; 193 } 194 195 work->type = IONIC_DW_TYPE_LINK_STATUS; 196 ionic_lif_deferred_enqueue(&lif->deferred, work); 197 } else { 198 ionic_link_status_check(lif); 199 } 200 } 201 202 static irqreturn_t ionic_isr(int irq, void *data) 203 { 204 struct napi_struct *napi = data; 205 206 napi_schedule_irqoff(napi); 207 208 return IRQ_HANDLED; 209 } 210 211 static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq) 212 { 213 struct ionic_intr_info *intr = &qcq->intr; 214 struct device *dev = lif->ionic->dev; 215 struct ionic_queue *q = &qcq->q; 216 const char *name; 217 218 if (lif->registered) 219 name = lif->netdev->name; 220 else 221 name = dev_name(dev); 222 223 snprintf(intr->name, sizeof(intr->name), 224 "%s-%s-%s", IONIC_DRV_NAME, name, q->name); 225 226 return devm_request_irq(dev, intr->vector, ionic_isr, 227 0, intr->name, &qcq->napi); 228 } 229 230 static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr) 231 { 232 struct ionic *ionic = lif->ionic; 233 int index; 234 235 index = find_first_zero_bit(ionic->intrs, ionic->nintrs); 236 if (index == ionic->nintrs) { 237 netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n", 238 __func__, index, ionic->nintrs); 239 return -ENOSPC; 240 } 241 242 set_bit(index, ionic->intrs); 243 ionic_intr_init(&ionic->idev, intr, index); 244 245 return 0; 246 } 247 248 static void ionic_intr_free(struct ionic *ionic, int index) 249 { 250 if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs) 251 clear_bit(index, ionic->intrs); 252 } 253 254 static int ionic_qcq_enable(struct ionic_qcq *qcq) 255 { 256 struct ionic_queue *q = &qcq->q; 257 struct ionic_lif *lif = q->lif; 258 struct ionic_dev *idev; 259 struct device *dev; 260 261 struct ionic_admin_ctx ctx = { 262 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 263 .cmd.q_control = { 264 .opcode = IONIC_CMD_Q_CONTROL, 265 .lif_index = cpu_to_le16(lif->index), 266 .type = q->type, 267 .index = cpu_to_le32(q->index), 268 .oper = IONIC_Q_ENABLE, 269 }, 270 }; 271 272 idev = &lif->ionic->idev; 273 dev = lif->ionic->dev; 274 275 dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n", 276 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 277 278 if (qcq->flags & IONIC_QCQ_F_INTR) { 279 irq_set_affinity_hint(qcq->intr.vector, 280 &qcq->intr.affinity_mask); 281 napi_enable(&qcq->napi); 282 ionic_intr_clean(idev->intr_ctrl, qcq->intr.index); 283 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 284 IONIC_INTR_MASK_CLEAR); 285 } 286 287 return ionic_adminq_post_wait(lif, &ctx); 288 } 289 290 static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw) 291 { 292 struct ionic_queue *q; 293 struct ionic_lif *lif; 294 int err = 0; 295 296 struct ionic_admin_ctx ctx = { 297 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 298 .cmd.q_control = { 299 .opcode = IONIC_CMD_Q_CONTROL, 300 .oper = IONIC_Q_DISABLE, 301 }, 302 }; 303 304 if (!qcq) 305 return -ENXIO; 306 307 q = &qcq->q; 308 lif = q->lif; 309 310 if (qcq->flags & IONIC_QCQ_F_INTR) { 311 struct ionic_dev *idev = &lif->ionic->idev; 312 313 cancel_work_sync(&qcq->dim.work); 314 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 315 IONIC_INTR_MASK_SET); 316 synchronize_irq(qcq->intr.vector); 317 irq_set_affinity_hint(qcq->intr.vector, NULL); 318 napi_disable(&qcq->napi); 319 } 320 321 if (send_to_hw) { 322 ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index); 323 ctx.cmd.q_control.type = q->type; 324 ctx.cmd.q_control.index = cpu_to_le32(q->index); 325 dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n", 326 ctx.cmd.q_control.index, ctx.cmd.q_control.type); 327 328 err = ionic_adminq_post_wait(lif, &ctx); 329 } 330 331 return err; 332 } 333 334 static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq) 335 { 336 struct ionic_dev *idev = &lif->ionic->idev; 337 338 if (!qcq) 339 return; 340 341 if (!(qcq->flags & IONIC_QCQ_F_INITED)) 342 return; 343 344 if (qcq->flags & IONIC_QCQ_F_INTR) { 345 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 346 IONIC_INTR_MASK_SET); 347 netif_napi_del(&qcq->napi); 348 } 349 350 qcq->flags &= ~IONIC_QCQ_F_INITED; 351 } 352 353 static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 354 { 355 if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0) 356 return; 357 358 irq_set_affinity_hint(qcq->intr.vector, NULL); 359 devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi); 360 qcq->intr.vector = 0; 361 ionic_intr_free(lif->ionic, qcq->intr.index); 362 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 363 } 364 365 static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq) 366 { 367 struct device *dev = lif->ionic->dev; 368 369 if (!qcq) 370 return; 371 372 ionic_debugfs_del_qcq(qcq); 373 374 if (qcq->q_base) { 375 dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa); 376 qcq->q_base = NULL; 377 qcq->q_base_pa = 0; 378 } 379 380 if (qcq->cq_base) { 381 dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa); 382 qcq->cq_base = NULL; 383 qcq->cq_base_pa = 0; 384 } 385 386 if (qcq->sg_base) { 387 dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa); 388 qcq->sg_base = NULL; 389 qcq->sg_base_pa = 0; 390 } 391 392 ionic_qcq_intr_free(lif, qcq); 393 394 if (qcq->cq.info) { 395 devm_kfree(dev, qcq->cq.info); 396 qcq->cq.info = NULL; 397 } 398 if (qcq->q.info) { 399 devm_kfree(dev, qcq->q.info); 400 qcq->q.info = NULL; 401 } 402 } 403 404 static void ionic_qcqs_free(struct ionic_lif *lif) 405 { 406 struct device *dev = lif->ionic->dev; 407 struct ionic_qcq *adminqcq; 408 unsigned long irqflags; 409 410 if (lif->notifyqcq) { 411 ionic_qcq_free(lif, lif->notifyqcq); 412 devm_kfree(dev, lif->notifyqcq); 413 lif->notifyqcq = NULL; 414 } 415 416 if (lif->adminqcq) { 417 spin_lock_irqsave(&lif->adminq_lock, irqflags); 418 adminqcq = READ_ONCE(lif->adminqcq); 419 lif->adminqcq = NULL; 420 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 421 if (adminqcq) { 422 ionic_qcq_free(lif, adminqcq); 423 devm_kfree(dev, adminqcq); 424 } 425 } 426 427 if (lif->rxqcqs) { 428 devm_kfree(dev, lif->rxqstats); 429 lif->rxqstats = NULL; 430 devm_kfree(dev, lif->rxqcqs); 431 lif->rxqcqs = NULL; 432 } 433 434 if (lif->txqcqs) { 435 devm_kfree(dev, lif->txqstats); 436 lif->txqstats = NULL; 437 devm_kfree(dev, lif->txqcqs); 438 lif->txqcqs = NULL; 439 } 440 } 441 442 static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq, 443 struct ionic_qcq *n_qcq) 444 { 445 if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) { 446 ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index); 447 n_qcq->flags &= ~IONIC_QCQ_F_INTR; 448 } 449 450 n_qcq->intr.vector = src_qcq->intr.vector; 451 n_qcq->intr.index = src_qcq->intr.index; 452 } 453 454 static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq) 455 { 456 int err; 457 458 if (!(qcq->flags & IONIC_QCQ_F_INTR)) { 459 qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED; 460 return 0; 461 } 462 463 err = ionic_intr_alloc(lif, &qcq->intr); 464 if (err) { 465 netdev_warn(lif->netdev, "no intr for %s: %d\n", 466 qcq->q.name, err); 467 goto err_out; 468 } 469 470 err = ionic_bus_get_irq(lif->ionic, qcq->intr.index); 471 if (err < 0) { 472 netdev_warn(lif->netdev, "no vector for %s: %d\n", 473 qcq->q.name, err); 474 goto err_out_free_intr; 475 } 476 qcq->intr.vector = err; 477 ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index, 478 IONIC_INTR_MASK_SET); 479 480 err = ionic_request_irq(lif, qcq); 481 if (err) { 482 netdev_warn(lif->netdev, "irq request failed %d\n", err); 483 goto err_out_free_intr; 484 } 485 486 /* try to get the irq on the local numa node first */ 487 qcq->intr.cpu = cpumask_local_spread(qcq->intr.index, 488 dev_to_node(lif->ionic->dev)); 489 if (qcq->intr.cpu != -1) 490 cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask); 491 492 netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index); 493 return 0; 494 495 err_out_free_intr: 496 ionic_intr_free(lif->ionic, qcq->intr.index); 497 err_out: 498 return err; 499 } 500 501 static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type, 502 unsigned int index, 503 const char *name, unsigned int flags, 504 unsigned int num_descs, unsigned int desc_size, 505 unsigned int cq_desc_size, 506 unsigned int sg_desc_size, 507 unsigned int pid, struct ionic_qcq **qcq) 508 { 509 struct ionic_dev *idev = &lif->ionic->idev; 510 struct device *dev = lif->ionic->dev; 511 void *q_base, *cq_base, *sg_base; 512 dma_addr_t cq_base_pa = 0; 513 dma_addr_t sg_base_pa = 0; 514 dma_addr_t q_base_pa = 0; 515 struct ionic_qcq *new; 516 int err; 517 518 *qcq = NULL; 519 520 new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL); 521 if (!new) { 522 netdev_err(lif->netdev, "Cannot allocate queue structure\n"); 523 err = -ENOMEM; 524 goto err_out; 525 } 526 527 new->q.dev = dev; 528 new->flags = flags; 529 530 new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info), 531 GFP_KERNEL); 532 if (!new->q.info) { 533 netdev_err(lif->netdev, "Cannot allocate queue info\n"); 534 err = -ENOMEM; 535 goto err_out_free_qcq; 536 } 537 538 new->q.type = type; 539 new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems; 540 541 err = ionic_q_init(lif, idev, &new->q, index, name, num_descs, 542 desc_size, sg_desc_size, pid); 543 if (err) { 544 netdev_err(lif->netdev, "Cannot initialize queue\n"); 545 goto err_out_free_q_info; 546 } 547 548 err = ionic_alloc_qcq_interrupt(lif, new); 549 if (err) 550 goto err_out; 551 552 new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info), 553 GFP_KERNEL); 554 if (!new->cq.info) { 555 netdev_err(lif->netdev, "Cannot allocate completion queue info\n"); 556 err = -ENOMEM; 557 goto err_out_free_irq; 558 } 559 560 err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size); 561 if (err) { 562 netdev_err(lif->netdev, "Cannot initialize completion queue\n"); 563 goto err_out_free_cq_info; 564 } 565 566 if (flags & IONIC_QCQ_F_NOTIFYQ) { 567 int q_size, cq_size; 568 569 /* q & cq need to be contiguous in case of notifyq */ 570 q_size = ALIGN(num_descs * desc_size, PAGE_SIZE); 571 cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE); 572 573 new->q_size = PAGE_SIZE + q_size + cq_size; 574 new->q_base = dma_alloc_coherent(dev, new->q_size, 575 &new->q_base_pa, GFP_KERNEL); 576 if (!new->q_base) { 577 netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n"); 578 err = -ENOMEM; 579 goto err_out_free_cq_info; 580 } 581 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 582 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 583 ionic_q_map(&new->q, q_base, q_base_pa); 584 585 cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE); 586 cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE); 587 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 588 ionic_cq_bind(&new->cq, &new->q); 589 } else { 590 new->q_size = PAGE_SIZE + (num_descs * desc_size); 591 new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa, 592 GFP_KERNEL); 593 if (!new->q_base) { 594 netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n"); 595 err = -ENOMEM; 596 goto err_out_free_cq_info; 597 } 598 q_base = PTR_ALIGN(new->q_base, PAGE_SIZE); 599 q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE); 600 ionic_q_map(&new->q, q_base, q_base_pa); 601 602 new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size); 603 new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa, 604 GFP_KERNEL); 605 if (!new->cq_base) { 606 netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n"); 607 err = -ENOMEM; 608 goto err_out_free_q; 609 } 610 cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE); 611 cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE); 612 ionic_cq_map(&new->cq, cq_base, cq_base_pa); 613 ionic_cq_bind(&new->cq, &new->q); 614 } 615 616 if (flags & IONIC_QCQ_F_SG) { 617 new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size); 618 new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa, 619 GFP_KERNEL); 620 if (!new->sg_base) { 621 netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n"); 622 err = -ENOMEM; 623 goto err_out_free_cq; 624 } 625 sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE); 626 sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE); 627 ionic_q_sg_map(&new->q, sg_base, sg_base_pa); 628 } 629 630 INIT_WORK(&new->dim.work, ionic_dim_work); 631 new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE; 632 633 *qcq = new; 634 635 return 0; 636 637 err_out_free_cq: 638 dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa); 639 err_out_free_q: 640 dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa); 641 err_out_free_cq_info: 642 devm_kfree(dev, new->cq.info); 643 err_out_free_irq: 644 if (flags & IONIC_QCQ_F_INTR) { 645 devm_free_irq(dev, new->intr.vector, &new->napi); 646 ionic_intr_free(lif->ionic, new->intr.index); 647 } 648 err_out_free_q_info: 649 devm_kfree(dev, new->q.info); 650 err_out_free_qcq: 651 devm_kfree(dev, new); 652 err_out: 653 dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err); 654 return err; 655 } 656 657 static int ionic_qcqs_alloc(struct ionic_lif *lif) 658 { 659 struct device *dev = lif->ionic->dev; 660 unsigned int flags; 661 int err; 662 663 flags = IONIC_QCQ_F_INTR; 664 err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags, 665 IONIC_ADMINQ_LENGTH, 666 sizeof(struct ionic_admin_cmd), 667 sizeof(struct ionic_admin_comp), 668 0, lif->kern_pid, &lif->adminqcq); 669 if (err) 670 return err; 671 ionic_debugfs_add_qcq(lif, lif->adminqcq); 672 673 if (lif->ionic->nnqs_per_lif) { 674 flags = IONIC_QCQ_F_NOTIFYQ; 675 err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq", 676 flags, IONIC_NOTIFYQ_LENGTH, 677 sizeof(struct ionic_notifyq_cmd), 678 sizeof(union ionic_notifyq_comp), 679 0, lif->kern_pid, &lif->notifyqcq); 680 if (err) 681 goto err_out; 682 ionic_debugfs_add_qcq(lif, lif->notifyqcq); 683 684 /* Let the notifyq ride on the adminq interrupt */ 685 ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq); 686 } 687 688 err = -ENOMEM; 689 lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif, 690 sizeof(*lif->txqcqs), GFP_KERNEL); 691 if (!lif->txqcqs) 692 goto err_out; 693 lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif, 694 sizeof(*lif->rxqcqs), GFP_KERNEL); 695 if (!lif->rxqcqs) 696 goto err_out; 697 698 lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1, 699 sizeof(*lif->txqstats), GFP_KERNEL); 700 if (!lif->txqstats) 701 goto err_out; 702 lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1, 703 sizeof(*lif->rxqstats), GFP_KERNEL); 704 if (!lif->rxqstats) 705 goto err_out; 706 707 return 0; 708 709 err_out: 710 ionic_qcqs_free(lif); 711 return err; 712 } 713 714 static void ionic_qcq_sanitize(struct ionic_qcq *qcq) 715 { 716 qcq->q.tail_idx = 0; 717 qcq->q.head_idx = 0; 718 qcq->cq.tail_idx = 0; 719 qcq->cq.done_color = 1; 720 memset(qcq->q_base, 0, qcq->q_size); 721 memset(qcq->cq_base, 0, qcq->cq_size); 722 memset(qcq->sg_base, 0, qcq->sg_size); 723 } 724 725 static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 726 { 727 struct device *dev = lif->ionic->dev; 728 struct ionic_queue *q = &qcq->q; 729 struct ionic_cq *cq = &qcq->cq; 730 struct ionic_admin_ctx ctx = { 731 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 732 .cmd.q_init = { 733 .opcode = IONIC_CMD_Q_INIT, 734 .lif_index = cpu_to_le16(lif->index), 735 .type = q->type, 736 .ver = lif->qtype_info[q->type].version, 737 .index = cpu_to_le32(q->index), 738 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 739 IONIC_QINIT_F_SG), 740 .pid = cpu_to_le16(q->pid), 741 .ring_size = ilog2(q->num_descs), 742 .ring_base = cpu_to_le64(q->base_pa), 743 .cq_ring_base = cpu_to_le64(cq->base_pa), 744 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 745 .features = cpu_to_le64(q->features), 746 }, 747 }; 748 unsigned int intr_index; 749 int err; 750 751 intr_index = qcq->intr.index; 752 753 ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index); 754 755 dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid); 756 dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index); 757 dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 758 dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 759 dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 760 dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver); 761 dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 762 763 ionic_qcq_sanitize(qcq); 764 765 err = ionic_adminq_post_wait(lif, &ctx); 766 if (err) 767 return err; 768 769 q->hw_type = ctx.comp.q_init.hw_type; 770 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 771 q->dbval = IONIC_DBELL_QID(q->hw_index); 772 773 dev_dbg(dev, "txq->hw_type %d\n", q->hw_type); 774 dev_dbg(dev, "txq->hw_index %d\n", q->hw_index); 775 776 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 777 netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi, 778 NAPI_POLL_WEIGHT); 779 780 qcq->flags |= IONIC_QCQ_F_INITED; 781 782 return 0; 783 } 784 785 static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq) 786 { 787 struct device *dev = lif->ionic->dev; 788 struct ionic_queue *q = &qcq->q; 789 struct ionic_cq *cq = &qcq->cq; 790 struct ionic_admin_ctx ctx = { 791 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 792 .cmd.q_init = { 793 .opcode = IONIC_CMD_Q_INIT, 794 .lif_index = cpu_to_le16(lif->index), 795 .type = q->type, 796 .ver = lif->qtype_info[q->type].version, 797 .index = cpu_to_le32(q->index), 798 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 799 IONIC_QINIT_F_SG), 800 .intr_index = cpu_to_le16(cq->bound_intr->index), 801 .pid = cpu_to_le16(q->pid), 802 .ring_size = ilog2(q->num_descs), 803 .ring_base = cpu_to_le64(q->base_pa), 804 .cq_ring_base = cpu_to_le64(cq->base_pa), 805 .sg_ring_base = cpu_to_le64(q->sg_base_pa), 806 .features = cpu_to_le64(q->features), 807 }, 808 }; 809 int err; 810 811 dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid); 812 dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index); 813 dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 814 dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 815 dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags); 816 dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver); 817 dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index); 818 819 ionic_qcq_sanitize(qcq); 820 821 err = ionic_adminq_post_wait(lif, &ctx); 822 if (err) 823 return err; 824 825 q->hw_type = ctx.comp.q_init.hw_type; 826 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 827 q->dbval = IONIC_DBELL_QID(q->hw_index); 828 829 dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type); 830 dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index); 831 832 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 833 netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi, 834 NAPI_POLL_WEIGHT); 835 else 836 netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi, 837 NAPI_POLL_WEIGHT); 838 839 qcq->flags |= IONIC_QCQ_F_INITED; 840 841 return 0; 842 } 843 844 int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif) 845 { 846 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 847 unsigned int txq_i, flags; 848 struct ionic_qcq *txq; 849 u64 features; 850 int err; 851 852 if (lif->hwstamp_txq) 853 return 0; 854 855 features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP; 856 857 num_desc = IONIC_MIN_TXRX_DESC; 858 desc_sz = sizeof(struct ionic_txq_desc); 859 comp_sz = 2 * sizeof(struct ionic_txq_comp); 860 861 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 862 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1)) 863 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 864 else 865 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 866 867 txq_i = lif->ionic->ntxqs_per_lif; 868 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 869 870 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags, 871 num_desc, desc_sz, comp_sz, sg_desc_sz, 872 lif->kern_pid, &txq); 873 if (err) 874 goto err_qcq_alloc; 875 876 txq->q.features = features; 877 878 ionic_link_qcq_interrupts(lif->adminqcq, txq); 879 ionic_debugfs_add_qcq(lif, txq); 880 881 lif->hwstamp_txq = txq; 882 883 if (netif_running(lif->netdev)) { 884 err = ionic_lif_txq_init(lif, txq); 885 if (err) 886 goto err_qcq_init; 887 888 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 889 err = ionic_qcq_enable(txq); 890 if (err) 891 goto err_qcq_enable; 892 } 893 } 894 895 return 0; 896 897 err_qcq_enable: 898 ionic_lif_qcq_deinit(lif, txq); 899 err_qcq_init: 900 lif->hwstamp_txq = NULL; 901 ionic_debugfs_del_qcq(txq); 902 ionic_qcq_free(lif, txq); 903 devm_kfree(lif->ionic->dev, txq); 904 err_qcq_alloc: 905 return err; 906 } 907 908 int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif) 909 { 910 unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz; 911 unsigned int rxq_i, flags; 912 struct ionic_qcq *rxq; 913 u64 features; 914 int err; 915 916 if (lif->hwstamp_rxq) 917 return 0; 918 919 features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 920 921 num_desc = IONIC_MIN_TXRX_DESC; 922 desc_sz = sizeof(struct ionic_rxq_desc); 923 comp_sz = 2 * sizeof(struct ionic_rxq_comp); 924 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 925 926 rxq_i = lif->ionic->nrxqs_per_lif; 927 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG; 928 929 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags, 930 num_desc, desc_sz, comp_sz, sg_desc_sz, 931 lif->kern_pid, &rxq); 932 if (err) 933 goto err_qcq_alloc; 934 935 rxq->q.features = features; 936 937 ionic_link_qcq_interrupts(lif->adminqcq, rxq); 938 ionic_debugfs_add_qcq(lif, rxq); 939 940 lif->hwstamp_rxq = rxq; 941 942 if (netif_running(lif->netdev)) { 943 err = ionic_lif_rxq_init(lif, rxq); 944 if (err) 945 goto err_qcq_init; 946 947 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 948 ionic_rx_fill(&rxq->q); 949 err = ionic_qcq_enable(rxq); 950 if (err) 951 goto err_qcq_enable; 952 } 953 } 954 955 return 0; 956 957 err_qcq_enable: 958 ionic_lif_qcq_deinit(lif, rxq); 959 err_qcq_init: 960 lif->hwstamp_rxq = NULL; 961 ionic_debugfs_del_qcq(rxq); 962 ionic_qcq_free(lif, rxq); 963 devm_kfree(lif->ionic->dev, rxq); 964 err_qcq_alloc: 965 return err; 966 } 967 968 int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all) 969 { 970 struct ionic_queue_params qparam; 971 972 ionic_init_queue_params(lif, &qparam); 973 974 if (rx_all) 975 qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP; 976 else 977 qparam.rxq_features = 0; 978 979 /* if we're not running, just set the values and return */ 980 if (!netif_running(lif->netdev)) { 981 lif->rxq_features = qparam.rxq_features; 982 return 0; 983 } 984 985 return ionic_reconfigure_queues(lif, &qparam); 986 } 987 988 int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode) 989 { 990 struct ionic_admin_ctx ctx = { 991 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 992 .cmd.lif_setattr = { 993 .opcode = IONIC_CMD_LIF_SETATTR, 994 .index = cpu_to_le16(lif->index), 995 .attr = IONIC_LIF_ATTR_TXSTAMP, 996 .txstamp_mode = cpu_to_le16(txstamp_mode), 997 }, 998 }; 999 1000 return ionic_adminq_post_wait(lif, &ctx); 1001 } 1002 1003 static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif) 1004 { 1005 struct ionic_admin_ctx ctx = { 1006 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1007 .cmd.rx_filter_del = { 1008 .opcode = IONIC_CMD_RX_FILTER_DEL, 1009 .lif_index = cpu_to_le16(lif->index), 1010 }, 1011 }; 1012 struct ionic_rx_filter *f; 1013 u32 filter_id; 1014 int err; 1015 1016 spin_lock_bh(&lif->rx_filters.lock); 1017 1018 f = ionic_rx_filter_rxsteer(lif); 1019 if (!f) { 1020 spin_unlock_bh(&lif->rx_filters.lock); 1021 return; 1022 } 1023 1024 filter_id = f->filter_id; 1025 ionic_rx_filter_free(lif, f); 1026 1027 spin_unlock_bh(&lif->rx_filters.lock); 1028 1029 netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id); 1030 1031 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id); 1032 1033 err = ionic_adminq_post_wait(lif, &ctx); 1034 if (err && err != -EEXIST) 1035 netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id); 1036 } 1037 1038 static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1039 { 1040 struct ionic_admin_ctx ctx = { 1041 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1042 .cmd.rx_filter_add = { 1043 .opcode = IONIC_CMD_RX_FILTER_ADD, 1044 .lif_index = cpu_to_le16(lif->index), 1045 .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS), 1046 .pkt_class = cpu_to_le64(pkt_class), 1047 }, 1048 }; 1049 u8 qtype; 1050 u32 qid; 1051 int err; 1052 1053 if (!lif->hwstamp_rxq) 1054 return -EINVAL; 1055 1056 qtype = lif->hwstamp_rxq->q.type; 1057 ctx.cmd.rx_filter_add.qtype = qtype; 1058 1059 qid = lif->hwstamp_rxq->q.index; 1060 ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid); 1061 1062 netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n"); 1063 err = ionic_adminq_post_wait(lif, &ctx); 1064 if (err && err != -EEXIST) 1065 return err; 1066 1067 spin_lock_bh(&lif->rx_filters.lock); 1068 err = ionic_rx_filter_save(lif, 0, qid, 0, &ctx, IONIC_FILTER_STATE_SYNCED); 1069 spin_unlock_bh(&lif->rx_filters.lock); 1070 1071 return err; 1072 } 1073 1074 int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class) 1075 { 1076 ionic_lif_del_hwstamp_rxfilt(lif); 1077 1078 if (!pkt_class) 1079 return 0; 1080 1081 return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class); 1082 } 1083 1084 static bool ionic_notifyq_service(struct ionic_cq *cq, 1085 struct ionic_cq_info *cq_info) 1086 { 1087 union ionic_notifyq_comp *comp = cq_info->cq_desc; 1088 struct ionic_deferred_work *work; 1089 struct net_device *netdev; 1090 struct ionic_queue *q; 1091 struct ionic_lif *lif; 1092 u64 eid; 1093 1094 q = cq->bound_q; 1095 lif = q->info[0].cb_arg; 1096 netdev = lif->netdev; 1097 eid = le64_to_cpu(comp->event.eid); 1098 1099 /* Have we run out of new completions to process? */ 1100 if ((s64)(eid - lif->last_eid) <= 0) 1101 return false; 1102 1103 lif->last_eid = eid; 1104 1105 dev_dbg(lif->ionic->dev, "notifyq event:\n"); 1106 dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1, 1107 comp, sizeof(*comp), true); 1108 1109 switch (le16_to_cpu(comp->event.ecode)) { 1110 case IONIC_EVENT_LINK_CHANGE: 1111 ionic_link_status_check_request(lif, CAN_NOT_SLEEP); 1112 break; 1113 case IONIC_EVENT_RESET: 1114 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1115 if (!work) { 1116 netdev_err(lif->netdev, "Reset event dropped\n"); 1117 } else { 1118 work->type = IONIC_DW_TYPE_LIF_RESET; 1119 ionic_lif_deferred_enqueue(&lif->deferred, work); 1120 } 1121 break; 1122 default: 1123 netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n", 1124 comp->event.ecode, eid); 1125 break; 1126 } 1127 1128 return true; 1129 } 1130 1131 static bool ionic_adminq_service(struct ionic_cq *cq, 1132 struct ionic_cq_info *cq_info) 1133 { 1134 struct ionic_admin_comp *comp = cq_info->cq_desc; 1135 1136 if (!color_match(comp->color, cq->done_color)) 1137 return false; 1138 1139 ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index)); 1140 1141 return true; 1142 } 1143 1144 static int ionic_adminq_napi(struct napi_struct *napi, int budget) 1145 { 1146 struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr; 1147 struct ionic_lif *lif = napi_to_cq(napi)->lif; 1148 struct ionic_dev *idev = &lif->ionic->idev; 1149 unsigned long irqflags; 1150 unsigned int flags = 0; 1151 int rx_work = 0; 1152 int tx_work = 0; 1153 int n_work = 0; 1154 int a_work = 0; 1155 int work_done; 1156 int credits; 1157 1158 if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED) 1159 n_work = ionic_cq_service(&lif->notifyqcq->cq, budget, 1160 ionic_notifyq_service, NULL, NULL); 1161 1162 spin_lock_irqsave(&lif->adminq_lock, irqflags); 1163 if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED) 1164 a_work = ionic_cq_service(&lif->adminqcq->cq, budget, 1165 ionic_adminq_service, NULL, NULL); 1166 spin_unlock_irqrestore(&lif->adminq_lock, irqflags); 1167 1168 if (lif->hwstamp_rxq) 1169 rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget, 1170 ionic_rx_service, NULL, NULL); 1171 1172 if (lif->hwstamp_txq) 1173 tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget, 1174 ionic_tx_service, NULL, NULL); 1175 1176 work_done = max(max(n_work, a_work), max(rx_work, tx_work)); 1177 if (work_done < budget && napi_complete_done(napi, work_done)) { 1178 flags |= IONIC_INTR_CRED_UNMASK; 1179 intr->rearm_count++; 1180 } 1181 1182 if (work_done || flags) { 1183 flags |= IONIC_INTR_CRED_RESET_COALESCE; 1184 credits = n_work + a_work + rx_work + tx_work; 1185 ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags); 1186 } 1187 1188 return work_done; 1189 } 1190 1191 void ionic_get_stats64(struct net_device *netdev, 1192 struct rtnl_link_stats64 *ns) 1193 { 1194 struct ionic_lif *lif = netdev_priv(netdev); 1195 struct ionic_lif_stats *ls; 1196 1197 memset(ns, 0, sizeof(*ns)); 1198 ls = &lif->info->stats; 1199 1200 ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) + 1201 le64_to_cpu(ls->rx_mcast_packets) + 1202 le64_to_cpu(ls->rx_bcast_packets); 1203 1204 ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) + 1205 le64_to_cpu(ls->tx_mcast_packets) + 1206 le64_to_cpu(ls->tx_bcast_packets); 1207 1208 ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) + 1209 le64_to_cpu(ls->rx_mcast_bytes) + 1210 le64_to_cpu(ls->rx_bcast_bytes); 1211 1212 ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) + 1213 le64_to_cpu(ls->tx_mcast_bytes) + 1214 le64_to_cpu(ls->tx_bcast_bytes); 1215 1216 ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) + 1217 le64_to_cpu(ls->rx_mcast_drop_packets) + 1218 le64_to_cpu(ls->rx_bcast_drop_packets); 1219 1220 ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) + 1221 le64_to_cpu(ls->tx_mcast_drop_packets) + 1222 le64_to_cpu(ls->tx_bcast_drop_packets); 1223 1224 ns->multicast = le64_to_cpu(ls->rx_mcast_packets); 1225 1226 ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty); 1227 1228 ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) + 1229 le64_to_cpu(ls->rx_queue_disabled) + 1230 le64_to_cpu(ls->rx_desc_fetch_error) + 1231 le64_to_cpu(ls->rx_desc_data_error); 1232 1233 ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) + 1234 le64_to_cpu(ls->tx_queue_disabled) + 1235 le64_to_cpu(ls->tx_desc_fetch_error) + 1236 le64_to_cpu(ls->tx_desc_data_error); 1237 1238 ns->rx_errors = ns->rx_over_errors + 1239 ns->rx_missed_errors; 1240 1241 ns->tx_errors = ns->tx_aborted_errors; 1242 } 1243 1244 int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr) 1245 { 1246 struct ionic_admin_ctx ctx = { 1247 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1248 .cmd.rx_filter_add = { 1249 .opcode = IONIC_CMD_RX_FILTER_ADD, 1250 .lif_index = cpu_to_le16(lif->index), 1251 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC), 1252 }, 1253 }; 1254 int nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1255 bool mc = is_multicast_ether_addr(addr); 1256 struct ionic_rx_filter *f; 1257 int err = 0; 1258 1259 memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN); 1260 1261 spin_lock_bh(&lif->rx_filters.lock); 1262 f = ionic_rx_filter_by_addr(lif, addr); 1263 if (f) { 1264 /* don't bother if we already have it and it is sync'd */ 1265 if (f->state == IONIC_FILTER_STATE_SYNCED) { 1266 spin_unlock_bh(&lif->rx_filters.lock); 1267 return 0; 1268 } 1269 1270 /* mark preemptively as sync'd to block any parallel attempts */ 1271 f->state = IONIC_FILTER_STATE_SYNCED; 1272 } else { 1273 /* save as SYNCED to catch any DEL requests while processing */ 1274 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1275 IONIC_FILTER_STATE_SYNCED); 1276 } 1277 spin_unlock_bh(&lif->rx_filters.lock); 1278 if (err) 1279 return err; 1280 1281 netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr); 1282 1283 /* Don't bother with the write to FW if we know there's no room, 1284 * we can try again on the next sync attempt. 1285 */ 1286 if ((lif->nucast + lif->nmcast) >= nfilters) 1287 err = -ENOSPC; 1288 else 1289 err = ionic_adminq_post_wait(lif, &ctx); 1290 1291 spin_lock_bh(&lif->rx_filters.lock); 1292 if (err && err != -EEXIST) { 1293 /* set the state back to NEW so we can try again later */ 1294 f = ionic_rx_filter_by_addr(lif, addr); 1295 if (f && f->state == IONIC_FILTER_STATE_SYNCED) 1296 f->state = IONIC_FILTER_STATE_NEW; 1297 1298 spin_unlock_bh(&lif->rx_filters.lock); 1299 1300 if (err == -ENOSPC) 1301 return 0; 1302 else 1303 return err; 1304 } 1305 1306 if (mc) 1307 lif->nmcast++; 1308 else 1309 lif->nucast++; 1310 1311 f = ionic_rx_filter_by_addr(lif, addr); 1312 if (f && f->state == IONIC_FILTER_STATE_OLD) { 1313 /* Someone requested a delete while we were adding 1314 * so update the filter info with the results from the add 1315 * and the data will be there for the delete on the next 1316 * sync cycle. 1317 */ 1318 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1319 IONIC_FILTER_STATE_OLD); 1320 } else { 1321 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1322 IONIC_FILTER_STATE_SYNCED); 1323 } 1324 1325 spin_unlock_bh(&lif->rx_filters.lock); 1326 1327 return err; 1328 } 1329 1330 int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr) 1331 { 1332 struct ionic_admin_ctx ctx = { 1333 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1334 .cmd.rx_filter_del = { 1335 .opcode = IONIC_CMD_RX_FILTER_DEL, 1336 .lif_index = cpu_to_le16(lif->index), 1337 }, 1338 }; 1339 struct ionic_rx_filter *f; 1340 int state; 1341 int err; 1342 1343 spin_lock_bh(&lif->rx_filters.lock); 1344 f = ionic_rx_filter_by_addr(lif, addr); 1345 if (!f) { 1346 spin_unlock_bh(&lif->rx_filters.lock); 1347 return -ENOENT; 1348 } 1349 1350 netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n", 1351 addr, f->filter_id); 1352 1353 state = f->state; 1354 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1355 ionic_rx_filter_free(lif, f); 1356 1357 if (is_multicast_ether_addr(addr) && lif->nmcast) 1358 lif->nmcast--; 1359 else if (!is_multicast_ether_addr(addr) && lif->nucast) 1360 lif->nucast--; 1361 1362 spin_unlock_bh(&lif->rx_filters.lock); 1363 1364 if (state != IONIC_FILTER_STATE_NEW) { 1365 err = ionic_adminq_post_wait(lif, &ctx); 1366 if (err && err != -EEXIST) 1367 return err; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int ionic_addr_add(struct net_device *netdev, const u8 *addr) 1374 { 1375 return ionic_lif_list_addr(netdev_priv(netdev), addr, ADD_ADDR); 1376 } 1377 1378 static int ionic_addr_del(struct net_device *netdev, const u8 *addr) 1379 { 1380 return ionic_lif_list_addr(netdev_priv(netdev), addr, DEL_ADDR); 1381 } 1382 1383 void ionic_lif_rx_mode(struct ionic_lif *lif) 1384 { 1385 struct net_device *netdev = lif->netdev; 1386 unsigned int nfilters; 1387 unsigned int nd_flags; 1388 char buf[128]; 1389 u16 rx_mode; 1390 int i; 1391 #define REMAIN(__x) (sizeof(buf) - (__x)) 1392 1393 mutex_lock(&lif->config_lock); 1394 1395 /* grab the flags once for local use */ 1396 nd_flags = netdev->flags; 1397 1398 rx_mode = IONIC_RX_MODE_F_UNICAST; 1399 rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0; 1400 rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0; 1401 rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0; 1402 rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0; 1403 1404 /* sync the mac filters */ 1405 ionic_rx_filter_sync(lif); 1406 1407 /* check for overflow state 1408 * if so, we track that we overflowed and enable NIC PROMISC 1409 * else if the overflow is set and not needed 1410 * we remove our overflow flag and check the netdev flags 1411 * to see if we can disable NIC PROMISC 1412 */ 1413 nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters); 1414 if ((lif->nucast + lif->nmcast) >= nfilters) { 1415 rx_mode |= IONIC_RX_MODE_F_PROMISC; 1416 rx_mode |= IONIC_RX_MODE_F_ALLMULTI; 1417 lif->uc_overflow = true; 1418 lif->mc_overflow = true; 1419 } else if (lif->uc_overflow) { 1420 lif->uc_overflow = false; 1421 lif->mc_overflow = false; 1422 if (!(nd_flags & IFF_PROMISC)) 1423 rx_mode &= ~IONIC_RX_MODE_F_PROMISC; 1424 if (!(nd_flags & IFF_ALLMULTI)) 1425 rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI; 1426 } 1427 1428 i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:", 1429 lif->rx_mode, rx_mode); 1430 if (rx_mode & IONIC_RX_MODE_F_UNICAST) 1431 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST"); 1432 if (rx_mode & IONIC_RX_MODE_F_MULTICAST) 1433 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST"); 1434 if (rx_mode & IONIC_RX_MODE_F_BROADCAST) 1435 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST"); 1436 if (rx_mode & IONIC_RX_MODE_F_PROMISC) 1437 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC"); 1438 if (rx_mode & IONIC_RX_MODE_F_ALLMULTI) 1439 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI"); 1440 if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER) 1441 i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER"); 1442 netdev_dbg(netdev, "lif%d %s\n", lif->index, buf); 1443 1444 if (lif->rx_mode != rx_mode) { 1445 struct ionic_admin_ctx ctx = { 1446 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1447 .cmd.rx_mode_set = { 1448 .opcode = IONIC_CMD_RX_MODE_SET, 1449 .lif_index = cpu_to_le16(lif->index), 1450 }, 1451 }; 1452 int err; 1453 1454 ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode); 1455 err = ionic_adminq_post_wait(lif, &ctx); 1456 if (err) 1457 netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n", 1458 rx_mode, err); 1459 else 1460 lif->rx_mode = rx_mode; 1461 } 1462 1463 mutex_unlock(&lif->config_lock); 1464 } 1465 1466 static void ionic_ndo_set_rx_mode(struct net_device *netdev) 1467 { 1468 struct ionic_lif *lif = netdev_priv(netdev); 1469 struct ionic_deferred_work *work; 1470 1471 /* Sync the kernel filter list with the driver filter list */ 1472 __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del); 1473 __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del); 1474 1475 /* Shove off the rest of the rxmode work to the work task 1476 * which will include syncing the filters to the firmware. 1477 */ 1478 work = kzalloc(sizeof(*work), GFP_ATOMIC); 1479 if (!work) { 1480 netdev_err(lif->netdev, "rxmode change dropped\n"); 1481 return; 1482 } 1483 work->type = IONIC_DW_TYPE_RX_MODE; 1484 netdev_dbg(lif->netdev, "deferred: rx_mode\n"); 1485 ionic_lif_deferred_enqueue(&lif->deferred, work); 1486 } 1487 1488 static __le64 ionic_netdev_features_to_nic(netdev_features_t features) 1489 { 1490 u64 wanted = 0; 1491 1492 if (features & NETIF_F_HW_VLAN_CTAG_TX) 1493 wanted |= IONIC_ETH_HW_VLAN_TX_TAG; 1494 if (features & NETIF_F_HW_VLAN_CTAG_RX) 1495 wanted |= IONIC_ETH_HW_VLAN_RX_STRIP; 1496 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1497 wanted |= IONIC_ETH_HW_VLAN_RX_FILTER; 1498 if (features & NETIF_F_RXHASH) 1499 wanted |= IONIC_ETH_HW_RX_HASH; 1500 if (features & NETIF_F_RXCSUM) 1501 wanted |= IONIC_ETH_HW_RX_CSUM; 1502 if (features & NETIF_F_SG) 1503 wanted |= IONIC_ETH_HW_TX_SG; 1504 if (features & NETIF_F_HW_CSUM) 1505 wanted |= IONIC_ETH_HW_TX_CSUM; 1506 if (features & NETIF_F_TSO) 1507 wanted |= IONIC_ETH_HW_TSO; 1508 if (features & NETIF_F_TSO6) 1509 wanted |= IONIC_ETH_HW_TSO_IPV6; 1510 if (features & NETIF_F_TSO_ECN) 1511 wanted |= IONIC_ETH_HW_TSO_ECN; 1512 if (features & NETIF_F_GSO_GRE) 1513 wanted |= IONIC_ETH_HW_TSO_GRE; 1514 if (features & NETIF_F_GSO_GRE_CSUM) 1515 wanted |= IONIC_ETH_HW_TSO_GRE_CSUM; 1516 if (features & NETIF_F_GSO_IPXIP4) 1517 wanted |= IONIC_ETH_HW_TSO_IPXIP4; 1518 if (features & NETIF_F_GSO_IPXIP6) 1519 wanted |= IONIC_ETH_HW_TSO_IPXIP6; 1520 if (features & NETIF_F_GSO_UDP_TUNNEL) 1521 wanted |= IONIC_ETH_HW_TSO_UDP; 1522 if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM) 1523 wanted |= IONIC_ETH_HW_TSO_UDP_CSUM; 1524 1525 return cpu_to_le64(wanted); 1526 } 1527 1528 static int ionic_set_nic_features(struct ionic_lif *lif, 1529 netdev_features_t features) 1530 { 1531 struct device *dev = lif->ionic->dev; 1532 struct ionic_admin_ctx ctx = { 1533 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1534 .cmd.lif_setattr = { 1535 .opcode = IONIC_CMD_LIF_SETATTR, 1536 .index = cpu_to_le16(lif->index), 1537 .attr = IONIC_LIF_ATTR_FEATURES, 1538 }, 1539 }; 1540 u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG | 1541 IONIC_ETH_HW_VLAN_RX_STRIP | 1542 IONIC_ETH_HW_VLAN_RX_FILTER; 1543 u64 old_hw_features; 1544 int err; 1545 1546 ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features); 1547 1548 if (lif->phc) 1549 ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP); 1550 1551 err = ionic_adminq_post_wait(lif, &ctx); 1552 if (err) 1553 return err; 1554 1555 old_hw_features = lif->hw_features; 1556 lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features & 1557 ctx.comp.lif_setattr.features); 1558 1559 if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH) 1560 ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1561 1562 if ((vlan_flags & features) && 1563 !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features))) 1564 dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n"); 1565 1566 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1567 dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n"); 1568 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1569 dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n"); 1570 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1571 dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n"); 1572 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1573 dev_dbg(dev, "feature ETH_HW_RX_HASH\n"); 1574 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1575 dev_dbg(dev, "feature ETH_HW_TX_SG\n"); 1576 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1577 dev_dbg(dev, "feature ETH_HW_TX_CSUM\n"); 1578 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1579 dev_dbg(dev, "feature ETH_HW_RX_CSUM\n"); 1580 if (lif->hw_features & IONIC_ETH_HW_TSO) 1581 dev_dbg(dev, "feature ETH_HW_TSO\n"); 1582 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1583 dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n"); 1584 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1585 dev_dbg(dev, "feature ETH_HW_TSO_ECN\n"); 1586 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1587 dev_dbg(dev, "feature ETH_HW_TSO_GRE\n"); 1588 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1589 dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n"); 1590 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1591 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n"); 1592 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1593 dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n"); 1594 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1595 dev_dbg(dev, "feature ETH_HW_TSO_UDP\n"); 1596 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1597 dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n"); 1598 if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP) 1599 dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n"); 1600 1601 return 0; 1602 } 1603 1604 static int ionic_init_nic_features(struct ionic_lif *lif) 1605 { 1606 struct net_device *netdev = lif->netdev; 1607 netdev_features_t features; 1608 int err; 1609 1610 /* set up what we expect to support by default */ 1611 features = NETIF_F_HW_VLAN_CTAG_TX | 1612 NETIF_F_HW_VLAN_CTAG_RX | 1613 NETIF_F_HW_VLAN_CTAG_FILTER | 1614 NETIF_F_SG | 1615 NETIF_F_HW_CSUM | 1616 NETIF_F_RXCSUM | 1617 NETIF_F_TSO | 1618 NETIF_F_TSO6 | 1619 NETIF_F_TSO_ECN; 1620 1621 if (lif->nxqs > 1) 1622 features |= NETIF_F_RXHASH; 1623 1624 err = ionic_set_nic_features(lif, features); 1625 if (err) 1626 return err; 1627 1628 /* tell the netdev what we actually can support */ 1629 netdev->features |= NETIF_F_HIGHDMA; 1630 1631 if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG) 1632 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 1633 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP) 1634 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 1635 if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER) 1636 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1637 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) 1638 netdev->hw_features |= NETIF_F_RXHASH; 1639 if (lif->hw_features & IONIC_ETH_HW_TX_SG) 1640 netdev->hw_features |= NETIF_F_SG; 1641 1642 if (lif->hw_features & IONIC_ETH_HW_TX_CSUM) 1643 netdev->hw_enc_features |= NETIF_F_HW_CSUM; 1644 if (lif->hw_features & IONIC_ETH_HW_RX_CSUM) 1645 netdev->hw_enc_features |= NETIF_F_RXCSUM; 1646 if (lif->hw_features & IONIC_ETH_HW_TSO) 1647 netdev->hw_enc_features |= NETIF_F_TSO; 1648 if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6) 1649 netdev->hw_enc_features |= NETIF_F_TSO6; 1650 if (lif->hw_features & IONIC_ETH_HW_TSO_ECN) 1651 netdev->hw_enc_features |= NETIF_F_TSO_ECN; 1652 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE) 1653 netdev->hw_enc_features |= NETIF_F_GSO_GRE; 1654 if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM) 1655 netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM; 1656 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4) 1657 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4; 1658 if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6) 1659 netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6; 1660 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP) 1661 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL; 1662 if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM) 1663 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM; 1664 1665 netdev->hw_features |= netdev->hw_enc_features; 1666 netdev->features |= netdev->hw_features; 1667 netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES; 1668 1669 netdev->priv_flags |= IFF_UNICAST_FLT | 1670 IFF_LIVE_ADDR_CHANGE; 1671 1672 return 0; 1673 } 1674 1675 static int ionic_set_features(struct net_device *netdev, 1676 netdev_features_t features) 1677 { 1678 struct ionic_lif *lif = netdev_priv(netdev); 1679 int err; 1680 1681 netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n", 1682 __func__, (u64)lif->netdev->features, (u64)features); 1683 1684 err = ionic_set_nic_features(lif, features); 1685 1686 return err; 1687 } 1688 1689 static int ionic_set_mac_address(struct net_device *netdev, void *sa) 1690 { 1691 struct sockaddr *addr = sa; 1692 u8 *mac; 1693 int err; 1694 1695 mac = (u8 *)addr->sa_data; 1696 if (ether_addr_equal(netdev->dev_addr, mac)) 1697 return 0; 1698 1699 err = eth_prepare_mac_addr_change(netdev, addr); 1700 if (err) 1701 return err; 1702 1703 if (!is_zero_ether_addr(netdev->dev_addr)) { 1704 netdev_info(netdev, "deleting mac addr %pM\n", 1705 netdev->dev_addr); 1706 ionic_lif_addr_del(netdev_priv(netdev), netdev->dev_addr); 1707 } 1708 1709 eth_commit_mac_addr_change(netdev, addr); 1710 netdev_info(netdev, "updating mac addr %pM\n", mac); 1711 1712 return ionic_lif_addr_add(netdev_priv(netdev), mac); 1713 } 1714 1715 static void ionic_stop_queues_reconfig(struct ionic_lif *lif) 1716 { 1717 /* Stop and clean the queues before reconfiguration */ 1718 mutex_lock(&lif->queue_lock); 1719 netif_device_detach(lif->netdev); 1720 ionic_stop_queues(lif); 1721 ionic_txrx_deinit(lif); 1722 } 1723 1724 static int ionic_start_queues_reconfig(struct ionic_lif *lif) 1725 { 1726 int err; 1727 1728 /* Re-init the queues after reconfiguration */ 1729 1730 /* The only way txrx_init can fail here is if communication 1731 * with FW is suddenly broken. There's not much we can do 1732 * at this point - error messages have already been printed, 1733 * so we can continue on and the user can eventually do a 1734 * DOWN and UP to try to reset and clear the issue. 1735 */ 1736 err = ionic_txrx_init(lif); 1737 mutex_unlock(&lif->queue_lock); 1738 ionic_link_status_check_request(lif, CAN_SLEEP); 1739 netif_device_attach(lif->netdev); 1740 1741 return err; 1742 } 1743 1744 static int ionic_change_mtu(struct net_device *netdev, int new_mtu) 1745 { 1746 struct ionic_lif *lif = netdev_priv(netdev); 1747 struct ionic_admin_ctx ctx = { 1748 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1749 .cmd.lif_setattr = { 1750 .opcode = IONIC_CMD_LIF_SETATTR, 1751 .index = cpu_to_le16(lif->index), 1752 .attr = IONIC_LIF_ATTR_MTU, 1753 .mtu = cpu_to_le32(new_mtu), 1754 }, 1755 }; 1756 int err; 1757 1758 err = ionic_adminq_post_wait(lif, &ctx); 1759 if (err) 1760 return err; 1761 1762 /* if we're not running, nothing more to do */ 1763 if (!netif_running(netdev)) { 1764 netdev->mtu = new_mtu; 1765 return 0; 1766 } 1767 1768 ionic_stop_queues_reconfig(lif); 1769 netdev->mtu = new_mtu; 1770 return ionic_start_queues_reconfig(lif); 1771 } 1772 1773 static void ionic_tx_timeout_work(struct work_struct *ws) 1774 { 1775 struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work); 1776 1777 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 1778 return; 1779 1780 /* if we were stopped before this scheduled job was launched, 1781 * don't bother the queues as they are already stopped. 1782 */ 1783 if (!netif_running(lif->netdev)) 1784 return; 1785 1786 ionic_stop_queues_reconfig(lif); 1787 ionic_start_queues_reconfig(lif); 1788 } 1789 1790 static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue) 1791 { 1792 struct ionic_lif *lif = netdev_priv(netdev); 1793 1794 netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue); 1795 schedule_work(&lif->tx_timeout_work); 1796 } 1797 1798 static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto, 1799 u16 vid) 1800 { 1801 struct ionic_lif *lif = netdev_priv(netdev); 1802 struct ionic_admin_ctx ctx = { 1803 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1804 .cmd.rx_filter_add = { 1805 .opcode = IONIC_CMD_RX_FILTER_ADD, 1806 .lif_index = cpu_to_le16(lif->index), 1807 .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN), 1808 .vlan.vlan = cpu_to_le16(vid), 1809 }, 1810 }; 1811 int err; 1812 1813 netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid); 1814 err = ionic_adminq_post_wait(lif, &ctx); 1815 if (err) 1816 return err; 1817 1818 spin_lock_bh(&lif->rx_filters.lock); 1819 err = ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx, 1820 IONIC_FILTER_STATE_SYNCED); 1821 spin_unlock_bh(&lif->rx_filters.lock); 1822 1823 return err; 1824 } 1825 1826 static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, 1827 u16 vid) 1828 { 1829 struct ionic_lif *lif = netdev_priv(netdev); 1830 struct ionic_admin_ctx ctx = { 1831 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1832 .cmd.rx_filter_del = { 1833 .opcode = IONIC_CMD_RX_FILTER_DEL, 1834 .lif_index = cpu_to_le16(lif->index), 1835 }, 1836 }; 1837 struct ionic_rx_filter *f; 1838 1839 spin_lock_bh(&lif->rx_filters.lock); 1840 1841 f = ionic_rx_filter_by_vlan(lif, vid); 1842 if (!f) { 1843 spin_unlock_bh(&lif->rx_filters.lock); 1844 return -ENOENT; 1845 } 1846 1847 netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n", 1848 vid, f->filter_id); 1849 1850 ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id); 1851 ionic_rx_filter_free(lif, f); 1852 spin_unlock_bh(&lif->rx_filters.lock); 1853 1854 return ionic_adminq_post_wait(lif, &ctx); 1855 } 1856 1857 int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types, 1858 const u8 *key, const u32 *indir) 1859 { 1860 struct ionic_admin_ctx ctx = { 1861 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1862 .cmd.lif_setattr = { 1863 .opcode = IONIC_CMD_LIF_SETATTR, 1864 .attr = IONIC_LIF_ATTR_RSS, 1865 .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa), 1866 }, 1867 }; 1868 unsigned int i, tbl_sz; 1869 1870 if (lif->hw_features & IONIC_ETH_HW_RX_HASH) { 1871 lif->rss_types = types; 1872 ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types); 1873 } 1874 1875 if (key) 1876 memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE); 1877 1878 if (indir) { 1879 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1880 for (i = 0; i < tbl_sz; i++) 1881 lif->rss_ind_tbl[i] = indir[i]; 1882 } 1883 1884 memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key, 1885 IONIC_RSS_HASH_KEY_SIZE); 1886 1887 return ionic_adminq_post_wait(lif, &ctx); 1888 } 1889 1890 static int ionic_lif_rss_init(struct ionic_lif *lif) 1891 { 1892 unsigned int tbl_sz; 1893 unsigned int i; 1894 1895 lif->rss_types = IONIC_RSS_TYPE_IPV4 | 1896 IONIC_RSS_TYPE_IPV4_TCP | 1897 IONIC_RSS_TYPE_IPV4_UDP | 1898 IONIC_RSS_TYPE_IPV6 | 1899 IONIC_RSS_TYPE_IPV6_TCP | 1900 IONIC_RSS_TYPE_IPV6_UDP; 1901 1902 /* Fill indirection table with 'default' values */ 1903 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1904 for (i = 0; i < tbl_sz; i++) 1905 lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs); 1906 1907 return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL); 1908 } 1909 1910 static void ionic_lif_rss_deinit(struct ionic_lif *lif) 1911 { 1912 int tbl_sz; 1913 1914 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 1915 memset(lif->rss_ind_tbl, 0, tbl_sz); 1916 memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE); 1917 1918 ionic_lif_rss_config(lif, 0x0, NULL, NULL); 1919 } 1920 1921 static void ionic_lif_quiesce(struct ionic_lif *lif) 1922 { 1923 struct ionic_admin_ctx ctx = { 1924 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 1925 .cmd.lif_setattr = { 1926 .opcode = IONIC_CMD_LIF_SETATTR, 1927 .index = cpu_to_le16(lif->index), 1928 .attr = IONIC_LIF_ATTR_STATE, 1929 .state = IONIC_LIF_QUIESCE, 1930 }, 1931 }; 1932 int err; 1933 1934 err = ionic_adminq_post_wait(lif, &ctx); 1935 if (err) 1936 netdev_err(lif->netdev, "lif quiesce failed %d\n", err); 1937 } 1938 1939 static void ionic_txrx_disable(struct ionic_lif *lif) 1940 { 1941 unsigned int i; 1942 int err = 0; 1943 1944 if (lif->txqcqs) { 1945 for (i = 0; i < lif->nxqs; i++) 1946 err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT)); 1947 } 1948 1949 if (lif->hwstamp_txq) 1950 err = ionic_qcq_disable(lif->hwstamp_txq, (err != -ETIMEDOUT)); 1951 1952 if (lif->rxqcqs) { 1953 for (i = 0; i < lif->nxqs; i++) 1954 err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 1955 } 1956 1957 if (lif->hwstamp_rxq) 1958 err = ionic_qcq_disable(lif->hwstamp_rxq, (err != -ETIMEDOUT)); 1959 1960 ionic_lif_quiesce(lif); 1961 } 1962 1963 static void ionic_txrx_deinit(struct ionic_lif *lif) 1964 { 1965 unsigned int i; 1966 1967 if (lif->txqcqs) { 1968 for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) { 1969 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 1970 ionic_tx_flush(&lif->txqcqs[i]->cq); 1971 ionic_tx_empty(&lif->txqcqs[i]->q); 1972 } 1973 } 1974 1975 if (lif->rxqcqs) { 1976 for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) { 1977 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 1978 ionic_rx_empty(&lif->rxqcqs[i]->q); 1979 } 1980 } 1981 lif->rx_mode = 0; 1982 1983 if (lif->hwstamp_txq) { 1984 ionic_lif_qcq_deinit(lif, lif->hwstamp_txq); 1985 ionic_tx_flush(&lif->hwstamp_txq->cq); 1986 ionic_tx_empty(&lif->hwstamp_txq->q); 1987 } 1988 1989 if (lif->hwstamp_rxq) { 1990 ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq); 1991 ionic_rx_empty(&lif->hwstamp_rxq->q); 1992 } 1993 } 1994 1995 static void ionic_txrx_free(struct ionic_lif *lif) 1996 { 1997 unsigned int i; 1998 1999 if (lif->txqcqs) { 2000 for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) { 2001 ionic_qcq_free(lif, lif->txqcqs[i]); 2002 devm_kfree(lif->ionic->dev, lif->txqcqs[i]); 2003 lif->txqcqs[i] = NULL; 2004 } 2005 } 2006 2007 if (lif->rxqcqs) { 2008 for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) { 2009 ionic_qcq_free(lif, lif->rxqcqs[i]); 2010 devm_kfree(lif->ionic->dev, lif->rxqcqs[i]); 2011 lif->rxqcqs[i] = NULL; 2012 } 2013 } 2014 2015 if (lif->hwstamp_txq) { 2016 ionic_qcq_free(lif, lif->hwstamp_txq); 2017 devm_kfree(lif->ionic->dev, lif->hwstamp_txq); 2018 lif->hwstamp_txq = NULL; 2019 } 2020 2021 if (lif->hwstamp_rxq) { 2022 ionic_qcq_free(lif, lif->hwstamp_rxq); 2023 devm_kfree(lif->ionic->dev, lif->hwstamp_rxq); 2024 lif->hwstamp_rxq = NULL; 2025 } 2026 } 2027 2028 static int ionic_txrx_alloc(struct ionic_lif *lif) 2029 { 2030 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2031 unsigned int flags, i; 2032 int err = 0; 2033 2034 num_desc = lif->ntxq_descs; 2035 desc_sz = sizeof(struct ionic_txq_desc); 2036 comp_sz = sizeof(struct ionic_txq_comp); 2037 2038 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2039 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2040 sizeof(struct ionic_txq_sg_desc_v1)) 2041 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2042 else 2043 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2044 2045 flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG; 2046 if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2047 flags |= IONIC_QCQ_F_INTR; 2048 for (i = 0; i < lif->nxqs; i++) { 2049 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2050 num_desc, desc_sz, comp_sz, sg_desc_sz, 2051 lif->kern_pid, &lif->txqcqs[i]); 2052 if (err) 2053 goto err_out; 2054 2055 if (flags & IONIC_QCQ_F_INTR) { 2056 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2057 lif->txqcqs[i]->intr.index, 2058 lif->tx_coalesce_hw); 2059 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2060 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2061 } 2062 2063 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2064 } 2065 2066 flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG | IONIC_QCQ_F_INTR; 2067 2068 num_desc = lif->nrxq_descs; 2069 desc_sz = sizeof(struct ionic_rxq_desc); 2070 comp_sz = sizeof(struct ionic_rxq_comp); 2071 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2072 2073 if (lif->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2074 comp_sz *= 2; 2075 2076 for (i = 0; i < lif->nxqs; i++) { 2077 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2078 num_desc, desc_sz, comp_sz, sg_desc_sz, 2079 lif->kern_pid, &lif->rxqcqs[i]); 2080 if (err) 2081 goto err_out; 2082 2083 lif->rxqcqs[i]->q.features = lif->rxq_features; 2084 2085 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2086 lif->rxqcqs[i]->intr.index, 2087 lif->rx_coalesce_hw); 2088 if (test_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state)) 2089 lif->rxqcqs[i]->intr.dim_coal_hw = lif->rx_coalesce_hw; 2090 2091 if (!test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state)) 2092 ionic_link_qcq_interrupts(lif->rxqcqs[i], 2093 lif->txqcqs[i]); 2094 2095 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2096 } 2097 2098 return 0; 2099 2100 err_out: 2101 ionic_txrx_free(lif); 2102 2103 return err; 2104 } 2105 2106 static int ionic_txrx_init(struct ionic_lif *lif) 2107 { 2108 unsigned int i; 2109 int err; 2110 2111 for (i = 0; i < lif->nxqs; i++) { 2112 err = ionic_lif_txq_init(lif, lif->txqcqs[i]); 2113 if (err) 2114 goto err_out; 2115 2116 err = ionic_lif_rxq_init(lif, lif->rxqcqs[i]); 2117 if (err) { 2118 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2119 goto err_out; 2120 } 2121 } 2122 2123 if (lif->netdev->features & NETIF_F_RXHASH) 2124 ionic_lif_rss_init(lif); 2125 2126 ionic_lif_rx_mode(lif); 2127 2128 return 0; 2129 2130 err_out: 2131 while (i--) { 2132 ionic_lif_qcq_deinit(lif, lif->txqcqs[i]); 2133 ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]); 2134 } 2135 2136 return err; 2137 } 2138 2139 static int ionic_txrx_enable(struct ionic_lif *lif) 2140 { 2141 int derr = 0; 2142 int i, err; 2143 2144 for (i = 0; i < lif->nxqs; i++) { 2145 if (!(lif->rxqcqs[i] && lif->txqcqs[i])) { 2146 dev_err(lif->ionic->dev, "%s: bad qcq %d\n", __func__, i); 2147 err = -ENXIO; 2148 goto err_out; 2149 } 2150 2151 ionic_rx_fill(&lif->rxqcqs[i]->q); 2152 err = ionic_qcq_enable(lif->rxqcqs[i]); 2153 if (err) 2154 goto err_out; 2155 2156 err = ionic_qcq_enable(lif->txqcqs[i]); 2157 if (err) { 2158 derr = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT)); 2159 goto err_out; 2160 } 2161 } 2162 2163 if (lif->hwstamp_rxq) { 2164 ionic_rx_fill(&lif->hwstamp_rxq->q); 2165 err = ionic_qcq_enable(lif->hwstamp_rxq); 2166 if (err) 2167 goto err_out_hwstamp_rx; 2168 } 2169 2170 if (lif->hwstamp_txq) { 2171 err = ionic_qcq_enable(lif->hwstamp_txq); 2172 if (err) 2173 goto err_out_hwstamp_tx; 2174 } 2175 2176 return 0; 2177 2178 err_out_hwstamp_tx: 2179 if (lif->hwstamp_rxq) 2180 derr = ionic_qcq_disable(lif->hwstamp_rxq, (derr != -ETIMEDOUT)); 2181 err_out_hwstamp_rx: 2182 i = lif->nxqs; 2183 err_out: 2184 while (i--) { 2185 derr = ionic_qcq_disable(lif->txqcqs[i], (derr != -ETIMEDOUT)); 2186 derr = ionic_qcq_disable(lif->rxqcqs[i], (derr != -ETIMEDOUT)); 2187 } 2188 2189 return err; 2190 } 2191 2192 static int ionic_start_queues(struct ionic_lif *lif) 2193 { 2194 int err; 2195 2196 if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) 2197 return -EIO; 2198 2199 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2200 return -EBUSY; 2201 2202 if (test_and_set_bit(IONIC_LIF_F_UP, lif->state)) 2203 return 0; 2204 2205 err = ionic_txrx_enable(lif); 2206 if (err) { 2207 clear_bit(IONIC_LIF_F_UP, lif->state); 2208 return err; 2209 } 2210 netif_tx_wake_all_queues(lif->netdev); 2211 2212 return 0; 2213 } 2214 2215 static int ionic_open(struct net_device *netdev) 2216 { 2217 struct ionic_lif *lif = netdev_priv(netdev); 2218 int err; 2219 2220 /* If recovering from a broken state, clear the bit and we'll try again */ 2221 if (test_and_clear_bit(IONIC_LIF_F_BROKEN, lif->state)) 2222 netdev_info(netdev, "clearing broken state\n"); 2223 2224 mutex_lock(&lif->queue_lock); 2225 2226 err = ionic_txrx_alloc(lif); 2227 if (err) 2228 goto err_unlock; 2229 2230 err = ionic_txrx_init(lif); 2231 if (err) 2232 goto err_txrx_free; 2233 2234 err = netif_set_real_num_tx_queues(netdev, lif->nxqs); 2235 if (err) 2236 goto err_txrx_deinit; 2237 2238 err = netif_set_real_num_rx_queues(netdev, lif->nxqs); 2239 if (err) 2240 goto err_txrx_deinit; 2241 2242 /* don't start the queues until we have link */ 2243 if (netif_carrier_ok(netdev)) { 2244 err = ionic_start_queues(lif); 2245 if (err) 2246 goto err_txrx_deinit; 2247 } 2248 2249 /* If hardware timestamping is enabled, but the queues were freed by 2250 * ionic_stop, those need to be reallocated and initialized, too. 2251 */ 2252 ionic_lif_hwstamp_recreate_queues(lif); 2253 2254 mutex_unlock(&lif->queue_lock); 2255 2256 return 0; 2257 2258 err_txrx_deinit: 2259 ionic_txrx_deinit(lif); 2260 err_txrx_free: 2261 ionic_txrx_free(lif); 2262 err_unlock: 2263 mutex_unlock(&lif->queue_lock); 2264 return err; 2265 } 2266 2267 static void ionic_stop_queues(struct ionic_lif *lif) 2268 { 2269 if (!test_and_clear_bit(IONIC_LIF_F_UP, lif->state)) 2270 return; 2271 2272 netif_tx_disable(lif->netdev); 2273 ionic_txrx_disable(lif); 2274 } 2275 2276 static int ionic_stop(struct net_device *netdev) 2277 { 2278 struct ionic_lif *lif = netdev_priv(netdev); 2279 2280 if (test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2281 return 0; 2282 2283 mutex_lock(&lif->queue_lock); 2284 ionic_stop_queues(lif); 2285 ionic_txrx_deinit(lif); 2286 ionic_txrx_free(lif); 2287 mutex_unlock(&lif->queue_lock); 2288 2289 return 0; 2290 } 2291 2292 static int ionic_eth_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2293 { 2294 struct ionic_lif *lif = netdev_priv(netdev); 2295 2296 switch (cmd) { 2297 case SIOCSHWTSTAMP: 2298 return ionic_lif_hwstamp_set(lif, ifr); 2299 case SIOCGHWTSTAMP: 2300 return ionic_lif_hwstamp_get(lif, ifr); 2301 default: 2302 return -EOPNOTSUPP; 2303 } 2304 } 2305 2306 static int ionic_get_vf_config(struct net_device *netdev, 2307 int vf, struct ifla_vf_info *ivf) 2308 { 2309 struct ionic_lif *lif = netdev_priv(netdev); 2310 struct ionic *ionic = lif->ionic; 2311 int ret = 0; 2312 2313 if (!netif_device_present(netdev)) 2314 return -EBUSY; 2315 2316 down_read(&ionic->vf_op_lock); 2317 2318 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2319 ret = -EINVAL; 2320 } else { 2321 ivf->vf = vf; 2322 ivf->vlan = le16_to_cpu(ionic->vfs[vf].vlanid); 2323 ivf->qos = 0; 2324 ivf->spoofchk = ionic->vfs[vf].spoofchk; 2325 ivf->linkstate = ionic->vfs[vf].linkstate; 2326 ivf->max_tx_rate = le32_to_cpu(ionic->vfs[vf].maxrate); 2327 ivf->trusted = ionic->vfs[vf].trusted; 2328 ether_addr_copy(ivf->mac, ionic->vfs[vf].macaddr); 2329 } 2330 2331 up_read(&ionic->vf_op_lock); 2332 return ret; 2333 } 2334 2335 static int ionic_get_vf_stats(struct net_device *netdev, int vf, 2336 struct ifla_vf_stats *vf_stats) 2337 { 2338 struct ionic_lif *lif = netdev_priv(netdev); 2339 struct ionic *ionic = lif->ionic; 2340 struct ionic_lif_stats *vs; 2341 int ret = 0; 2342 2343 if (!netif_device_present(netdev)) 2344 return -EBUSY; 2345 2346 down_read(&ionic->vf_op_lock); 2347 2348 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2349 ret = -EINVAL; 2350 } else { 2351 memset(vf_stats, 0, sizeof(*vf_stats)); 2352 vs = &ionic->vfs[vf].stats; 2353 2354 vf_stats->rx_packets = le64_to_cpu(vs->rx_ucast_packets); 2355 vf_stats->tx_packets = le64_to_cpu(vs->tx_ucast_packets); 2356 vf_stats->rx_bytes = le64_to_cpu(vs->rx_ucast_bytes); 2357 vf_stats->tx_bytes = le64_to_cpu(vs->tx_ucast_bytes); 2358 vf_stats->broadcast = le64_to_cpu(vs->rx_bcast_packets); 2359 vf_stats->multicast = le64_to_cpu(vs->rx_mcast_packets); 2360 vf_stats->rx_dropped = le64_to_cpu(vs->rx_ucast_drop_packets) + 2361 le64_to_cpu(vs->rx_mcast_drop_packets) + 2362 le64_to_cpu(vs->rx_bcast_drop_packets); 2363 vf_stats->tx_dropped = le64_to_cpu(vs->tx_ucast_drop_packets) + 2364 le64_to_cpu(vs->tx_mcast_drop_packets) + 2365 le64_to_cpu(vs->tx_bcast_drop_packets); 2366 } 2367 2368 up_read(&ionic->vf_op_lock); 2369 return ret; 2370 } 2371 2372 static int ionic_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2373 { 2374 struct ionic_lif *lif = netdev_priv(netdev); 2375 struct ionic *ionic = lif->ionic; 2376 int ret; 2377 2378 if (!(is_zero_ether_addr(mac) || is_valid_ether_addr(mac))) 2379 return -EINVAL; 2380 2381 if (!netif_device_present(netdev)) 2382 return -EBUSY; 2383 2384 down_write(&ionic->vf_op_lock); 2385 2386 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2387 ret = -EINVAL; 2388 } else { 2389 ret = ionic_set_vf_config(ionic, vf, IONIC_VF_ATTR_MAC, mac); 2390 if (!ret) 2391 ether_addr_copy(ionic->vfs[vf].macaddr, mac); 2392 } 2393 2394 up_write(&ionic->vf_op_lock); 2395 return ret; 2396 } 2397 2398 static int ionic_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, 2399 u8 qos, __be16 proto) 2400 { 2401 struct ionic_lif *lif = netdev_priv(netdev); 2402 struct ionic *ionic = lif->ionic; 2403 int ret; 2404 2405 /* until someday when we support qos */ 2406 if (qos) 2407 return -EINVAL; 2408 2409 if (vlan > 4095) 2410 return -EINVAL; 2411 2412 if (proto != htons(ETH_P_8021Q)) 2413 return -EPROTONOSUPPORT; 2414 2415 if (!netif_device_present(netdev)) 2416 return -EBUSY; 2417 2418 down_write(&ionic->vf_op_lock); 2419 2420 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2421 ret = -EINVAL; 2422 } else { 2423 ret = ionic_set_vf_config(ionic, vf, 2424 IONIC_VF_ATTR_VLAN, (u8 *)&vlan); 2425 if (!ret) 2426 ionic->vfs[vf].vlanid = cpu_to_le16(vlan); 2427 } 2428 2429 up_write(&ionic->vf_op_lock); 2430 return ret; 2431 } 2432 2433 static int ionic_set_vf_rate(struct net_device *netdev, int vf, 2434 int tx_min, int tx_max) 2435 { 2436 struct ionic_lif *lif = netdev_priv(netdev); 2437 struct ionic *ionic = lif->ionic; 2438 int ret; 2439 2440 /* setting the min just seems silly */ 2441 if (tx_min) 2442 return -EINVAL; 2443 2444 if (!netif_device_present(netdev)) 2445 return -EBUSY; 2446 2447 down_write(&ionic->vf_op_lock); 2448 2449 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2450 ret = -EINVAL; 2451 } else { 2452 ret = ionic_set_vf_config(ionic, vf, 2453 IONIC_VF_ATTR_RATE, (u8 *)&tx_max); 2454 if (!ret) 2455 lif->ionic->vfs[vf].maxrate = cpu_to_le32(tx_max); 2456 } 2457 2458 up_write(&ionic->vf_op_lock); 2459 return ret; 2460 } 2461 2462 static int ionic_set_vf_spoofchk(struct net_device *netdev, int vf, bool set) 2463 { 2464 struct ionic_lif *lif = netdev_priv(netdev); 2465 struct ionic *ionic = lif->ionic; 2466 u8 data = set; /* convert to u8 for config */ 2467 int ret; 2468 2469 if (!netif_device_present(netdev)) 2470 return -EBUSY; 2471 2472 down_write(&ionic->vf_op_lock); 2473 2474 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2475 ret = -EINVAL; 2476 } else { 2477 ret = ionic_set_vf_config(ionic, vf, 2478 IONIC_VF_ATTR_SPOOFCHK, &data); 2479 if (!ret) 2480 ionic->vfs[vf].spoofchk = data; 2481 } 2482 2483 up_write(&ionic->vf_op_lock); 2484 return ret; 2485 } 2486 2487 static int ionic_set_vf_trust(struct net_device *netdev, int vf, bool set) 2488 { 2489 struct ionic_lif *lif = netdev_priv(netdev); 2490 struct ionic *ionic = lif->ionic; 2491 u8 data = set; /* convert to u8 for config */ 2492 int ret; 2493 2494 if (!netif_device_present(netdev)) 2495 return -EBUSY; 2496 2497 down_write(&ionic->vf_op_lock); 2498 2499 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2500 ret = -EINVAL; 2501 } else { 2502 ret = ionic_set_vf_config(ionic, vf, 2503 IONIC_VF_ATTR_TRUST, &data); 2504 if (!ret) 2505 ionic->vfs[vf].trusted = data; 2506 } 2507 2508 up_write(&ionic->vf_op_lock); 2509 return ret; 2510 } 2511 2512 static int ionic_set_vf_link_state(struct net_device *netdev, int vf, int set) 2513 { 2514 struct ionic_lif *lif = netdev_priv(netdev); 2515 struct ionic *ionic = lif->ionic; 2516 u8 data; 2517 int ret; 2518 2519 switch (set) { 2520 case IFLA_VF_LINK_STATE_ENABLE: 2521 data = IONIC_VF_LINK_STATUS_UP; 2522 break; 2523 case IFLA_VF_LINK_STATE_DISABLE: 2524 data = IONIC_VF_LINK_STATUS_DOWN; 2525 break; 2526 case IFLA_VF_LINK_STATE_AUTO: 2527 data = IONIC_VF_LINK_STATUS_AUTO; 2528 break; 2529 default: 2530 return -EINVAL; 2531 } 2532 2533 if (!netif_device_present(netdev)) 2534 return -EBUSY; 2535 2536 down_write(&ionic->vf_op_lock); 2537 2538 if (vf >= pci_num_vf(ionic->pdev) || !ionic->vfs) { 2539 ret = -EINVAL; 2540 } else { 2541 ret = ionic_set_vf_config(ionic, vf, 2542 IONIC_VF_ATTR_LINKSTATE, &data); 2543 if (!ret) 2544 ionic->vfs[vf].linkstate = set; 2545 } 2546 2547 up_write(&ionic->vf_op_lock); 2548 return ret; 2549 } 2550 2551 static const struct net_device_ops ionic_netdev_ops = { 2552 .ndo_open = ionic_open, 2553 .ndo_stop = ionic_stop, 2554 .ndo_eth_ioctl = ionic_eth_ioctl, 2555 .ndo_start_xmit = ionic_start_xmit, 2556 .ndo_get_stats64 = ionic_get_stats64, 2557 .ndo_set_rx_mode = ionic_ndo_set_rx_mode, 2558 .ndo_set_features = ionic_set_features, 2559 .ndo_set_mac_address = ionic_set_mac_address, 2560 .ndo_validate_addr = eth_validate_addr, 2561 .ndo_tx_timeout = ionic_tx_timeout, 2562 .ndo_change_mtu = ionic_change_mtu, 2563 .ndo_vlan_rx_add_vid = ionic_vlan_rx_add_vid, 2564 .ndo_vlan_rx_kill_vid = ionic_vlan_rx_kill_vid, 2565 .ndo_set_vf_vlan = ionic_set_vf_vlan, 2566 .ndo_set_vf_trust = ionic_set_vf_trust, 2567 .ndo_set_vf_mac = ionic_set_vf_mac, 2568 .ndo_set_vf_rate = ionic_set_vf_rate, 2569 .ndo_set_vf_spoofchk = ionic_set_vf_spoofchk, 2570 .ndo_get_vf_config = ionic_get_vf_config, 2571 .ndo_set_vf_link_state = ionic_set_vf_link_state, 2572 .ndo_get_vf_stats = ionic_get_vf_stats, 2573 }; 2574 2575 static void ionic_swap_queues(struct ionic_qcq *a, struct ionic_qcq *b) 2576 { 2577 /* only swapping the queues, not the napi, flags, or other stuff */ 2578 swap(a->q.features, b->q.features); 2579 swap(a->q.num_descs, b->q.num_descs); 2580 swap(a->q.desc_size, b->q.desc_size); 2581 swap(a->q.base, b->q.base); 2582 swap(a->q.base_pa, b->q.base_pa); 2583 swap(a->q.info, b->q.info); 2584 swap(a->q_base, b->q_base); 2585 swap(a->q_base_pa, b->q_base_pa); 2586 swap(a->q_size, b->q_size); 2587 2588 swap(a->q.sg_desc_size, b->q.sg_desc_size); 2589 swap(a->q.sg_base, b->q.sg_base); 2590 swap(a->q.sg_base_pa, b->q.sg_base_pa); 2591 swap(a->sg_base, b->sg_base); 2592 swap(a->sg_base_pa, b->sg_base_pa); 2593 swap(a->sg_size, b->sg_size); 2594 2595 swap(a->cq.num_descs, b->cq.num_descs); 2596 swap(a->cq.desc_size, b->cq.desc_size); 2597 swap(a->cq.base, b->cq.base); 2598 swap(a->cq.base_pa, b->cq.base_pa); 2599 swap(a->cq.info, b->cq.info); 2600 swap(a->cq_base, b->cq_base); 2601 swap(a->cq_base_pa, b->cq_base_pa); 2602 swap(a->cq_size, b->cq_size); 2603 2604 ionic_debugfs_del_qcq(a); 2605 ionic_debugfs_add_qcq(a->q.lif, a); 2606 } 2607 2608 int ionic_reconfigure_queues(struct ionic_lif *lif, 2609 struct ionic_queue_params *qparam) 2610 { 2611 unsigned int comp_sz, desc_sz, num_desc, sg_desc_sz; 2612 struct ionic_qcq **tx_qcqs = NULL; 2613 struct ionic_qcq **rx_qcqs = NULL; 2614 unsigned int flags, i; 2615 int err = 0; 2616 2617 /* allocate temporary qcq arrays to hold new queue structs */ 2618 if (qparam->nxqs != lif->nxqs || qparam->ntxq_descs != lif->ntxq_descs) { 2619 tx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->ntxqs_per_lif, 2620 sizeof(struct ionic_qcq *), GFP_KERNEL); 2621 if (!tx_qcqs) { 2622 err = -ENOMEM; 2623 goto err_out; 2624 } 2625 } 2626 if (qparam->nxqs != lif->nxqs || 2627 qparam->nrxq_descs != lif->nrxq_descs || 2628 qparam->rxq_features != lif->rxq_features) { 2629 rx_qcqs = devm_kcalloc(lif->ionic->dev, lif->ionic->nrxqs_per_lif, 2630 sizeof(struct ionic_qcq *), GFP_KERNEL); 2631 if (!rx_qcqs) { 2632 err = -ENOMEM; 2633 goto err_out; 2634 } 2635 } 2636 2637 /* allocate new desc_info and rings, but leave the interrupt setup 2638 * until later so as to not mess with the still-running queues 2639 */ 2640 if (tx_qcqs) { 2641 num_desc = qparam->ntxq_descs; 2642 desc_sz = sizeof(struct ionic_txq_desc); 2643 comp_sz = sizeof(struct ionic_txq_comp); 2644 2645 if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 && 2646 lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == 2647 sizeof(struct ionic_txq_sg_desc_v1)) 2648 sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1); 2649 else 2650 sg_desc_sz = sizeof(struct ionic_txq_sg_desc); 2651 2652 for (i = 0; i < qparam->nxqs; i++) { 2653 flags = lif->txqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2654 err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, i, "tx", flags, 2655 num_desc, desc_sz, comp_sz, sg_desc_sz, 2656 lif->kern_pid, &tx_qcqs[i]); 2657 if (err) 2658 goto err_out; 2659 } 2660 } 2661 2662 if (rx_qcqs) { 2663 num_desc = qparam->nrxq_descs; 2664 desc_sz = sizeof(struct ionic_rxq_desc); 2665 comp_sz = sizeof(struct ionic_rxq_comp); 2666 sg_desc_sz = sizeof(struct ionic_rxq_sg_desc); 2667 2668 if (qparam->rxq_features & IONIC_Q_F_2X_CQ_DESC) 2669 comp_sz *= 2; 2670 2671 for (i = 0; i < qparam->nxqs; i++) { 2672 flags = lif->rxqcqs[i]->flags & ~IONIC_QCQ_F_INTR; 2673 err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, i, "rx", flags, 2674 num_desc, desc_sz, comp_sz, sg_desc_sz, 2675 lif->kern_pid, &rx_qcqs[i]); 2676 if (err) 2677 goto err_out; 2678 2679 rx_qcqs[i]->q.features = qparam->rxq_features; 2680 } 2681 } 2682 2683 /* stop and clean the queues */ 2684 ionic_stop_queues_reconfig(lif); 2685 2686 if (qparam->nxqs != lif->nxqs) { 2687 err = netif_set_real_num_tx_queues(lif->netdev, qparam->nxqs); 2688 if (err) 2689 goto err_out_reinit_unlock; 2690 err = netif_set_real_num_rx_queues(lif->netdev, qparam->nxqs); 2691 if (err) { 2692 netif_set_real_num_tx_queues(lif->netdev, lif->nxqs); 2693 goto err_out_reinit_unlock; 2694 } 2695 } 2696 2697 /* swap new desc_info and rings, keeping existing interrupt config */ 2698 if (tx_qcqs) { 2699 lif->ntxq_descs = qparam->ntxq_descs; 2700 for (i = 0; i < qparam->nxqs; i++) 2701 ionic_swap_queues(lif->txqcqs[i], tx_qcqs[i]); 2702 } 2703 2704 if (rx_qcqs) { 2705 lif->nrxq_descs = qparam->nrxq_descs; 2706 for (i = 0; i < qparam->nxqs; i++) 2707 ionic_swap_queues(lif->rxqcqs[i], rx_qcqs[i]); 2708 } 2709 2710 /* if we need to change the interrupt layout, this is the time */ 2711 if (qparam->intr_split != test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state) || 2712 qparam->nxqs != lif->nxqs) { 2713 if (qparam->intr_split) { 2714 set_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2715 } else { 2716 clear_bit(IONIC_LIF_F_SPLIT_INTR, lif->state); 2717 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2718 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2719 } 2720 2721 /* clear existing interrupt assignments */ 2722 for (i = 0; i < lif->ionic->ntxqs_per_lif; i++) { 2723 ionic_qcq_intr_free(lif, lif->txqcqs[i]); 2724 ionic_qcq_intr_free(lif, lif->rxqcqs[i]); 2725 } 2726 2727 /* re-assign the interrupts */ 2728 for (i = 0; i < qparam->nxqs; i++) { 2729 lif->rxqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2730 err = ionic_alloc_qcq_interrupt(lif, lif->rxqcqs[i]); 2731 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2732 lif->rxqcqs[i]->intr.index, 2733 lif->rx_coalesce_hw); 2734 2735 if (qparam->intr_split) { 2736 lif->txqcqs[i]->flags |= IONIC_QCQ_F_INTR; 2737 err = ionic_alloc_qcq_interrupt(lif, lif->txqcqs[i]); 2738 ionic_intr_coal_init(lif->ionic->idev.intr_ctrl, 2739 lif->txqcqs[i]->intr.index, 2740 lif->tx_coalesce_hw); 2741 if (test_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state)) 2742 lif->txqcqs[i]->intr.dim_coal_hw = lif->tx_coalesce_hw; 2743 } else { 2744 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2745 ionic_link_qcq_interrupts(lif->rxqcqs[i], lif->txqcqs[i]); 2746 } 2747 } 2748 } 2749 2750 /* now we can rework the debugfs mappings */ 2751 if (tx_qcqs) { 2752 for (i = 0; i < qparam->nxqs; i++) { 2753 ionic_debugfs_del_qcq(lif->txqcqs[i]); 2754 ionic_debugfs_add_qcq(lif, lif->txqcqs[i]); 2755 } 2756 } 2757 2758 if (rx_qcqs) { 2759 for (i = 0; i < qparam->nxqs; i++) { 2760 ionic_debugfs_del_qcq(lif->rxqcqs[i]); 2761 ionic_debugfs_add_qcq(lif, lif->rxqcqs[i]); 2762 } 2763 } 2764 2765 swap(lif->nxqs, qparam->nxqs); 2766 swap(lif->rxq_features, qparam->rxq_features); 2767 2768 err_out_reinit_unlock: 2769 /* re-init the queues, but don't lose an error code */ 2770 if (err) 2771 ionic_start_queues_reconfig(lif); 2772 else 2773 err = ionic_start_queues_reconfig(lif); 2774 2775 err_out: 2776 /* free old allocs without cleaning intr */ 2777 for (i = 0; i < qparam->nxqs; i++) { 2778 if (tx_qcqs && tx_qcqs[i]) { 2779 tx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2780 ionic_qcq_free(lif, tx_qcqs[i]); 2781 devm_kfree(lif->ionic->dev, tx_qcqs[i]); 2782 tx_qcqs[i] = NULL; 2783 } 2784 if (rx_qcqs && rx_qcqs[i]) { 2785 rx_qcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2786 ionic_qcq_free(lif, rx_qcqs[i]); 2787 devm_kfree(lif->ionic->dev, rx_qcqs[i]); 2788 rx_qcqs[i] = NULL; 2789 } 2790 } 2791 2792 /* free q array */ 2793 if (rx_qcqs) { 2794 devm_kfree(lif->ionic->dev, rx_qcqs); 2795 rx_qcqs = NULL; 2796 } 2797 if (tx_qcqs) { 2798 devm_kfree(lif->ionic->dev, tx_qcqs); 2799 tx_qcqs = NULL; 2800 } 2801 2802 /* clean the unused dma and info allocations when new set is smaller 2803 * than the full array, but leave the qcq shells in place 2804 */ 2805 for (i = lif->nxqs; i < lif->ionic->ntxqs_per_lif; i++) { 2806 lif->txqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2807 ionic_qcq_free(lif, lif->txqcqs[i]); 2808 2809 lif->rxqcqs[i]->flags &= ~IONIC_QCQ_F_INTR; 2810 ionic_qcq_free(lif, lif->rxqcqs[i]); 2811 } 2812 2813 if (err) 2814 netdev_info(lif->netdev, "%s: failed %d\n", __func__, err); 2815 2816 return err; 2817 } 2818 2819 int ionic_lif_alloc(struct ionic *ionic) 2820 { 2821 struct device *dev = ionic->dev; 2822 union ionic_lif_identity *lid; 2823 struct net_device *netdev; 2824 struct ionic_lif *lif; 2825 int tbl_sz; 2826 int err; 2827 2828 lid = kzalloc(sizeof(*lid), GFP_KERNEL); 2829 if (!lid) 2830 return -ENOMEM; 2831 2832 netdev = alloc_etherdev_mqs(sizeof(*lif), 2833 ionic->ntxqs_per_lif, ionic->ntxqs_per_lif); 2834 if (!netdev) { 2835 dev_err(dev, "Cannot allocate netdev, aborting\n"); 2836 err = -ENOMEM; 2837 goto err_out_free_lid; 2838 } 2839 2840 SET_NETDEV_DEV(netdev, dev); 2841 2842 lif = netdev_priv(netdev); 2843 lif->netdev = netdev; 2844 ionic->lif = lif; 2845 netdev->netdev_ops = &ionic_netdev_ops; 2846 ionic_ethtool_set_ops(netdev); 2847 2848 netdev->watchdog_timeo = 2 * HZ; 2849 netif_carrier_off(netdev); 2850 2851 lif->identity = lid; 2852 lif->lif_type = IONIC_LIF_TYPE_CLASSIC; 2853 err = ionic_lif_identify(ionic, lif->lif_type, lif->identity); 2854 if (err) { 2855 dev_err(ionic->dev, "Cannot identify type %d: %d\n", 2856 lif->lif_type, err); 2857 goto err_out_free_netdev; 2858 } 2859 lif->netdev->min_mtu = max_t(unsigned int, ETH_MIN_MTU, 2860 le32_to_cpu(lif->identity->eth.min_frame_size)); 2861 lif->netdev->max_mtu = 2862 le32_to_cpu(lif->identity->eth.max_frame_size) - ETH_HLEN - VLAN_HLEN; 2863 2864 lif->neqs = ionic->neqs_per_lif; 2865 lif->nxqs = ionic->ntxqs_per_lif; 2866 2867 lif->ionic = ionic; 2868 lif->index = 0; 2869 2870 if (is_kdump_kernel()) { 2871 lif->ntxq_descs = IONIC_MIN_TXRX_DESC; 2872 lif->nrxq_descs = IONIC_MIN_TXRX_DESC; 2873 } else { 2874 lif->ntxq_descs = IONIC_DEF_TXRX_DESC; 2875 lif->nrxq_descs = IONIC_DEF_TXRX_DESC; 2876 } 2877 2878 /* Convert the default coalesce value to actual hw resolution */ 2879 lif->rx_coalesce_usecs = IONIC_ITR_COAL_USEC_DEFAULT; 2880 lif->rx_coalesce_hw = ionic_coal_usec_to_hw(lif->ionic, 2881 lif->rx_coalesce_usecs); 2882 lif->tx_coalesce_usecs = lif->rx_coalesce_usecs; 2883 lif->tx_coalesce_hw = lif->rx_coalesce_hw; 2884 set_bit(IONIC_LIF_F_RX_DIM_INTR, lif->state); 2885 set_bit(IONIC_LIF_F_TX_DIM_INTR, lif->state); 2886 2887 snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index); 2888 2889 spin_lock_init(&lif->adminq_lock); 2890 2891 spin_lock_init(&lif->deferred.lock); 2892 INIT_LIST_HEAD(&lif->deferred.list); 2893 INIT_WORK(&lif->deferred.work, ionic_lif_deferred_work); 2894 2895 /* allocate lif info */ 2896 lif->info_sz = ALIGN(sizeof(*lif->info), PAGE_SIZE); 2897 lif->info = dma_alloc_coherent(dev, lif->info_sz, 2898 &lif->info_pa, GFP_KERNEL); 2899 if (!lif->info) { 2900 dev_err(dev, "Failed to allocate lif info, aborting\n"); 2901 err = -ENOMEM; 2902 goto err_out_free_netdev; 2903 } 2904 2905 ionic_debugfs_add_lif(lif); 2906 2907 /* allocate control queues and txrx queue arrays */ 2908 ionic_lif_queue_identify(lif); 2909 err = ionic_qcqs_alloc(lif); 2910 if (err) 2911 goto err_out_free_lif_info; 2912 2913 /* allocate rss indirection table */ 2914 tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz); 2915 lif->rss_ind_tbl_sz = sizeof(*lif->rss_ind_tbl) * tbl_sz; 2916 lif->rss_ind_tbl = dma_alloc_coherent(dev, lif->rss_ind_tbl_sz, 2917 &lif->rss_ind_tbl_pa, 2918 GFP_KERNEL); 2919 2920 if (!lif->rss_ind_tbl) { 2921 err = -ENOMEM; 2922 dev_err(dev, "Failed to allocate rss indirection table, aborting\n"); 2923 goto err_out_free_qcqs; 2924 } 2925 netdev_rss_key_fill(lif->rss_hash_key, IONIC_RSS_HASH_KEY_SIZE); 2926 2927 ionic_lif_alloc_phc(lif); 2928 2929 return 0; 2930 2931 err_out_free_qcqs: 2932 ionic_qcqs_free(lif); 2933 err_out_free_lif_info: 2934 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 2935 lif->info = NULL; 2936 lif->info_pa = 0; 2937 err_out_free_netdev: 2938 free_netdev(lif->netdev); 2939 lif = NULL; 2940 err_out_free_lid: 2941 kfree(lid); 2942 2943 return err; 2944 } 2945 2946 static void ionic_lif_reset(struct ionic_lif *lif) 2947 { 2948 struct ionic_dev *idev = &lif->ionic->idev; 2949 2950 mutex_lock(&lif->ionic->dev_cmd_lock); 2951 ionic_dev_cmd_lif_reset(idev, lif->index); 2952 ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 2953 mutex_unlock(&lif->ionic->dev_cmd_lock); 2954 } 2955 2956 static void ionic_lif_handle_fw_down(struct ionic_lif *lif) 2957 { 2958 struct ionic *ionic = lif->ionic; 2959 2960 if (test_and_set_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2961 return; 2962 2963 dev_info(ionic->dev, "FW Down: Stopping LIFs\n"); 2964 2965 netif_device_detach(lif->netdev); 2966 2967 if (test_bit(IONIC_LIF_F_UP, lif->state)) { 2968 dev_info(ionic->dev, "Surprise FW stop, stopping queues\n"); 2969 mutex_lock(&lif->queue_lock); 2970 ionic_stop_queues(lif); 2971 mutex_unlock(&lif->queue_lock); 2972 } 2973 2974 if (netif_running(lif->netdev)) { 2975 ionic_txrx_deinit(lif); 2976 ionic_txrx_free(lif); 2977 } 2978 ionic_lif_deinit(lif); 2979 ionic_reset(ionic); 2980 ionic_qcqs_free(lif); 2981 2982 dev_info(ionic->dev, "FW Down: LIFs stopped\n"); 2983 } 2984 2985 static void ionic_lif_handle_fw_up(struct ionic_lif *lif) 2986 { 2987 struct ionic *ionic = lif->ionic; 2988 int err; 2989 2990 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 2991 return; 2992 2993 dev_info(ionic->dev, "FW Up: restarting LIFs\n"); 2994 2995 ionic_init_devinfo(ionic); 2996 err = ionic_identify(ionic); 2997 if (err) 2998 goto err_out; 2999 err = ionic_port_identify(ionic); 3000 if (err) 3001 goto err_out; 3002 err = ionic_port_init(ionic); 3003 if (err) 3004 goto err_out; 3005 err = ionic_qcqs_alloc(lif); 3006 if (err) 3007 goto err_out; 3008 3009 err = ionic_lif_init(lif); 3010 if (err) 3011 goto err_qcqs_free; 3012 3013 if (lif->registered) 3014 ionic_lif_set_netdev_info(lif); 3015 3016 ionic_rx_filter_replay(lif); 3017 3018 if (netif_running(lif->netdev)) { 3019 err = ionic_txrx_alloc(lif); 3020 if (err) 3021 goto err_lifs_deinit; 3022 3023 err = ionic_txrx_init(lif); 3024 if (err) 3025 goto err_txrx_free; 3026 } 3027 3028 clear_bit(IONIC_LIF_F_FW_RESET, lif->state); 3029 ionic_link_status_check_request(lif, CAN_SLEEP); 3030 netif_device_attach(lif->netdev); 3031 dev_info(ionic->dev, "FW Up: LIFs restarted\n"); 3032 3033 /* restore the hardware timestamping queues */ 3034 ionic_lif_hwstamp_replay(lif); 3035 3036 return; 3037 3038 err_txrx_free: 3039 ionic_txrx_free(lif); 3040 err_lifs_deinit: 3041 ionic_lif_deinit(lif); 3042 err_qcqs_free: 3043 ionic_qcqs_free(lif); 3044 err_out: 3045 dev_err(ionic->dev, "FW Up: LIFs restart failed - err %d\n", err); 3046 } 3047 3048 void ionic_lif_free(struct ionic_lif *lif) 3049 { 3050 struct device *dev = lif->ionic->dev; 3051 3052 ionic_lif_free_phc(lif); 3053 3054 /* free rss indirection table */ 3055 dma_free_coherent(dev, lif->rss_ind_tbl_sz, lif->rss_ind_tbl, 3056 lif->rss_ind_tbl_pa); 3057 lif->rss_ind_tbl = NULL; 3058 lif->rss_ind_tbl_pa = 0; 3059 3060 /* free queues */ 3061 ionic_qcqs_free(lif); 3062 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) 3063 ionic_lif_reset(lif); 3064 3065 /* free lif info */ 3066 kfree(lif->identity); 3067 dma_free_coherent(dev, lif->info_sz, lif->info, lif->info_pa); 3068 lif->info = NULL; 3069 lif->info_pa = 0; 3070 3071 /* unmap doorbell page */ 3072 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3073 lif->kern_dbpage = NULL; 3074 kfree(lif->dbid_inuse); 3075 lif->dbid_inuse = NULL; 3076 3077 /* free netdev & lif */ 3078 ionic_debugfs_del_lif(lif); 3079 free_netdev(lif->netdev); 3080 } 3081 3082 void ionic_lif_deinit(struct ionic_lif *lif) 3083 { 3084 if (!test_and_clear_bit(IONIC_LIF_F_INITED, lif->state)) 3085 return; 3086 3087 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3088 cancel_work_sync(&lif->deferred.work); 3089 cancel_work_sync(&lif->tx_timeout_work); 3090 ionic_rx_filters_deinit(lif); 3091 if (lif->netdev->features & NETIF_F_RXHASH) 3092 ionic_lif_rss_deinit(lif); 3093 } 3094 3095 napi_disable(&lif->adminqcq->napi); 3096 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3097 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3098 3099 mutex_destroy(&lif->config_lock); 3100 mutex_destroy(&lif->queue_lock); 3101 ionic_lif_reset(lif); 3102 } 3103 3104 static int ionic_lif_adminq_init(struct ionic_lif *lif) 3105 { 3106 struct device *dev = lif->ionic->dev; 3107 struct ionic_q_init_comp comp; 3108 struct ionic_dev *idev; 3109 struct ionic_qcq *qcq; 3110 struct ionic_queue *q; 3111 int err; 3112 3113 idev = &lif->ionic->idev; 3114 qcq = lif->adminqcq; 3115 q = &qcq->q; 3116 3117 mutex_lock(&lif->ionic->dev_cmd_lock); 3118 ionic_dev_cmd_adminq_init(idev, qcq, lif->index, qcq->intr.index); 3119 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3120 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3121 mutex_unlock(&lif->ionic->dev_cmd_lock); 3122 if (err) { 3123 netdev_err(lif->netdev, "adminq init failed %d\n", err); 3124 return err; 3125 } 3126 3127 q->hw_type = comp.hw_type; 3128 q->hw_index = le32_to_cpu(comp.hw_index); 3129 q->dbval = IONIC_DBELL_QID(q->hw_index); 3130 3131 dev_dbg(dev, "adminq->hw_type %d\n", q->hw_type); 3132 dev_dbg(dev, "adminq->hw_index %d\n", q->hw_index); 3133 3134 netif_napi_add(lif->netdev, &qcq->napi, ionic_adminq_napi, 3135 NAPI_POLL_WEIGHT); 3136 3137 napi_enable(&qcq->napi); 3138 3139 if (qcq->flags & IONIC_QCQ_F_INTR) 3140 ionic_intr_mask(idev->intr_ctrl, qcq->intr.index, 3141 IONIC_INTR_MASK_CLEAR); 3142 3143 qcq->flags |= IONIC_QCQ_F_INITED; 3144 3145 return 0; 3146 } 3147 3148 static int ionic_lif_notifyq_init(struct ionic_lif *lif) 3149 { 3150 struct ionic_qcq *qcq = lif->notifyqcq; 3151 struct device *dev = lif->ionic->dev; 3152 struct ionic_queue *q = &qcq->q; 3153 int err; 3154 3155 struct ionic_admin_ctx ctx = { 3156 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3157 .cmd.q_init = { 3158 .opcode = IONIC_CMD_Q_INIT, 3159 .lif_index = cpu_to_le16(lif->index), 3160 .type = q->type, 3161 .ver = lif->qtype_info[q->type].version, 3162 .index = cpu_to_le32(q->index), 3163 .flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 3164 IONIC_QINIT_F_ENA), 3165 .intr_index = cpu_to_le16(lif->adminqcq->intr.index), 3166 .pid = cpu_to_le16(q->pid), 3167 .ring_size = ilog2(q->num_descs), 3168 .ring_base = cpu_to_le64(q->base_pa), 3169 } 3170 }; 3171 3172 dev_dbg(dev, "notifyq_init.pid %d\n", ctx.cmd.q_init.pid); 3173 dev_dbg(dev, "notifyq_init.index %d\n", ctx.cmd.q_init.index); 3174 dev_dbg(dev, "notifyq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base); 3175 dev_dbg(dev, "notifyq_init.ring_size %d\n", ctx.cmd.q_init.ring_size); 3176 3177 err = ionic_adminq_post_wait(lif, &ctx); 3178 if (err) 3179 return err; 3180 3181 lif->last_eid = 0; 3182 q->hw_type = ctx.comp.q_init.hw_type; 3183 q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index); 3184 q->dbval = IONIC_DBELL_QID(q->hw_index); 3185 3186 dev_dbg(dev, "notifyq->hw_type %d\n", q->hw_type); 3187 dev_dbg(dev, "notifyq->hw_index %d\n", q->hw_index); 3188 3189 /* preset the callback info */ 3190 q->info[0].cb_arg = lif; 3191 3192 qcq->flags |= IONIC_QCQ_F_INITED; 3193 3194 return 0; 3195 } 3196 3197 static int ionic_station_set(struct ionic_lif *lif) 3198 { 3199 struct net_device *netdev = lif->netdev; 3200 struct ionic_admin_ctx ctx = { 3201 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3202 .cmd.lif_getattr = { 3203 .opcode = IONIC_CMD_LIF_GETATTR, 3204 .index = cpu_to_le16(lif->index), 3205 .attr = IONIC_LIF_ATTR_MAC, 3206 }, 3207 }; 3208 struct sockaddr addr; 3209 int err; 3210 3211 err = ionic_adminq_post_wait(lif, &ctx); 3212 if (err) 3213 return err; 3214 netdev_dbg(lif->netdev, "found initial MAC addr %pM\n", 3215 ctx.comp.lif_getattr.mac); 3216 if (is_zero_ether_addr(ctx.comp.lif_getattr.mac)) 3217 return 0; 3218 3219 if (!is_zero_ether_addr(netdev->dev_addr)) { 3220 /* If the netdev mac is non-zero and doesn't match the default 3221 * device address, it was set by something earlier and we're 3222 * likely here again after a fw-upgrade reset. We need to be 3223 * sure the netdev mac is in our filter list. 3224 */ 3225 if (!ether_addr_equal(ctx.comp.lif_getattr.mac, 3226 netdev->dev_addr)) 3227 ionic_lif_addr_add(lif, netdev->dev_addr); 3228 } else { 3229 /* Update the netdev mac with the device's mac */ 3230 memcpy(addr.sa_data, ctx.comp.lif_getattr.mac, netdev->addr_len); 3231 addr.sa_family = AF_INET; 3232 err = eth_prepare_mac_addr_change(netdev, &addr); 3233 if (err) { 3234 netdev_warn(lif->netdev, "ignoring bad MAC addr from NIC %pM - err %d\n", 3235 addr.sa_data, err); 3236 return 0; 3237 } 3238 3239 eth_commit_mac_addr_change(netdev, &addr); 3240 } 3241 3242 netdev_dbg(lif->netdev, "adding station MAC addr %pM\n", 3243 netdev->dev_addr); 3244 ionic_lif_addr_add(lif, netdev->dev_addr); 3245 3246 return 0; 3247 } 3248 3249 int ionic_lif_init(struct ionic_lif *lif) 3250 { 3251 struct ionic_dev *idev = &lif->ionic->idev; 3252 struct device *dev = lif->ionic->dev; 3253 struct ionic_lif_init_comp comp; 3254 int dbpage_num; 3255 int err; 3256 3257 mutex_lock(&lif->ionic->dev_cmd_lock); 3258 ionic_dev_cmd_lif_init(idev, lif->index, lif->info_pa); 3259 err = ionic_dev_cmd_wait(lif->ionic, DEVCMD_TIMEOUT); 3260 ionic_dev_cmd_comp(idev, (union ionic_dev_cmd_comp *)&comp); 3261 mutex_unlock(&lif->ionic->dev_cmd_lock); 3262 if (err) 3263 return err; 3264 3265 lif->hw_index = le16_to_cpu(comp.hw_index); 3266 mutex_init(&lif->queue_lock); 3267 mutex_init(&lif->config_lock); 3268 3269 /* now that we have the hw_index we can figure out our doorbell page */ 3270 lif->dbid_count = le32_to_cpu(lif->ionic->ident.dev.ndbpgs_per_lif); 3271 if (!lif->dbid_count) { 3272 dev_err(dev, "No doorbell pages, aborting\n"); 3273 return -EINVAL; 3274 } 3275 3276 lif->dbid_inuse = bitmap_alloc(lif->dbid_count, GFP_KERNEL); 3277 if (!lif->dbid_inuse) { 3278 dev_err(dev, "Failed alloc doorbell id bitmap, aborting\n"); 3279 return -ENOMEM; 3280 } 3281 3282 /* first doorbell id reserved for kernel (dbid aka pid == zero) */ 3283 set_bit(0, lif->dbid_inuse); 3284 lif->kern_pid = 0; 3285 3286 dbpage_num = ionic_db_page_num(lif, lif->kern_pid); 3287 lif->kern_dbpage = ionic_bus_map_dbpage(lif->ionic, dbpage_num); 3288 if (!lif->kern_dbpage) { 3289 dev_err(dev, "Cannot map dbpage, aborting\n"); 3290 err = -ENOMEM; 3291 goto err_out_free_dbid; 3292 } 3293 3294 err = ionic_lif_adminq_init(lif); 3295 if (err) 3296 goto err_out_adminq_deinit; 3297 3298 if (lif->ionic->nnqs_per_lif) { 3299 err = ionic_lif_notifyq_init(lif); 3300 if (err) 3301 goto err_out_notifyq_deinit; 3302 } 3303 3304 err = ionic_init_nic_features(lif); 3305 if (err) 3306 goto err_out_notifyq_deinit; 3307 3308 if (!test_bit(IONIC_LIF_F_FW_RESET, lif->state)) { 3309 err = ionic_rx_filters_init(lif); 3310 if (err) 3311 goto err_out_notifyq_deinit; 3312 } 3313 3314 err = ionic_station_set(lif); 3315 if (err) 3316 goto err_out_notifyq_deinit; 3317 3318 lif->rx_copybreak = IONIC_RX_COPYBREAK_DEFAULT; 3319 3320 set_bit(IONIC_LIF_F_INITED, lif->state); 3321 3322 INIT_WORK(&lif->tx_timeout_work, ionic_tx_timeout_work); 3323 3324 return 0; 3325 3326 err_out_notifyq_deinit: 3327 ionic_lif_qcq_deinit(lif, lif->notifyqcq); 3328 err_out_adminq_deinit: 3329 ionic_lif_qcq_deinit(lif, lif->adminqcq); 3330 ionic_lif_reset(lif); 3331 ionic_bus_unmap_dbpage(lif->ionic, lif->kern_dbpage); 3332 lif->kern_dbpage = NULL; 3333 err_out_free_dbid: 3334 kfree(lif->dbid_inuse); 3335 lif->dbid_inuse = NULL; 3336 3337 return err; 3338 } 3339 3340 static void ionic_lif_notify_work(struct work_struct *ws) 3341 { 3342 } 3343 3344 static void ionic_lif_set_netdev_info(struct ionic_lif *lif) 3345 { 3346 struct ionic_admin_ctx ctx = { 3347 .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work), 3348 .cmd.lif_setattr = { 3349 .opcode = IONIC_CMD_LIF_SETATTR, 3350 .index = cpu_to_le16(lif->index), 3351 .attr = IONIC_LIF_ATTR_NAME, 3352 }, 3353 }; 3354 3355 strlcpy(ctx.cmd.lif_setattr.name, lif->netdev->name, 3356 sizeof(ctx.cmd.lif_setattr.name)); 3357 3358 ionic_adminq_post_wait(lif, &ctx); 3359 } 3360 3361 static struct ionic_lif *ionic_netdev_lif(struct net_device *netdev) 3362 { 3363 if (!netdev || netdev->netdev_ops->ndo_start_xmit != ionic_start_xmit) 3364 return NULL; 3365 3366 return netdev_priv(netdev); 3367 } 3368 3369 static int ionic_lif_notify(struct notifier_block *nb, 3370 unsigned long event, void *info) 3371 { 3372 struct net_device *ndev = netdev_notifier_info_to_dev(info); 3373 struct ionic *ionic = container_of(nb, struct ionic, nb); 3374 struct ionic_lif *lif = ionic_netdev_lif(ndev); 3375 3376 if (!lif || lif->ionic != ionic) 3377 return NOTIFY_DONE; 3378 3379 switch (event) { 3380 case NETDEV_CHANGENAME: 3381 ionic_lif_set_netdev_info(lif); 3382 break; 3383 } 3384 3385 return NOTIFY_DONE; 3386 } 3387 3388 int ionic_lif_register(struct ionic_lif *lif) 3389 { 3390 int err; 3391 3392 ionic_lif_register_phc(lif); 3393 3394 INIT_WORK(&lif->ionic->nb_work, ionic_lif_notify_work); 3395 3396 lif->ionic->nb.notifier_call = ionic_lif_notify; 3397 3398 err = register_netdevice_notifier(&lif->ionic->nb); 3399 if (err) 3400 lif->ionic->nb.notifier_call = NULL; 3401 3402 /* only register LIF0 for now */ 3403 err = register_netdev(lif->netdev); 3404 if (err) { 3405 dev_err(lif->ionic->dev, "Cannot register net device, aborting\n"); 3406 ionic_lif_unregister_phc(lif); 3407 return err; 3408 } 3409 3410 ionic_link_status_check_request(lif, CAN_SLEEP); 3411 lif->registered = true; 3412 ionic_lif_set_netdev_info(lif); 3413 3414 return 0; 3415 } 3416 3417 void ionic_lif_unregister(struct ionic_lif *lif) 3418 { 3419 if (lif->ionic->nb.notifier_call) { 3420 unregister_netdevice_notifier(&lif->ionic->nb); 3421 cancel_work_sync(&lif->ionic->nb_work); 3422 lif->ionic->nb.notifier_call = NULL; 3423 } 3424 3425 if (lif->netdev->reg_state == NETREG_REGISTERED) 3426 unregister_netdev(lif->netdev); 3427 3428 ionic_lif_unregister_phc(lif); 3429 3430 lif->registered = false; 3431 } 3432 3433 static void ionic_lif_queue_identify(struct ionic_lif *lif) 3434 { 3435 union ionic_q_identity __iomem *q_ident; 3436 struct ionic *ionic = lif->ionic; 3437 struct ionic_dev *idev; 3438 int qtype; 3439 int err; 3440 3441 idev = &lif->ionic->idev; 3442 q_ident = (union ionic_q_identity __iomem *)&idev->dev_cmd_regs->data; 3443 3444 for (qtype = 0; qtype < ARRAY_SIZE(ionic_qtype_versions); qtype++) { 3445 struct ionic_qtype_info *qti = &lif->qtype_info[qtype]; 3446 3447 /* filter out the ones we know about */ 3448 switch (qtype) { 3449 case IONIC_QTYPE_ADMINQ: 3450 case IONIC_QTYPE_NOTIFYQ: 3451 case IONIC_QTYPE_RXQ: 3452 case IONIC_QTYPE_TXQ: 3453 break; 3454 default: 3455 continue; 3456 } 3457 3458 memset(qti, 0, sizeof(*qti)); 3459 3460 mutex_lock(&ionic->dev_cmd_lock); 3461 ionic_dev_cmd_queue_identify(idev, lif->lif_type, qtype, 3462 ionic_qtype_versions[qtype]); 3463 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3464 if (!err) { 3465 qti->version = readb(&q_ident->version); 3466 qti->supported = readb(&q_ident->supported); 3467 qti->features = readq(&q_ident->features); 3468 qti->desc_sz = readw(&q_ident->desc_sz); 3469 qti->comp_sz = readw(&q_ident->comp_sz); 3470 qti->sg_desc_sz = readw(&q_ident->sg_desc_sz); 3471 qti->max_sg_elems = readw(&q_ident->max_sg_elems); 3472 qti->sg_desc_stride = readw(&q_ident->sg_desc_stride); 3473 } 3474 mutex_unlock(&ionic->dev_cmd_lock); 3475 3476 if (err == -EINVAL) { 3477 dev_err(ionic->dev, "qtype %d not supported\n", qtype); 3478 continue; 3479 } else if (err == -EIO) { 3480 dev_err(ionic->dev, "q_ident failed, not supported on older FW\n"); 3481 return; 3482 } else if (err) { 3483 dev_err(ionic->dev, "q_ident failed, qtype %d: %d\n", 3484 qtype, err); 3485 return; 3486 } 3487 3488 dev_dbg(ionic->dev, " qtype[%d].version = %d\n", 3489 qtype, qti->version); 3490 dev_dbg(ionic->dev, " qtype[%d].supported = 0x%02x\n", 3491 qtype, qti->supported); 3492 dev_dbg(ionic->dev, " qtype[%d].features = 0x%04llx\n", 3493 qtype, qti->features); 3494 dev_dbg(ionic->dev, " qtype[%d].desc_sz = %d\n", 3495 qtype, qti->desc_sz); 3496 dev_dbg(ionic->dev, " qtype[%d].comp_sz = %d\n", 3497 qtype, qti->comp_sz); 3498 dev_dbg(ionic->dev, " qtype[%d].sg_desc_sz = %d\n", 3499 qtype, qti->sg_desc_sz); 3500 dev_dbg(ionic->dev, " qtype[%d].max_sg_elems = %d\n", 3501 qtype, qti->max_sg_elems); 3502 dev_dbg(ionic->dev, " qtype[%d].sg_desc_stride = %d\n", 3503 qtype, qti->sg_desc_stride); 3504 } 3505 } 3506 3507 int ionic_lif_identify(struct ionic *ionic, u8 lif_type, 3508 union ionic_lif_identity *lid) 3509 { 3510 struct ionic_dev *idev = &ionic->idev; 3511 size_t sz; 3512 int err; 3513 3514 sz = min(sizeof(*lid), sizeof(idev->dev_cmd_regs->data)); 3515 3516 mutex_lock(&ionic->dev_cmd_lock); 3517 ionic_dev_cmd_lif_identify(idev, lif_type, IONIC_IDENTITY_VERSION_1); 3518 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 3519 memcpy_fromio(lid, &idev->dev_cmd_regs->data, sz); 3520 mutex_unlock(&ionic->dev_cmd_lock); 3521 if (err) 3522 return (err); 3523 3524 dev_dbg(ionic->dev, "capabilities 0x%llx\n", 3525 le64_to_cpu(lid->capabilities)); 3526 3527 dev_dbg(ionic->dev, "eth.max_ucast_filters %d\n", 3528 le32_to_cpu(lid->eth.max_ucast_filters)); 3529 dev_dbg(ionic->dev, "eth.max_mcast_filters %d\n", 3530 le32_to_cpu(lid->eth.max_mcast_filters)); 3531 dev_dbg(ionic->dev, "eth.features 0x%llx\n", 3532 le64_to_cpu(lid->eth.config.features)); 3533 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_ADMINQ] %d\n", 3534 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_ADMINQ])); 3535 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_NOTIFYQ] %d\n", 3536 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_NOTIFYQ])); 3537 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_RXQ] %d\n", 3538 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_RXQ])); 3539 dev_dbg(ionic->dev, "eth.queue_count[IONIC_QTYPE_TXQ] %d\n", 3540 le32_to_cpu(lid->eth.config.queue_count[IONIC_QTYPE_TXQ])); 3541 dev_dbg(ionic->dev, "eth.config.name %s\n", lid->eth.config.name); 3542 dev_dbg(ionic->dev, "eth.config.mac %pM\n", lid->eth.config.mac); 3543 dev_dbg(ionic->dev, "eth.config.mtu %d\n", 3544 le32_to_cpu(lid->eth.config.mtu)); 3545 3546 return 0; 3547 } 3548 3549 int ionic_lif_size(struct ionic *ionic) 3550 { 3551 struct ionic_identity *ident = &ionic->ident; 3552 unsigned int nintrs, dev_nintrs; 3553 union ionic_lif_config *lc; 3554 unsigned int ntxqs_per_lif; 3555 unsigned int nrxqs_per_lif; 3556 unsigned int neqs_per_lif; 3557 unsigned int nnqs_per_lif; 3558 unsigned int nxqs, neqs; 3559 unsigned int min_intrs; 3560 int err; 3561 3562 /* retrieve basic values from FW */ 3563 lc = &ident->lif.eth.config; 3564 dev_nintrs = le32_to_cpu(ident->dev.nintrs); 3565 neqs_per_lif = le32_to_cpu(ident->lif.rdma.eq_qtype.qid_count); 3566 nnqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_NOTIFYQ]); 3567 ntxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_TXQ]); 3568 nrxqs_per_lif = le32_to_cpu(lc->queue_count[IONIC_QTYPE_RXQ]); 3569 3570 /* limit values to play nice with kdump */ 3571 if (is_kdump_kernel()) { 3572 dev_nintrs = 2; 3573 neqs_per_lif = 0; 3574 nnqs_per_lif = 0; 3575 ntxqs_per_lif = 1; 3576 nrxqs_per_lif = 1; 3577 } 3578 3579 /* reserve last queue id for hardware timestamping */ 3580 if (lc->features & cpu_to_le64(IONIC_ETH_HW_TIMESTAMP)) { 3581 if (ntxqs_per_lif <= 1 || nrxqs_per_lif <= 1) { 3582 lc->features &= cpu_to_le64(~IONIC_ETH_HW_TIMESTAMP); 3583 } else { 3584 ntxqs_per_lif -= 1; 3585 nrxqs_per_lif -= 1; 3586 } 3587 } 3588 3589 nxqs = min(ntxqs_per_lif, nrxqs_per_lif); 3590 nxqs = min(nxqs, num_online_cpus()); 3591 neqs = min(neqs_per_lif, num_online_cpus()); 3592 3593 try_again: 3594 /* interrupt usage: 3595 * 1 for master lif adminq/notifyq 3596 * 1 for each CPU for master lif TxRx queue pairs 3597 * whatever's left is for RDMA queues 3598 */ 3599 nintrs = 1 + nxqs + neqs; 3600 min_intrs = 2; /* adminq + 1 TxRx queue pair */ 3601 3602 if (nintrs > dev_nintrs) 3603 goto try_fewer; 3604 3605 err = ionic_bus_alloc_irq_vectors(ionic, nintrs); 3606 if (err < 0 && err != -ENOSPC) { 3607 dev_err(ionic->dev, "Can't get intrs from OS: %d\n", err); 3608 return err; 3609 } 3610 if (err == -ENOSPC) 3611 goto try_fewer; 3612 3613 if (err != nintrs) { 3614 ionic_bus_free_irq_vectors(ionic); 3615 goto try_fewer; 3616 } 3617 3618 ionic->nnqs_per_lif = nnqs_per_lif; 3619 ionic->neqs_per_lif = neqs; 3620 ionic->ntxqs_per_lif = nxqs; 3621 ionic->nrxqs_per_lif = nxqs; 3622 ionic->nintrs = nintrs; 3623 3624 ionic_debugfs_add_sizes(ionic); 3625 3626 return 0; 3627 3628 try_fewer: 3629 if (nnqs_per_lif > 1) { 3630 nnqs_per_lif >>= 1; 3631 goto try_again; 3632 } 3633 if (neqs > 1) { 3634 neqs >>= 1; 3635 goto try_again; 3636 } 3637 if (nxqs > 1) { 3638 nxqs >>= 1; 3639 goto try_again; 3640 } 3641 dev_err(ionic->dev, "Can't get minimum %d intrs from OS\n", min_intrs); 3642 return -ENOSPC; 3643 } 3644