1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /** 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 38 IONIC_CMD_RX_MODE_SET = 30, 39 IONIC_CMD_RX_FILTER_ADD = 31, 40 IONIC_CMD_RX_FILTER_DEL = 32, 41 42 /* Queue commands */ 43 IONIC_CMD_Q_IDENTIFY = 39, 44 IONIC_CMD_Q_INIT = 40, 45 IONIC_CMD_Q_CONTROL = 41, 46 47 /* RDMA commands */ 48 IONIC_CMD_RDMA_RESET_LIF = 50, 49 IONIC_CMD_RDMA_CREATE_EQ = 51, 50 IONIC_CMD_RDMA_CREATE_CQ = 52, 51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 52 53 /* SR/IOV commands */ 54 IONIC_CMD_VF_GETATTR = 60, 55 IONIC_CMD_VF_SETATTR = 61, 56 57 /* QoS commands */ 58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 59 IONIC_CMD_QOS_CLASS_INIT = 241, 60 IONIC_CMD_QOS_CLASS_RESET = 242, 61 IONIC_CMD_QOS_CLASS_UPDATE = 243, 62 IONIC_CMD_QOS_CLEAR_STATS = 244, 63 IONIC_CMD_QOS_RESET = 245, 64 65 /* Firmware commands */ 66 IONIC_CMD_FW_DOWNLOAD = 252, 67 IONIC_CMD_FW_CONTROL = 253, 68 IONIC_CMD_FW_DOWNLOAD_V1 = 254, 69 IONIC_CMD_FW_CONTROL_V1 = 255, 70 }; 71 72 /** 73 * enum ionic_status_code - Device command return codes 74 */ 75 enum ionic_status_code { 76 IONIC_RC_SUCCESS = 0, /* Success */ 77 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 78 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 79 IONIC_RC_EIO = 3, /* I/O error */ 80 IONIC_RC_EPERM = 4, /* Permission denied */ 81 IONIC_RC_EQID = 5, /* Bad qid */ 82 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 83 IONIC_RC_ENOENT = 7, /* No such element */ 84 IONIC_RC_EINTR = 8, /* operation interrupted */ 85 IONIC_RC_EAGAIN = 9, /* Try again */ 86 IONIC_RC_ENOMEM = 10, /* Out of memory */ 87 IONIC_RC_EFAULT = 11, /* Bad address */ 88 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 89 IONIC_RC_EEXIST = 13, /* object already exists */ 90 IONIC_RC_EINVAL = 14, /* Invalid argument */ 91 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 92 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 93 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 94 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 95 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 96 IONIC_RC_ERROR = 29, /* Generic error */ 97 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 98 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 99 }; 100 101 enum ionic_notifyq_opcode { 102 IONIC_EVENT_LINK_CHANGE = 1, 103 IONIC_EVENT_RESET = 2, 104 IONIC_EVENT_HEARTBEAT = 3, 105 IONIC_EVENT_LOG = 4, 106 IONIC_EVENT_XCVR = 5, 107 }; 108 109 /** 110 * struct ionic_admin_cmd - General admin command format 111 * @opcode: Opcode for the command 112 * @lif_index: LIF index 113 * @cmd_data: Opcode-specific command bytes 114 */ 115 struct ionic_admin_cmd { 116 u8 opcode; 117 u8 rsvd; 118 __le16 lif_index; 119 u8 cmd_data[60]; 120 }; 121 122 /** 123 * struct ionic_admin_comp - General admin command completion format 124 * @status: Status of the command (enum ionic_status_code) 125 * @comp_index: Index in the descriptor ring for which this is the completion 126 * @cmd_data: Command-specific bytes 127 * @color: Color bit (Always 0 for commands issued to the 128 * Device Cmd Registers) 129 */ 130 struct ionic_admin_comp { 131 u8 status; 132 u8 rsvd; 133 __le16 comp_index; 134 u8 cmd_data[11]; 135 u8 color; 136 #define IONIC_COMP_COLOR_MASK 0x80 137 }; 138 139 static inline u8 color_match(u8 color, u8 done_color) 140 { 141 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 142 } 143 144 /** 145 * struct ionic_nop_cmd - NOP command 146 * @opcode: opcode 147 */ 148 struct ionic_nop_cmd { 149 u8 opcode; 150 u8 rsvd[63]; 151 }; 152 153 /** 154 * struct ionic_nop_comp - NOP command completion 155 * @status: Status of the command (enum ionic_status_code) 156 */ 157 struct ionic_nop_comp { 158 u8 status; 159 u8 rsvd[15]; 160 }; 161 162 /** 163 * struct ionic_dev_init_cmd - Device init command 164 * @opcode: opcode 165 * @type: Device type 166 */ 167 struct ionic_dev_init_cmd { 168 u8 opcode; 169 u8 type; 170 u8 rsvd[62]; 171 }; 172 173 /** 174 * struct ionic_dev_init_comp - Device init command completion 175 * @status: Status of the command (enum ionic_status_code) 176 */ 177 struct ionic_dev_init_comp { 178 u8 status; 179 u8 rsvd[15]; 180 }; 181 182 /** 183 * struct ionic_dev_reset_cmd - Device reset command 184 * @opcode: opcode 185 */ 186 struct ionic_dev_reset_cmd { 187 u8 opcode; 188 u8 rsvd[63]; 189 }; 190 191 /** 192 * struct ionic_dev_reset_comp - Reset command completion 193 * @status: Status of the command (enum ionic_status_code) 194 */ 195 struct ionic_dev_reset_comp { 196 u8 status; 197 u8 rsvd[15]; 198 }; 199 200 #define IONIC_IDENTITY_VERSION_1 1 201 202 /** 203 * struct ionic_dev_identify_cmd - Driver/device identify command 204 * @opcode: opcode 205 * @ver: Highest version of identify supported by driver 206 */ 207 struct ionic_dev_identify_cmd { 208 u8 opcode; 209 u8 ver; 210 u8 rsvd[62]; 211 }; 212 213 /** 214 * struct ionic_dev_identify_comp - Driver/device identify command completion 215 * @status: Status of the command (enum ionic_status_code) 216 * @ver: Version of identify returned by device 217 */ 218 struct ionic_dev_identify_comp { 219 u8 status; 220 u8 ver; 221 u8 rsvd[14]; 222 }; 223 224 enum ionic_os_type { 225 IONIC_OS_TYPE_LINUX = 1, 226 IONIC_OS_TYPE_WIN = 2, 227 IONIC_OS_TYPE_DPDK = 3, 228 IONIC_OS_TYPE_FREEBSD = 4, 229 IONIC_OS_TYPE_IPXE = 5, 230 IONIC_OS_TYPE_ESXI = 6, 231 }; 232 233 /** 234 * union ionic_drv_identity - driver identity information 235 * @os_type: OS type (see enum ionic_os_type) 236 * @os_dist: OS distribution, numeric format 237 * @os_dist_str: OS distribution, string format 238 * @kernel_ver: Kernel version, numeric format 239 * @kernel_ver_str: Kernel version, string format 240 * @driver_ver_str: Driver version, string format 241 */ 242 union ionic_drv_identity { 243 struct { 244 __le32 os_type; 245 __le32 os_dist; 246 char os_dist_str[128]; 247 __le32 kernel_ver; 248 char kernel_ver_str[32]; 249 char driver_ver_str[32]; 250 }; 251 __le32 words[478]; 252 }; 253 254 /** 255 * union ionic_dev_identity - device identity information 256 * @version: Version of device identify 257 * @type: Identify type (0 for now) 258 * @nports: Number of ports provisioned 259 * @nlifs: Number of LIFs provisioned 260 * @nintrs: Number of interrupts provisioned 261 * @ndbpgs_per_lif: Number of doorbell pages per LIF 262 * @intr_coal_mult: Interrupt coalescing multiplication factor 263 * Scale user-supplied interrupt coalescing 264 * value in usecs to device units using: 265 * device units = usecs * mult / div 266 * @intr_coal_div: Interrupt coalescing division factor 267 * Scale user-supplied interrupt coalescing 268 * value in usecs to device units using: 269 * device units = usecs * mult / div 270 * @eq_count: Number of shared event queues 271 */ 272 union ionic_dev_identity { 273 struct { 274 u8 version; 275 u8 type; 276 u8 rsvd[2]; 277 u8 nports; 278 u8 rsvd2[3]; 279 __le32 nlifs; 280 __le32 nintrs; 281 __le32 ndbpgs_per_lif; 282 __le32 intr_coal_mult; 283 __le32 intr_coal_div; 284 __le32 eq_count; 285 }; 286 __le32 words[478]; 287 }; 288 289 enum ionic_lif_type { 290 IONIC_LIF_TYPE_CLASSIC = 0, 291 IONIC_LIF_TYPE_MACVLAN = 1, 292 IONIC_LIF_TYPE_NETQUEUE = 2, 293 }; 294 295 /** 296 * struct ionic_lif_identify_cmd - LIF identify command 297 * @opcode: opcode 298 * @type: LIF type (enum ionic_lif_type) 299 * @ver: Version of identify returned by device 300 */ 301 struct ionic_lif_identify_cmd { 302 u8 opcode; 303 u8 type; 304 u8 ver; 305 u8 rsvd[61]; 306 }; 307 308 /** 309 * struct ionic_lif_identify_comp - LIF identify command completion 310 * @status: Status of the command (enum ionic_status_code) 311 * @ver: Version of identify returned by device 312 */ 313 struct ionic_lif_identify_comp { 314 u8 status; 315 u8 ver; 316 u8 rsvd2[14]; 317 }; 318 319 /** 320 * enum ionic_lif_capability - LIF capabilities 321 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 322 * @IONIC_LIF_CAP_RDMA: LIF support RDMA 323 */ 324 enum ionic_lif_capability { 325 IONIC_LIF_CAP_ETH = BIT(0), 326 IONIC_LIF_CAP_RDMA = BIT(1), 327 }; 328 329 /** 330 * enum ionic_logical_qtype - Logical Queue Types 331 * @IONIC_QTYPE_ADMINQ: Administrative Queue 332 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 333 * @IONIC_QTYPE_RXQ: Receive Queue 334 * @IONIC_QTYPE_TXQ: Transmit Queue 335 * @IONIC_QTYPE_EQ: Event Queue 336 * @IONIC_QTYPE_MAX: Max queue type supported 337 */ 338 enum ionic_logical_qtype { 339 IONIC_QTYPE_ADMINQ = 0, 340 IONIC_QTYPE_NOTIFYQ = 1, 341 IONIC_QTYPE_RXQ = 2, 342 IONIC_QTYPE_TXQ = 3, 343 IONIC_QTYPE_EQ = 4, 344 IONIC_QTYPE_MAX = 16, 345 }; 346 347 /** 348 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 349 * @qtype: Hardware Queue Type 350 * @qid_count: Number of Queue IDs of the logical type 351 * @qid_base: Minimum Queue ID of the logical type 352 */ 353 struct ionic_lif_logical_qtype { 354 u8 qtype; 355 u8 rsvd[3]; 356 __le32 qid_count; 357 __le32 qid_base; 358 }; 359 360 /** 361 * enum ionic_lif_state - LIF state 362 * @IONIC_LIF_DISABLE: LIF disabled 363 * @IONIC_LIF_ENABLE: LIF enabled 364 * @IONIC_LIF_QUIESCE: LIF Quiesced 365 */ 366 enum ionic_lif_state { 367 IONIC_LIF_QUIESCE = 0, 368 IONIC_LIF_ENABLE = 1, 369 IONIC_LIF_DISABLE = 2, 370 }; 371 372 /** 373 * union ionic_lif_config - LIF configuration 374 * @state: LIF state (enum ionic_lif_state) 375 * @name: LIF name 376 * @mtu: MTU 377 * @mac: Station MAC address 378 * @vlan: Default Vlan ID 379 * @features: Features (enum ionic_eth_hw_features) 380 * @queue_count: Queue counts per queue-type 381 */ 382 union ionic_lif_config { 383 struct { 384 u8 state; 385 u8 rsvd[3]; 386 char name[IONIC_IFNAMSIZ]; 387 __le32 mtu; 388 u8 mac[6]; 389 __le16 vlan; 390 __le64 features; 391 __le32 queue_count[IONIC_QTYPE_MAX]; 392 } __packed; 393 __le32 words[64]; 394 }; 395 396 /** 397 * struct ionic_lif_identity - LIF identity information (type-specific) 398 * 399 * @capabilities: LIF capabilities 400 * 401 * @eth: Ethernet identify structure 402 * @version: Ethernet identify structure version 403 * @max_ucast_filters: Number of perfect unicast addresses supported 404 * @max_mcast_filters: Number of perfect multicast addresses supported 405 * @min_frame_size: Minimum size of frames to be sent 406 * @max_frame_size: Maximim size of frames to be sent 407 * @config: LIF config struct with features, mtu, mac, q counts 408 * 409 * @rdma: RDMA identify structure 410 * @version: RDMA version of opcodes and queue descriptors 411 * @qp_opcodes: Number of RDMA queue pair opcodes supported 412 * @admin_opcodes: Number of RDMA admin opcodes supported 413 * @npts_per_lif: Page table size per LIF 414 * @nmrs_per_lif: Number of memory regions per LIF 415 * @nahs_per_lif: Number of address handles per LIF 416 * @max_stride: Max work request stride 417 * @cl_stride: Cache line stride 418 * @pte_stride: Page table entry stride 419 * @rrq_stride: Remote RQ work request stride 420 * @rsq_stride: Remote SQ work request stride 421 * @dcqcn_profiles: Number of DCQCN profiles 422 * @aq_qtype: RDMA Admin Qtype 423 * @sq_qtype: RDMA Send Qtype 424 * @rq_qtype: RDMA Receive Qtype 425 * @cq_qtype: RDMA Completion Qtype 426 * @eq_qtype: RDMA Event Qtype 427 */ 428 union ionic_lif_identity { 429 struct { 430 __le64 capabilities; 431 432 struct { 433 u8 version; 434 u8 rsvd[3]; 435 __le32 max_ucast_filters; 436 __le32 max_mcast_filters; 437 __le16 rss_ind_tbl_sz; 438 __le32 min_frame_size; 439 __le32 max_frame_size; 440 u8 rsvd2[106]; 441 union ionic_lif_config config; 442 } __packed eth; 443 444 struct { 445 u8 version; 446 u8 qp_opcodes; 447 u8 admin_opcodes; 448 u8 rsvd; 449 __le32 npts_per_lif; 450 __le32 nmrs_per_lif; 451 __le32 nahs_per_lif; 452 u8 max_stride; 453 u8 cl_stride; 454 u8 pte_stride; 455 u8 rrq_stride; 456 u8 rsq_stride; 457 u8 dcqcn_profiles; 458 u8 rsvd_dimensions[10]; 459 struct ionic_lif_logical_qtype aq_qtype; 460 struct ionic_lif_logical_qtype sq_qtype; 461 struct ionic_lif_logical_qtype rq_qtype; 462 struct ionic_lif_logical_qtype cq_qtype; 463 struct ionic_lif_logical_qtype eq_qtype; 464 } __packed rdma; 465 } __packed; 466 __le32 words[478]; 467 }; 468 469 /** 470 * struct ionic_lif_init_cmd - LIF init command 471 * @opcode: Opcode 472 * @type: LIF type (enum ionic_lif_type) 473 * @index: LIF index 474 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 475 */ 476 struct ionic_lif_init_cmd { 477 u8 opcode; 478 u8 type; 479 __le16 index; 480 __le32 rsvd; 481 __le64 info_pa; 482 u8 rsvd2[48]; 483 }; 484 485 /** 486 * struct ionic_lif_init_comp - LIF init command completion 487 * @status: Status of the command (enum ionic_status_code) 488 * @hw_index: Hardware index of the initialized LIF 489 */ 490 struct ionic_lif_init_comp { 491 u8 status; 492 u8 rsvd; 493 __le16 hw_index; 494 u8 rsvd2[12]; 495 }; 496 497 /** 498 * struct ionic_q_identify_cmd - queue identify command 499 * @opcode: opcode 500 * @lif_type: LIF type (enum ionic_lif_type) 501 * @type: Logical queue type (enum ionic_logical_qtype) 502 * @ver: Highest queue type version that the driver supports 503 */ 504 struct ionic_q_identify_cmd { 505 u8 opcode; 506 u8 rsvd; 507 __le16 lif_type; 508 u8 type; 509 u8 ver; 510 u8 rsvd2[58]; 511 }; 512 513 /** 514 * struct ionic_q_identify_comp - queue identify command completion 515 * @status: Status of the command (enum ionic_status_code) 516 * @comp_index: Index in the descriptor ring for which this is the completion 517 * @ver: Queue type version that can be used with FW 518 */ 519 struct ionic_q_identify_comp { 520 u8 status; 521 u8 rsvd; 522 __le16 comp_index; 523 u8 ver; 524 u8 rsvd2[11]; 525 }; 526 527 /** 528 * union ionic_q_identity - queue identity information 529 * @version: Queue type version that can be used with FW 530 * @supported: Bitfield of queue versions, first bit = ver 0 531 * @features: Queue features 532 * @desc_sz: Descriptor size 533 * @comp_sz: Completion descriptor size 534 * @sg_desc_sz: Scatter/Gather descriptor size 535 * @max_sg_elems: Maximum number of Scatter/Gather elements 536 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 537 */ 538 union ionic_q_identity { 539 struct { 540 u8 version; 541 u8 supported; 542 u8 rsvd[6]; 543 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */ 544 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */ 545 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */ 546 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */ 547 __le64 features; 548 __le16 desc_sz; 549 __le16 comp_sz; 550 __le16 sg_desc_sz; 551 __le16 max_sg_elems; 552 __le16 sg_desc_stride; 553 }; 554 __le32 words[478]; 555 }; 556 557 /** 558 * struct ionic_q_init_cmd - Queue init command 559 * @opcode: opcode 560 * @type: Logical queue type 561 * @ver: Queue type version 562 * @lif_index: LIF index 563 * @index: (LIF, qtype) relative admin queue index 564 * @intr_index: Interrupt control register index, or Event queue index 565 * @pid: Process ID 566 * @flags: 567 * IRQ: Interrupt requested on completion 568 * ENA: Enable the queue. If ENA=0 the queue is initialized 569 * but remains disabled, to be later enabled with the 570 * Queue Enable command. If ENA=1, then queue is 571 * initialized and then enabled. 572 * SG: Enable Scatter-Gather on the queue. 573 * in number of descs. The actual ring size is 574 * (1 << ring_size). For example, to 575 * select a ring size of 64 descriptors write 576 * ring_size = 6. The minimum ring_size value is 2 577 * for a ring size of 4 descriptors. The maximum 578 * ring_size value is 16 for a ring size of 64k 579 * descriptors. Values of ring_size <2 and >16 are 580 * reserved. 581 * EQ: Enable the Event Queue 582 * @cos: Class of service for this queue 583 * @ring_size: Queue ring size, encoded as a log2(size) 584 * @ring_base: Queue ring base address 585 * @cq_ring_base: Completion queue ring base address 586 * @sg_ring_base: Scatter/Gather ring base address 587 */ 588 struct ionic_q_init_cmd { 589 u8 opcode; 590 u8 rsvd; 591 __le16 lif_index; 592 u8 type; 593 u8 ver; 594 u8 rsvd1[2]; 595 __le32 index; 596 __le16 pid; 597 __le16 intr_index; 598 __le16 flags; 599 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 600 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 601 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 602 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 603 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 604 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 605 u8 cos; 606 u8 ring_size; 607 __le64 ring_base; 608 __le64 cq_ring_base; 609 __le64 sg_ring_base; 610 u8 rsvd2[20]; 611 } __packed; 612 613 /** 614 * struct ionic_q_init_comp - Queue init command completion 615 * @status: Status of the command (enum ionic_status_code) 616 * @comp_index: Index in the descriptor ring for which this is the completion 617 * @hw_index: Hardware Queue ID 618 * @hw_type: Hardware Queue type 619 * @color: Color 620 */ 621 struct ionic_q_init_comp { 622 u8 status; 623 u8 rsvd; 624 __le16 comp_index; 625 __le32 hw_index; 626 u8 hw_type; 627 u8 rsvd2[6]; 628 u8 color; 629 }; 630 631 /* the device's internal addressing uses up to 52 bits */ 632 #define IONIC_ADDR_LEN 52 633 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 634 635 enum ionic_txq_desc_opcode { 636 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 637 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 638 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 639 IONIC_TXQ_DESC_OPCODE_TSO = 3, 640 }; 641 642 /** 643 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 644 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 645 * 646 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 647 * Non-offload send. No segmentation, 648 * fragmentation or checksum calc/insertion is 649 * performed by device; packet is prepared 650 * to send by software stack and requires 651 * no further manipulation from device. 652 * 653 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 654 * Offload 16-bit L4 checksum 655 * calculation/insertion. The device will 656 * calculate the L4 checksum value and 657 * insert the result in the packet's L4 658 * header checksum field. The L4 checksum 659 * is calculated starting at @csum_start bytes 660 * into the packet to the end of the packet. 661 * The checksum insertion position is given 662 * in @csum_offset, which is the offset from 663 * @csum_start to the checksum field in the L4 664 * header. This feature is only applicable to 665 * protocols such as TCP, UDP and ICMP where a 666 * standard (i.e. the 'IP-style' checksum) 667 * one's complement 16-bit checksum is used, 668 * using an IP pseudo-header to seed the 669 * calculation. Software will preload the L4 670 * checksum field with the IP pseudo-header 671 * checksum. 672 * 673 * For tunnel encapsulation, @csum_start and 674 * @csum_offset refer to the inner L4 675 * header. Supported tunnels encapsulations 676 * are: IPIP, GRE, and UDP. If the @encap 677 * is clear, no further processing by the 678 * device is required; software will 679 * calculate the outer header checksums. If 680 * the @encap is set, the device will 681 * offload the outer header checksums using 682 * LCO (local checksum offload) (see 683 * Documentation/networking/checksum-offloads.rst 684 * for more info). 685 * 686 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 687 * Offload 16-bit checksum computation to hardware. 688 * If @csum_l3 is set then the packet's L3 checksum is 689 * updated. Similarly, if @csum_l4 is set the the L4 690 * checksum is updated. If @encap is set then encap header 691 * checksums are also updated. 692 * 693 * IONIC_TXQ_DESC_OPCODE_TSO: 694 * Device preforms TCP segmentation offload 695 * (TSO). @hdr_len is the number of bytes 696 * to the end of TCP header (the offset to 697 * the TCP payload). @mss is the desired 698 * MSS, the TCP payload length for each 699 * segment. The device will calculate/ 700 * insert IP (IPv4 only) and TCP checksums 701 * for each segment. In the first data 702 * buffer containing the header template, 703 * the driver will set IPv4 checksum to 0 704 * and preload TCP checksum with the IP 705 * pseudo header calculated with IP length = 0. 706 * 707 * Supported tunnel encapsulations are IPIP, 708 * layer-3 GRE, and UDP. @hdr_len includes 709 * both outer and inner headers. The driver 710 * will set IPv4 checksum to zero and 711 * preload TCP checksum with IP pseudo 712 * header on the inner header. 713 * 714 * TCP ECN offload is supported. The device 715 * will set CWR flag in the first segment if 716 * CWR is set in the template header, and 717 * clear CWR in remaining segments. 718 * @flags: 719 * vlan: 720 * Insert an L2 VLAN header using @vlan_tci 721 * encap: 722 * Calculate encap header checksum 723 * csum_l3: 724 * Compute L3 header checksum 725 * csum_l4: 726 * Compute L4 header checksum 727 * tso_sot: 728 * TSO start 729 * tso_eot: 730 * TSO end 731 * @num_sg_elems: Number of scatter-gather elements in SG 732 * descriptor 733 * @addr: First data buffer's DMA address 734 * (Subsequent data buffers are on txq_sg_desc) 735 * @len: First data buffer's length, in bytes 736 * @vlan_tci: VLAN tag to insert in the packet (if requested 737 * by @V-bit). Includes .1p and .1q tags 738 * @hdr_len: Length of packet headers, including 739 * encapsulating outer header, if applicable 740 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 741 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 742 * all other modes. For 743 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 744 * of headers up to inner-most L4 header. For 745 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 746 * inner-most L4 payload, so inclusive of 747 * inner-most L4 header. 748 * @mss: Desired MSS value for TSO; only applicable for 749 * IONIC_TXQ_DESC_OPCODE_TSO 750 * @csum_start: Offset from packet to first byte checked in L4 checksum 751 * @csum_offset: Offset from csum_start to L4 checksum field 752 */ 753 struct ionic_txq_desc { 754 __le64 cmd; 755 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 756 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 757 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 758 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 759 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 760 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 761 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 762 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 763 764 /* common flags */ 765 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 766 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 767 768 /* flags for csum_hw opcode */ 769 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 770 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 771 772 /* flags for tso opcode */ 773 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 774 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 775 776 __le16 len; 777 union { 778 __le16 vlan_tci; 779 __le16 hword0; 780 }; 781 union { 782 __le16 csum_start; 783 __le16 hdr_len; 784 __le16 hword1; 785 }; 786 union { 787 __le16 csum_offset; 788 __le16 mss; 789 __le16 hword2; 790 }; 791 }; 792 793 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 794 u8 nsge, u64 addr) 795 { 796 u64 cmd; 797 798 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 799 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 800 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 801 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 802 803 return cmd; 804 }; 805 806 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 807 u8 *nsge, u64 *addr) 808 { 809 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 810 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 811 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 812 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 813 }; 814 815 /** 816 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 817 * @addr: DMA address of SG element data buffer 818 * @len: Length of SG element data buffer, in bytes 819 */ 820 struct ionic_txq_sg_elem { 821 __le64 addr; 822 __le16 len; 823 __le16 rsvd[3]; 824 }; 825 826 /** 827 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 828 * @elems: Scatter-gather elements 829 */ 830 struct ionic_txq_sg_desc { 831 #define IONIC_TX_MAX_SG_ELEMS 8 832 #define IONIC_TX_SG_DESC_STRIDE 8 833 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 834 }; 835 836 struct ionic_txq_sg_desc_v1 { 837 #define IONIC_TX_MAX_SG_ELEMS_V1 15 838 #define IONIC_TX_SG_DESC_STRIDE_V1 16 839 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 840 }; 841 842 /** 843 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 844 * @status: Status of the command (enum ionic_status_code) 845 * @comp_index: Index in the descriptor ring for which this is the completion 846 * @color: Color bit 847 */ 848 struct ionic_txq_comp { 849 u8 status; 850 u8 rsvd; 851 __le16 comp_index; 852 u8 rsvd2[11]; 853 u8 color; 854 }; 855 856 enum ionic_rxq_desc_opcode { 857 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 858 IONIC_RXQ_DESC_OPCODE_SG = 1, 859 }; 860 861 /** 862 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 863 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 864 * 865 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 866 * Receive full packet into data buffer 867 * starting at @addr. Results of 868 * receive, including actual bytes received, 869 * are recorded in Rx completion descriptor. 870 * 871 * @len: Data buffer's length, in bytes 872 * @addr: Data buffer's DMA address 873 */ 874 struct ionic_rxq_desc { 875 u8 opcode; 876 u8 rsvd[5]; 877 __le16 len; 878 __le64 addr; 879 }; 880 881 /** 882 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 883 * @addr: DMA address of SG element data buffer 884 * @len: Length of SG element data buffer, in bytes 885 */ 886 struct ionic_rxq_sg_elem { 887 __le64 addr; 888 __le16 len; 889 __le16 rsvd[3]; 890 }; 891 892 /** 893 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 894 * @elems: Scatter-gather elements 895 */ 896 struct ionic_rxq_sg_desc { 897 #define IONIC_RX_MAX_SG_ELEMS 8 898 #define IONIC_RX_SG_DESC_STRIDE 8 899 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 900 }; 901 902 /** 903 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 904 * @status: Status of the command (enum ionic_status_code) 905 * @num_sg_elems: Number of SG elements used by this descriptor 906 * @comp_index: Index in the descriptor ring for which this is the completion 907 * @rss_hash: 32-bit RSS hash 908 * @csum: 16-bit sum of the packet's L2 payload 909 * If the packet's L2 payload is odd length, an extra 910 * zero-value byte is included in the @csum calculation but 911 * not included in @len. 912 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 913 * set. Includes .1p and .1q tags. 914 * @len: Received packet length, in bytes. Excludes FCS. 915 * @csum_calc L2 payload checksum is computed or not 916 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 917 * 918 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 919 * The TCP checksum calculated by the device 920 * matched the checksum in the receive packet's 921 * TCP header. 922 * 923 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 924 * The TCP checksum calculated by the device did 925 * not match the checksum in the receive packet's 926 * TCP header. 927 * 928 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 929 * The UDP checksum calculated by the device 930 * matched the checksum in the receive packet's 931 * UDP header 932 * 933 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 934 * The UDP checksum calculated by the device did 935 * not match the checksum in the receive packet's 936 * UDP header. 937 * 938 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 939 * The IPv4 checksum calculated by the device 940 * matched the checksum in the receive packet's 941 * first IPv4 header. If the receive packet 942 * contains both a tunnel IPv4 header and a 943 * transport IPv4 header, the device validates the 944 * checksum for the both IPv4 headers. 945 * 946 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 947 * The IPv4 checksum calculated by the device did 948 * not match the checksum in the receive packet's 949 * first IPv4 header. If the receive packet 950 * contains both a tunnel IPv4 header and a 951 * transport IPv4 header, the device validates the 952 * checksum for both IP headers. 953 * 954 * IONIC_RXQ_COMP_CSUM_F_VLAN: 955 * The VLAN header was stripped and placed in @vlan_tci. 956 * 957 * IONIC_RXQ_COMP_CSUM_F_CALC: 958 * The checksum was calculated by the device. 959 * 960 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 961 */ 962 struct ionic_rxq_comp { 963 u8 status; 964 u8 num_sg_elems; 965 __le16 comp_index; 966 __le32 rss_hash; 967 __le16 csum; 968 __le16 vlan_tci; 969 __le16 len; 970 u8 csum_flags; 971 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 972 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 973 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 974 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 975 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 976 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 977 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 978 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 979 u8 pkt_type_color; 980 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 981 }; 982 983 enum ionic_pkt_type { 984 IONIC_PKT_TYPE_NON_IP = 0x000, 985 IONIC_PKT_TYPE_IPV4 = 0x001, 986 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 987 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 988 IONIC_PKT_TYPE_IPV6 = 0x008, 989 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 990 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 991 /* below types are only used if encap offloads are enabled on lif */ 992 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 993 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 994 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 995 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 996 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 997 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 998 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 999 }; 1000 1001 enum ionic_eth_hw_features { 1002 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1003 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1004 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1005 IONIC_ETH_HW_RX_HASH = BIT(3), 1006 IONIC_ETH_HW_RX_CSUM = BIT(4), 1007 IONIC_ETH_HW_TX_SG = BIT(5), 1008 IONIC_ETH_HW_RX_SG = BIT(6), 1009 IONIC_ETH_HW_TX_CSUM = BIT(7), 1010 IONIC_ETH_HW_TSO = BIT(8), 1011 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1012 IONIC_ETH_HW_TSO_ECN = BIT(10), 1013 IONIC_ETH_HW_TSO_GRE = BIT(11), 1014 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1015 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1016 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1017 IONIC_ETH_HW_TSO_UDP = BIT(15), 1018 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1019 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1020 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1021 IONIC_ETH_HW_TSO_GENEVE = BIT(19) 1022 }; 1023 1024 /** 1025 * struct ionic_q_control_cmd - Queue control command 1026 * @opcode: opcode 1027 * @type: Queue type 1028 * @lif_index: LIF index 1029 * @index: Queue index 1030 * @oper: Operation (enum ionic_q_control_oper) 1031 */ 1032 struct ionic_q_control_cmd { 1033 u8 opcode; 1034 u8 type; 1035 __le16 lif_index; 1036 __le32 index; 1037 u8 oper; 1038 u8 rsvd[55]; 1039 }; 1040 1041 typedef struct ionic_admin_comp ionic_q_control_comp; 1042 1043 enum q_control_oper { 1044 IONIC_Q_DISABLE = 0, 1045 IONIC_Q_ENABLE = 1, 1046 IONIC_Q_HANG_RESET = 2, 1047 }; 1048 1049 /** 1050 * enum ionic_phy_type - Physical connection type 1051 * @IONIC_PHY_TYPE_NONE: No PHY installed 1052 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1053 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1054 */ 1055 enum ionic_phy_type { 1056 IONIC_PHY_TYPE_NONE = 0, 1057 IONIC_PHY_TYPE_COPPER = 1, 1058 IONIC_PHY_TYPE_FIBER = 2, 1059 }; 1060 1061 /** 1062 * enum ionic_xcvr_state - Transceiver status 1063 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1064 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1065 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1066 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1067 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1068 */ 1069 enum ionic_xcvr_state { 1070 IONIC_XCVR_STATE_REMOVED = 0, 1071 IONIC_XCVR_STATE_INSERTED = 1, 1072 IONIC_XCVR_STATE_PENDING = 2, 1073 IONIC_XCVR_STATE_SPROM_READ = 3, 1074 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1075 }; 1076 1077 /** 1078 * enum ionic_xcvr_pid - Supported link modes 1079 */ 1080 enum ionic_xcvr_pid { 1081 IONIC_XCVR_PID_UNKNOWN = 0, 1082 1083 /* CU */ 1084 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1085 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1086 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1087 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1088 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1089 1090 /* Fiber */ 1091 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1092 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1093 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1094 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1095 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1096 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1097 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1098 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1099 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1100 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1101 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1102 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1103 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1104 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1105 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1106 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1107 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1108 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1109 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1110 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1111 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1112 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1113 }; 1114 1115 /** 1116 * enum ionic_port_type - Port types 1117 * @IONIC_PORT_TYPE_NONE: Port type not configured 1118 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1119 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1120 */ 1121 enum ionic_port_type { 1122 IONIC_PORT_TYPE_NONE = 0, 1123 IONIC_PORT_TYPE_ETH = 1, 1124 IONIC_PORT_TYPE_MGMT = 2, 1125 }; 1126 1127 /** 1128 * enum ionic_port_admin_state - Port config state 1129 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1130 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1131 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1132 */ 1133 enum ionic_port_admin_state { 1134 IONIC_PORT_ADMIN_STATE_NONE = 0, 1135 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1136 IONIC_PORT_ADMIN_STATE_UP = 2, 1137 }; 1138 1139 /** 1140 * enum ionic_port_oper_status - Port operational status 1141 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1142 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1143 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1144 */ 1145 enum ionic_port_oper_status { 1146 IONIC_PORT_OPER_STATUS_NONE = 0, 1147 IONIC_PORT_OPER_STATUS_UP = 1, 1148 IONIC_PORT_OPER_STATUS_DOWN = 2, 1149 }; 1150 1151 /** 1152 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1153 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1154 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1155 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1156 */ 1157 enum ionic_port_fec_type { 1158 IONIC_PORT_FEC_TYPE_NONE = 0, 1159 IONIC_PORT_FEC_TYPE_FC = 1, 1160 IONIC_PORT_FEC_TYPE_RS = 2, 1161 }; 1162 1163 /** 1164 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1165 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1166 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1167 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1168 */ 1169 enum ionic_port_pause_type { 1170 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1171 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1172 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1173 }; 1174 1175 /** 1176 * enum ionic_port_loopback_mode - Loopback modes 1177 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1178 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1179 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1180 */ 1181 enum ionic_port_loopback_mode { 1182 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1183 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1184 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1185 }; 1186 1187 /** 1188 * struct ionic_xcvr_status - Transceiver Status information 1189 * @state: Transceiver status (enum ionic_xcvr_state) 1190 * @phy: Physical connection type (enum ionic_phy_type) 1191 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1192 * @sprom: Transceiver sprom contents 1193 */ 1194 struct ionic_xcvr_status { 1195 u8 state; 1196 u8 phy; 1197 __le16 pid; 1198 u8 sprom[256]; 1199 }; 1200 1201 /** 1202 * union ionic_port_config - Port configuration 1203 * @speed: port speed (in Mbps) 1204 * @mtu: mtu 1205 * @state: port admin state (enum ionic_port_admin_state) 1206 * @an_enable: autoneg enable 1207 * @fec_type: fec type (enum ionic_port_fec_type) 1208 * @pause_type: pause type (enum ionic_port_pause_type) 1209 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1210 */ 1211 union ionic_port_config { 1212 struct { 1213 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1214 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1215 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1216 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1217 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1218 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1219 __le32 speed; 1220 __le32 mtu; 1221 u8 state; 1222 u8 an_enable; 1223 u8 fec_type; 1224 #define IONIC_PAUSE_TYPE_MASK 0x0f 1225 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1226 #define IONIC_PAUSE_F_TX 0x10 1227 #define IONIC_PAUSE_F_RX 0x20 1228 u8 pause_type; 1229 u8 loopback_mode; 1230 }; 1231 __le32 words[64]; 1232 }; 1233 1234 /** 1235 * struct ionic_port_status - Port Status information 1236 * @status: link status (enum ionic_port_oper_status) 1237 * @id: port id 1238 * @speed: link speed (in Mbps) 1239 * @link_down_count: number of times link went from from up to down 1240 * @fec_type: fec type (enum ionic_port_fec_type) 1241 * @xcvr: tranceiver status 1242 */ 1243 struct ionic_port_status { 1244 __le32 id; 1245 __le32 speed; 1246 u8 status; 1247 __le16 link_down_count; 1248 u8 fec_type; 1249 u8 rsvd[48]; 1250 struct ionic_xcvr_status xcvr; 1251 } __packed; 1252 1253 /** 1254 * struct ionic_port_identify_cmd - Port identify command 1255 * @opcode: opcode 1256 * @index: port index 1257 * @ver: Highest version of identify supported by driver 1258 */ 1259 struct ionic_port_identify_cmd { 1260 u8 opcode; 1261 u8 index; 1262 u8 ver; 1263 u8 rsvd[61]; 1264 }; 1265 1266 /** 1267 * struct ionic_port_identify_comp - Port identify command completion 1268 * @status: Status of the command (enum ionic_status_code) 1269 * @ver: Version of identify returned by device 1270 */ 1271 struct ionic_port_identify_comp { 1272 u8 status; 1273 u8 ver; 1274 u8 rsvd[14]; 1275 }; 1276 1277 /** 1278 * struct ionic_port_init_cmd - Port initialization command 1279 * @opcode: opcode 1280 * @index: port index 1281 * @info_pa: destination address for port info (struct ionic_port_info) 1282 */ 1283 struct ionic_port_init_cmd { 1284 u8 opcode; 1285 u8 index; 1286 u8 rsvd[6]; 1287 __le64 info_pa; 1288 u8 rsvd2[48]; 1289 }; 1290 1291 /** 1292 * struct ionic_port_init_comp - Port initialization command completion 1293 * @status: Status of the command (enum ionic_status_code) 1294 */ 1295 struct ionic_port_init_comp { 1296 u8 status; 1297 u8 rsvd[15]; 1298 }; 1299 1300 /** 1301 * struct ionic_port_reset_cmd - Port reset command 1302 * @opcode: opcode 1303 * @index: port index 1304 */ 1305 struct ionic_port_reset_cmd { 1306 u8 opcode; 1307 u8 index; 1308 u8 rsvd[62]; 1309 }; 1310 1311 /** 1312 * struct ionic_port_reset_comp - Port reset command completion 1313 * @status: Status of the command (enum ionic_status_code) 1314 */ 1315 struct ionic_port_reset_comp { 1316 u8 status; 1317 u8 rsvd[15]; 1318 }; 1319 1320 /** 1321 * enum ionic_stats_ctl_cmd - List of commands for stats control 1322 * @IONIC_STATS_CTL_RESET: Reset statistics 1323 */ 1324 enum ionic_stats_ctl_cmd { 1325 IONIC_STATS_CTL_RESET = 0, 1326 }; 1327 1328 /** 1329 * enum ionic_port_attr - List of device attributes 1330 * @IONIC_PORT_ATTR_STATE: Port state attribute 1331 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1332 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1333 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute 1334 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1335 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1336 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1337 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1338 */ 1339 enum ionic_port_attr { 1340 IONIC_PORT_ATTR_STATE = 0, 1341 IONIC_PORT_ATTR_SPEED = 1, 1342 IONIC_PORT_ATTR_MTU = 2, 1343 IONIC_PORT_ATTR_AUTONEG = 3, 1344 IONIC_PORT_ATTR_FEC = 4, 1345 IONIC_PORT_ATTR_PAUSE = 5, 1346 IONIC_PORT_ATTR_LOOPBACK = 6, 1347 IONIC_PORT_ATTR_STATS_CTRL = 7, 1348 }; 1349 1350 /** 1351 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1352 * @opcode: Opcode 1353 * @index: Port index 1354 * @attr: Attribute type (enum ionic_port_attr) 1355 * @state: Port state 1356 * @speed: Port speed 1357 * @mtu: Port MTU 1358 * @an_enable: Port autonegotiation setting 1359 * @fec_type: Port FEC type setting 1360 * @pause_type: Port pause type setting 1361 * @loopback_mode: Port loopback mode 1362 * @stats_ctl: Port stats setting 1363 */ 1364 struct ionic_port_setattr_cmd { 1365 u8 opcode; 1366 u8 index; 1367 u8 attr; 1368 u8 rsvd; 1369 union { 1370 u8 state; 1371 __le32 speed; 1372 __le32 mtu; 1373 u8 an_enable; 1374 u8 fec_type; 1375 u8 pause_type; 1376 u8 loopback_mode; 1377 u8 stats_ctl; 1378 u8 rsvd2[60]; 1379 }; 1380 }; 1381 1382 /** 1383 * struct ionic_port_setattr_comp - Port set attr command completion 1384 * @status: Status of the command (enum ionic_status_code) 1385 * @color: Color bit 1386 */ 1387 struct ionic_port_setattr_comp { 1388 u8 status; 1389 u8 rsvd[14]; 1390 u8 color; 1391 }; 1392 1393 /** 1394 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1395 * @opcode: Opcode 1396 * @index: port index 1397 * @attr: Attribute type (enum ionic_port_attr) 1398 */ 1399 struct ionic_port_getattr_cmd { 1400 u8 opcode; 1401 u8 index; 1402 u8 attr; 1403 u8 rsvd[61]; 1404 }; 1405 1406 /** 1407 * struct ionic_port_getattr_comp - Port get attr command completion 1408 * @status: Status of the command (enum ionic_status_code) 1409 * @state: Port state 1410 * @speed: Port speed 1411 * @mtu: Port MTU 1412 * @an_enable: Port autonegotiation setting 1413 * @fec_type: Port FEC type setting 1414 * @pause_type: Port pause type setting 1415 * @loopback_mode: Port loopback mode 1416 * @color: Color bit 1417 */ 1418 struct ionic_port_getattr_comp { 1419 u8 status; 1420 u8 rsvd[3]; 1421 union { 1422 u8 state; 1423 __le32 speed; 1424 __le32 mtu; 1425 u8 an_enable; 1426 u8 fec_type; 1427 u8 pause_type; 1428 u8 loopback_mode; 1429 u8 rsvd2[11]; 1430 } __packed; 1431 u8 color; 1432 }; 1433 1434 /** 1435 * struct ionic_lif_status - LIF status register 1436 * @eid: most recent NotifyQ event id 1437 * @port_num: port the LIF is connected to 1438 * @link_status: port status (enum ionic_port_oper_status) 1439 * @link_speed: speed of link in Mbps 1440 * @link_down_count: number of times link went from up to down 1441 */ 1442 struct ionic_lif_status { 1443 __le64 eid; 1444 u8 port_num; 1445 u8 rsvd; 1446 __le16 link_status; 1447 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1448 __le16 link_down_count; 1449 u8 rsvd2[46]; 1450 }; 1451 1452 /** 1453 * struct ionic_lif_reset_cmd - LIF reset command 1454 * @opcode: opcode 1455 * @index: LIF index 1456 */ 1457 struct ionic_lif_reset_cmd { 1458 u8 opcode; 1459 u8 rsvd; 1460 __le16 index; 1461 __le32 rsvd2[15]; 1462 }; 1463 1464 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1465 1466 enum ionic_dev_state { 1467 IONIC_DEV_DISABLE = 0, 1468 IONIC_DEV_ENABLE = 1, 1469 IONIC_DEV_HANG_RESET = 2, 1470 }; 1471 1472 /** 1473 * enum ionic_dev_attr - List of device attributes 1474 * @IONIC_DEV_ATTR_STATE: Device state attribute 1475 * @IONIC_DEV_ATTR_NAME: Device name attribute 1476 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1477 */ 1478 enum ionic_dev_attr { 1479 IONIC_DEV_ATTR_STATE = 0, 1480 IONIC_DEV_ATTR_NAME = 1, 1481 IONIC_DEV_ATTR_FEATURES = 2, 1482 }; 1483 1484 /** 1485 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1486 * @opcode: Opcode 1487 * @attr: Attribute type (enum ionic_dev_attr) 1488 * @state: Device state (enum ionic_dev_state) 1489 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1490 * @features: Device features 1491 */ 1492 struct ionic_dev_setattr_cmd { 1493 u8 opcode; 1494 u8 attr; 1495 __le16 rsvd; 1496 union { 1497 u8 state; 1498 char name[IONIC_IFNAMSIZ]; 1499 __le64 features; 1500 u8 rsvd2[60]; 1501 } __packed; 1502 }; 1503 1504 /** 1505 * struct ionic_dev_setattr_comp - Device set attr command completion 1506 * @status: Status of the command (enum ionic_status_code) 1507 * @features: Device features 1508 * @color: Color bit 1509 */ 1510 struct ionic_dev_setattr_comp { 1511 u8 status; 1512 u8 rsvd[3]; 1513 union { 1514 __le64 features; 1515 u8 rsvd2[11]; 1516 } __packed; 1517 u8 color; 1518 }; 1519 1520 /** 1521 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1522 * @opcode: opcode 1523 * @attr: Attribute type (enum ionic_dev_attr) 1524 */ 1525 struct ionic_dev_getattr_cmd { 1526 u8 opcode; 1527 u8 attr; 1528 u8 rsvd[62]; 1529 }; 1530 1531 /** 1532 * struct ionic_dev_setattr_comp - Device set attr command completion 1533 * @status: Status of the command (enum ionic_status_code) 1534 * @features: Device features 1535 * @color: Color bit 1536 */ 1537 struct ionic_dev_getattr_comp { 1538 u8 status; 1539 u8 rsvd[3]; 1540 union { 1541 __le64 features; 1542 u8 rsvd2[11]; 1543 } __packed; 1544 u8 color; 1545 }; 1546 1547 /** 1548 * RSS parameters 1549 */ 1550 #define IONIC_RSS_HASH_KEY_SIZE 40 1551 1552 enum ionic_rss_hash_types { 1553 IONIC_RSS_TYPE_IPV4 = BIT(0), 1554 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1555 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1556 IONIC_RSS_TYPE_IPV6 = BIT(3), 1557 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1558 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1559 }; 1560 1561 /** 1562 * enum ionic_lif_attr - List of LIF attributes 1563 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1564 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1565 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1566 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1567 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1568 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1569 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1570 */ 1571 enum ionic_lif_attr { 1572 IONIC_LIF_ATTR_STATE = 0, 1573 IONIC_LIF_ATTR_NAME = 1, 1574 IONIC_LIF_ATTR_MTU = 2, 1575 IONIC_LIF_ATTR_MAC = 3, 1576 IONIC_LIF_ATTR_FEATURES = 4, 1577 IONIC_LIF_ATTR_RSS = 5, 1578 IONIC_LIF_ATTR_STATS_CTRL = 6, 1579 }; 1580 1581 /** 1582 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1583 * @opcode: Opcode 1584 * @attr: Attribute type (enum ionic_lif_attr) 1585 * @index: LIF index 1586 * @state: LIF state (enum ionic_lif_state) 1587 * @name: The netdev name string, 0 terminated 1588 * @mtu: Mtu 1589 * @mac: Station mac 1590 * @features: Features (enum ionic_eth_hw_features) 1591 * @rss: RSS properties 1592 * @types: The hash types to enable (see rss_hash_types) 1593 * @key: The hash secret key 1594 * @addr: Address for the indirection table shared memory 1595 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1596 */ 1597 struct ionic_lif_setattr_cmd { 1598 u8 opcode; 1599 u8 attr; 1600 __le16 index; 1601 union { 1602 u8 state; 1603 char name[IONIC_IFNAMSIZ]; 1604 __le32 mtu; 1605 u8 mac[6]; 1606 __le64 features; 1607 struct { 1608 __le16 types; 1609 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1610 u8 rsvd[6]; 1611 __le64 addr; 1612 } rss; 1613 u8 stats_ctl; 1614 u8 rsvd[60]; 1615 } __packed; 1616 }; 1617 1618 /** 1619 * struct ionic_lif_setattr_comp - LIF set attr command completion 1620 * @status: Status of the command (enum ionic_status_code) 1621 * @comp_index: Index in the descriptor ring for which this is the completion 1622 * @features: features (enum ionic_eth_hw_features) 1623 * @color: Color bit 1624 */ 1625 struct ionic_lif_setattr_comp { 1626 u8 status; 1627 u8 rsvd; 1628 __le16 comp_index; 1629 union { 1630 __le64 features; 1631 u8 rsvd2[11]; 1632 } __packed; 1633 u8 color; 1634 }; 1635 1636 /** 1637 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1638 * @opcode: Opcode 1639 * @attr: Attribute type (enum ionic_lif_attr) 1640 * @index: LIF index 1641 */ 1642 struct ionic_lif_getattr_cmd { 1643 u8 opcode; 1644 u8 attr; 1645 __le16 index; 1646 u8 rsvd[60]; 1647 }; 1648 1649 /** 1650 * struct ionic_lif_getattr_comp - LIF get attr command completion 1651 * @status: Status of the command (enum ionic_status_code) 1652 * @comp_index: Index in the descriptor ring for which this is the completion 1653 * @state: LIF state (enum ionic_lif_state) 1654 * @name: The netdev name string, 0 terminated 1655 * @mtu: Mtu 1656 * @mac: Station mac 1657 * @features: Features (enum ionic_eth_hw_features) 1658 * @color: Color bit 1659 */ 1660 struct ionic_lif_getattr_comp { 1661 u8 status; 1662 u8 rsvd; 1663 __le16 comp_index; 1664 union { 1665 u8 state; 1666 __le32 mtu; 1667 u8 mac[6]; 1668 __le64 features; 1669 u8 rsvd2[11]; 1670 } __packed; 1671 u8 color; 1672 }; 1673 1674 enum ionic_rx_mode { 1675 IONIC_RX_MODE_F_UNICAST = BIT(0), 1676 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1677 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1678 IONIC_RX_MODE_F_PROMISC = BIT(3), 1679 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1680 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1681 }; 1682 1683 /** 1684 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1685 * @opcode: opcode 1686 * @lif_index: LIF index 1687 * @rx_mode: Rx mode flags: 1688 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1689 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1690 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1691 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1692 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1693 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1694 */ 1695 struct ionic_rx_mode_set_cmd { 1696 u8 opcode; 1697 u8 rsvd; 1698 __le16 lif_index; 1699 __le16 rx_mode; 1700 __le16 rsvd2[29]; 1701 }; 1702 1703 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1704 1705 enum ionic_rx_filter_match_type { 1706 IONIC_RX_FILTER_MATCH_VLAN = 0, 1707 IONIC_RX_FILTER_MATCH_MAC, 1708 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1709 }; 1710 1711 /** 1712 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1713 * @opcode: opcode 1714 * @qtype: Queue type 1715 * @lif_index: LIF index 1716 * @qid: Queue ID 1717 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1718 * @vlan: VLAN filter 1719 * @vlan: VLAN ID 1720 * @mac: MAC filter 1721 * @addr: MAC address (network-byte order) 1722 * @mac_vlan: MACVLAN filter 1723 * @vlan: VLAN ID 1724 * @addr: MAC address (network-byte order) 1725 */ 1726 struct ionic_rx_filter_add_cmd { 1727 u8 opcode; 1728 u8 qtype; 1729 __le16 lif_index; 1730 __le32 qid; 1731 __le16 match; 1732 union { 1733 struct { 1734 __le16 vlan; 1735 } vlan; 1736 struct { 1737 u8 addr[6]; 1738 } mac; 1739 struct { 1740 __le16 vlan; 1741 u8 addr[6]; 1742 } mac_vlan; 1743 u8 rsvd[54]; 1744 }; 1745 }; 1746 1747 /** 1748 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1749 * @status: Status of the command (enum ionic_status_code) 1750 * @comp_index: Index in the descriptor ring for which this is the completion 1751 * @filter_id: Filter ID 1752 * @color: Color bit 1753 */ 1754 struct ionic_rx_filter_add_comp { 1755 u8 status; 1756 u8 rsvd; 1757 __le16 comp_index; 1758 __le32 filter_id; 1759 u8 rsvd2[7]; 1760 u8 color; 1761 }; 1762 1763 /** 1764 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1765 * @opcode: opcode 1766 * @lif_index: LIF index 1767 * @filter_id: Filter ID 1768 */ 1769 struct ionic_rx_filter_del_cmd { 1770 u8 opcode; 1771 u8 rsvd; 1772 __le16 lif_index; 1773 __le32 filter_id; 1774 u8 rsvd2[56]; 1775 }; 1776 1777 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1778 1779 enum ionic_vf_attr { 1780 IONIC_VF_ATTR_SPOOFCHK = 1, 1781 IONIC_VF_ATTR_TRUST = 2, 1782 IONIC_VF_ATTR_MAC = 3, 1783 IONIC_VF_ATTR_LINKSTATE = 4, 1784 IONIC_VF_ATTR_VLAN = 5, 1785 IONIC_VF_ATTR_RATE = 6, 1786 IONIC_VF_ATTR_STATSADDR = 7, 1787 }; 1788 1789 /** 1790 * enum ionic_vf_link_status - Virtual Function link status 1791 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1792 * @IONIC_VF_LINK_STATUS_UP: Link always up 1793 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 1794 */ 1795 enum ionic_vf_link_status { 1796 IONIC_VF_LINK_STATUS_AUTO = 0, 1797 IONIC_VF_LINK_STATUS_UP = 1, 1798 IONIC_VF_LINK_STATUS_DOWN = 2, 1799 }; 1800 1801 /** 1802 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1803 * @opcode: Opcode 1804 * @attr: Attribute type (enum ionic_vf_attr) 1805 * @vf_index: VF index 1806 * @macaddr: mac address 1807 * @vlanid: vlan ID 1808 * @maxrate: max Tx rate in Mbps 1809 * @spoofchk: enable address spoof checking 1810 * @trust: enable VF trust 1811 * @linkstate: set link up or down 1812 * @stats_pa: set DMA address for VF stats 1813 */ 1814 struct ionic_vf_setattr_cmd { 1815 u8 opcode; 1816 u8 attr; 1817 __le16 vf_index; 1818 union { 1819 u8 macaddr[6]; 1820 __le16 vlanid; 1821 __le32 maxrate; 1822 u8 spoofchk; 1823 u8 trust; 1824 u8 linkstate; 1825 __le64 stats_pa; 1826 u8 pad[60]; 1827 } __packed; 1828 }; 1829 1830 struct ionic_vf_setattr_comp { 1831 u8 status; 1832 u8 attr; 1833 __le16 vf_index; 1834 __le16 comp_index; 1835 u8 rsvd[9]; 1836 u8 color; 1837 }; 1838 1839 /** 1840 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 1841 * @opcode: Opcode 1842 * @attr: Attribute type (enum ionic_vf_attr) 1843 * @vf_index: VF index 1844 */ 1845 struct ionic_vf_getattr_cmd { 1846 u8 opcode; 1847 u8 attr; 1848 __le16 vf_index; 1849 u8 rsvd[60]; 1850 }; 1851 1852 struct ionic_vf_getattr_comp { 1853 u8 status; 1854 u8 attr; 1855 __le16 vf_index; 1856 union { 1857 u8 macaddr[6]; 1858 __le16 vlanid; 1859 __le32 maxrate; 1860 u8 spoofchk; 1861 u8 trust; 1862 u8 linkstate; 1863 __le64 stats_pa; 1864 u8 pad[11]; 1865 } __packed; 1866 u8 color; 1867 }; 1868 1869 /** 1870 * struct ionic_qos_identify_cmd - QoS identify command 1871 * @opcode: opcode 1872 * @ver: Highest version of identify supported by driver 1873 * 1874 */ 1875 struct ionic_qos_identify_cmd { 1876 u8 opcode; 1877 u8 ver; 1878 u8 rsvd[62]; 1879 }; 1880 1881 /** 1882 * struct ionic_qos_identify_comp - QoS identify command completion 1883 * @status: Status of the command (enum ionic_status_code) 1884 * @ver: Version of identify returned by device 1885 */ 1886 struct ionic_qos_identify_comp { 1887 u8 status; 1888 u8 ver; 1889 u8 rsvd[14]; 1890 }; 1891 1892 #define IONIC_QOS_TC_MAX 8 1893 #define IONIC_QOS_ALL_TC 0xFF 1894 /* Capri max supported, should be renamed. */ 1895 #define IONIC_QOS_CLASS_MAX 7 1896 #define IONIC_QOS_PCP_MAX 8 1897 #define IONIC_QOS_CLASS_NAME_SZ 32 1898 #define IONIC_QOS_DSCP_MAX 64 1899 #define IONIC_QOS_ALL_PCP 0xFF 1900 #define IONIC_DSCP_BLOCK_SIZE 8 1901 1902 /** 1903 * enum ionic_qos_class 1904 */ 1905 enum ionic_qos_class { 1906 IONIC_QOS_CLASS_DEFAULT = 0, 1907 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1908 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1909 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1910 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1911 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1912 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1913 }; 1914 1915 /** 1916 * enum ionic_qos_class_type - Traffic classification criteria 1917 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 1918 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 1919 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 1920 */ 1921 enum ionic_qos_class_type { 1922 IONIC_QOS_CLASS_TYPE_NONE = 0, 1923 IONIC_QOS_CLASS_TYPE_PCP = 1, 1924 IONIC_QOS_CLASS_TYPE_DSCP = 2, 1925 }; 1926 1927 /** 1928 * enum ionic_qos_sched_type - QoS class scheduling type 1929 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 1930 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 1931 */ 1932 enum ionic_qos_sched_type { 1933 IONIC_QOS_SCHED_TYPE_STRICT = 0, 1934 IONIC_QOS_SCHED_TYPE_DWRR = 1, 1935 }; 1936 1937 /** 1938 * union ionic_qos_config - QoS configuration structure 1939 * @flags: Configuration flags 1940 * IONIC_QOS_CONFIG_F_ENABLE enable 1941 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 1942 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1943 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1944 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 1945 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 1946 * @class_type: QoS class type (enum ionic_qos_class_type) 1947 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 1948 * @name: QoS class name 1949 * @mtu: MTU of the class 1950 * @pfc_cos: Priority-Flow Control class of service 1951 * @dwrr_weight: QoS class scheduling weight 1952 * @strict_rlmt: Rate limit for strict priority scheduling 1953 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) 1954 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) 1955 * @dot1q_pcp: Dot1q pcp value 1956 * @ndscp: Number of valid dscp values in the ip_dscp field 1957 * @ip_dscp: IP dscp values 1958 */ 1959 union ionic_qos_config { 1960 struct { 1961 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1962 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 1963 /* Used to rewrite PCP or DSCP value. */ 1964 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1965 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1966 /* Non-disruptive TC update */ 1967 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 1968 u8 flags; 1969 u8 sched_type; 1970 u8 class_type; 1971 u8 pause_type; 1972 char name[IONIC_QOS_CLASS_NAME_SZ]; 1973 __le32 mtu; 1974 /* flow control */ 1975 u8 pfc_cos; 1976 /* scheduler */ 1977 union { 1978 u8 dwrr_weight; 1979 __le64 strict_rlmt; 1980 }; 1981 /* marking */ 1982 /* Used to rewrite PCP or DSCP value. */ 1983 union { 1984 u8 rw_dot1q_pcp; 1985 u8 rw_ip_dscp; 1986 }; 1987 /* classification */ 1988 union { 1989 u8 dot1q_pcp; 1990 struct { 1991 u8 ndscp; 1992 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 1993 }; 1994 }; 1995 }; 1996 __le32 words[64]; 1997 }; 1998 1999 /** 2000 * union ionic_qos_identity - QoS identity structure 2001 * @version: Version of the identify structure 2002 * @type: QoS system type 2003 * @nclasses: Number of usable QoS classes 2004 * @config: Current configuration of classes 2005 */ 2006 union ionic_qos_identity { 2007 struct { 2008 u8 version; 2009 u8 type; 2010 u8 rsvd[62]; 2011 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2012 }; 2013 __le32 words[478]; 2014 }; 2015 2016 /** 2017 * struct ionic_qos_init_cmd - QoS config init command 2018 * @opcode: Opcode 2019 * @group: QoS class id 2020 * @info_pa: destination address for qos info 2021 */ 2022 struct ionic_qos_init_cmd { 2023 u8 opcode; 2024 u8 group; 2025 u8 rsvd[6]; 2026 __le64 info_pa; 2027 u8 rsvd1[48]; 2028 }; 2029 2030 typedef struct ionic_admin_comp ionic_qos_init_comp; 2031 2032 /** 2033 * struct ionic_qos_reset_cmd - QoS config reset command 2034 * @opcode: Opcode 2035 * @group: QoS class id 2036 */ 2037 struct ionic_qos_reset_cmd { 2038 u8 opcode; 2039 u8 group; 2040 u8 rsvd[62]; 2041 }; 2042 2043 /** 2044 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 2045 * @opcode: Opcode 2046 */ 2047 struct ionic_qos_clear_stats_cmd { 2048 u8 opcode; 2049 u8 group_bitmap; 2050 u8 rsvd[62]; 2051 }; 2052 2053 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2054 2055 /** 2056 * struct ionic_fw_download_cmd - Firmware download command 2057 * @opcode: opcode 2058 * @addr: dma address of the firmware buffer 2059 * @offset: offset of the firmware buffer within the full image 2060 * @length: number of valid bytes in the firmware buffer 2061 */ 2062 struct ionic_fw_download_cmd { 2063 u8 opcode; 2064 u8 rsvd[3]; 2065 __le32 offset; 2066 __le64 addr; 2067 __le32 length; 2068 }; 2069 2070 typedef struct ionic_admin_comp ionic_fw_download_comp; 2071 2072 /** 2073 * enum ionic_fw_control_oper - FW control operations 2074 * @IONIC_FW_RESET: Reset firmware 2075 * @IONIC_FW_INSTALL: Install firmware 2076 * @IONIC_FW_ACTIVATE: Activate firmware 2077 * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 2078 * @IONIC_FW_INSTALL_STATUS: Firmware installation status 2079 * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 2080 * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2081 */ 2082 enum ionic_fw_control_oper { 2083 IONIC_FW_RESET = 0, 2084 IONIC_FW_INSTALL = 1, 2085 IONIC_FW_ACTIVATE = 2, 2086 IONIC_FW_INSTALL_ASYNC = 3, 2087 IONIC_FW_INSTALL_STATUS = 4, 2088 IONIC_FW_ACTIVATE_ASYNC = 5, 2089 IONIC_FW_ACTIVATE_STATUS = 6, 2090 IONIC_FW_UPDATE_CLEANUP = 7, 2091 }; 2092 2093 /** 2094 * struct ionic_fw_control_cmd - Firmware control command 2095 * @opcode: opcode 2096 * @oper: firmware control operation (enum ionic_fw_control_oper) 2097 * @slot: slot to activate 2098 */ 2099 struct ionic_fw_control_cmd { 2100 u8 opcode; 2101 u8 rsvd[3]; 2102 u8 oper; 2103 u8 slot; 2104 u8 rsvd1[58]; 2105 }; 2106 2107 /** 2108 * struct ionic_fw_control_comp - Firmware control copletion 2109 * @status: Status of the command (enum ionic_status_code) 2110 * @comp_index: Index in the descriptor ring for which this is the completion 2111 * @slot: Slot where the firmware was installed 2112 * @color: Color bit 2113 */ 2114 struct ionic_fw_control_comp { 2115 u8 status; 2116 u8 rsvd; 2117 __le16 comp_index; 2118 u8 slot; 2119 u8 rsvd1[10]; 2120 u8 color; 2121 }; 2122 2123 /****************************************************************** 2124 ******************* RDMA Commands ******************************** 2125 ******************************************************************/ 2126 2127 /** 2128 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2129 * @opcode: opcode 2130 * @lif_index: LIF index 2131 * 2132 * There is no RDMA specific dev command completion struct. Completion uses 2133 * the common struct ionic_admin_comp. Only the status is indicated. 2134 * Nonzero status means the LIF does not support RDMA. 2135 **/ 2136 struct ionic_rdma_reset_cmd { 2137 u8 opcode; 2138 u8 rsvd; 2139 __le16 lif_index; 2140 u8 rsvd2[60]; 2141 }; 2142 2143 /** 2144 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2145 * @opcode: opcode, 52, 53 2146 * @lif_index: LIF index 2147 * @qid_ver: (qid | (RDMA version << 24)) 2148 * @cid: intr, eq_id, or cq_id 2149 * @dbid: doorbell page id 2150 * @depth_log2: log base two of queue depth 2151 * @stride_log2: log base two of queue stride 2152 * @dma_addr: address of the queue memory 2153 * 2154 * The same command struct is used to create an RDMA event queue, completion 2155 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2156 * queue, an event queue id for a completion queue, or a completion queue id 2157 * for an RDMA admin queue. 2158 * 2159 * The queue created via a dev command must be contiguous in dma space. 2160 * 2161 * The dev commands are intended only to be used during driver initialization, 2162 * to create queues supporting the RDMA admin queue. Other queues, and other 2163 * types of RDMA resources like memory regions, will be created and registered 2164 * via the RDMA admin queue, and will support a more complete interface 2165 * providing scatter gather lists for larger, scattered queue buffers and 2166 * memory registration. 2167 * 2168 * There is no RDMA specific dev command completion struct. Completion uses 2169 * the common struct ionic_admin_comp. Only the status is indicated. 2170 **/ 2171 struct ionic_rdma_queue_cmd { 2172 u8 opcode; 2173 u8 rsvd; 2174 __le16 lif_index; 2175 __le32 qid_ver; 2176 __le32 cid; 2177 __le16 dbid; 2178 u8 depth_log2; 2179 u8 stride_log2; 2180 __le64 dma_addr; 2181 u8 rsvd2[40]; 2182 }; 2183 2184 /****************************************************************** 2185 ******************* Notify Events ******************************** 2186 ******************************************************************/ 2187 2188 /** 2189 * struct ionic_notifyq_event - Generic event reporting structure 2190 * @eid: event number 2191 * @ecode: event code 2192 * @data: unspecified data about the event 2193 * 2194 * This is the generic event report struct from which the other 2195 * actual events will be formed. 2196 */ 2197 struct ionic_notifyq_event { 2198 __le64 eid; 2199 __le16 ecode; 2200 u8 data[54]; 2201 }; 2202 2203 /** 2204 * struct ionic_link_change_event - Link change event notification 2205 * @eid: event number 2206 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2207 * @link_status: link up/down, with error bits (enum ionic_port_status) 2208 * @link_speed: speed of the network link 2209 * 2210 * Sent when the network link state changes between UP and DOWN 2211 */ 2212 struct ionic_link_change_event { 2213 __le64 eid; 2214 __le16 ecode; 2215 __le16 link_status; 2216 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2217 u8 rsvd[48]; 2218 }; 2219 2220 /** 2221 * struct ionic_reset_event - Reset event notification 2222 * @eid: event number 2223 * @ecode: event code = IONIC_EVENT_RESET 2224 * @reset_code: reset type 2225 * @state: 0=pending, 1=complete, 2=error 2226 * 2227 * Sent when the NIC or some subsystem is going to be or 2228 * has been reset. 2229 */ 2230 struct ionic_reset_event { 2231 __le64 eid; 2232 __le16 ecode; 2233 u8 reset_code; 2234 u8 state; 2235 u8 rsvd[52]; 2236 }; 2237 2238 /** 2239 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2240 * @eid: event number 2241 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2242 */ 2243 struct ionic_heartbeat_event { 2244 __le64 eid; 2245 __le16 ecode; 2246 u8 rsvd[54]; 2247 }; 2248 2249 /** 2250 * struct ionic_log_event - Sent to notify the driver of an internal error 2251 * @eid: event number 2252 * @ecode: event code = IONIC_EVENT_LOG 2253 * @data: log data 2254 */ 2255 struct ionic_log_event { 2256 __le64 eid; 2257 __le16 ecode; 2258 u8 data[54]; 2259 }; 2260 2261 /** 2262 * struct ionic_xcvr_event - Transceiver change event 2263 * @eid: event number 2264 * @ecode: event code = IONIC_EVENT_XCVR 2265 */ 2266 struct ionic_xcvr_event { 2267 __le64 eid; 2268 __le16 ecode; 2269 u8 rsvd[54]; 2270 }; 2271 2272 /** 2273 * struct ionic_port_stats - Port statistics structure 2274 */ 2275 struct ionic_port_stats { 2276 __le64 frames_rx_ok; 2277 __le64 frames_rx_all; 2278 __le64 frames_rx_bad_fcs; 2279 __le64 frames_rx_bad_all; 2280 __le64 octets_rx_ok; 2281 __le64 octets_rx_all; 2282 __le64 frames_rx_unicast; 2283 __le64 frames_rx_multicast; 2284 __le64 frames_rx_broadcast; 2285 __le64 frames_rx_pause; 2286 __le64 frames_rx_bad_length; 2287 __le64 frames_rx_undersized; 2288 __le64 frames_rx_oversized; 2289 __le64 frames_rx_fragments; 2290 __le64 frames_rx_jabber; 2291 __le64 frames_rx_pripause; 2292 __le64 frames_rx_stomped_crc; 2293 __le64 frames_rx_too_long; 2294 __le64 frames_rx_vlan_good; 2295 __le64 frames_rx_dropped; 2296 __le64 frames_rx_less_than_64b; 2297 __le64 frames_rx_64b; 2298 __le64 frames_rx_65b_127b; 2299 __le64 frames_rx_128b_255b; 2300 __le64 frames_rx_256b_511b; 2301 __le64 frames_rx_512b_1023b; 2302 __le64 frames_rx_1024b_1518b; 2303 __le64 frames_rx_1519b_2047b; 2304 __le64 frames_rx_2048b_4095b; 2305 __le64 frames_rx_4096b_8191b; 2306 __le64 frames_rx_8192b_9215b; 2307 __le64 frames_rx_other; 2308 __le64 frames_tx_ok; 2309 __le64 frames_tx_all; 2310 __le64 frames_tx_bad; 2311 __le64 octets_tx_ok; 2312 __le64 octets_tx_total; 2313 __le64 frames_tx_unicast; 2314 __le64 frames_tx_multicast; 2315 __le64 frames_tx_broadcast; 2316 __le64 frames_tx_pause; 2317 __le64 frames_tx_pripause; 2318 __le64 frames_tx_vlan; 2319 __le64 frames_tx_less_than_64b; 2320 __le64 frames_tx_64b; 2321 __le64 frames_tx_65b_127b; 2322 __le64 frames_tx_128b_255b; 2323 __le64 frames_tx_256b_511b; 2324 __le64 frames_tx_512b_1023b; 2325 __le64 frames_tx_1024b_1518b; 2326 __le64 frames_tx_1519b_2047b; 2327 __le64 frames_tx_2048b_4095b; 2328 __le64 frames_tx_4096b_8191b; 2329 __le64 frames_tx_8192b_9215b; 2330 __le64 frames_tx_other; 2331 __le64 frames_tx_pri_0; 2332 __le64 frames_tx_pri_1; 2333 __le64 frames_tx_pri_2; 2334 __le64 frames_tx_pri_3; 2335 __le64 frames_tx_pri_4; 2336 __le64 frames_tx_pri_5; 2337 __le64 frames_tx_pri_6; 2338 __le64 frames_tx_pri_7; 2339 __le64 frames_rx_pri_0; 2340 __le64 frames_rx_pri_1; 2341 __le64 frames_rx_pri_2; 2342 __le64 frames_rx_pri_3; 2343 __le64 frames_rx_pri_4; 2344 __le64 frames_rx_pri_5; 2345 __le64 frames_rx_pri_6; 2346 __le64 frames_rx_pri_7; 2347 __le64 tx_pripause_0_1us_count; 2348 __le64 tx_pripause_1_1us_count; 2349 __le64 tx_pripause_2_1us_count; 2350 __le64 tx_pripause_3_1us_count; 2351 __le64 tx_pripause_4_1us_count; 2352 __le64 tx_pripause_5_1us_count; 2353 __le64 tx_pripause_6_1us_count; 2354 __le64 tx_pripause_7_1us_count; 2355 __le64 rx_pripause_0_1us_count; 2356 __le64 rx_pripause_1_1us_count; 2357 __le64 rx_pripause_2_1us_count; 2358 __le64 rx_pripause_3_1us_count; 2359 __le64 rx_pripause_4_1us_count; 2360 __le64 rx_pripause_5_1us_count; 2361 __le64 rx_pripause_6_1us_count; 2362 __le64 rx_pripause_7_1us_count; 2363 __le64 rx_pause_1us_count; 2364 __le64 frames_tx_truncated; 2365 }; 2366 2367 struct ionic_mgmt_port_stats { 2368 __le64 frames_rx_ok; 2369 __le64 frames_rx_all; 2370 __le64 frames_rx_bad_fcs; 2371 __le64 frames_rx_bad_all; 2372 __le64 octets_rx_ok; 2373 __le64 octets_rx_all; 2374 __le64 frames_rx_unicast; 2375 __le64 frames_rx_multicast; 2376 __le64 frames_rx_broadcast; 2377 __le64 frames_rx_pause; 2378 __le64 frames_rx_bad_length; 2379 __le64 frames_rx_undersized; 2380 __le64 frames_rx_oversized; 2381 __le64 frames_rx_fragments; 2382 __le64 frames_rx_jabber; 2383 __le64 frames_rx_64b; 2384 __le64 frames_rx_65b_127b; 2385 __le64 frames_rx_128b_255b; 2386 __le64 frames_rx_256b_511b; 2387 __le64 frames_rx_512b_1023b; 2388 __le64 frames_rx_1024b_1518b; 2389 __le64 frames_rx_gt_1518b; 2390 __le64 frames_rx_fifo_full; 2391 __le64 frames_tx_ok; 2392 __le64 frames_tx_all; 2393 __le64 frames_tx_bad; 2394 __le64 octets_tx_ok; 2395 __le64 octets_tx_total; 2396 __le64 frames_tx_unicast; 2397 __le64 frames_tx_multicast; 2398 __le64 frames_tx_broadcast; 2399 __le64 frames_tx_pause; 2400 }; 2401 2402 enum ionic_pb_buffer_drop_stats { 2403 IONIC_BUFFER_INTRINSIC_DROP = 0, 2404 IONIC_BUFFER_DISCARDED, 2405 IONIC_BUFFER_ADMITTED, 2406 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2407 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2408 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2409 IONIC_BUFFER_TRUNCATION_DROP, 2410 IONIC_BUFFER_PORT_DISABLED_DROP, 2411 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2412 IONIC_BUFFER_SPAN_TAIL_DROP, 2413 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2414 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2415 IONIC_BUFFER_INVALID_PORT_DROP, 2416 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2417 IONIC_BUFFER_DROP_MAX, 2418 }; 2419 2420 enum ionic_oflow_drop_stats { 2421 IONIC_OFLOW_OCCUPANCY_DROP, 2422 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2423 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2424 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2425 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2426 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2427 IONIC_OFLOW_DROP_MAX, 2428 }; 2429 2430 /** 2431 * struct port_pb_stats - packet buffers system stats 2432 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2433 */ 2434 struct ionic_port_pb_stats { 2435 __le64 sop_count_in; 2436 __le64 eop_count_in; 2437 __le64 sop_count_out; 2438 __le64 eop_count_out; 2439 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2440 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2441 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2442 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2443 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2444 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2445 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2446 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2447 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2448 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2449 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2450 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2451 }; 2452 2453 /** 2454 * struct ionic_port_identity - port identity structure 2455 * @version: identity structure version 2456 * @type: type of port (enum ionic_port_type) 2457 * @num_lanes: number of lanes for the port 2458 * @autoneg: autoneg supported 2459 * @min_frame_size: minimum frame size supported 2460 * @max_frame_size: maximum frame size supported 2461 * @fec_type: supported fec types 2462 * @pause_type: supported pause types 2463 * @loopback_mode: supported loopback mode 2464 * @speeds: supported speeds 2465 * @config: current port configuration 2466 */ 2467 union ionic_port_identity { 2468 struct { 2469 u8 version; 2470 u8 type; 2471 u8 num_lanes; 2472 u8 autoneg; 2473 __le32 min_frame_size; 2474 __le32 max_frame_size; 2475 u8 fec_type[4]; 2476 u8 pause_type[2]; 2477 u8 loopback_mode[2]; 2478 __le32 speeds[16]; 2479 u8 rsvd2[44]; 2480 union ionic_port_config config; 2481 }; 2482 __le32 words[478]; 2483 }; 2484 2485 /** 2486 * struct ionic_port_info - port info structure 2487 * @config: Port configuration data 2488 * @status: Port status data 2489 * @stats: Port statistics data 2490 * @mgmt_stats: Port management statistics data 2491 * @port_pb_drop_stats: uplink pb drop stats 2492 */ 2493 struct ionic_port_info { 2494 union ionic_port_config config; 2495 struct ionic_port_status status; 2496 union { 2497 struct ionic_port_stats stats; 2498 struct ionic_mgmt_port_stats mgmt_stats; 2499 }; 2500 /* room for pb_stats to start at 2k offset */ 2501 u8 rsvd[760]; 2502 struct ionic_port_pb_stats pb_stats; 2503 }; 2504 2505 /** 2506 * struct ionic_lif_stats - LIF statistics structure 2507 */ 2508 struct ionic_lif_stats { 2509 /* RX */ 2510 __le64 rx_ucast_bytes; 2511 __le64 rx_ucast_packets; 2512 __le64 rx_mcast_bytes; 2513 __le64 rx_mcast_packets; 2514 __le64 rx_bcast_bytes; 2515 __le64 rx_bcast_packets; 2516 __le64 rsvd0; 2517 __le64 rsvd1; 2518 /* RX drops */ 2519 __le64 rx_ucast_drop_bytes; 2520 __le64 rx_ucast_drop_packets; 2521 __le64 rx_mcast_drop_bytes; 2522 __le64 rx_mcast_drop_packets; 2523 __le64 rx_bcast_drop_bytes; 2524 __le64 rx_bcast_drop_packets; 2525 __le64 rx_dma_error; 2526 __le64 rsvd2; 2527 /* TX */ 2528 __le64 tx_ucast_bytes; 2529 __le64 tx_ucast_packets; 2530 __le64 tx_mcast_bytes; 2531 __le64 tx_mcast_packets; 2532 __le64 tx_bcast_bytes; 2533 __le64 tx_bcast_packets; 2534 __le64 rsvd3; 2535 __le64 rsvd4; 2536 /* TX drops */ 2537 __le64 tx_ucast_drop_bytes; 2538 __le64 tx_ucast_drop_packets; 2539 __le64 tx_mcast_drop_bytes; 2540 __le64 tx_mcast_drop_packets; 2541 __le64 tx_bcast_drop_bytes; 2542 __le64 tx_bcast_drop_packets; 2543 __le64 tx_dma_error; 2544 __le64 rsvd5; 2545 /* Rx Queue/Ring drops */ 2546 __le64 rx_queue_disabled; 2547 __le64 rx_queue_empty; 2548 __le64 rx_queue_error; 2549 __le64 rx_desc_fetch_error; 2550 __le64 rx_desc_data_error; 2551 __le64 rsvd6; 2552 __le64 rsvd7; 2553 __le64 rsvd8; 2554 /* Tx Queue/Ring drops */ 2555 __le64 tx_queue_disabled; 2556 __le64 tx_queue_error; 2557 __le64 tx_desc_fetch_error; 2558 __le64 tx_desc_data_error; 2559 __le64 tx_queue_empty; 2560 __le64 rsvd10; 2561 __le64 rsvd11; 2562 __le64 rsvd12; 2563 2564 /* RDMA/ROCE TX */ 2565 __le64 tx_rdma_ucast_bytes; 2566 __le64 tx_rdma_ucast_packets; 2567 __le64 tx_rdma_mcast_bytes; 2568 __le64 tx_rdma_mcast_packets; 2569 __le64 tx_rdma_cnp_packets; 2570 __le64 rsvd13; 2571 __le64 rsvd14; 2572 __le64 rsvd15; 2573 2574 /* RDMA/ROCE RX */ 2575 __le64 rx_rdma_ucast_bytes; 2576 __le64 rx_rdma_ucast_packets; 2577 __le64 rx_rdma_mcast_bytes; 2578 __le64 rx_rdma_mcast_packets; 2579 __le64 rx_rdma_cnp_packets; 2580 __le64 rx_rdma_ecn_packets; 2581 __le64 rsvd16; 2582 __le64 rsvd17; 2583 2584 __le64 rsvd18; 2585 __le64 rsvd19; 2586 __le64 rsvd20; 2587 __le64 rsvd21; 2588 __le64 rsvd22; 2589 __le64 rsvd23; 2590 __le64 rsvd24; 2591 __le64 rsvd25; 2592 2593 __le64 rsvd26; 2594 __le64 rsvd27; 2595 __le64 rsvd28; 2596 __le64 rsvd29; 2597 __le64 rsvd30; 2598 __le64 rsvd31; 2599 __le64 rsvd32; 2600 __le64 rsvd33; 2601 2602 __le64 rsvd34; 2603 __le64 rsvd35; 2604 __le64 rsvd36; 2605 __le64 rsvd37; 2606 __le64 rsvd38; 2607 __le64 rsvd39; 2608 __le64 rsvd40; 2609 __le64 rsvd41; 2610 2611 __le64 rsvd42; 2612 __le64 rsvd43; 2613 __le64 rsvd44; 2614 __le64 rsvd45; 2615 __le64 rsvd46; 2616 __le64 rsvd47; 2617 __le64 rsvd48; 2618 __le64 rsvd49; 2619 2620 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2621 __le64 rdma_req_rx_pkt_seq_err; 2622 __le64 rdma_req_rx_rnr_retry_err; 2623 __le64 rdma_req_rx_remote_access_err; 2624 __le64 rdma_req_rx_remote_inv_req_err; 2625 __le64 rdma_req_rx_remote_oper_err; 2626 __le64 rdma_req_rx_implied_nak_seq_err; 2627 __le64 rdma_req_rx_cqe_err; 2628 __le64 rdma_req_rx_cqe_flush_err; 2629 2630 __le64 rdma_req_rx_dup_responses; 2631 __le64 rdma_req_rx_invalid_packets; 2632 __le64 rdma_req_tx_local_access_err; 2633 __le64 rdma_req_tx_local_oper_err; 2634 __le64 rdma_req_tx_memory_mgmt_err; 2635 __le64 rsvd52; 2636 __le64 rsvd53; 2637 __le64 rsvd54; 2638 2639 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2640 __le64 rdma_resp_rx_dup_requests; 2641 __le64 rdma_resp_rx_out_of_buffer; 2642 __le64 rdma_resp_rx_out_of_seq_pkts; 2643 __le64 rdma_resp_rx_cqe_err; 2644 __le64 rdma_resp_rx_cqe_flush_err; 2645 __le64 rdma_resp_rx_local_len_err; 2646 __le64 rdma_resp_rx_inv_request_err; 2647 __le64 rdma_resp_rx_local_qp_oper_err; 2648 2649 __le64 rdma_resp_rx_out_of_atomic_resource; 2650 __le64 rdma_resp_tx_pkt_seq_err; 2651 __le64 rdma_resp_tx_remote_inv_req_err; 2652 __le64 rdma_resp_tx_remote_access_err; 2653 __le64 rdma_resp_tx_remote_oper_err; 2654 __le64 rdma_resp_tx_rnr_retry_err; 2655 __le64 rsvd57; 2656 __le64 rsvd58; 2657 }; 2658 2659 /** 2660 * struct ionic_lif_info - LIF info structure 2661 * @config: LIF configuration structure 2662 * @status: LIF status structure 2663 * @stats: LIF statistics structure 2664 */ 2665 struct ionic_lif_info { 2666 union ionic_lif_config config; 2667 struct ionic_lif_status status; 2668 struct ionic_lif_stats stats; 2669 }; 2670 2671 union ionic_dev_cmd { 2672 u32 words[16]; 2673 struct ionic_admin_cmd cmd; 2674 struct ionic_nop_cmd nop; 2675 2676 struct ionic_dev_identify_cmd identify; 2677 struct ionic_dev_init_cmd init; 2678 struct ionic_dev_reset_cmd reset; 2679 struct ionic_dev_getattr_cmd getattr; 2680 struct ionic_dev_setattr_cmd setattr; 2681 2682 struct ionic_port_identify_cmd port_identify; 2683 struct ionic_port_init_cmd port_init; 2684 struct ionic_port_reset_cmd port_reset; 2685 struct ionic_port_getattr_cmd port_getattr; 2686 struct ionic_port_setattr_cmd port_setattr; 2687 2688 struct ionic_vf_setattr_cmd vf_setattr; 2689 struct ionic_vf_getattr_cmd vf_getattr; 2690 2691 struct ionic_lif_identify_cmd lif_identify; 2692 struct ionic_lif_init_cmd lif_init; 2693 struct ionic_lif_reset_cmd lif_reset; 2694 2695 struct ionic_qos_identify_cmd qos_identify; 2696 struct ionic_qos_init_cmd qos_init; 2697 struct ionic_qos_reset_cmd qos_reset; 2698 struct ionic_qos_clear_stats_cmd qos_clear_stats; 2699 2700 struct ionic_q_identify_cmd q_identify; 2701 struct ionic_q_init_cmd q_init; 2702 struct ionic_q_control_cmd q_control; 2703 2704 struct ionic_fw_download_cmd fw_download; 2705 struct ionic_fw_control_cmd fw_control; 2706 }; 2707 2708 union ionic_dev_cmd_comp { 2709 u32 words[4]; 2710 u8 status; 2711 struct ionic_admin_comp comp; 2712 struct ionic_nop_comp nop; 2713 2714 struct ionic_dev_identify_comp identify; 2715 struct ionic_dev_init_comp init; 2716 struct ionic_dev_reset_comp reset; 2717 struct ionic_dev_getattr_comp getattr; 2718 struct ionic_dev_setattr_comp setattr; 2719 2720 struct ionic_port_identify_comp port_identify; 2721 struct ionic_port_init_comp port_init; 2722 struct ionic_port_reset_comp port_reset; 2723 struct ionic_port_getattr_comp port_getattr; 2724 struct ionic_port_setattr_comp port_setattr; 2725 2726 struct ionic_vf_setattr_comp vf_setattr; 2727 struct ionic_vf_getattr_comp vf_getattr; 2728 2729 struct ionic_lif_identify_comp lif_identify; 2730 struct ionic_lif_init_comp lif_init; 2731 ionic_lif_reset_comp lif_reset; 2732 2733 struct ionic_qos_identify_comp qos_identify; 2734 ionic_qos_init_comp qos_init; 2735 ionic_qos_reset_comp qos_reset; 2736 2737 struct ionic_q_identify_comp q_identify; 2738 struct ionic_q_init_comp q_init; 2739 2740 ionic_fw_download_comp fw_download; 2741 struct ionic_fw_control_comp fw_control; 2742 }; 2743 2744 /** 2745 * union ionic_dev_info_regs - Device info register format (read-only) 2746 * @signature: Signature value of 0x44455649 ('DEVI') 2747 * @version: Current version of info 2748 * @asic_type: Asic type 2749 * @asic_rev: Asic revision 2750 * @fw_status: Firmware status 2751 * @fw_heartbeat: Firmware heartbeat counter 2752 * @serial_num: Serial number 2753 * @fw_version: Firmware version 2754 */ 2755 union ionic_dev_info_regs { 2756 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2757 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2758 struct { 2759 u32 signature; 2760 u8 version; 2761 u8 asic_type; 2762 u8 asic_rev; 2763 #define IONIC_FW_STS_F_RUNNING 0x1 2764 u8 fw_status; 2765 u32 fw_heartbeat; 2766 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2767 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2768 }; 2769 u32 words[512]; 2770 }; 2771 2772 /** 2773 * union ionic_dev_cmd_regs - Device command register format (read-write) 2774 * @doorbell: Device Cmd Doorbell, write-only 2775 * Write a 1 to signal device to process cmd, 2776 * poll done for completion. 2777 * @done: Done indicator, bit 0 == 1 when command is complete 2778 * @cmd: Opcode-specific command bytes 2779 * @comp: Opcode-specific response bytes 2780 * @data: Opcode-specific side-data 2781 */ 2782 union ionic_dev_cmd_regs { 2783 struct { 2784 u32 doorbell; 2785 u32 done; 2786 union ionic_dev_cmd cmd; 2787 union ionic_dev_cmd_comp comp; 2788 u8 rsvd[48]; 2789 u32 data[478]; 2790 } __packed; 2791 u32 words[512]; 2792 }; 2793 2794 /** 2795 * union ionic_dev_regs - Device register format for bar 0 page 0 2796 * @info: Device info registers 2797 * @devcmd: Device command registers 2798 */ 2799 union ionic_dev_regs { 2800 struct { 2801 union ionic_dev_info_regs info; 2802 union ionic_dev_cmd_regs devcmd; 2803 } __packed; 2804 __le32 words[1024]; 2805 }; 2806 2807 union ionic_adminq_cmd { 2808 struct ionic_admin_cmd cmd; 2809 struct ionic_nop_cmd nop; 2810 struct ionic_q_identify_cmd q_identify; 2811 struct ionic_q_init_cmd q_init; 2812 struct ionic_q_control_cmd q_control; 2813 struct ionic_lif_setattr_cmd lif_setattr; 2814 struct ionic_lif_getattr_cmd lif_getattr; 2815 struct ionic_rx_mode_set_cmd rx_mode_set; 2816 struct ionic_rx_filter_add_cmd rx_filter_add; 2817 struct ionic_rx_filter_del_cmd rx_filter_del; 2818 struct ionic_rdma_reset_cmd rdma_reset; 2819 struct ionic_rdma_queue_cmd rdma_queue; 2820 struct ionic_fw_download_cmd fw_download; 2821 struct ionic_fw_control_cmd fw_control; 2822 }; 2823 2824 union ionic_adminq_comp { 2825 struct ionic_admin_comp comp; 2826 struct ionic_nop_comp nop; 2827 struct ionic_q_identify_comp q_identify; 2828 struct ionic_q_init_comp q_init; 2829 struct ionic_lif_setattr_comp lif_setattr; 2830 struct ionic_lif_getattr_comp lif_getattr; 2831 struct ionic_rx_filter_add_comp rx_filter_add; 2832 struct ionic_fw_control_comp fw_control; 2833 }; 2834 2835 #define IONIC_BARS_MAX 6 2836 #define IONIC_PCI_BAR_DBELL 1 2837 2838 /* BAR0 */ 2839 #define IONIC_BAR0_SIZE 0x8000 2840 2841 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2842 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2843 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2844 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2845 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2846 #define IONIC_DEV_CMD_DONE 0x00000001 2847 2848 #define IONIC_ASIC_TYPE_CAPRI 0 2849 2850 /** 2851 * struct ionic_doorbell - Doorbell register layout 2852 * @p_index: Producer index 2853 * @ring: Selects the specific ring of the queue to update 2854 * Type-specific meaning: 2855 * ring=0: Default producer/consumer queue 2856 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2857 * send events to EQs when armed. EQs send 2858 * interrupts when armed. 2859 * @qid_lo: Queue destination for the producer index and flags (low bits) 2860 * @qid_hi: Queue destination for the producer index and flags (high bits) 2861 */ 2862 struct ionic_doorbell { 2863 __le16 p_index; 2864 u8 ring; 2865 u8 qid_lo; 2866 __le16 qid_hi; 2867 u16 rsvd2; 2868 }; 2869 2870 struct ionic_intr_status { 2871 u32 status[2]; 2872 }; 2873 2874 struct ionic_notifyq_cmd { 2875 __le32 data; /* Not used but needed for qcq structure */ 2876 }; 2877 2878 union ionic_notifyq_comp { 2879 struct ionic_notifyq_event event; 2880 struct ionic_link_change_event link_change; 2881 struct ionic_reset_event reset; 2882 struct ionic_heartbeat_event heartbeat; 2883 struct ionic_log_event log; 2884 }; 2885 2886 /* Deprecate */ 2887 struct ionic_identity { 2888 union ionic_drv_identity drv; 2889 union ionic_dev_identity dev; 2890 union ionic_lif_identity lif; 2891 union ionic_port_identity port; 2892 union ionic_qos_identity qos; 2893 union ionic_q_identity txq; 2894 }; 2895 2896 #endif /* _IONIC_IF_H_ */ 2897