1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2019 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #pragma pack(push, 1) 8 9 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 10 #define IONIC_DEV_INFO_VERSION 1 11 #define IONIC_IFNAMSIZ 16 12 13 /** 14 * Commands 15 */ 16 enum ionic_cmd_opcode { 17 IONIC_CMD_NOP = 0, 18 19 /* Device commands */ 20 IONIC_CMD_IDENTIFY = 1, 21 IONIC_CMD_INIT = 2, 22 IONIC_CMD_RESET = 3, 23 IONIC_CMD_GETATTR = 4, 24 IONIC_CMD_SETATTR = 5, 25 26 /* Port commands */ 27 IONIC_CMD_PORT_IDENTIFY = 10, 28 IONIC_CMD_PORT_INIT = 11, 29 IONIC_CMD_PORT_RESET = 12, 30 IONIC_CMD_PORT_GETATTR = 13, 31 IONIC_CMD_PORT_SETATTR = 14, 32 33 /* LIF commands */ 34 IONIC_CMD_LIF_IDENTIFY = 20, 35 IONIC_CMD_LIF_INIT = 21, 36 IONIC_CMD_LIF_RESET = 22, 37 IONIC_CMD_LIF_GETATTR = 23, 38 IONIC_CMD_LIF_SETATTR = 24, 39 40 IONIC_CMD_RX_MODE_SET = 30, 41 IONIC_CMD_RX_FILTER_ADD = 31, 42 IONIC_CMD_RX_FILTER_DEL = 32, 43 44 /* Queue commands */ 45 IONIC_CMD_Q_INIT = 40, 46 IONIC_CMD_Q_CONTROL = 41, 47 48 /* RDMA commands */ 49 IONIC_CMD_RDMA_RESET_LIF = 50, 50 IONIC_CMD_RDMA_CREATE_EQ = 51, 51 IONIC_CMD_RDMA_CREATE_CQ = 52, 52 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53 54 /* QoS commands */ 55 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 56 IONIC_CMD_QOS_CLASS_INIT = 241, 57 IONIC_CMD_QOS_CLASS_RESET = 242, 58 59 /* Firmware commands */ 60 IONIC_CMD_FW_DOWNLOAD = 254, 61 IONIC_CMD_FW_CONTROL = 255, 62 }; 63 64 /** 65 * Command Return codes 66 */ 67 enum ionic_status_code { 68 IONIC_RC_SUCCESS = 0, /* Success */ 69 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 70 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 71 IONIC_RC_EIO = 3, /* I/O error */ 72 IONIC_RC_EPERM = 4, /* Permission denied */ 73 IONIC_RC_EQID = 5, /* Bad qid */ 74 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 75 IONIC_RC_ENOENT = 7, /* No such element */ 76 IONIC_RC_EINTR = 8, /* operation interrupted */ 77 IONIC_RC_EAGAIN = 9, /* Try again */ 78 IONIC_RC_ENOMEM = 10, /* Out of memory */ 79 IONIC_RC_EFAULT = 11, /* Bad address */ 80 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 81 IONIC_RC_EEXIST = 13, /* object already exists */ 82 IONIC_RC_EINVAL = 14, /* Invalid argument */ 83 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 84 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 85 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 86 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 87 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 88 IONIC_RC_ERROR = 29, /* Generic error */ 89 90 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 91 }; 92 93 enum ionic_notifyq_opcode { 94 IONIC_EVENT_LINK_CHANGE = 1, 95 IONIC_EVENT_RESET = 2, 96 IONIC_EVENT_HEARTBEAT = 3, 97 IONIC_EVENT_LOG = 4, 98 }; 99 100 /** 101 * struct cmd - General admin command format 102 * @opcode: Opcode for the command 103 * @lif_index: LIF index 104 * @cmd_data: Opcode-specific command bytes 105 */ 106 struct ionic_admin_cmd { 107 u8 opcode; 108 u8 rsvd; 109 __le16 lif_index; 110 u8 cmd_data[60]; 111 }; 112 113 /** 114 * struct ionic_admin_comp - General admin command completion format 115 * @status: The status of the command (enum status_code) 116 * @comp_index: The index in the descriptor ring for which this 117 * is the completion. 118 * @cmd_data: Command-specific bytes. 119 * @color: Color bit. (Always 0 for commands issued to the 120 * Device Cmd Registers.) 121 */ 122 struct ionic_admin_comp { 123 u8 status; 124 u8 rsvd; 125 __le16 comp_index; 126 u8 cmd_data[11]; 127 u8 color; 128 #define IONIC_COMP_COLOR_MASK 0x80 129 }; 130 131 static inline u8 color_match(u8 color, u8 done_color) 132 { 133 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 134 } 135 136 /** 137 * struct ionic_nop_cmd - NOP command 138 * @opcode: opcode 139 */ 140 struct ionic_nop_cmd { 141 u8 opcode; 142 u8 rsvd[63]; 143 }; 144 145 /** 146 * struct ionic_nop_comp - NOP command completion 147 * @status: The status of the command (enum status_code) 148 */ 149 struct ionic_nop_comp { 150 u8 status; 151 u8 rsvd[15]; 152 }; 153 154 /** 155 * struct ionic_dev_init_cmd - Device init command 156 * @opcode: opcode 157 * @type: device type 158 */ 159 struct ionic_dev_init_cmd { 160 u8 opcode; 161 u8 type; 162 u8 rsvd[62]; 163 }; 164 165 /** 166 * struct init_comp - Device init command completion 167 * @status: The status of the command (enum status_code) 168 */ 169 struct ionic_dev_init_comp { 170 u8 status; 171 u8 rsvd[15]; 172 }; 173 174 /** 175 * struct ionic_dev_reset_cmd - Device reset command 176 * @opcode: opcode 177 */ 178 struct ionic_dev_reset_cmd { 179 u8 opcode; 180 u8 rsvd[63]; 181 }; 182 183 /** 184 * struct reset_comp - Reset command completion 185 * @status: The status of the command (enum status_code) 186 */ 187 struct ionic_dev_reset_comp { 188 u8 status; 189 u8 rsvd[15]; 190 }; 191 192 #define IONIC_IDENTITY_VERSION_1 1 193 194 /** 195 * struct ionic_dev_identify_cmd - Driver/device identify command 196 * @opcode: opcode 197 * @ver: Highest version of identify supported by driver 198 */ 199 struct ionic_dev_identify_cmd { 200 u8 opcode; 201 u8 ver; 202 u8 rsvd[62]; 203 }; 204 205 /** 206 * struct dev_identify_comp - Driver/device identify command completion 207 * @status: The status of the command (enum status_code) 208 * @ver: Version of identify returned by device 209 */ 210 struct ionic_dev_identify_comp { 211 u8 status; 212 u8 ver; 213 u8 rsvd[14]; 214 }; 215 216 enum ionic_os_type { 217 IONIC_OS_TYPE_LINUX = 1, 218 IONIC_OS_TYPE_WIN = 2, 219 IONIC_OS_TYPE_DPDK = 3, 220 IONIC_OS_TYPE_FREEBSD = 4, 221 IONIC_OS_TYPE_IPXE = 5, 222 IONIC_OS_TYPE_ESXI = 6, 223 }; 224 225 /** 226 * union drv_identity - driver identity information 227 * @os_type: OS type (see enum os_type) 228 * @os_dist: OS distribution, numeric format 229 * @os_dist_str: OS distribution, string format 230 * @kernel_ver: Kernel version, numeric format 231 * @kernel_ver_str: Kernel version, string format 232 * @driver_ver_str: Driver version, string format 233 */ 234 union ionic_drv_identity { 235 struct { 236 __le32 os_type; 237 __le32 os_dist; 238 char os_dist_str[128]; 239 __le32 kernel_ver; 240 char kernel_ver_str[32]; 241 char driver_ver_str[32]; 242 }; 243 __le32 words[512]; 244 }; 245 246 /** 247 * union dev_identity - device identity information 248 * @version: Version of device identify 249 * @type: Identify type (0 for now) 250 * @nports: Number of ports provisioned 251 * @nlifs: Number of LIFs provisioned 252 * @nintrs: Number of interrupts provisioned 253 * @ndbpgs_per_lif: Number of doorbell pages per LIF 254 * @intr_coal_mult: Interrupt coalescing multiplication factor. 255 * Scale user-supplied interrupt coalescing 256 * value in usecs to device units using: 257 * device units = usecs * mult / div 258 * @intr_coal_div: Interrupt coalescing division factor. 259 * Scale user-supplied interrupt coalescing 260 * value in usecs to device units using: 261 * device units = usecs * mult / div 262 * 263 */ 264 union ionic_dev_identity { 265 struct { 266 u8 version; 267 u8 type; 268 u8 rsvd[2]; 269 u8 nports; 270 u8 rsvd2[3]; 271 __le32 nlifs; 272 __le32 nintrs; 273 __le32 ndbpgs_per_lif; 274 __le32 intr_coal_mult; 275 __le32 intr_coal_div; 276 }; 277 __le32 words[512]; 278 }; 279 280 enum ionic_lif_type { 281 IONIC_LIF_TYPE_CLASSIC = 0, 282 IONIC_LIF_TYPE_MACVLAN = 1, 283 IONIC_LIF_TYPE_NETQUEUE = 2, 284 }; 285 286 /** 287 * struct ionic_lif_identify_cmd - lif identify command 288 * @opcode: opcode 289 * @type: lif type (enum lif_type) 290 * @ver: version of identify returned by device 291 */ 292 struct ionic_lif_identify_cmd { 293 u8 opcode; 294 u8 type; 295 u8 ver; 296 u8 rsvd[61]; 297 }; 298 299 /** 300 * struct ionic_lif_identify_comp - lif identify command completion 301 * @status: status of the command (enum status_code) 302 * @ver: version of identify returned by device 303 */ 304 struct ionic_lif_identify_comp { 305 u8 status; 306 u8 ver; 307 u8 rsvd2[14]; 308 }; 309 310 enum ionic_lif_capability { 311 IONIC_LIF_CAP_ETH = BIT(0), 312 IONIC_LIF_CAP_RDMA = BIT(1), 313 }; 314 315 /** 316 * Logical Queue Types 317 */ 318 enum ionic_logical_qtype { 319 IONIC_QTYPE_ADMINQ = 0, 320 IONIC_QTYPE_NOTIFYQ = 1, 321 IONIC_QTYPE_RXQ = 2, 322 IONIC_QTYPE_TXQ = 3, 323 IONIC_QTYPE_EQ = 4, 324 IONIC_QTYPE_MAX = 16, 325 }; 326 327 /** 328 * struct ionic_lif_logical_qtype - Descriptor of logical to hardware queue type. 329 * @qtype: Hardware Queue Type. 330 * @qid_count: Number of Queue IDs of the logical type. 331 * @qid_base: Minimum Queue ID of the logical type. 332 */ 333 struct ionic_lif_logical_qtype { 334 u8 qtype; 335 u8 rsvd[3]; 336 __le32 qid_count; 337 __le32 qid_base; 338 }; 339 340 enum ionic_lif_state { 341 IONIC_LIF_DISABLE = 0, 342 IONIC_LIF_ENABLE = 1, 343 IONIC_LIF_HANG_RESET = 2, 344 }; 345 346 /** 347 * LIF configuration 348 * @state: lif state (enum lif_state) 349 * @name: lif name 350 * @mtu: mtu 351 * @mac: station mac address 352 * @features: features (enum ionic_eth_hw_features) 353 * @queue_count: queue counts per queue-type 354 */ 355 union ionic_lif_config { 356 struct { 357 u8 state; 358 u8 rsvd[3]; 359 char name[IONIC_IFNAMSIZ]; 360 __le32 mtu; 361 u8 mac[6]; 362 u8 rsvd2[2]; 363 __le64 features; 364 __le32 queue_count[IONIC_QTYPE_MAX]; 365 }; 366 __le32 words[64]; 367 }; 368 369 /** 370 * struct ionic_lif_identity - lif identity information (type-specific) 371 * 372 * @capabilities LIF capabilities 373 * 374 * Ethernet: 375 * @version: Ethernet identify structure version. 376 * @features: Ethernet features supported on this lif type. 377 * @max_ucast_filters: Number of perfect unicast addresses supported. 378 * @max_mcast_filters: Number of perfect multicast addresses supported. 379 * @min_frame_size: Minimum size of frames to be sent 380 * @max_frame_size: Maximim size of frames to be sent 381 * @config: LIF config struct with features, mtu, mac, q counts 382 * 383 * RDMA: 384 * @version: RDMA version of opcodes and queue descriptors. 385 * @qp_opcodes: Number of rdma queue pair opcodes supported. 386 * @admin_opcodes: Number of rdma admin opcodes supported. 387 * @npts_per_lif: Page table size per lif 388 * @nmrs_per_lif: Number of memory regions per lif 389 * @nahs_per_lif: Number of address handles per lif 390 * @max_stride: Max work request stride. 391 * @cl_stride: Cache line stride. 392 * @pte_stride: Page table entry stride. 393 * @rrq_stride: Remote RQ work request stride. 394 * @rsq_stride: Remote SQ work request stride. 395 * @dcqcn_profiles: Number of DCQCN profiles 396 * @aq_qtype: RDMA Admin Qtype. 397 * @sq_qtype: RDMA Send Qtype. 398 * @rq_qtype: RDMA Receive Qtype. 399 * @cq_qtype: RDMA Completion Qtype. 400 * @eq_qtype: RDMA Event Qtype. 401 */ 402 union ionic_lif_identity { 403 struct { 404 __le64 capabilities; 405 406 struct { 407 u8 version; 408 u8 rsvd[3]; 409 __le32 max_ucast_filters; 410 __le32 max_mcast_filters; 411 __le16 rss_ind_tbl_sz; 412 __le32 min_frame_size; 413 __le32 max_frame_size; 414 u8 rsvd2[106]; 415 union ionic_lif_config config; 416 } eth; 417 418 struct { 419 u8 version; 420 u8 qp_opcodes; 421 u8 admin_opcodes; 422 u8 rsvd; 423 __le32 npts_per_lif; 424 __le32 nmrs_per_lif; 425 __le32 nahs_per_lif; 426 u8 max_stride; 427 u8 cl_stride; 428 u8 pte_stride; 429 u8 rrq_stride; 430 u8 rsq_stride; 431 u8 dcqcn_profiles; 432 u8 rsvd_dimensions[10]; 433 struct ionic_lif_logical_qtype aq_qtype; 434 struct ionic_lif_logical_qtype sq_qtype; 435 struct ionic_lif_logical_qtype rq_qtype; 436 struct ionic_lif_logical_qtype cq_qtype; 437 struct ionic_lif_logical_qtype eq_qtype; 438 } rdma; 439 }; 440 __le32 words[512]; 441 }; 442 443 /** 444 * struct ionic_lif_init_cmd - LIF init command 445 * @opcode: opcode 446 * @type: LIF type (enum lif_type) 447 * @index: LIF index 448 * @info_pa: destination address for lif info (struct ionic_lif_info) 449 */ 450 struct ionic_lif_init_cmd { 451 u8 opcode; 452 u8 type; 453 __le16 index; 454 __le32 rsvd; 455 __le64 info_pa; 456 u8 rsvd2[48]; 457 }; 458 459 /** 460 * struct ionic_lif_init_comp - LIF init command completion 461 * @status: The status of the command (enum status_code) 462 */ 463 struct ionic_lif_init_comp { 464 u8 status; 465 u8 rsvd; 466 __le16 hw_index; 467 u8 rsvd2[12]; 468 }; 469 470 /** 471 * struct ionic_q_init_cmd - Queue init command 472 * @opcode: opcode 473 * @type: Logical queue type 474 * @ver: Queue version (defines opcode/descriptor scope) 475 * @lif_index: LIF index 476 * @index: (lif, qtype) relative admin queue index 477 * @intr_index: Interrupt control register index 478 * @pid: Process ID 479 * @flags: 480 * IRQ: Interrupt requested on completion 481 * ENA: Enable the queue. If ENA=0 the queue is initialized 482 * but remains disabled, to be later enabled with the 483 * Queue Enable command. If ENA=1, then queue is 484 * initialized and then enabled. 485 * SG: Enable Scatter-Gather on the queue. 486 * in number of descs. The actual ring size is 487 * (1 << ring_size). For example, to 488 * select a ring size of 64 descriptors write 489 * ring_size = 6. The minimum ring_size value is 2 490 * for a ring size of 4 descriptors. The maximum 491 * ring_size value is 16 for a ring size of 64k 492 * descriptors. Values of ring_size <2 and >16 are 493 * reserved. 494 * EQ: Enable the Event Queue 495 * @cos: Class of service for this queue. 496 * @ring_size: Queue ring size, encoded as a log2(size) 497 * @ring_base: Queue ring base address 498 * @cq_ring_base: Completion queue ring base address 499 * @sg_ring_base: Scatter/Gather ring base address 500 * @eq_index: Event queue index 501 */ 502 struct ionic_q_init_cmd { 503 u8 opcode; 504 u8 rsvd; 505 __le16 lif_index; 506 u8 type; 507 u8 ver; 508 u8 rsvd1[2]; 509 __le32 index; 510 __le16 pid; 511 __le16 intr_index; 512 __le16 flags; 513 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 514 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 515 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 516 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 517 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 518 u8 cos; 519 u8 ring_size; 520 __le64 ring_base; 521 __le64 cq_ring_base; 522 __le64 sg_ring_base; 523 __le32 eq_index; 524 u8 rsvd2[16]; 525 }; 526 527 /** 528 * struct ionic_q_init_comp - Queue init command completion 529 * @status: The status of the command (enum status_code) 530 * @ver: Queue version (defines opcode/descriptor scope) 531 * @comp_index: The index in the descriptor ring for which this 532 * is the completion. 533 * @hw_index: Hardware Queue ID 534 * @hw_type: Hardware Queue type 535 * @color: Color 536 */ 537 struct ionic_q_init_comp { 538 u8 status; 539 u8 ver; 540 __le16 comp_index; 541 __le32 hw_index; 542 u8 hw_type; 543 u8 rsvd2[6]; 544 u8 color; 545 }; 546 547 /* the device's internal addressing uses up to 52 bits */ 548 #define IONIC_ADDR_LEN 52 549 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 550 551 enum ionic_txq_desc_opcode { 552 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 553 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 554 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 555 IONIC_TXQ_DESC_OPCODE_TSO = 3, 556 }; 557 558 /** 559 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 560 * @opcode: Tx operation, see TXQ_DESC_OPCODE_*: 561 * 562 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 563 * 564 * Non-offload send. No segmentation, 565 * fragmentation or checksum calc/insertion is 566 * performed by device; packet is prepared 567 * to send by software stack and requires 568 * no further manipulation from device. 569 * 570 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 571 * 572 * Offload 16-bit L4 checksum 573 * calculation/insertion. The device will 574 * calculate the L4 checksum value and 575 * insert the result in the packet's L4 576 * header checksum field. The L4 checksum 577 * is calculated starting at @csum_start bytes 578 * into the packet to the end of the packet. 579 * The checksum insertion position is given 580 * in @csum_offset. This feature is only 581 * applicable to protocols such as TCP, UDP 582 * and ICMP where a standard (i.e. the 583 * 'IP-style' checksum) one's complement 584 * 16-bit checksum is used, using an IP 585 * pseudo-header to seed the calculation. 586 * Software will preload the L4 checksum 587 * field with the IP pseudo-header checksum. 588 * 589 * For tunnel encapsulation, @csum_start and 590 * @csum_offset refer to the inner L4 591 * header. Supported tunnels encapsulations 592 * are: IPIP, GRE, and UDP. If the @encap 593 * is clear, no further processing by the 594 * device is required; software will 595 * calculate the outer header checksums. If 596 * the @encap is set, the device will 597 * offload the outer header checksums using 598 * LCO (local checksum offload) (see 599 * Documentation/networking/checksum-offloads.rst 600 * for more info). 601 * 602 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 603 * 604 * Offload 16-bit checksum computation to hardware. 605 * If @csum_l3 is set then the packet's L3 checksum is 606 * updated. Similarly, if @csum_l4 is set the the L4 607 * checksum is updated. If @encap is set then encap header 608 * checksums are also updated. 609 * 610 * IONIC_TXQ_DESC_OPCODE_TSO: 611 * 612 * Device preforms TCP segmentation offload 613 * (TSO). @hdr_len is the number of bytes 614 * to the end of TCP header (the offset to 615 * the TCP payload). @mss is the desired 616 * MSS, the TCP payload length for each 617 * segment. The device will calculate/ 618 * insert IP (IPv4 only) and TCP checksums 619 * for each segment. In the first data 620 * buffer containing the header template, 621 * the driver will set IPv4 checksum to 0 622 * and preload TCP checksum with the IP 623 * pseudo header calculated with IP length = 0. 624 * 625 * Supported tunnel encapsulations are IPIP, 626 * layer-3 GRE, and UDP. @hdr_len includes 627 * both outer and inner headers. The driver 628 * will set IPv4 checksum to zero and 629 * preload TCP checksum with IP pseudo 630 * header on the inner header. 631 * 632 * TCP ECN offload is supported. The device 633 * will set CWR flag in the first segment if 634 * CWR is set in the template header, and 635 * clear CWR in remaining segments. 636 * @flags: 637 * vlan: 638 * Insert an L2 VLAN header using @vlan_tci. 639 * encap: 640 * Calculate encap header checksum. 641 * csum_l3: 642 * Compute L3 header checksum. 643 * csum_l4: 644 * Compute L4 header checksum. 645 * tso_sot: 646 * TSO start 647 * tso_eot: 648 * TSO end 649 * @num_sg_elems: Number of scatter-gather elements in SG 650 * descriptor 651 * @addr: First data buffer's DMA address. 652 * (Subsequent data buffers are on txq_sg_desc). 653 * @len: First data buffer's length, in bytes 654 * @vlan_tci: VLAN tag to insert in the packet (if requested 655 * by @V-bit). Includes .1p and .1q tags 656 * @hdr_len: Length of packet headers, including 657 * encapsulating outer header, if applicable. 658 * Valid for opcodes TXQ_DESC_OPCODE_CALC_CSUM and 659 * TXQ_DESC_OPCODE_TSO. Should be set to zero for 660 * all other modes. For 661 * TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 662 * of headers up to inner-most L4 header. For 663 * TXQ_DESC_OPCODE_TSO, @hdr_len is up to 664 * inner-most L4 payload, so inclusive of 665 * inner-most L4 header. 666 * @mss: Desired MSS value for TSO. Only applicable for 667 * TXQ_DESC_OPCODE_TSO. 668 * @csum_start: Offset into inner-most L3 header of checksum 669 * @csum_offset: Offset into inner-most L4 header of checksum 670 */ 671 672 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 673 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 674 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 675 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 676 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 677 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 678 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 679 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 680 681 /* common flags */ 682 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 683 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 684 685 /* flags for csum_hw opcode */ 686 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 687 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 688 689 /* flags for tso opcode */ 690 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 691 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 692 693 struct ionic_txq_desc { 694 __le64 cmd; 695 __le16 len; 696 union { 697 __le16 vlan_tci; 698 __le16 hword0; 699 }; 700 union { 701 __le16 csum_start; 702 __le16 hdr_len; 703 __le16 hword1; 704 }; 705 union { 706 __le16 csum_offset; 707 __le16 mss; 708 __le16 hword2; 709 }; 710 }; 711 712 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 713 u8 nsge, u64 addr) 714 { 715 u64 cmd; 716 717 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 718 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 719 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 720 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 721 722 return cmd; 723 }; 724 725 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 726 u8 *nsge, u64 *addr) 727 { 728 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 729 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 730 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 731 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 732 }; 733 734 #define IONIC_TX_MAX_SG_ELEMS 8 735 #define IONIC_RX_MAX_SG_ELEMS 8 736 737 /** 738 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 739 * @addr: DMA address of SG element data buffer 740 * @len: Length of SG element data buffer, in bytes 741 */ 742 struct ionic_txq_sg_desc { 743 struct ionic_txq_sg_elem { 744 __le64 addr; 745 __le16 len; 746 __le16 rsvd[3]; 747 } elems[IONIC_TX_MAX_SG_ELEMS]; 748 }; 749 750 /** 751 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 752 * @status: The status of the command (enum status_code) 753 * @comp_index: The index in the descriptor ring for which this 754 * is the completion. 755 * @color: Color bit. 756 */ 757 struct ionic_txq_comp { 758 u8 status; 759 u8 rsvd; 760 __le16 comp_index; 761 u8 rsvd2[11]; 762 u8 color; 763 }; 764 765 enum ionic_rxq_desc_opcode { 766 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 767 IONIC_RXQ_DESC_OPCODE_SG = 1, 768 }; 769 770 /** 771 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 772 * @opcode: Rx operation, see RXQ_DESC_OPCODE_*: 773 * 774 * RXQ_DESC_OPCODE_SIMPLE: 775 * 776 * Receive full packet into data buffer 777 * starting at @addr. Results of 778 * receive, including actual bytes received, 779 * are recorded in Rx completion descriptor. 780 * 781 * @len: Data buffer's length, in bytes. 782 * @addr: Data buffer's DMA address 783 */ 784 struct ionic_rxq_desc { 785 u8 opcode; 786 u8 rsvd[5]; 787 __le16 len; 788 __le64 addr; 789 }; 790 791 /** 792 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 793 * @addr: DMA address of SG element data buffer 794 * @len: Length of SG element data buffer, in bytes 795 */ 796 struct ionic_rxq_sg_desc { 797 struct ionic_rxq_sg_elem { 798 __le64 addr; 799 __le16 len; 800 __le16 rsvd[3]; 801 } elems[IONIC_RX_MAX_SG_ELEMS]; 802 }; 803 804 /** 805 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 806 * @status: The status of the command (enum status_code) 807 * @num_sg_elems: Number of SG elements used by this descriptor 808 * @comp_index: The index in the descriptor ring for which this 809 * is the completion. 810 * @rss_hash: 32-bit RSS hash 811 * @csum: 16-bit sum of the packet's L2 payload. 812 * If the packet's L2 payload is odd length, an extra 813 * zero-value byte is included in the @csum calculation but 814 * not included in @len. 815 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 816 * set. Includes .1p and .1q tags. 817 * @len: Received packet length, in bytes. Excludes FCS. 818 * @csum_calc L2 payload checksum is computed or not 819 * @csum_tcp_ok: The TCP checksum calculated by the device 820 * matched the checksum in the receive packet's 821 * TCP header 822 * @csum_tcp_bad: The TCP checksum calculated by the device did 823 * not match the checksum in the receive packet's 824 * TCP header. 825 * @csum_udp_ok: The UDP checksum calculated by the device 826 * matched the checksum in the receive packet's 827 * UDP header 828 * @csum_udp_bad: The UDP checksum calculated by the device did 829 * not match the checksum in the receive packet's 830 * UDP header. 831 * @csum_ip_ok: The IPv4 checksum calculated by the device 832 * matched the checksum in the receive packet's 833 * first IPv4 header. If the receive packet 834 * contains both a tunnel IPv4 header and a 835 * transport IPv4 header, the device validates the 836 * checksum for the both IPv4 headers. 837 * @csum_ip_bad: The IPv4 checksum calculated by the device did 838 * not match the checksum in the receive packet's 839 * first IPv4 header. If the receive packet 840 * contains both a tunnel IPv4 header and a 841 * transport IPv4 header, the device validates the 842 * checksum for both IP headers. 843 * @VLAN: VLAN header was stripped and placed in @vlan_tci. 844 * @pkt_type: Packet type 845 * @color: Color bit. 846 */ 847 struct ionic_rxq_comp { 848 u8 status; 849 u8 num_sg_elems; 850 __le16 comp_index; 851 __le32 rss_hash; 852 __le16 csum; 853 __le16 vlan_tci; 854 __le16 len; 855 u8 csum_flags; 856 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 857 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 858 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 859 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 860 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 861 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 862 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 863 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 864 u8 pkt_type_color; 865 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x0f 866 }; 867 868 enum ionic_pkt_type { 869 IONIC_PKT_TYPE_NON_IP = 0x000, 870 IONIC_PKT_TYPE_IPV4 = 0x001, 871 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 872 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 873 IONIC_PKT_TYPE_IPV6 = 0x008, 874 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 875 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 876 }; 877 878 enum ionic_eth_hw_features { 879 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 880 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 881 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 882 IONIC_ETH_HW_RX_HASH = BIT(3), 883 IONIC_ETH_HW_RX_CSUM = BIT(4), 884 IONIC_ETH_HW_TX_SG = BIT(5), 885 IONIC_ETH_HW_RX_SG = BIT(6), 886 IONIC_ETH_HW_TX_CSUM = BIT(7), 887 IONIC_ETH_HW_TSO = BIT(8), 888 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 889 IONIC_ETH_HW_TSO_ECN = BIT(10), 890 IONIC_ETH_HW_TSO_GRE = BIT(11), 891 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 892 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 893 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 894 IONIC_ETH_HW_TSO_UDP = BIT(15), 895 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 896 }; 897 898 /** 899 * struct ionic_q_control_cmd - Queue control command 900 * @opcode: opcode 901 * @type: Queue type 902 * @lif_index: LIF index 903 * @index: Queue index 904 * @oper: Operation (enum q_control_oper) 905 */ 906 struct ionic_q_control_cmd { 907 u8 opcode; 908 u8 type; 909 __le16 lif_index; 910 __le32 index; 911 u8 oper; 912 u8 rsvd[55]; 913 }; 914 915 typedef struct ionic_admin_comp ionic_q_control_comp; 916 917 enum q_control_oper { 918 IONIC_Q_DISABLE = 0, 919 IONIC_Q_ENABLE = 1, 920 IONIC_Q_HANG_RESET = 2, 921 }; 922 923 /** 924 * Physical connection type 925 */ 926 enum ionic_phy_type { 927 IONIC_PHY_TYPE_NONE = 0, 928 IONIC_PHY_TYPE_COPPER = 1, 929 IONIC_PHY_TYPE_FIBER = 2, 930 }; 931 932 /** 933 * Transceiver status 934 */ 935 enum ionic_xcvr_state { 936 IONIC_XCVR_STATE_REMOVED = 0, 937 IONIC_XCVR_STATE_INSERTED = 1, 938 IONIC_XCVR_STATE_PENDING = 2, 939 IONIC_XCVR_STATE_SPROM_READ = 3, 940 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 941 }; 942 943 /** 944 * Supported link modes 945 */ 946 enum ionic_xcvr_pid { 947 IONIC_XCVR_PID_UNKNOWN = 0, 948 949 /* CU */ 950 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 951 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 952 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 953 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 954 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 955 956 /* Fiber */ 957 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 958 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 959 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 960 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 961 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 962 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 963 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 964 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 965 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 966 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 967 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 968 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 969 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 970 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 971 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 972 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 973 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 974 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 975 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 976 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 977 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 978 }; 979 980 /** 981 * Port types 982 */ 983 enum ionic_port_type { 984 IONIC_PORT_TYPE_NONE = 0, /* port type not configured */ 985 IONIC_PORT_TYPE_ETH = 1, /* port carries ethernet traffic (inband) */ 986 IONIC_PORT_TYPE_MGMT = 2, /* port carries mgmt traffic (out-of-band) */ 987 }; 988 989 /** 990 * Port config state 991 */ 992 enum ionic_port_admin_state { 993 IONIC_PORT_ADMIN_STATE_NONE = 0, /* port admin state not configured */ 994 IONIC_PORT_ADMIN_STATE_DOWN = 1, /* port is admin disabled */ 995 IONIC_PORT_ADMIN_STATE_UP = 2, /* port is admin enabled */ 996 }; 997 998 /** 999 * Port operational status 1000 */ 1001 enum ionic_port_oper_status { 1002 IONIC_PORT_OPER_STATUS_NONE = 0, /* port is disabled */ 1003 IONIC_PORT_OPER_STATUS_UP = 1, /* port is linked up */ 1004 IONIC_PORT_OPER_STATUS_DOWN = 2, /* port link status is down */ 1005 }; 1006 1007 /** 1008 * Ethernet Forward error correction (fec) modes 1009 */ 1010 enum ionic_port_fec_type { 1011 IONIC_PORT_FEC_TYPE_NONE = 0, /* Disabled */ 1012 IONIC_PORT_FEC_TYPE_FC = 1, /* FireCode */ 1013 IONIC_PORT_FEC_TYPE_RS = 2, /* ReedSolomon */ 1014 }; 1015 1016 /** 1017 * Ethernet pause (flow control) modes 1018 */ 1019 enum ionic_port_pause_type { 1020 IONIC_PORT_PAUSE_TYPE_NONE = 0, /* Disable Pause */ 1021 IONIC_PORT_PAUSE_TYPE_LINK = 1, /* Link level pause */ 1022 IONIC_PORT_PAUSE_TYPE_PFC = 2, /* Priority-Flow control */ 1023 }; 1024 1025 /** 1026 * Loopback modes 1027 */ 1028 enum ionic_port_loopback_mode { 1029 IONIC_PORT_LOOPBACK_MODE_NONE = 0, /* Disable loopback */ 1030 IONIC_PORT_LOOPBACK_MODE_MAC = 1, /* MAC loopback */ 1031 IONIC_PORT_LOOPBACK_MODE_PHY = 2, /* PHY/Serdes loopback */ 1032 }; 1033 1034 /** 1035 * Transceiver Status information 1036 * @state: Transceiver status (enum ionic_xcvr_state) 1037 * @phy: Physical connection type (enum ionic_phy_type) 1038 * @pid: Transceiver link mode (enum pid) 1039 * @sprom: Transceiver sprom contents 1040 */ 1041 struct ionic_xcvr_status { 1042 u8 state; 1043 u8 phy; 1044 __le16 pid; 1045 u8 sprom[256]; 1046 }; 1047 1048 /** 1049 * Port configuration 1050 * @speed: port speed (in Mbps) 1051 * @mtu: mtu 1052 * @state: port admin state (enum port_admin_state) 1053 * @an_enable: autoneg enable 1054 * @fec_type: fec type (enum ionic_port_fec_type) 1055 * @pause_type: pause type (enum ionic_port_pause_type) 1056 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1057 */ 1058 union ionic_port_config { 1059 struct { 1060 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1061 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1062 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1063 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1064 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1065 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1066 __le32 speed; 1067 __le32 mtu; 1068 u8 state; 1069 u8 an_enable; 1070 u8 fec_type; 1071 #define IONIC_PAUSE_TYPE_MASK 0x0f 1072 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1073 #define IONIC_PAUSE_F_TX 0x10 1074 #define IONIC_PAUSE_F_RX 0x20 1075 u8 pause_type; 1076 u8 loopback_mode; 1077 }; 1078 __le32 words[64]; 1079 }; 1080 1081 /** 1082 * Port Status information 1083 * @status: link status (enum ionic_port_oper_status) 1084 * @id: port id 1085 * @speed: link speed (in Mbps) 1086 * @xcvr: tranceiver status 1087 */ 1088 struct ionic_port_status { 1089 __le32 id; 1090 __le32 speed; 1091 u8 status; 1092 u8 rsvd[51]; 1093 struct ionic_xcvr_status xcvr; 1094 }; 1095 1096 /** 1097 * struct ionic_port_identify_cmd - Port identify command 1098 * @opcode: opcode 1099 * @index: port index 1100 * @ver: Highest version of identify supported by driver 1101 */ 1102 struct ionic_port_identify_cmd { 1103 u8 opcode; 1104 u8 index; 1105 u8 ver; 1106 u8 rsvd[61]; 1107 }; 1108 1109 /** 1110 * struct ionic_port_identify_comp - Port identify command completion 1111 * @status: The status of the command (enum status_code) 1112 * @ver: Version of identify returned by device 1113 */ 1114 struct ionic_port_identify_comp { 1115 u8 status; 1116 u8 ver; 1117 u8 rsvd[14]; 1118 }; 1119 1120 /** 1121 * struct ionic_port_init_cmd - Port initialization command 1122 * @opcode: opcode 1123 * @index: port index 1124 * @info_pa: destination address for port info (struct ionic_port_info) 1125 */ 1126 struct ionic_port_init_cmd { 1127 u8 opcode; 1128 u8 index; 1129 u8 rsvd[6]; 1130 __le64 info_pa; 1131 u8 rsvd2[48]; 1132 }; 1133 1134 /** 1135 * struct ionic_port_init_comp - Port initialization command completion 1136 * @status: The status of the command (enum status_code) 1137 */ 1138 struct ionic_port_init_comp { 1139 u8 status; 1140 u8 rsvd[15]; 1141 }; 1142 1143 /** 1144 * struct ionic_port_reset_cmd - Port reset command 1145 * @opcode: opcode 1146 * @index: port index 1147 */ 1148 struct ionic_port_reset_cmd { 1149 u8 opcode; 1150 u8 index; 1151 u8 rsvd[62]; 1152 }; 1153 1154 /** 1155 * struct ionic_port_reset_comp - Port reset command completion 1156 * @status: The status of the command (enum status_code) 1157 */ 1158 struct ionic_port_reset_comp { 1159 u8 status; 1160 u8 rsvd[15]; 1161 }; 1162 1163 /** 1164 * enum stats_ctl_cmd - List of commands for stats control 1165 */ 1166 enum ionic_stats_ctl_cmd { 1167 IONIC_STATS_CTL_RESET = 0, 1168 }; 1169 1170 1171 /** 1172 * enum ionic_port_attr - List of device attributes 1173 */ 1174 enum ionic_port_attr { 1175 IONIC_PORT_ATTR_STATE = 0, 1176 IONIC_PORT_ATTR_SPEED = 1, 1177 IONIC_PORT_ATTR_MTU = 2, 1178 IONIC_PORT_ATTR_AUTONEG = 3, 1179 IONIC_PORT_ATTR_FEC = 4, 1180 IONIC_PORT_ATTR_PAUSE = 5, 1181 IONIC_PORT_ATTR_LOOPBACK = 6, 1182 IONIC_PORT_ATTR_STATS_CTRL = 7, 1183 }; 1184 1185 /** 1186 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1187 * @opcode: Opcode 1188 * @index: port index 1189 * @attr: Attribute type (enum ionic_port_attr) 1190 */ 1191 struct ionic_port_setattr_cmd { 1192 u8 opcode; 1193 u8 index; 1194 u8 attr; 1195 u8 rsvd; 1196 union { 1197 u8 state; 1198 __le32 speed; 1199 __le32 mtu; 1200 u8 an_enable; 1201 u8 fec_type; 1202 u8 pause_type; 1203 u8 loopback_mode; 1204 u8 stats_ctl; 1205 u8 rsvd2[60]; 1206 }; 1207 }; 1208 1209 /** 1210 * struct ionic_port_setattr_comp - Port set attr command completion 1211 * @status: The status of the command (enum status_code) 1212 * @color: Color bit 1213 */ 1214 struct ionic_port_setattr_comp { 1215 u8 status; 1216 u8 rsvd[14]; 1217 u8 color; 1218 }; 1219 1220 /** 1221 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1222 * @opcode: Opcode 1223 * @index: port index 1224 * @attr: Attribute type (enum ionic_port_attr) 1225 */ 1226 struct ionic_port_getattr_cmd { 1227 u8 opcode; 1228 u8 index; 1229 u8 attr; 1230 u8 rsvd[61]; 1231 }; 1232 1233 /** 1234 * struct ionic_port_getattr_comp - Port get attr command completion 1235 * @status: The status of the command (enum status_code) 1236 * @color: Color bit 1237 */ 1238 struct ionic_port_getattr_comp { 1239 u8 status; 1240 u8 rsvd[3]; 1241 union { 1242 u8 state; 1243 __le32 speed; 1244 __le32 mtu; 1245 u8 an_enable; 1246 u8 fec_type; 1247 u8 pause_type; 1248 u8 loopback_mode; 1249 u8 rsvd2[11]; 1250 }; 1251 u8 color; 1252 }; 1253 1254 /** 1255 * struct ionic_lif_status - Lif status register 1256 * @eid: most recent NotifyQ event id 1257 * @port_num: port the lif is connected to 1258 * @link_status: port status (enum ionic_port_oper_status) 1259 * @link_speed: speed of link in Mbps 1260 * @link_down_count: number of times link status changes 1261 */ 1262 struct ionic_lif_status { 1263 __le64 eid; 1264 u8 port_num; 1265 u8 rsvd; 1266 __le16 link_status; 1267 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1268 __le16 link_down_count; 1269 u8 rsvd2[46]; 1270 }; 1271 1272 /** 1273 * struct ionic_lif_reset_cmd - LIF reset command 1274 * @opcode: opcode 1275 * @index: LIF index 1276 */ 1277 struct ionic_lif_reset_cmd { 1278 u8 opcode; 1279 u8 rsvd; 1280 __le16 index; 1281 __le32 rsvd2[15]; 1282 }; 1283 1284 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1285 1286 enum ionic_dev_state { 1287 IONIC_DEV_DISABLE = 0, 1288 IONIC_DEV_ENABLE = 1, 1289 IONIC_DEV_HANG_RESET = 2, 1290 }; 1291 1292 /** 1293 * enum ionic_dev_attr - List of device attributes 1294 */ 1295 enum ionic_dev_attr { 1296 IONIC_DEV_ATTR_STATE = 0, 1297 IONIC_DEV_ATTR_NAME = 1, 1298 IONIC_DEV_ATTR_FEATURES = 2, 1299 }; 1300 1301 /** 1302 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1303 * @opcode: Opcode 1304 * @attr: Attribute type (enum ionic_dev_attr) 1305 * @state: Device state (enum ionic_dev_state) 1306 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1307 * @features: Device features 1308 */ 1309 struct ionic_dev_setattr_cmd { 1310 u8 opcode; 1311 u8 attr; 1312 __le16 rsvd; 1313 union { 1314 u8 state; 1315 char name[IONIC_IFNAMSIZ]; 1316 __le64 features; 1317 u8 rsvd2[60]; 1318 }; 1319 }; 1320 1321 /** 1322 * struct ionic_dev_setattr_comp - Device set attr command completion 1323 * @status: The status of the command (enum status_code) 1324 * @features: Device features 1325 * @color: Color bit 1326 */ 1327 struct ionic_dev_setattr_comp { 1328 u8 status; 1329 u8 rsvd[3]; 1330 union { 1331 __le64 features; 1332 u8 rsvd2[11]; 1333 }; 1334 u8 color; 1335 }; 1336 1337 /** 1338 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1339 * @opcode: opcode 1340 * @attr: Attribute type (enum ionic_dev_attr) 1341 */ 1342 struct ionic_dev_getattr_cmd { 1343 u8 opcode; 1344 u8 attr; 1345 u8 rsvd[62]; 1346 }; 1347 1348 /** 1349 * struct ionic_dev_setattr_comp - Device set attr command completion 1350 * @status: The status of the command (enum status_code) 1351 * @features: Device features 1352 * @color: Color bit 1353 */ 1354 struct ionic_dev_getattr_comp { 1355 u8 status; 1356 u8 rsvd[3]; 1357 union { 1358 __le64 features; 1359 u8 rsvd2[11]; 1360 }; 1361 u8 color; 1362 }; 1363 1364 /** 1365 * RSS parameters 1366 */ 1367 #define IONIC_RSS_HASH_KEY_SIZE 40 1368 1369 enum ionic_rss_hash_types { 1370 IONIC_RSS_TYPE_IPV4 = BIT(0), 1371 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1372 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1373 IONIC_RSS_TYPE_IPV6 = BIT(3), 1374 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1375 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1376 }; 1377 1378 /** 1379 * enum ionic_lif_attr - List of LIF attributes 1380 */ 1381 enum ionic_lif_attr { 1382 IONIC_LIF_ATTR_STATE = 0, 1383 IONIC_LIF_ATTR_NAME = 1, 1384 IONIC_LIF_ATTR_MTU = 2, 1385 IONIC_LIF_ATTR_MAC = 3, 1386 IONIC_LIF_ATTR_FEATURES = 4, 1387 IONIC_LIF_ATTR_RSS = 5, 1388 IONIC_LIF_ATTR_STATS_CTRL = 6, 1389 }; 1390 1391 /** 1392 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1393 * @opcode: Opcode 1394 * @type: Attribute type (enum ionic_lif_attr) 1395 * @index: LIF index 1396 * @state: lif state (enum lif_state) 1397 * @name: The netdev name string, 0 terminated 1398 * @mtu: Mtu 1399 * @mac: Station mac 1400 * @features: Features (enum ionic_eth_hw_features) 1401 * @rss: RSS properties 1402 * @types: The hash types to enable (see rss_hash_types). 1403 * @key: The hash secret key. 1404 * @addr: Address for the indirection table shared memory. 1405 * @stats_ctl: stats control commands (enum stats_ctl_cmd) 1406 */ 1407 struct ionic_lif_setattr_cmd { 1408 u8 opcode; 1409 u8 attr; 1410 __le16 index; 1411 union { 1412 u8 state; 1413 char name[IONIC_IFNAMSIZ]; 1414 __le32 mtu; 1415 u8 mac[6]; 1416 __le64 features; 1417 struct { 1418 __le16 types; 1419 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1420 u8 rsvd[6]; 1421 __le64 addr; 1422 } rss; 1423 u8 stats_ctl; 1424 u8 rsvd[60]; 1425 }; 1426 }; 1427 1428 /** 1429 * struct ionic_lif_setattr_comp - LIF set attr command completion 1430 * @status: The status of the command (enum status_code) 1431 * @comp_index: The index in the descriptor ring for which this 1432 * is the completion. 1433 * @features: features (enum ionic_eth_hw_features) 1434 * @color: Color bit 1435 */ 1436 struct ionic_lif_setattr_comp { 1437 u8 status; 1438 u8 rsvd; 1439 __le16 comp_index; 1440 union { 1441 __le64 features; 1442 u8 rsvd2[11]; 1443 }; 1444 u8 color; 1445 }; 1446 1447 /** 1448 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1449 * @opcode: Opcode 1450 * @attr: Attribute type (enum ionic_lif_attr) 1451 * @index: LIF index 1452 */ 1453 struct ionic_lif_getattr_cmd { 1454 u8 opcode; 1455 u8 attr; 1456 __le16 index; 1457 u8 rsvd[60]; 1458 }; 1459 1460 /** 1461 * struct ionic_lif_getattr_comp - LIF get attr command completion 1462 * @status: The status of the command (enum status_code) 1463 * @comp_index: The index in the descriptor ring for which this 1464 * is the completion. 1465 * @state: lif state (enum lif_state) 1466 * @name: The netdev name string, 0 terminated 1467 * @mtu: Mtu 1468 * @mac: Station mac 1469 * @features: Features (enum ionic_eth_hw_features) 1470 * @color: Color bit 1471 */ 1472 struct ionic_lif_getattr_comp { 1473 u8 status; 1474 u8 rsvd; 1475 __le16 comp_index; 1476 union { 1477 u8 state; 1478 __le32 mtu; 1479 u8 mac[6]; 1480 __le64 features; 1481 u8 rsvd2[11]; 1482 }; 1483 u8 color; 1484 }; 1485 1486 enum ionic_rx_mode { 1487 IONIC_RX_MODE_F_UNICAST = BIT(0), 1488 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1489 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1490 IONIC_RX_MODE_F_PROMISC = BIT(3), 1491 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1492 }; 1493 1494 /** 1495 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1496 * @opcode: opcode 1497 * @lif_index: LIF index 1498 * @rx_mode: Rx mode flags: 1499 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets. 1500 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets. 1501 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets. 1502 * IONIC_RX_MODE_F_PROMISC: Accept any packets. 1503 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets. 1504 */ 1505 struct ionic_rx_mode_set_cmd { 1506 u8 opcode; 1507 u8 rsvd; 1508 __le16 lif_index; 1509 __le16 rx_mode; 1510 __le16 rsvd2[29]; 1511 }; 1512 1513 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1514 1515 enum ionic_rx_filter_match_type { 1516 IONIC_RX_FILTER_MATCH_VLAN = 0, 1517 IONIC_RX_FILTER_MATCH_MAC, 1518 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1519 }; 1520 1521 /** 1522 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1523 * @opcode: opcode 1524 * @qtype: Queue type 1525 * @lif_index: LIF index 1526 * @qid: Queue ID 1527 * @match: Rx filter match type. (See IONIC_RX_FILTER_MATCH_xxx) 1528 * @vlan: VLAN ID 1529 * @addr: MAC address (network-byte order) 1530 */ 1531 struct ionic_rx_filter_add_cmd { 1532 u8 opcode; 1533 u8 qtype; 1534 __le16 lif_index; 1535 __le32 qid; 1536 __le16 match; 1537 union { 1538 struct { 1539 __le16 vlan; 1540 } vlan; 1541 struct { 1542 u8 addr[6]; 1543 } mac; 1544 struct { 1545 __le16 vlan; 1546 u8 addr[6]; 1547 } mac_vlan; 1548 u8 rsvd[54]; 1549 }; 1550 }; 1551 1552 /** 1553 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1554 * @status: The status of the command (enum status_code) 1555 * @comp_index: The index in the descriptor ring for which this 1556 * is the completion. 1557 * @filter_id: Filter ID 1558 * @color: Color bit. 1559 */ 1560 struct ionic_rx_filter_add_comp { 1561 u8 status; 1562 u8 rsvd; 1563 __le16 comp_index; 1564 __le32 filter_id; 1565 u8 rsvd2[7]; 1566 u8 color; 1567 }; 1568 1569 /** 1570 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1571 * @opcode: opcode 1572 * @lif_index: LIF index 1573 * @filter_id: Filter ID 1574 */ 1575 struct ionic_rx_filter_del_cmd { 1576 u8 opcode; 1577 u8 rsvd; 1578 __le16 lif_index; 1579 __le32 filter_id; 1580 u8 rsvd2[56]; 1581 }; 1582 1583 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1584 1585 /** 1586 * struct ionic_qos_identify_cmd - QoS identify command 1587 * @opcode: opcode 1588 * @ver: Highest version of identify supported by driver 1589 * 1590 */ 1591 struct ionic_qos_identify_cmd { 1592 u8 opcode; 1593 u8 ver; 1594 u8 rsvd[62]; 1595 }; 1596 1597 /** 1598 * struct ionic_qos_identify_comp - QoS identify command completion 1599 * @status: The status of the command (enum status_code) 1600 * @ver: Version of identify returned by device 1601 */ 1602 struct ionic_qos_identify_comp { 1603 u8 status; 1604 u8 ver; 1605 u8 rsvd[14]; 1606 }; 1607 1608 #define IONIC_QOS_CLASS_MAX 7 1609 #define IONIC_QOS_CLASS_NAME_SZ 32 1610 #define IONIC_QOS_DSCP_MAX_VALUES 64 1611 1612 /** 1613 * enum ionic_qos_class 1614 */ 1615 enum ionic_qos_class { 1616 IONIC_QOS_CLASS_DEFAULT = 0, 1617 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1618 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1619 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1620 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1621 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1622 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1623 }; 1624 1625 /** 1626 * enum ionic_qos_class_type - Traffic classification criteria 1627 */ 1628 enum ionic_qos_class_type { 1629 IONIC_QOS_CLASS_TYPE_NONE = 0, 1630 IONIC_QOS_CLASS_TYPE_PCP = 1, /* Dot1Q pcp */ 1631 IONIC_QOS_CLASS_TYPE_DSCP = 2, /* IP dscp */ 1632 }; 1633 1634 /** 1635 * enum ionic_qos_sched_type - Qos class scheduling type 1636 */ 1637 enum ionic_qos_sched_type { 1638 IONIC_QOS_SCHED_TYPE_STRICT = 0, /* Strict priority */ 1639 IONIC_QOS_SCHED_TYPE_DWRR = 1, /* Deficit weighted round-robin */ 1640 }; 1641 1642 /** 1643 * union ionic_qos_config - Qos configuration structure 1644 * @flags: Configuration flags 1645 * IONIC_QOS_CONFIG_F_ENABLE enable 1646 * IONIC_QOS_CONFIG_F_DROP drop/nodrop 1647 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1648 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1649 * @sched_type: Qos class scheduling type (enum ionic_qos_sched_type) 1650 * @class_type: Qos class type (enum ionic_qos_class_type) 1651 * @pause_type: Qos pause type (enum ionic_qos_pause_type) 1652 * @name: Qos class name 1653 * @mtu: MTU of the class 1654 * @pfc_dot1q_pcp: Pcp value for pause frames (valid iff F_NODROP) 1655 * @dwrr_weight: Qos class scheduling weight 1656 * @strict_rlmt: Rate limit for strict priority scheduling 1657 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) 1658 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) 1659 * @dot1q_pcp: Dot1q pcp value 1660 * @ndscp: Number of valid dscp values in the ip_dscp field 1661 * @ip_dscp: IP dscp values 1662 */ 1663 union ionic_qos_config { 1664 struct { 1665 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1666 #define IONIC_QOS_CONFIG_F_DROP BIT(1) 1667 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1668 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1669 u8 flags; 1670 u8 sched_type; 1671 u8 class_type; 1672 u8 pause_type; 1673 char name[IONIC_QOS_CLASS_NAME_SZ]; 1674 __le32 mtu; 1675 /* flow control */ 1676 u8 pfc_cos; 1677 /* scheduler */ 1678 union { 1679 u8 dwrr_weight; 1680 __le64 strict_rlmt; 1681 }; 1682 /* marking */ 1683 union { 1684 u8 rw_dot1q_pcp; 1685 u8 rw_ip_dscp; 1686 }; 1687 /* classification */ 1688 union { 1689 u8 dot1q_pcp; 1690 struct { 1691 u8 ndscp; 1692 u8 ip_dscp[IONIC_QOS_DSCP_MAX_VALUES]; 1693 }; 1694 }; 1695 }; 1696 __le32 words[64]; 1697 }; 1698 1699 /** 1700 * union ionic_qos_identity - QoS identity structure 1701 * @version: Version of the identify structure 1702 * @type: QoS system type 1703 * @nclasses: Number of usable QoS classes 1704 * @config: Current configuration of classes 1705 */ 1706 union ionic_qos_identity { 1707 struct { 1708 u8 version; 1709 u8 type; 1710 u8 rsvd[62]; 1711 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 1712 }; 1713 __le32 words[512]; 1714 }; 1715 1716 /** 1717 * struct qos_init_cmd - QoS config init command 1718 * @opcode: Opcode 1719 * @group: Qos class id 1720 * @info_pa: destination address for qos info 1721 */ 1722 struct ionic_qos_init_cmd { 1723 u8 opcode; 1724 u8 group; 1725 u8 rsvd[6]; 1726 __le64 info_pa; 1727 u8 rsvd1[48]; 1728 }; 1729 1730 typedef struct ionic_admin_comp ionic_qos_init_comp; 1731 1732 /** 1733 * struct ionic_qos_reset_cmd - Qos config reset command 1734 * @opcode: Opcode 1735 */ 1736 struct ionic_qos_reset_cmd { 1737 u8 opcode; 1738 u8 group; 1739 u8 rsvd[62]; 1740 }; 1741 1742 typedef struct ionic_admin_comp ionic_qos_reset_comp; 1743 1744 /** 1745 * struct ionic_fw_download_cmd - Firmware download command 1746 * @opcode: opcode 1747 * @addr: dma address of the firmware buffer 1748 * @offset: offset of the firmware buffer within the full image 1749 * @length: number of valid bytes in the firmware buffer 1750 */ 1751 struct ionic_fw_download_cmd { 1752 u8 opcode; 1753 u8 rsvd[3]; 1754 __le32 offset; 1755 __le64 addr; 1756 __le32 length; 1757 }; 1758 1759 typedef struct ionic_admin_comp ionic_fw_download_comp; 1760 1761 enum ionic_fw_control_oper { 1762 IONIC_FW_RESET = 0, /* Reset firmware */ 1763 IONIC_FW_INSTALL = 1, /* Install firmware */ 1764 IONIC_FW_ACTIVATE = 2, /* Activate firmware */ 1765 }; 1766 1767 /** 1768 * struct ionic_fw_control_cmd - Firmware control command 1769 * @opcode: opcode 1770 * @oper: firmware control operation (enum ionic_fw_control_oper) 1771 * @slot: slot to activate 1772 */ 1773 struct ionic_fw_control_cmd { 1774 u8 opcode; 1775 u8 rsvd[3]; 1776 u8 oper; 1777 u8 slot; 1778 u8 rsvd1[58]; 1779 }; 1780 1781 /** 1782 * struct ionic_fw_control_comp - Firmware control copletion 1783 * @opcode: opcode 1784 * @slot: slot where the firmware was installed 1785 */ 1786 struct ionic_fw_control_comp { 1787 u8 status; 1788 u8 rsvd; 1789 __le16 comp_index; 1790 u8 slot; 1791 u8 rsvd1[10]; 1792 u8 color; 1793 }; 1794 1795 /****************************************************************** 1796 ******************* RDMA Commands ******************************** 1797 ******************************************************************/ 1798 1799 /** 1800 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 1801 * @opcode: opcode 1802 * @lif_index: lif index 1803 * 1804 * There is no rdma specific dev command completion struct. Completion uses 1805 * the common struct ionic_admin_comp. Only the status is indicated. 1806 * Nonzero status means the LIF does not support rdma. 1807 **/ 1808 struct ionic_rdma_reset_cmd { 1809 u8 opcode; 1810 u8 rsvd; 1811 __le16 lif_index; 1812 u8 rsvd2[60]; 1813 }; 1814 1815 /** 1816 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 1817 * @opcode: opcode, 52, 53 1818 * @lif_index lif index 1819 * @qid_ver: (qid | (rdma version << 24)) 1820 * @cid: intr, eq_id, or cq_id 1821 * @dbid: doorbell page id 1822 * @depth_log2: log base two of queue depth 1823 * @stride_log2: log base two of queue stride 1824 * @dma_addr: address of the queue memory 1825 * @xxx_table_index: temporary, but should not need pgtbl for contig. queues. 1826 * 1827 * The same command struct is used to create an rdma event queue, completion 1828 * queue, or rdma admin queue. The cid is an interrupt number for an event 1829 * queue, an event queue id for a completion queue, or a completion queue id 1830 * for an rdma admin queue. 1831 * 1832 * The queue created via a dev command must be contiguous in dma space. 1833 * 1834 * The dev commands are intended only to be used during driver initialization, 1835 * to create queues supporting the rdma admin queue. Other queues, and other 1836 * types of rdma resources like memory regions, will be created and registered 1837 * via the rdma admin queue, and will support a more complete interface 1838 * providing scatter gather lists for larger, scattered queue buffers and 1839 * memory registration. 1840 * 1841 * There is no rdma specific dev command completion struct. Completion uses 1842 * the common struct ionic_admin_comp. Only the status is indicated. 1843 **/ 1844 struct ionic_rdma_queue_cmd { 1845 u8 opcode; 1846 u8 rsvd; 1847 __le16 lif_index; 1848 __le32 qid_ver; 1849 __le32 cid; 1850 __le16 dbid; 1851 u8 depth_log2; 1852 u8 stride_log2; 1853 __le64 dma_addr; 1854 u8 rsvd2[36]; 1855 __le32 xxx_table_index; 1856 }; 1857 1858 /****************************************************************** 1859 ******************* Notify Events ******************************** 1860 ******************************************************************/ 1861 1862 /** 1863 * struct ionic_notifyq_event 1864 * @eid: event number 1865 * @ecode: event code 1866 * @data: unspecified data about the event 1867 * 1868 * This is the generic event report struct from which the other 1869 * actual events will be formed. 1870 */ 1871 struct ionic_notifyq_event { 1872 __le64 eid; 1873 __le16 ecode; 1874 u8 data[54]; 1875 }; 1876 1877 /** 1878 * struct ionic_link_change_event 1879 * @eid: event number 1880 * @ecode: event code = EVENT_OPCODE_LINK_CHANGE 1881 * @link_status: link up or down, with error bits (enum port_status) 1882 * @link_speed: speed of the network link 1883 * 1884 * Sent when the network link state changes between UP and DOWN 1885 */ 1886 struct ionic_link_change_event { 1887 __le64 eid; 1888 __le16 ecode; 1889 __le16 link_status; 1890 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 1891 u8 rsvd[48]; 1892 }; 1893 1894 /** 1895 * struct ionic_reset_event 1896 * @eid: event number 1897 * @ecode: event code = EVENT_OPCODE_RESET 1898 * @reset_code: reset type 1899 * @state: 0=pending, 1=complete, 2=error 1900 * 1901 * Sent when the NIC or some subsystem is going to be or 1902 * has been reset. 1903 */ 1904 struct ionic_reset_event { 1905 __le64 eid; 1906 __le16 ecode; 1907 u8 reset_code; 1908 u8 state; 1909 u8 rsvd[52]; 1910 }; 1911 1912 /** 1913 * struct ionic_heartbeat_event 1914 * @eid: event number 1915 * @ecode: event code = EVENT_OPCODE_HEARTBEAT 1916 * 1917 * Sent periodically by the NIC to indicate continued health 1918 */ 1919 struct ionic_heartbeat_event { 1920 __le64 eid; 1921 __le16 ecode; 1922 u8 rsvd[54]; 1923 }; 1924 1925 /** 1926 * struct ionic_log_event 1927 * @eid: event number 1928 * @ecode: event code = EVENT_OPCODE_LOG 1929 * @data: log data 1930 * 1931 * Sent to notify the driver of an internal error. 1932 */ 1933 struct ionic_log_event { 1934 __le64 eid; 1935 __le16 ecode; 1936 u8 data[54]; 1937 }; 1938 1939 /** 1940 * struct ionic_port_stats 1941 */ 1942 struct ionic_port_stats { 1943 __le64 frames_rx_ok; 1944 __le64 frames_rx_all; 1945 __le64 frames_rx_bad_fcs; 1946 __le64 frames_rx_bad_all; 1947 __le64 octets_rx_ok; 1948 __le64 octets_rx_all; 1949 __le64 frames_rx_unicast; 1950 __le64 frames_rx_multicast; 1951 __le64 frames_rx_broadcast; 1952 __le64 frames_rx_pause; 1953 __le64 frames_rx_bad_length; 1954 __le64 frames_rx_undersized; 1955 __le64 frames_rx_oversized; 1956 __le64 frames_rx_fragments; 1957 __le64 frames_rx_jabber; 1958 __le64 frames_rx_pripause; 1959 __le64 frames_rx_stomped_crc; 1960 __le64 frames_rx_too_long; 1961 __le64 frames_rx_vlan_good; 1962 __le64 frames_rx_dropped; 1963 __le64 frames_rx_less_than_64b; 1964 __le64 frames_rx_64b; 1965 __le64 frames_rx_65b_127b; 1966 __le64 frames_rx_128b_255b; 1967 __le64 frames_rx_256b_511b; 1968 __le64 frames_rx_512b_1023b; 1969 __le64 frames_rx_1024b_1518b; 1970 __le64 frames_rx_1519b_2047b; 1971 __le64 frames_rx_2048b_4095b; 1972 __le64 frames_rx_4096b_8191b; 1973 __le64 frames_rx_8192b_9215b; 1974 __le64 frames_rx_other; 1975 __le64 frames_tx_ok; 1976 __le64 frames_tx_all; 1977 __le64 frames_tx_bad; 1978 __le64 octets_tx_ok; 1979 __le64 octets_tx_total; 1980 __le64 frames_tx_unicast; 1981 __le64 frames_tx_multicast; 1982 __le64 frames_tx_broadcast; 1983 __le64 frames_tx_pause; 1984 __le64 frames_tx_pripause; 1985 __le64 frames_tx_vlan; 1986 __le64 frames_tx_less_than_64b; 1987 __le64 frames_tx_64b; 1988 __le64 frames_tx_65b_127b; 1989 __le64 frames_tx_128b_255b; 1990 __le64 frames_tx_256b_511b; 1991 __le64 frames_tx_512b_1023b; 1992 __le64 frames_tx_1024b_1518b; 1993 __le64 frames_tx_1519b_2047b; 1994 __le64 frames_tx_2048b_4095b; 1995 __le64 frames_tx_4096b_8191b; 1996 __le64 frames_tx_8192b_9215b; 1997 __le64 frames_tx_other; 1998 __le64 frames_tx_pri_0; 1999 __le64 frames_tx_pri_1; 2000 __le64 frames_tx_pri_2; 2001 __le64 frames_tx_pri_3; 2002 __le64 frames_tx_pri_4; 2003 __le64 frames_tx_pri_5; 2004 __le64 frames_tx_pri_6; 2005 __le64 frames_tx_pri_7; 2006 __le64 frames_rx_pri_0; 2007 __le64 frames_rx_pri_1; 2008 __le64 frames_rx_pri_2; 2009 __le64 frames_rx_pri_3; 2010 __le64 frames_rx_pri_4; 2011 __le64 frames_rx_pri_5; 2012 __le64 frames_rx_pri_6; 2013 __le64 frames_rx_pri_7; 2014 __le64 tx_pripause_0_1us_count; 2015 __le64 tx_pripause_1_1us_count; 2016 __le64 tx_pripause_2_1us_count; 2017 __le64 tx_pripause_3_1us_count; 2018 __le64 tx_pripause_4_1us_count; 2019 __le64 tx_pripause_5_1us_count; 2020 __le64 tx_pripause_6_1us_count; 2021 __le64 tx_pripause_7_1us_count; 2022 __le64 rx_pripause_0_1us_count; 2023 __le64 rx_pripause_1_1us_count; 2024 __le64 rx_pripause_2_1us_count; 2025 __le64 rx_pripause_3_1us_count; 2026 __le64 rx_pripause_4_1us_count; 2027 __le64 rx_pripause_5_1us_count; 2028 __le64 rx_pripause_6_1us_count; 2029 __le64 rx_pripause_7_1us_count; 2030 __le64 rx_pause_1us_count; 2031 __le64 frames_tx_truncated; 2032 }; 2033 2034 struct ionic_mgmt_port_stats { 2035 __le64 frames_rx_ok; 2036 __le64 frames_rx_all; 2037 __le64 frames_rx_bad_fcs; 2038 __le64 frames_rx_bad_all; 2039 __le64 octets_rx_ok; 2040 __le64 octets_rx_all; 2041 __le64 frames_rx_unicast; 2042 __le64 frames_rx_multicast; 2043 __le64 frames_rx_broadcast; 2044 __le64 frames_rx_pause; 2045 __le64 frames_rx_bad_length0; 2046 __le64 frames_rx_undersized1; 2047 __le64 frames_rx_oversized2; 2048 __le64 frames_rx_fragments3; 2049 __le64 frames_rx_jabber4; 2050 __le64 frames_rx_64b5; 2051 __le64 frames_rx_65b_127b6; 2052 __le64 frames_rx_128b_255b7; 2053 __le64 frames_rx_256b_511b8; 2054 __le64 frames_rx_512b_1023b9; 2055 __le64 frames_rx_1024b_1518b0; 2056 __le64 frames_rx_gt_1518b1; 2057 __le64 frames_rx_fifo_full2; 2058 __le64 frames_tx_ok3; 2059 __le64 frames_tx_all4; 2060 __le64 frames_tx_bad5; 2061 __le64 octets_tx_ok6; 2062 __le64 octets_tx_total7; 2063 __le64 frames_tx_unicast8; 2064 __le64 frames_tx_multicast9; 2065 __le64 frames_tx_broadcast0; 2066 __le64 frames_tx_pause1; 2067 }; 2068 2069 /** 2070 * struct ionic_port_identity - port identity structure 2071 * @version: identity structure version 2072 * @type: type of port (enum port_type) 2073 * @num_lanes: number of lanes for the port 2074 * @autoneg: autoneg supported 2075 * @min_frame_size: minimum frame size supported 2076 * @max_frame_size: maximum frame size supported 2077 * @fec_type: supported fec types 2078 * @pause_type: supported pause types 2079 * @loopback_mode: supported loopback mode 2080 * @speeds: supported speeds 2081 * @config: current port configuration 2082 */ 2083 union ionic_port_identity { 2084 struct { 2085 u8 version; 2086 u8 type; 2087 u8 num_lanes; 2088 u8 autoneg; 2089 __le32 min_frame_size; 2090 __le32 max_frame_size; 2091 u8 fec_type[4]; 2092 u8 pause_type[2]; 2093 u8 loopback_mode[2]; 2094 __le32 speeds[16]; 2095 u8 rsvd2[44]; 2096 union ionic_port_config config; 2097 }; 2098 __le32 words[512]; 2099 }; 2100 2101 /** 2102 * struct ionic_port_info - port info structure 2103 * @port_status: port status 2104 * @port_stats: port stats 2105 */ 2106 struct ionic_port_info { 2107 union ionic_port_config config; 2108 struct ionic_port_status status; 2109 struct ionic_port_stats stats; 2110 }; 2111 2112 /** 2113 * struct ionic_lif_stats 2114 */ 2115 struct ionic_lif_stats { 2116 /* RX */ 2117 __le64 rx_ucast_bytes; 2118 __le64 rx_ucast_packets; 2119 __le64 rx_mcast_bytes; 2120 __le64 rx_mcast_packets; 2121 __le64 rx_bcast_bytes; 2122 __le64 rx_bcast_packets; 2123 __le64 rsvd0; 2124 __le64 rsvd1; 2125 /* RX drops */ 2126 __le64 rx_ucast_drop_bytes; 2127 __le64 rx_ucast_drop_packets; 2128 __le64 rx_mcast_drop_bytes; 2129 __le64 rx_mcast_drop_packets; 2130 __le64 rx_bcast_drop_bytes; 2131 __le64 rx_bcast_drop_packets; 2132 __le64 rx_dma_error; 2133 __le64 rsvd2; 2134 /* TX */ 2135 __le64 tx_ucast_bytes; 2136 __le64 tx_ucast_packets; 2137 __le64 tx_mcast_bytes; 2138 __le64 tx_mcast_packets; 2139 __le64 tx_bcast_bytes; 2140 __le64 tx_bcast_packets; 2141 __le64 rsvd3; 2142 __le64 rsvd4; 2143 /* TX drops */ 2144 __le64 tx_ucast_drop_bytes; 2145 __le64 tx_ucast_drop_packets; 2146 __le64 tx_mcast_drop_bytes; 2147 __le64 tx_mcast_drop_packets; 2148 __le64 tx_bcast_drop_bytes; 2149 __le64 tx_bcast_drop_packets; 2150 __le64 tx_dma_error; 2151 __le64 rsvd5; 2152 /* Rx Queue/Ring drops */ 2153 __le64 rx_queue_disabled; 2154 __le64 rx_queue_empty; 2155 __le64 rx_queue_error; 2156 __le64 rx_desc_fetch_error; 2157 __le64 rx_desc_data_error; 2158 __le64 rsvd6; 2159 __le64 rsvd7; 2160 __le64 rsvd8; 2161 /* Tx Queue/Ring drops */ 2162 __le64 tx_queue_disabled; 2163 __le64 tx_queue_error; 2164 __le64 tx_desc_fetch_error; 2165 __le64 tx_desc_data_error; 2166 __le64 rsvd9; 2167 __le64 rsvd10; 2168 __le64 rsvd11; 2169 __le64 rsvd12; 2170 2171 /* RDMA/ROCE TX */ 2172 __le64 tx_rdma_ucast_bytes; 2173 __le64 tx_rdma_ucast_packets; 2174 __le64 tx_rdma_mcast_bytes; 2175 __le64 tx_rdma_mcast_packets; 2176 __le64 tx_rdma_cnp_packets; 2177 __le64 rsvd13; 2178 __le64 rsvd14; 2179 __le64 rsvd15; 2180 2181 /* RDMA/ROCE RX */ 2182 __le64 rx_rdma_ucast_bytes; 2183 __le64 rx_rdma_ucast_packets; 2184 __le64 rx_rdma_mcast_bytes; 2185 __le64 rx_rdma_mcast_packets; 2186 __le64 rx_rdma_cnp_packets; 2187 __le64 rx_rdma_ecn_packets; 2188 __le64 rsvd16; 2189 __le64 rsvd17; 2190 2191 __le64 rsvd18; 2192 __le64 rsvd19; 2193 __le64 rsvd20; 2194 __le64 rsvd21; 2195 __le64 rsvd22; 2196 __le64 rsvd23; 2197 __le64 rsvd24; 2198 __le64 rsvd25; 2199 2200 __le64 rsvd26; 2201 __le64 rsvd27; 2202 __le64 rsvd28; 2203 __le64 rsvd29; 2204 __le64 rsvd30; 2205 __le64 rsvd31; 2206 __le64 rsvd32; 2207 __le64 rsvd33; 2208 2209 __le64 rsvd34; 2210 __le64 rsvd35; 2211 __le64 rsvd36; 2212 __le64 rsvd37; 2213 __le64 rsvd38; 2214 __le64 rsvd39; 2215 __le64 rsvd40; 2216 __le64 rsvd41; 2217 2218 __le64 rsvd42; 2219 __le64 rsvd43; 2220 __le64 rsvd44; 2221 __le64 rsvd45; 2222 __le64 rsvd46; 2223 __le64 rsvd47; 2224 __le64 rsvd48; 2225 __le64 rsvd49; 2226 2227 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2228 __le64 rdma_req_rx_pkt_seq_err; 2229 __le64 rdma_req_rx_rnr_retry_err; 2230 __le64 rdma_req_rx_remote_access_err; 2231 __le64 rdma_req_rx_remote_inv_req_err; 2232 __le64 rdma_req_rx_remote_oper_err; 2233 __le64 rdma_req_rx_implied_nak_seq_err; 2234 __le64 rdma_req_rx_cqe_err; 2235 __le64 rdma_req_rx_cqe_flush_err; 2236 2237 __le64 rdma_req_rx_dup_responses; 2238 __le64 rdma_req_rx_invalid_packets; 2239 __le64 rdma_req_tx_local_access_err; 2240 __le64 rdma_req_tx_local_oper_err; 2241 __le64 rdma_req_tx_memory_mgmt_err; 2242 __le64 rsvd52; 2243 __le64 rsvd53; 2244 __le64 rsvd54; 2245 2246 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2247 __le64 rdma_resp_rx_dup_requests; 2248 __le64 rdma_resp_rx_out_of_buffer; 2249 __le64 rdma_resp_rx_out_of_seq_pkts; 2250 __le64 rdma_resp_rx_cqe_err; 2251 __le64 rdma_resp_rx_cqe_flush_err; 2252 __le64 rdma_resp_rx_local_len_err; 2253 __le64 rdma_resp_rx_inv_request_err; 2254 __le64 rdma_resp_rx_local_qp_oper_err; 2255 2256 __le64 rdma_resp_rx_out_of_atomic_resource; 2257 __le64 rdma_resp_tx_pkt_seq_err; 2258 __le64 rdma_resp_tx_remote_inv_req_err; 2259 __le64 rdma_resp_tx_remote_access_err; 2260 __le64 rdma_resp_tx_remote_oper_err; 2261 __le64 rdma_resp_tx_rnr_retry_err; 2262 __le64 rsvd57; 2263 __le64 rsvd58; 2264 }; 2265 2266 /** 2267 * struct ionic_lif_info - lif info structure 2268 */ 2269 struct ionic_lif_info { 2270 union ionic_lif_config config; 2271 struct ionic_lif_status status; 2272 struct ionic_lif_stats stats; 2273 }; 2274 2275 union ionic_dev_cmd { 2276 u32 words[16]; 2277 struct ionic_admin_cmd cmd; 2278 struct ionic_nop_cmd nop; 2279 2280 struct ionic_dev_identify_cmd identify; 2281 struct ionic_dev_init_cmd init; 2282 struct ionic_dev_reset_cmd reset; 2283 struct ionic_dev_getattr_cmd getattr; 2284 struct ionic_dev_setattr_cmd setattr; 2285 2286 struct ionic_port_identify_cmd port_identify; 2287 struct ionic_port_init_cmd port_init; 2288 struct ionic_port_reset_cmd port_reset; 2289 struct ionic_port_getattr_cmd port_getattr; 2290 struct ionic_port_setattr_cmd port_setattr; 2291 2292 struct ionic_lif_identify_cmd lif_identify; 2293 struct ionic_lif_init_cmd lif_init; 2294 struct ionic_lif_reset_cmd lif_reset; 2295 2296 struct ionic_qos_identify_cmd qos_identify; 2297 struct ionic_qos_init_cmd qos_init; 2298 struct ionic_qos_reset_cmd qos_reset; 2299 2300 struct ionic_q_init_cmd q_init; 2301 }; 2302 2303 union ionic_dev_cmd_comp { 2304 u32 words[4]; 2305 u8 status; 2306 struct ionic_admin_comp comp; 2307 struct ionic_nop_comp nop; 2308 2309 struct ionic_dev_identify_comp identify; 2310 struct ionic_dev_init_comp init; 2311 struct ionic_dev_reset_comp reset; 2312 struct ionic_dev_getattr_comp getattr; 2313 struct ionic_dev_setattr_comp setattr; 2314 2315 struct ionic_port_identify_comp port_identify; 2316 struct ionic_port_init_comp port_init; 2317 struct ionic_port_reset_comp port_reset; 2318 struct ionic_port_getattr_comp port_getattr; 2319 struct ionic_port_setattr_comp port_setattr; 2320 2321 struct ionic_lif_identify_comp lif_identify; 2322 struct ionic_lif_init_comp lif_init; 2323 ionic_lif_reset_comp lif_reset; 2324 2325 struct ionic_qos_identify_comp qos_identify; 2326 ionic_qos_init_comp qos_init; 2327 ionic_qos_reset_comp qos_reset; 2328 2329 struct ionic_q_init_comp q_init; 2330 }; 2331 2332 /** 2333 * union dev_info - Device info register format (read-only) 2334 * @signature: Signature value of 0x44455649 ('DEVI'). 2335 * @version: Current version of info. 2336 * @asic_type: Asic type. 2337 * @asic_rev: Asic revision. 2338 * @fw_status: Firmware status. 2339 * @fw_heartbeat: Firmware heartbeat counter. 2340 * @serial_num: Serial number. 2341 * @fw_version: Firmware version. 2342 */ 2343 union ionic_dev_info_regs { 2344 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2345 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2346 struct { 2347 u32 signature; 2348 u8 version; 2349 u8 asic_type; 2350 u8 asic_rev; 2351 u8 fw_status; 2352 u32 fw_heartbeat; 2353 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2354 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2355 }; 2356 u32 words[512]; 2357 }; 2358 2359 /** 2360 * union ionic_dev_cmd_regs - Device command register format (read-write) 2361 * @doorbell: Device Cmd Doorbell, write-only. 2362 * Write a 1 to signal device to process cmd, 2363 * poll done for completion. 2364 * @done: Done indicator, bit 0 == 1 when command is complete. 2365 * @cmd: Opcode-specific command bytes 2366 * @comp: Opcode-specific response bytes 2367 * @data: Opcode-specific side-data 2368 */ 2369 union ionic_dev_cmd_regs { 2370 struct { 2371 u32 doorbell; 2372 u32 done; 2373 union ionic_dev_cmd cmd; 2374 union ionic_dev_cmd_comp comp; 2375 u8 rsvd[48]; 2376 u32 data[478]; 2377 }; 2378 u32 words[512]; 2379 }; 2380 2381 /** 2382 * union ionic_dev_regs - Device register format in for bar 0 page 0 2383 * @info: Device info registers 2384 * @devcmd: Device command registers 2385 */ 2386 union ionic_dev_regs { 2387 struct { 2388 union ionic_dev_info_regs info; 2389 union ionic_dev_cmd_regs devcmd; 2390 }; 2391 __le32 words[1024]; 2392 }; 2393 2394 union ionic_adminq_cmd { 2395 struct ionic_admin_cmd cmd; 2396 struct ionic_nop_cmd nop; 2397 struct ionic_q_init_cmd q_init; 2398 struct ionic_q_control_cmd q_control; 2399 struct ionic_lif_setattr_cmd lif_setattr; 2400 struct ionic_lif_getattr_cmd lif_getattr; 2401 struct ionic_rx_mode_set_cmd rx_mode_set; 2402 struct ionic_rx_filter_add_cmd rx_filter_add; 2403 struct ionic_rx_filter_del_cmd rx_filter_del; 2404 struct ionic_rdma_reset_cmd rdma_reset; 2405 struct ionic_rdma_queue_cmd rdma_queue; 2406 struct ionic_fw_download_cmd fw_download; 2407 struct ionic_fw_control_cmd fw_control; 2408 }; 2409 2410 union ionic_adminq_comp { 2411 struct ionic_admin_comp comp; 2412 struct ionic_nop_comp nop; 2413 struct ionic_q_init_comp q_init; 2414 struct ionic_lif_setattr_comp lif_setattr; 2415 struct ionic_lif_getattr_comp lif_getattr; 2416 struct ionic_rx_filter_add_comp rx_filter_add; 2417 struct ionic_fw_control_comp fw_control; 2418 }; 2419 2420 #define IONIC_BARS_MAX 6 2421 #define IONIC_PCI_BAR_DBELL 1 2422 2423 /* BAR0 */ 2424 #define IONIC_BAR0_SIZE 0x8000 2425 2426 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2427 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2428 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2429 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2430 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2431 #define IONIC_DEV_CMD_DONE 0x00000001 2432 2433 #define IONIC_ASIC_TYPE_CAPRI 0 2434 2435 /** 2436 * struct ionic_doorbell - Doorbell register layout 2437 * @p_index: Producer index 2438 * @ring: Selects the specific ring of the queue to update. 2439 * Type-specific meaning: 2440 * ring=0: Default producer/consumer queue. 2441 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2442 * send events to EQs when armed. EQs send 2443 * interrupts when armed. 2444 * @qid: The queue id selects the queue destination for the 2445 * producer index and flags. 2446 */ 2447 struct ionic_doorbell { 2448 __le16 p_index; 2449 u8 ring; 2450 u8 qid_lo; 2451 __le16 qid_hi; 2452 u16 rsvd2; 2453 }; 2454 2455 struct ionic_intr_status { 2456 u32 status[2]; 2457 }; 2458 2459 struct ionic_notifyq_cmd { 2460 __le32 data; /* Not used but needed for qcq structure */ 2461 }; 2462 2463 union ionic_notifyq_comp { 2464 struct ionic_notifyq_event event; 2465 struct ionic_link_change_event link_change; 2466 struct ionic_reset_event reset; 2467 struct ionic_heartbeat_event heartbeat; 2468 struct ionic_log_event log; 2469 }; 2470 2471 /* Deprecate */ 2472 struct ionic_identity { 2473 union ionic_drv_identity drv; 2474 union ionic_dev_identity dev; 2475 union ionic_lif_identity lif; 2476 union ionic_port_identity port; 2477 union ionic_qos_identity qos; 2478 }; 2479 2480 #pragma pack(pop) 2481 2482 #endif /* _IONIC_IF_H_ */ 2483