1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /** 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 38 IONIC_CMD_RX_MODE_SET = 30, 39 IONIC_CMD_RX_FILTER_ADD = 31, 40 IONIC_CMD_RX_FILTER_DEL = 32, 41 42 /* Queue commands */ 43 IONIC_CMD_Q_IDENTIFY = 39, 44 IONIC_CMD_Q_INIT = 40, 45 IONIC_CMD_Q_CONTROL = 41, 46 47 /* RDMA commands */ 48 IONIC_CMD_RDMA_RESET_LIF = 50, 49 IONIC_CMD_RDMA_CREATE_EQ = 51, 50 IONIC_CMD_RDMA_CREATE_CQ = 52, 51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 52 53 /* SR/IOV commands */ 54 IONIC_CMD_VF_GETATTR = 60, 55 IONIC_CMD_VF_SETATTR = 61, 56 57 /* QoS commands */ 58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 59 IONIC_CMD_QOS_CLASS_INIT = 241, 60 IONIC_CMD_QOS_CLASS_RESET = 242, 61 IONIC_CMD_QOS_CLASS_UPDATE = 243, 62 IONIC_CMD_QOS_CLEAR_STATS = 244, 63 IONIC_CMD_QOS_RESET = 245, 64 65 /* Firmware commands */ 66 IONIC_CMD_FW_DOWNLOAD = 254, 67 IONIC_CMD_FW_CONTROL = 255, 68 }; 69 70 /** 71 * enum ionic_status_code - Device command return codes 72 */ 73 enum ionic_status_code { 74 IONIC_RC_SUCCESS = 0, /* Success */ 75 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 76 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 77 IONIC_RC_EIO = 3, /* I/O error */ 78 IONIC_RC_EPERM = 4, /* Permission denied */ 79 IONIC_RC_EQID = 5, /* Bad qid */ 80 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 81 IONIC_RC_ENOENT = 7, /* No such element */ 82 IONIC_RC_EINTR = 8, /* operation interrupted */ 83 IONIC_RC_EAGAIN = 9, /* Try again */ 84 IONIC_RC_ENOMEM = 10, /* Out of memory */ 85 IONIC_RC_EFAULT = 11, /* Bad address */ 86 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 87 IONIC_RC_EEXIST = 13, /* object already exists */ 88 IONIC_RC_EINVAL = 14, /* Invalid argument */ 89 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 90 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 91 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 92 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 93 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 94 IONIC_RC_ERROR = 29, /* Generic error */ 95 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 96 IONIC_RC_EVFID = 31, /* VF ID does not exist */ 97 }; 98 99 enum ionic_notifyq_opcode { 100 IONIC_EVENT_LINK_CHANGE = 1, 101 IONIC_EVENT_RESET = 2, 102 IONIC_EVENT_HEARTBEAT = 3, 103 IONIC_EVENT_LOG = 4, 104 IONIC_EVENT_XCVR = 5, 105 }; 106 107 /** 108 * struct ionic_admin_cmd - General admin command format 109 * @opcode: Opcode for the command 110 * @lif_index: LIF index 111 * @cmd_data: Opcode-specific command bytes 112 */ 113 struct ionic_admin_cmd { 114 u8 opcode; 115 u8 rsvd; 116 __le16 lif_index; 117 u8 cmd_data[60]; 118 }; 119 120 /** 121 * struct ionic_admin_comp - General admin command completion format 122 * @status: Status of the command (enum ionic_status_code) 123 * @comp_index: Index in the descriptor ring for which this is the completion 124 * @cmd_data: Command-specific bytes 125 * @color: Color bit (Always 0 for commands issued to the 126 * Device Cmd Registers) 127 */ 128 struct ionic_admin_comp { 129 u8 status; 130 u8 rsvd; 131 __le16 comp_index; 132 u8 cmd_data[11]; 133 u8 color; 134 #define IONIC_COMP_COLOR_MASK 0x80 135 }; 136 137 static inline u8 color_match(u8 color, u8 done_color) 138 { 139 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 140 } 141 142 /** 143 * struct ionic_nop_cmd - NOP command 144 * @opcode: opcode 145 */ 146 struct ionic_nop_cmd { 147 u8 opcode; 148 u8 rsvd[63]; 149 }; 150 151 /** 152 * struct ionic_nop_comp - NOP command completion 153 * @status: Status of the command (enum ionic_status_code) 154 */ 155 struct ionic_nop_comp { 156 u8 status; 157 u8 rsvd[15]; 158 }; 159 160 /** 161 * struct ionic_dev_init_cmd - Device init command 162 * @opcode: opcode 163 * @type: Device type 164 */ 165 struct ionic_dev_init_cmd { 166 u8 opcode; 167 u8 type; 168 u8 rsvd[62]; 169 }; 170 171 /** 172 * struct ionic_dev_init_comp - Device init command completion 173 * @status: Status of the command (enum ionic_status_code) 174 */ 175 struct ionic_dev_init_comp { 176 u8 status; 177 u8 rsvd[15]; 178 }; 179 180 /** 181 * struct ionic_dev_reset_cmd - Device reset command 182 * @opcode: opcode 183 */ 184 struct ionic_dev_reset_cmd { 185 u8 opcode; 186 u8 rsvd[63]; 187 }; 188 189 /** 190 * struct ionic_dev_reset_comp - Reset command completion 191 * @status: Status of the command (enum ionic_status_code) 192 */ 193 struct ionic_dev_reset_comp { 194 u8 status; 195 u8 rsvd[15]; 196 }; 197 198 #define IONIC_IDENTITY_VERSION_1 1 199 200 /** 201 * struct ionic_dev_identify_cmd - Driver/device identify command 202 * @opcode: opcode 203 * @ver: Highest version of identify supported by driver 204 */ 205 struct ionic_dev_identify_cmd { 206 u8 opcode; 207 u8 ver; 208 u8 rsvd[62]; 209 }; 210 211 /** 212 * struct ionic_dev_identify_comp - Driver/device identify command completion 213 * @status: Status of the command (enum ionic_status_code) 214 * @ver: Version of identify returned by device 215 */ 216 struct ionic_dev_identify_comp { 217 u8 status; 218 u8 ver; 219 u8 rsvd[14]; 220 }; 221 222 enum ionic_os_type { 223 IONIC_OS_TYPE_LINUX = 1, 224 IONIC_OS_TYPE_WIN = 2, 225 IONIC_OS_TYPE_DPDK = 3, 226 IONIC_OS_TYPE_FREEBSD = 4, 227 IONIC_OS_TYPE_IPXE = 5, 228 IONIC_OS_TYPE_ESXI = 6, 229 }; 230 231 /** 232 * union ionic_drv_identity - driver identity information 233 * @os_type: OS type (see enum ionic_os_type) 234 * @os_dist: OS distribution, numeric format 235 * @os_dist_str: OS distribution, string format 236 * @kernel_ver: Kernel version, numeric format 237 * @kernel_ver_str: Kernel version, string format 238 * @driver_ver_str: Driver version, string format 239 */ 240 union ionic_drv_identity { 241 struct { 242 __le32 os_type; 243 __le32 os_dist; 244 char os_dist_str[128]; 245 __le32 kernel_ver; 246 char kernel_ver_str[32]; 247 char driver_ver_str[32]; 248 }; 249 __le32 words[478]; 250 }; 251 252 /** 253 * union ionic_dev_identity - device identity information 254 * @version: Version of device identify 255 * @type: Identify type (0 for now) 256 * @nports: Number of ports provisioned 257 * @nlifs: Number of LIFs provisioned 258 * @nintrs: Number of interrupts provisioned 259 * @ndbpgs_per_lif: Number of doorbell pages per LIF 260 * @intr_coal_mult: Interrupt coalescing multiplication factor 261 * Scale user-supplied interrupt coalescing 262 * value in usecs to device units using: 263 * device units = usecs * mult / div 264 * @intr_coal_div: Interrupt coalescing division factor 265 * Scale user-supplied interrupt coalescing 266 * value in usecs to device units using: 267 * device units = usecs * mult / div 268 * @eq_count: Number of shared event queues 269 */ 270 union ionic_dev_identity { 271 struct { 272 u8 version; 273 u8 type; 274 u8 rsvd[2]; 275 u8 nports; 276 u8 rsvd2[3]; 277 __le32 nlifs; 278 __le32 nintrs; 279 __le32 ndbpgs_per_lif; 280 __le32 intr_coal_mult; 281 __le32 intr_coal_div; 282 __le32 eq_count; 283 }; 284 __le32 words[478]; 285 }; 286 287 enum ionic_lif_type { 288 IONIC_LIF_TYPE_CLASSIC = 0, 289 IONIC_LIF_TYPE_MACVLAN = 1, 290 IONIC_LIF_TYPE_NETQUEUE = 2, 291 }; 292 293 /** 294 * struct ionic_lif_identify_cmd - LIF identify command 295 * @opcode: opcode 296 * @type: LIF type (enum ionic_lif_type) 297 * @ver: Version of identify returned by device 298 */ 299 struct ionic_lif_identify_cmd { 300 u8 opcode; 301 u8 type; 302 u8 ver; 303 u8 rsvd[61]; 304 }; 305 306 /** 307 * struct ionic_lif_identify_comp - LIF identify command completion 308 * @status: Status of the command (enum ionic_status_code) 309 * @ver: Version of identify returned by device 310 */ 311 struct ionic_lif_identify_comp { 312 u8 status; 313 u8 ver; 314 u8 rsvd2[14]; 315 }; 316 317 /** 318 * enum ionic_lif_capability - LIF capabilities 319 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 320 * @IONIC_LIF_CAP_RDMA: LIF support RDMA 321 */ 322 enum ionic_lif_capability { 323 IONIC_LIF_CAP_ETH = BIT(0), 324 IONIC_LIF_CAP_RDMA = BIT(1), 325 }; 326 327 /** 328 * enum ionic_logical_qtype - Logical Queue Types 329 * @IONIC_QTYPE_ADMINQ: Administrative Queue 330 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 331 * @IONIC_QTYPE_RXQ: Receive Queue 332 * @IONIC_QTYPE_TXQ: Transmit Queue 333 * @IONIC_QTYPE_EQ: Event Queue 334 * @IONIC_QTYPE_MAX: Max queue type supported 335 */ 336 enum ionic_logical_qtype { 337 IONIC_QTYPE_ADMINQ = 0, 338 IONIC_QTYPE_NOTIFYQ = 1, 339 IONIC_QTYPE_RXQ = 2, 340 IONIC_QTYPE_TXQ = 3, 341 IONIC_QTYPE_EQ = 4, 342 IONIC_QTYPE_MAX = 16, 343 }; 344 345 /** 346 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 347 * @qtype: Hardware Queue Type 348 * @qid_count: Number of Queue IDs of the logical type 349 * @qid_base: Minimum Queue ID of the logical type 350 */ 351 struct ionic_lif_logical_qtype { 352 u8 qtype; 353 u8 rsvd[3]; 354 __le32 qid_count; 355 __le32 qid_base; 356 }; 357 358 /** 359 * enum ionic_lif_state - LIF state 360 * @IONIC_LIF_DISABLE: LIF disabled 361 * @IONIC_LIF_ENABLE: LIF enabled 362 * @IONIC_LIF_QUIESCE: LIF Quiesced 363 */ 364 enum ionic_lif_state { 365 IONIC_LIF_QUIESCE = 0, 366 IONIC_LIF_ENABLE = 1, 367 IONIC_LIF_DISABLE = 2, 368 }; 369 370 /** 371 * union ionic_lif_config - LIF configuration 372 * @state: LIF state (enum ionic_lif_state) 373 * @name: LIF name 374 * @mtu: MTU 375 * @mac: Station MAC address 376 * @vlan: Default Vlan ID 377 * @features: Features (enum ionic_eth_hw_features) 378 * @queue_count: Queue counts per queue-type 379 */ 380 union ionic_lif_config { 381 struct { 382 u8 state; 383 u8 rsvd[3]; 384 char name[IONIC_IFNAMSIZ]; 385 __le32 mtu; 386 u8 mac[6]; 387 __le16 vlan; 388 __le64 features; 389 __le32 queue_count[IONIC_QTYPE_MAX]; 390 } __packed; 391 __le32 words[64]; 392 }; 393 394 /** 395 * struct ionic_lif_identity - LIF identity information (type-specific) 396 * 397 * @capabilities: LIF capabilities 398 * 399 * @eth: Ethernet identify structure 400 * @version: Ethernet identify structure version 401 * @max_ucast_filters: Number of perfect unicast addresses supported 402 * @max_mcast_filters: Number of perfect multicast addresses supported 403 * @min_frame_size: Minimum size of frames to be sent 404 * @max_frame_size: Maximim size of frames to be sent 405 * @config: LIF config struct with features, mtu, mac, q counts 406 * 407 * @rdma: RDMA identify structure 408 * @version: RDMA version of opcodes and queue descriptors 409 * @qp_opcodes: Number of RDMA queue pair opcodes supported 410 * @admin_opcodes: Number of RDMA admin opcodes supported 411 * @npts_per_lif: Page table size per LIF 412 * @nmrs_per_lif: Number of memory regions per LIF 413 * @nahs_per_lif: Number of address handles per LIF 414 * @max_stride: Max work request stride 415 * @cl_stride: Cache line stride 416 * @pte_stride: Page table entry stride 417 * @rrq_stride: Remote RQ work request stride 418 * @rsq_stride: Remote SQ work request stride 419 * @dcqcn_profiles: Number of DCQCN profiles 420 * @aq_qtype: RDMA Admin Qtype 421 * @sq_qtype: RDMA Send Qtype 422 * @rq_qtype: RDMA Receive Qtype 423 * @cq_qtype: RDMA Completion Qtype 424 * @eq_qtype: RDMA Event Qtype 425 */ 426 union ionic_lif_identity { 427 struct { 428 __le64 capabilities; 429 430 struct { 431 u8 version; 432 u8 rsvd[3]; 433 __le32 max_ucast_filters; 434 __le32 max_mcast_filters; 435 __le16 rss_ind_tbl_sz; 436 __le32 min_frame_size; 437 __le32 max_frame_size; 438 u8 rsvd2[106]; 439 union ionic_lif_config config; 440 } __packed eth; 441 442 struct { 443 u8 version; 444 u8 qp_opcodes; 445 u8 admin_opcodes; 446 u8 rsvd; 447 __le32 npts_per_lif; 448 __le32 nmrs_per_lif; 449 __le32 nahs_per_lif; 450 u8 max_stride; 451 u8 cl_stride; 452 u8 pte_stride; 453 u8 rrq_stride; 454 u8 rsq_stride; 455 u8 dcqcn_profiles; 456 u8 rsvd_dimensions[10]; 457 struct ionic_lif_logical_qtype aq_qtype; 458 struct ionic_lif_logical_qtype sq_qtype; 459 struct ionic_lif_logical_qtype rq_qtype; 460 struct ionic_lif_logical_qtype cq_qtype; 461 struct ionic_lif_logical_qtype eq_qtype; 462 } __packed rdma; 463 } __packed; 464 __le32 words[478]; 465 }; 466 467 /** 468 * struct ionic_lif_init_cmd - LIF init command 469 * @opcode: Opcode 470 * @type: LIF type (enum ionic_lif_type) 471 * @index: LIF index 472 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 473 */ 474 struct ionic_lif_init_cmd { 475 u8 opcode; 476 u8 type; 477 __le16 index; 478 __le32 rsvd; 479 __le64 info_pa; 480 u8 rsvd2[48]; 481 }; 482 483 /** 484 * struct ionic_lif_init_comp - LIF init command completion 485 * @status: Status of the command (enum ionic_status_code) 486 * @hw_index: Hardware index of the initialized LIF 487 */ 488 struct ionic_lif_init_comp { 489 u8 status; 490 u8 rsvd; 491 __le16 hw_index; 492 u8 rsvd2[12]; 493 }; 494 495 /** 496 * struct ionic_q_identify_cmd - queue identify command 497 * @opcode: opcode 498 * @lif_type: LIF type (enum ionic_lif_type) 499 * @type: Logical queue type (enum ionic_logical_qtype) 500 * @ver: Highest queue type version that the driver supports 501 */ 502 struct ionic_q_identify_cmd { 503 u8 opcode; 504 u8 rsvd; 505 __le16 lif_type; 506 u8 type; 507 u8 ver; 508 u8 rsvd2[58]; 509 }; 510 511 /** 512 * struct ionic_q_identify_comp - queue identify command completion 513 * @status: Status of the command (enum ionic_status_code) 514 * @comp_index: Index in the descriptor ring for which this is the completion 515 * @ver: Queue type version that can be used with FW 516 */ 517 struct ionic_q_identify_comp { 518 u8 status; 519 u8 rsvd; 520 __le16 comp_index; 521 u8 ver; 522 u8 rsvd2[11]; 523 }; 524 525 /** 526 * union ionic_q_identity - queue identity information 527 * @version: Queue type version that can be used with FW 528 * @supported: Bitfield of queue versions, first bit = ver 0 529 * @features: Queue features 530 * @desc_sz: Descriptor size 531 * @comp_sz: Completion descriptor size 532 * @sg_desc_sz: Scatter/Gather descriptor size 533 * @max_sg_elems: Maximum number of Scatter/Gather elements 534 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 535 */ 536 union ionic_q_identity { 537 struct { 538 u8 version; 539 u8 supported; 540 u8 rsvd[6]; 541 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */ 542 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */ 543 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */ 544 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */ 545 __le64 features; 546 __le16 desc_sz; 547 __le16 comp_sz; 548 __le16 sg_desc_sz; 549 __le16 max_sg_elems; 550 __le16 sg_desc_stride; 551 }; 552 __le32 words[478]; 553 }; 554 555 /** 556 * struct ionic_q_init_cmd - Queue init command 557 * @opcode: opcode 558 * @type: Logical queue type 559 * @ver: Queue type version 560 * @lif_index: LIF index 561 * @index: (LIF, qtype) relative admin queue index 562 * @intr_index: Interrupt control register index, or Event queue index 563 * @pid: Process ID 564 * @flags: 565 * IRQ: Interrupt requested on completion 566 * ENA: Enable the queue. If ENA=0 the queue is initialized 567 * but remains disabled, to be later enabled with the 568 * Queue Enable command. If ENA=1, then queue is 569 * initialized and then enabled. 570 * SG: Enable Scatter-Gather on the queue. 571 * in number of descs. The actual ring size is 572 * (1 << ring_size). For example, to 573 * select a ring size of 64 descriptors write 574 * ring_size = 6. The minimum ring_size value is 2 575 * for a ring size of 4 descriptors. The maximum 576 * ring_size value is 16 for a ring size of 64k 577 * descriptors. Values of ring_size <2 and >16 are 578 * reserved. 579 * EQ: Enable the Event Queue 580 * @cos: Class of service for this queue 581 * @ring_size: Queue ring size, encoded as a log2(size) 582 * @ring_base: Queue ring base address 583 * @cq_ring_base: Completion queue ring base address 584 * @sg_ring_base: Scatter/Gather ring base address 585 */ 586 struct ionic_q_init_cmd { 587 u8 opcode; 588 u8 rsvd; 589 __le16 lif_index; 590 u8 type; 591 u8 ver; 592 u8 rsvd1[2]; 593 __le32 index; 594 __le16 pid; 595 __le16 intr_index; 596 __le16 flags; 597 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 598 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 599 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 600 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 601 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 602 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 603 u8 cos; 604 u8 ring_size; 605 __le64 ring_base; 606 __le64 cq_ring_base; 607 __le64 sg_ring_base; 608 u8 rsvd2[20]; 609 } __packed; 610 611 /** 612 * struct ionic_q_init_comp - Queue init command completion 613 * @status: Status of the command (enum ionic_status_code) 614 * @comp_index: Index in the descriptor ring for which this is the completion 615 * @hw_index: Hardware Queue ID 616 * @hw_type: Hardware Queue type 617 * @color: Color 618 */ 619 struct ionic_q_init_comp { 620 u8 status; 621 u8 rsvd; 622 __le16 comp_index; 623 __le32 hw_index; 624 u8 hw_type; 625 u8 rsvd2[6]; 626 u8 color; 627 }; 628 629 /* the device's internal addressing uses up to 52 bits */ 630 #define IONIC_ADDR_LEN 52 631 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 632 633 enum ionic_txq_desc_opcode { 634 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 635 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 636 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 637 IONIC_TXQ_DESC_OPCODE_TSO = 3, 638 }; 639 640 /** 641 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 642 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 643 * 644 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 645 * Non-offload send. No segmentation, 646 * fragmentation or checksum calc/insertion is 647 * performed by device; packet is prepared 648 * to send by software stack and requires 649 * no further manipulation from device. 650 * 651 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 652 * Offload 16-bit L4 checksum 653 * calculation/insertion. The device will 654 * calculate the L4 checksum value and 655 * insert the result in the packet's L4 656 * header checksum field. The L4 checksum 657 * is calculated starting at @csum_start bytes 658 * into the packet to the end of the packet. 659 * The checksum insertion position is given 660 * in @csum_offset, which is the offset from 661 * @csum_start to the checksum field in the L4 662 * header. This feature is only applicable to 663 * protocols such as TCP, UDP and ICMP where a 664 * standard (i.e. the 'IP-style' checksum) 665 * one's complement 16-bit checksum is used, 666 * using an IP pseudo-header to seed the 667 * calculation. Software will preload the L4 668 * checksum field with the IP pseudo-header 669 * checksum. 670 * 671 * For tunnel encapsulation, @csum_start and 672 * @csum_offset refer to the inner L4 673 * header. Supported tunnels encapsulations 674 * are: IPIP, GRE, and UDP. If the @encap 675 * is clear, no further processing by the 676 * device is required; software will 677 * calculate the outer header checksums. If 678 * the @encap is set, the device will 679 * offload the outer header checksums using 680 * LCO (local checksum offload) (see 681 * Documentation/networking/checksum-offloads.rst 682 * for more info). 683 * 684 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 685 * Offload 16-bit checksum computation to hardware. 686 * If @csum_l3 is set then the packet's L3 checksum is 687 * updated. Similarly, if @csum_l4 is set the the L4 688 * checksum is updated. If @encap is set then encap header 689 * checksums are also updated. 690 * 691 * IONIC_TXQ_DESC_OPCODE_TSO: 692 * Device preforms TCP segmentation offload 693 * (TSO). @hdr_len is the number of bytes 694 * to the end of TCP header (the offset to 695 * the TCP payload). @mss is the desired 696 * MSS, the TCP payload length for each 697 * segment. The device will calculate/ 698 * insert IP (IPv4 only) and TCP checksums 699 * for each segment. In the first data 700 * buffer containing the header template, 701 * the driver will set IPv4 checksum to 0 702 * and preload TCP checksum with the IP 703 * pseudo header calculated with IP length = 0. 704 * 705 * Supported tunnel encapsulations are IPIP, 706 * layer-3 GRE, and UDP. @hdr_len includes 707 * both outer and inner headers. The driver 708 * will set IPv4 checksum to zero and 709 * preload TCP checksum with IP pseudo 710 * header on the inner header. 711 * 712 * TCP ECN offload is supported. The device 713 * will set CWR flag in the first segment if 714 * CWR is set in the template header, and 715 * clear CWR in remaining segments. 716 * @flags: 717 * vlan: 718 * Insert an L2 VLAN header using @vlan_tci 719 * encap: 720 * Calculate encap header checksum 721 * csum_l3: 722 * Compute L3 header checksum 723 * csum_l4: 724 * Compute L4 header checksum 725 * tso_sot: 726 * TSO start 727 * tso_eot: 728 * TSO end 729 * @num_sg_elems: Number of scatter-gather elements in SG 730 * descriptor 731 * @addr: First data buffer's DMA address 732 * (Subsequent data buffers are on txq_sg_desc) 733 * @len: First data buffer's length, in bytes 734 * @vlan_tci: VLAN tag to insert in the packet (if requested 735 * by @V-bit). Includes .1p and .1q tags 736 * @hdr_len: Length of packet headers, including 737 * encapsulating outer header, if applicable 738 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 739 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 740 * all other modes. For 741 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 742 * of headers up to inner-most L4 header. For 743 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 744 * inner-most L4 payload, so inclusive of 745 * inner-most L4 header. 746 * @mss: Desired MSS value for TSO; only applicable for 747 * IONIC_TXQ_DESC_OPCODE_TSO 748 * @csum_start: Offset from packet to first byte checked in L4 checksum 749 * @csum_offset: Offset from csum_start to L4 checksum field 750 */ 751 struct ionic_txq_desc { 752 __le64 cmd; 753 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 754 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 755 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 756 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 757 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 758 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 759 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 760 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 761 762 /* common flags */ 763 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 764 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 765 766 /* flags for csum_hw opcode */ 767 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 768 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 769 770 /* flags for tso opcode */ 771 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 772 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 773 774 __le16 len; 775 union { 776 __le16 vlan_tci; 777 __le16 hword0; 778 }; 779 union { 780 __le16 csum_start; 781 __le16 hdr_len; 782 __le16 hword1; 783 }; 784 union { 785 __le16 csum_offset; 786 __le16 mss; 787 __le16 hword2; 788 }; 789 }; 790 791 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 792 u8 nsge, u64 addr) 793 { 794 u64 cmd; 795 796 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 797 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 798 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 799 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 800 801 return cmd; 802 }; 803 804 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 805 u8 *nsge, u64 *addr) 806 { 807 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 808 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 809 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 810 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 811 }; 812 813 /** 814 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 815 * @addr: DMA address of SG element data buffer 816 * @len: Length of SG element data buffer, in bytes 817 */ 818 struct ionic_txq_sg_elem { 819 __le64 addr; 820 __le16 len; 821 __le16 rsvd[3]; 822 }; 823 824 /** 825 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 826 * @elems: Scatter-gather elements 827 */ 828 struct ionic_txq_sg_desc { 829 #define IONIC_TX_MAX_SG_ELEMS 8 830 #define IONIC_TX_SG_DESC_STRIDE 8 831 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 832 }; 833 834 struct ionic_txq_sg_desc_v1 { 835 #define IONIC_TX_MAX_SG_ELEMS_V1 15 836 #define IONIC_TX_SG_DESC_STRIDE_V1 16 837 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 838 }; 839 840 /** 841 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 842 * @status: Status of the command (enum ionic_status_code) 843 * @comp_index: Index in the descriptor ring for which this is the completion 844 * @color: Color bit 845 */ 846 struct ionic_txq_comp { 847 u8 status; 848 u8 rsvd; 849 __le16 comp_index; 850 u8 rsvd2[11]; 851 u8 color; 852 }; 853 854 enum ionic_rxq_desc_opcode { 855 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 856 IONIC_RXQ_DESC_OPCODE_SG = 1, 857 }; 858 859 /** 860 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 861 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 862 * 863 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 864 * Receive full packet into data buffer 865 * starting at @addr. Results of 866 * receive, including actual bytes received, 867 * are recorded in Rx completion descriptor. 868 * 869 * @len: Data buffer's length, in bytes 870 * @addr: Data buffer's DMA address 871 */ 872 struct ionic_rxq_desc { 873 u8 opcode; 874 u8 rsvd[5]; 875 __le16 len; 876 __le64 addr; 877 }; 878 879 /** 880 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 881 * @addr: DMA address of SG element data buffer 882 * @len: Length of SG element data buffer, in bytes 883 */ 884 struct ionic_rxq_sg_elem { 885 __le64 addr; 886 __le16 len; 887 __le16 rsvd[3]; 888 }; 889 890 /** 891 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 892 * @elems: Scatter-gather elements 893 */ 894 struct ionic_rxq_sg_desc { 895 #define IONIC_RX_MAX_SG_ELEMS 8 896 #define IONIC_RX_SG_DESC_STRIDE 8 897 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 898 }; 899 900 /** 901 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 902 * @status: Status of the command (enum ionic_status_code) 903 * @num_sg_elems: Number of SG elements used by this descriptor 904 * @comp_index: Index in the descriptor ring for which this is the completion 905 * @rss_hash: 32-bit RSS hash 906 * @csum: 16-bit sum of the packet's L2 payload 907 * If the packet's L2 payload is odd length, an extra 908 * zero-value byte is included in the @csum calculation but 909 * not included in @len. 910 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 911 * set. Includes .1p and .1q tags. 912 * @len: Received packet length, in bytes. Excludes FCS. 913 * @csum_calc L2 payload checksum is computed or not 914 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 915 * 916 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 917 * The TCP checksum calculated by the device 918 * matched the checksum in the receive packet's 919 * TCP header. 920 * 921 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 922 * The TCP checksum calculated by the device did 923 * not match the checksum in the receive packet's 924 * TCP header. 925 * 926 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 927 * The UDP checksum calculated by the device 928 * matched the checksum in the receive packet's 929 * UDP header 930 * 931 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 932 * The UDP checksum calculated by the device did 933 * not match the checksum in the receive packet's 934 * UDP header. 935 * 936 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 937 * The IPv4 checksum calculated by the device 938 * matched the checksum in the receive packet's 939 * first IPv4 header. If the receive packet 940 * contains both a tunnel IPv4 header and a 941 * transport IPv4 header, the device validates the 942 * checksum for the both IPv4 headers. 943 * 944 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 945 * The IPv4 checksum calculated by the device did 946 * not match the checksum in the receive packet's 947 * first IPv4 header. If the receive packet 948 * contains both a tunnel IPv4 header and a 949 * transport IPv4 header, the device validates the 950 * checksum for both IP headers. 951 * 952 * IONIC_RXQ_COMP_CSUM_F_VLAN: 953 * The VLAN header was stripped and placed in @vlan_tci. 954 * 955 * IONIC_RXQ_COMP_CSUM_F_CALC: 956 * The checksum was calculated by the device. 957 * 958 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 959 */ 960 struct ionic_rxq_comp { 961 u8 status; 962 u8 num_sg_elems; 963 __le16 comp_index; 964 __le32 rss_hash; 965 __le16 csum; 966 __le16 vlan_tci; 967 __le16 len; 968 u8 csum_flags; 969 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 970 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 971 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 972 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 973 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 974 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 975 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 976 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 977 u8 pkt_type_color; 978 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 979 }; 980 981 enum ionic_pkt_type { 982 IONIC_PKT_TYPE_NON_IP = 0x000, 983 IONIC_PKT_TYPE_IPV4 = 0x001, 984 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 985 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 986 IONIC_PKT_TYPE_IPV6 = 0x008, 987 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 988 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 989 /* below types are only used if encap offloads are enabled on lif */ 990 IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 991 IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 992 IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 993 IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 994 IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 995 IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 996 IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 997 }; 998 999 enum ionic_eth_hw_features { 1000 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1001 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1002 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1003 IONIC_ETH_HW_RX_HASH = BIT(3), 1004 IONIC_ETH_HW_RX_CSUM = BIT(4), 1005 IONIC_ETH_HW_TX_SG = BIT(5), 1006 IONIC_ETH_HW_RX_SG = BIT(6), 1007 IONIC_ETH_HW_TX_CSUM = BIT(7), 1008 IONIC_ETH_HW_TSO = BIT(8), 1009 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1010 IONIC_ETH_HW_TSO_ECN = BIT(10), 1011 IONIC_ETH_HW_TSO_GRE = BIT(11), 1012 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1013 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1014 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1015 IONIC_ETH_HW_TSO_UDP = BIT(15), 1016 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1017 IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 1018 IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 1019 IONIC_ETH_HW_TSO_GENEVE = BIT(19) 1020 }; 1021 1022 /** 1023 * struct ionic_q_control_cmd - Queue control command 1024 * @opcode: opcode 1025 * @type: Queue type 1026 * @lif_index: LIF index 1027 * @index: Queue index 1028 * @oper: Operation (enum ionic_q_control_oper) 1029 */ 1030 struct ionic_q_control_cmd { 1031 u8 opcode; 1032 u8 type; 1033 __le16 lif_index; 1034 __le32 index; 1035 u8 oper; 1036 u8 rsvd[55]; 1037 }; 1038 1039 typedef struct ionic_admin_comp ionic_q_control_comp; 1040 1041 enum q_control_oper { 1042 IONIC_Q_DISABLE = 0, 1043 IONIC_Q_ENABLE = 1, 1044 IONIC_Q_HANG_RESET = 2, 1045 }; 1046 1047 /** 1048 * enum ionic_phy_type - Physical connection type 1049 * @IONIC_PHY_TYPE_NONE: No PHY installed 1050 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1051 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1052 */ 1053 enum ionic_phy_type { 1054 IONIC_PHY_TYPE_NONE = 0, 1055 IONIC_PHY_TYPE_COPPER = 1, 1056 IONIC_PHY_TYPE_FIBER = 2, 1057 }; 1058 1059 /** 1060 * enum ionic_xcvr_state - Transceiver status 1061 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1062 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1063 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1064 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1065 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1066 */ 1067 enum ionic_xcvr_state { 1068 IONIC_XCVR_STATE_REMOVED = 0, 1069 IONIC_XCVR_STATE_INSERTED = 1, 1070 IONIC_XCVR_STATE_PENDING = 2, 1071 IONIC_XCVR_STATE_SPROM_READ = 3, 1072 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1073 }; 1074 1075 /** 1076 * enum ionic_xcvr_pid - Supported link modes 1077 */ 1078 enum ionic_xcvr_pid { 1079 IONIC_XCVR_PID_UNKNOWN = 0, 1080 1081 /* CU */ 1082 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1083 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1084 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1085 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1086 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1087 1088 /* Fiber */ 1089 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1090 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1091 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1092 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1093 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1094 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1095 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1096 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1097 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1098 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1099 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1100 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1101 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1102 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1103 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1104 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1105 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1106 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1107 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1108 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1109 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1110 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1111 }; 1112 1113 /** 1114 * enum ionic_port_type - Port types 1115 * @IONIC_PORT_TYPE_NONE: Port type not configured 1116 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1117 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1118 */ 1119 enum ionic_port_type { 1120 IONIC_PORT_TYPE_NONE = 0, 1121 IONIC_PORT_TYPE_ETH = 1, 1122 IONIC_PORT_TYPE_MGMT = 2, 1123 }; 1124 1125 /** 1126 * enum ionic_port_admin_state - Port config state 1127 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1128 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1129 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1130 */ 1131 enum ionic_port_admin_state { 1132 IONIC_PORT_ADMIN_STATE_NONE = 0, 1133 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1134 IONIC_PORT_ADMIN_STATE_UP = 2, 1135 }; 1136 1137 /** 1138 * enum ionic_port_oper_status - Port operational status 1139 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1140 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1141 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1142 */ 1143 enum ionic_port_oper_status { 1144 IONIC_PORT_OPER_STATUS_NONE = 0, 1145 IONIC_PORT_OPER_STATUS_UP = 1, 1146 IONIC_PORT_OPER_STATUS_DOWN = 2, 1147 }; 1148 1149 /** 1150 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1151 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1152 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1153 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1154 */ 1155 enum ionic_port_fec_type { 1156 IONIC_PORT_FEC_TYPE_NONE = 0, 1157 IONIC_PORT_FEC_TYPE_FC = 1, 1158 IONIC_PORT_FEC_TYPE_RS = 2, 1159 }; 1160 1161 /** 1162 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1163 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1164 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1165 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1166 */ 1167 enum ionic_port_pause_type { 1168 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1169 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1170 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1171 }; 1172 1173 /** 1174 * enum ionic_port_loopback_mode - Loopback modes 1175 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1176 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1177 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1178 */ 1179 enum ionic_port_loopback_mode { 1180 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1181 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1182 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1183 }; 1184 1185 /** 1186 * struct ionic_xcvr_status - Transceiver Status information 1187 * @state: Transceiver status (enum ionic_xcvr_state) 1188 * @phy: Physical connection type (enum ionic_phy_type) 1189 * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1190 * @sprom: Transceiver sprom contents 1191 */ 1192 struct ionic_xcvr_status { 1193 u8 state; 1194 u8 phy; 1195 __le16 pid; 1196 u8 sprom[256]; 1197 }; 1198 1199 /** 1200 * union ionic_port_config - Port configuration 1201 * @speed: port speed (in Mbps) 1202 * @mtu: mtu 1203 * @state: port admin state (enum ionic_port_admin_state) 1204 * @an_enable: autoneg enable 1205 * @fec_type: fec type (enum ionic_port_fec_type) 1206 * @pause_type: pause type (enum ionic_port_pause_type) 1207 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1208 */ 1209 union ionic_port_config { 1210 struct { 1211 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1212 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1213 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1214 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1215 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1216 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1217 __le32 speed; 1218 __le32 mtu; 1219 u8 state; 1220 u8 an_enable; 1221 u8 fec_type; 1222 #define IONIC_PAUSE_TYPE_MASK 0x0f 1223 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1224 #define IONIC_PAUSE_F_TX 0x10 1225 #define IONIC_PAUSE_F_RX 0x20 1226 u8 pause_type; 1227 u8 loopback_mode; 1228 }; 1229 __le32 words[64]; 1230 }; 1231 1232 /** 1233 * struct ionic_port_status - Port Status information 1234 * @status: link status (enum ionic_port_oper_status) 1235 * @id: port id 1236 * @speed: link speed (in Mbps) 1237 * @link_down_count: number of times link went from from up to down 1238 * @fec_type: fec type (enum ionic_port_fec_type) 1239 * @xcvr: tranceiver status 1240 */ 1241 struct ionic_port_status { 1242 __le32 id; 1243 __le32 speed; 1244 u8 status; 1245 __le16 link_down_count; 1246 u8 fec_type; 1247 u8 rsvd[48]; 1248 struct ionic_xcvr_status xcvr; 1249 } __packed; 1250 1251 /** 1252 * struct ionic_port_identify_cmd - Port identify command 1253 * @opcode: opcode 1254 * @index: port index 1255 * @ver: Highest version of identify supported by driver 1256 */ 1257 struct ionic_port_identify_cmd { 1258 u8 opcode; 1259 u8 index; 1260 u8 ver; 1261 u8 rsvd[61]; 1262 }; 1263 1264 /** 1265 * struct ionic_port_identify_comp - Port identify command completion 1266 * @status: Status of the command (enum ionic_status_code) 1267 * @ver: Version of identify returned by device 1268 */ 1269 struct ionic_port_identify_comp { 1270 u8 status; 1271 u8 ver; 1272 u8 rsvd[14]; 1273 }; 1274 1275 /** 1276 * struct ionic_port_init_cmd - Port initialization command 1277 * @opcode: opcode 1278 * @index: port index 1279 * @info_pa: destination address for port info (struct ionic_port_info) 1280 */ 1281 struct ionic_port_init_cmd { 1282 u8 opcode; 1283 u8 index; 1284 u8 rsvd[6]; 1285 __le64 info_pa; 1286 u8 rsvd2[48]; 1287 }; 1288 1289 /** 1290 * struct ionic_port_init_comp - Port initialization command completion 1291 * @status: Status of the command (enum ionic_status_code) 1292 */ 1293 struct ionic_port_init_comp { 1294 u8 status; 1295 u8 rsvd[15]; 1296 }; 1297 1298 /** 1299 * struct ionic_port_reset_cmd - Port reset command 1300 * @opcode: opcode 1301 * @index: port index 1302 */ 1303 struct ionic_port_reset_cmd { 1304 u8 opcode; 1305 u8 index; 1306 u8 rsvd[62]; 1307 }; 1308 1309 /** 1310 * struct ionic_port_reset_comp - Port reset command completion 1311 * @status: Status of the command (enum ionic_status_code) 1312 */ 1313 struct ionic_port_reset_comp { 1314 u8 status; 1315 u8 rsvd[15]; 1316 }; 1317 1318 /** 1319 * enum ionic_stats_ctl_cmd - List of commands for stats control 1320 * @IONIC_STATS_CTL_RESET: Reset statistics 1321 */ 1322 enum ionic_stats_ctl_cmd { 1323 IONIC_STATS_CTL_RESET = 0, 1324 }; 1325 1326 /** 1327 * enum ionic_port_attr - List of device attributes 1328 * @IONIC_PORT_ATTR_STATE: Port state attribute 1329 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1330 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1331 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute 1332 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1333 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1334 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1335 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1336 */ 1337 enum ionic_port_attr { 1338 IONIC_PORT_ATTR_STATE = 0, 1339 IONIC_PORT_ATTR_SPEED = 1, 1340 IONIC_PORT_ATTR_MTU = 2, 1341 IONIC_PORT_ATTR_AUTONEG = 3, 1342 IONIC_PORT_ATTR_FEC = 4, 1343 IONIC_PORT_ATTR_PAUSE = 5, 1344 IONIC_PORT_ATTR_LOOPBACK = 6, 1345 IONIC_PORT_ATTR_STATS_CTRL = 7, 1346 }; 1347 1348 /** 1349 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1350 * @opcode: Opcode 1351 * @index: Port index 1352 * @attr: Attribute type (enum ionic_port_attr) 1353 * @state: Port state 1354 * @speed: Port speed 1355 * @mtu: Port MTU 1356 * @an_enable: Port autonegotiation setting 1357 * @fec_type: Port FEC type setting 1358 * @pause_type: Port pause type setting 1359 * @loopback_mode: Port loopback mode 1360 * @stats_ctl: Port stats setting 1361 */ 1362 struct ionic_port_setattr_cmd { 1363 u8 opcode; 1364 u8 index; 1365 u8 attr; 1366 u8 rsvd; 1367 union { 1368 u8 state; 1369 __le32 speed; 1370 __le32 mtu; 1371 u8 an_enable; 1372 u8 fec_type; 1373 u8 pause_type; 1374 u8 loopback_mode; 1375 u8 stats_ctl; 1376 u8 rsvd2[60]; 1377 }; 1378 }; 1379 1380 /** 1381 * struct ionic_port_setattr_comp - Port set attr command completion 1382 * @status: Status of the command (enum ionic_status_code) 1383 * @color: Color bit 1384 */ 1385 struct ionic_port_setattr_comp { 1386 u8 status; 1387 u8 rsvd[14]; 1388 u8 color; 1389 }; 1390 1391 /** 1392 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1393 * @opcode: Opcode 1394 * @index: port index 1395 * @attr: Attribute type (enum ionic_port_attr) 1396 */ 1397 struct ionic_port_getattr_cmd { 1398 u8 opcode; 1399 u8 index; 1400 u8 attr; 1401 u8 rsvd[61]; 1402 }; 1403 1404 /** 1405 * struct ionic_port_getattr_comp - Port get attr command completion 1406 * @status: Status of the command (enum ionic_status_code) 1407 * @state: Port state 1408 * @speed: Port speed 1409 * @mtu: Port MTU 1410 * @an_enable: Port autonegotiation setting 1411 * @fec_type: Port FEC type setting 1412 * @pause_type: Port pause type setting 1413 * @loopback_mode: Port loopback mode 1414 * @color: Color bit 1415 */ 1416 struct ionic_port_getattr_comp { 1417 u8 status; 1418 u8 rsvd[3]; 1419 union { 1420 u8 state; 1421 __le32 speed; 1422 __le32 mtu; 1423 u8 an_enable; 1424 u8 fec_type; 1425 u8 pause_type; 1426 u8 loopback_mode; 1427 u8 rsvd2[11]; 1428 } __packed; 1429 u8 color; 1430 }; 1431 1432 /** 1433 * struct ionic_lif_status - LIF status register 1434 * @eid: most recent NotifyQ event id 1435 * @port_num: port the LIF is connected to 1436 * @link_status: port status (enum ionic_port_oper_status) 1437 * @link_speed: speed of link in Mbps 1438 * @link_down_count: number of times link went from up to down 1439 */ 1440 struct ionic_lif_status { 1441 __le64 eid; 1442 u8 port_num; 1443 u8 rsvd; 1444 __le16 link_status; 1445 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1446 __le16 link_down_count; 1447 u8 rsvd2[46]; 1448 }; 1449 1450 /** 1451 * struct ionic_lif_reset_cmd - LIF reset command 1452 * @opcode: opcode 1453 * @index: LIF index 1454 */ 1455 struct ionic_lif_reset_cmd { 1456 u8 opcode; 1457 u8 rsvd; 1458 __le16 index; 1459 __le32 rsvd2[15]; 1460 }; 1461 1462 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1463 1464 enum ionic_dev_state { 1465 IONIC_DEV_DISABLE = 0, 1466 IONIC_DEV_ENABLE = 1, 1467 IONIC_DEV_HANG_RESET = 2, 1468 }; 1469 1470 /** 1471 * enum ionic_dev_attr - List of device attributes 1472 * @IONIC_DEV_ATTR_STATE: Device state attribute 1473 * @IONIC_DEV_ATTR_NAME: Device name attribute 1474 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1475 */ 1476 enum ionic_dev_attr { 1477 IONIC_DEV_ATTR_STATE = 0, 1478 IONIC_DEV_ATTR_NAME = 1, 1479 IONIC_DEV_ATTR_FEATURES = 2, 1480 }; 1481 1482 /** 1483 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1484 * @opcode: Opcode 1485 * @attr: Attribute type (enum ionic_dev_attr) 1486 * @state: Device state (enum ionic_dev_state) 1487 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1488 * @features: Device features 1489 */ 1490 struct ionic_dev_setattr_cmd { 1491 u8 opcode; 1492 u8 attr; 1493 __le16 rsvd; 1494 union { 1495 u8 state; 1496 char name[IONIC_IFNAMSIZ]; 1497 __le64 features; 1498 u8 rsvd2[60]; 1499 } __packed; 1500 }; 1501 1502 /** 1503 * struct ionic_dev_setattr_comp - Device set attr command completion 1504 * @status: Status of the command (enum ionic_status_code) 1505 * @features: Device features 1506 * @color: Color bit 1507 */ 1508 struct ionic_dev_setattr_comp { 1509 u8 status; 1510 u8 rsvd[3]; 1511 union { 1512 __le64 features; 1513 u8 rsvd2[11]; 1514 } __packed; 1515 u8 color; 1516 }; 1517 1518 /** 1519 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1520 * @opcode: opcode 1521 * @attr: Attribute type (enum ionic_dev_attr) 1522 */ 1523 struct ionic_dev_getattr_cmd { 1524 u8 opcode; 1525 u8 attr; 1526 u8 rsvd[62]; 1527 }; 1528 1529 /** 1530 * struct ionic_dev_setattr_comp - Device set attr command completion 1531 * @status: Status of the command (enum ionic_status_code) 1532 * @features: Device features 1533 * @color: Color bit 1534 */ 1535 struct ionic_dev_getattr_comp { 1536 u8 status; 1537 u8 rsvd[3]; 1538 union { 1539 __le64 features; 1540 u8 rsvd2[11]; 1541 } __packed; 1542 u8 color; 1543 }; 1544 1545 /** 1546 * RSS parameters 1547 */ 1548 #define IONIC_RSS_HASH_KEY_SIZE 40 1549 1550 enum ionic_rss_hash_types { 1551 IONIC_RSS_TYPE_IPV4 = BIT(0), 1552 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1553 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1554 IONIC_RSS_TYPE_IPV6 = BIT(3), 1555 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1556 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1557 }; 1558 1559 /** 1560 * enum ionic_lif_attr - List of LIF attributes 1561 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1562 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1563 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1564 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1565 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1566 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1567 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1568 */ 1569 enum ionic_lif_attr { 1570 IONIC_LIF_ATTR_STATE = 0, 1571 IONIC_LIF_ATTR_NAME = 1, 1572 IONIC_LIF_ATTR_MTU = 2, 1573 IONIC_LIF_ATTR_MAC = 3, 1574 IONIC_LIF_ATTR_FEATURES = 4, 1575 IONIC_LIF_ATTR_RSS = 5, 1576 IONIC_LIF_ATTR_STATS_CTRL = 6, 1577 }; 1578 1579 /** 1580 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1581 * @opcode: Opcode 1582 * @attr: Attribute type (enum ionic_lif_attr) 1583 * @index: LIF index 1584 * @state: LIF state (enum ionic_lif_state) 1585 * @name: The netdev name string, 0 terminated 1586 * @mtu: Mtu 1587 * @mac: Station mac 1588 * @features: Features (enum ionic_eth_hw_features) 1589 * @rss: RSS properties 1590 * @types: The hash types to enable (see rss_hash_types) 1591 * @key: The hash secret key 1592 * @addr: Address for the indirection table shared memory 1593 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1594 */ 1595 struct ionic_lif_setattr_cmd { 1596 u8 opcode; 1597 u8 attr; 1598 __le16 index; 1599 union { 1600 u8 state; 1601 char name[IONIC_IFNAMSIZ]; 1602 __le32 mtu; 1603 u8 mac[6]; 1604 __le64 features; 1605 struct { 1606 __le16 types; 1607 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1608 u8 rsvd[6]; 1609 __le64 addr; 1610 } rss; 1611 u8 stats_ctl; 1612 u8 rsvd[60]; 1613 } __packed; 1614 }; 1615 1616 /** 1617 * struct ionic_lif_setattr_comp - LIF set attr command completion 1618 * @status: Status of the command (enum ionic_status_code) 1619 * @comp_index: Index in the descriptor ring for which this is the completion 1620 * @features: features (enum ionic_eth_hw_features) 1621 * @color: Color bit 1622 */ 1623 struct ionic_lif_setattr_comp { 1624 u8 status; 1625 u8 rsvd; 1626 __le16 comp_index; 1627 union { 1628 __le64 features; 1629 u8 rsvd2[11]; 1630 } __packed; 1631 u8 color; 1632 }; 1633 1634 /** 1635 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1636 * @opcode: Opcode 1637 * @attr: Attribute type (enum ionic_lif_attr) 1638 * @index: LIF index 1639 */ 1640 struct ionic_lif_getattr_cmd { 1641 u8 opcode; 1642 u8 attr; 1643 __le16 index; 1644 u8 rsvd[60]; 1645 }; 1646 1647 /** 1648 * struct ionic_lif_getattr_comp - LIF get attr command completion 1649 * @status: Status of the command (enum ionic_status_code) 1650 * @comp_index: Index in the descriptor ring for which this is the completion 1651 * @state: LIF state (enum ionic_lif_state) 1652 * @name: The netdev name string, 0 terminated 1653 * @mtu: Mtu 1654 * @mac: Station mac 1655 * @features: Features (enum ionic_eth_hw_features) 1656 * @color: Color bit 1657 */ 1658 struct ionic_lif_getattr_comp { 1659 u8 status; 1660 u8 rsvd; 1661 __le16 comp_index; 1662 union { 1663 u8 state; 1664 __le32 mtu; 1665 u8 mac[6]; 1666 __le64 features; 1667 u8 rsvd2[11]; 1668 } __packed; 1669 u8 color; 1670 }; 1671 1672 enum ionic_rx_mode { 1673 IONIC_RX_MODE_F_UNICAST = BIT(0), 1674 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1675 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1676 IONIC_RX_MODE_F_PROMISC = BIT(3), 1677 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1678 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1679 }; 1680 1681 /** 1682 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1683 * @opcode: opcode 1684 * @lif_index: LIF index 1685 * @rx_mode: Rx mode flags: 1686 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1687 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1688 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1689 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1690 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1691 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1692 */ 1693 struct ionic_rx_mode_set_cmd { 1694 u8 opcode; 1695 u8 rsvd; 1696 __le16 lif_index; 1697 __le16 rx_mode; 1698 __le16 rsvd2[29]; 1699 }; 1700 1701 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1702 1703 enum ionic_rx_filter_match_type { 1704 IONIC_RX_FILTER_MATCH_VLAN = 0, 1705 IONIC_RX_FILTER_MATCH_MAC, 1706 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1707 }; 1708 1709 /** 1710 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1711 * @opcode: opcode 1712 * @qtype: Queue type 1713 * @lif_index: LIF index 1714 * @qid: Queue ID 1715 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1716 * @vlan: VLAN filter 1717 * @vlan: VLAN ID 1718 * @mac: MAC filter 1719 * @addr: MAC address (network-byte order) 1720 * @mac_vlan: MACVLAN filter 1721 * @vlan: VLAN ID 1722 * @addr: MAC address (network-byte order) 1723 */ 1724 struct ionic_rx_filter_add_cmd { 1725 u8 opcode; 1726 u8 qtype; 1727 __le16 lif_index; 1728 __le32 qid; 1729 __le16 match; 1730 union { 1731 struct { 1732 __le16 vlan; 1733 } vlan; 1734 struct { 1735 u8 addr[6]; 1736 } mac; 1737 struct { 1738 __le16 vlan; 1739 u8 addr[6]; 1740 } mac_vlan; 1741 u8 rsvd[54]; 1742 }; 1743 }; 1744 1745 /** 1746 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1747 * @status: Status of the command (enum ionic_status_code) 1748 * @comp_index: Index in the descriptor ring for which this is the completion 1749 * @filter_id: Filter ID 1750 * @color: Color bit 1751 */ 1752 struct ionic_rx_filter_add_comp { 1753 u8 status; 1754 u8 rsvd; 1755 __le16 comp_index; 1756 __le32 filter_id; 1757 u8 rsvd2[7]; 1758 u8 color; 1759 }; 1760 1761 /** 1762 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1763 * @opcode: opcode 1764 * @lif_index: LIF index 1765 * @filter_id: Filter ID 1766 */ 1767 struct ionic_rx_filter_del_cmd { 1768 u8 opcode; 1769 u8 rsvd; 1770 __le16 lif_index; 1771 __le32 filter_id; 1772 u8 rsvd2[56]; 1773 }; 1774 1775 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1776 1777 enum ionic_vf_attr { 1778 IONIC_VF_ATTR_SPOOFCHK = 1, 1779 IONIC_VF_ATTR_TRUST = 2, 1780 IONIC_VF_ATTR_MAC = 3, 1781 IONIC_VF_ATTR_LINKSTATE = 4, 1782 IONIC_VF_ATTR_VLAN = 5, 1783 IONIC_VF_ATTR_RATE = 6, 1784 IONIC_VF_ATTR_STATSADDR = 7, 1785 }; 1786 1787 /** 1788 * enum ionic_vf_link_status - Virtual Function link status 1789 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1790 * @IONIC_VF_LINK_STATUS_UP: Link always up 1791 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 1792 */ 1793 enum ionic_vf_link_status { 1794 IONIC_VF_LINK_STATUS_AUTO = 0, 1795 IONIC_VF_LINK_STATUS_UP = 1, 1796 IONIC_VF_LINK_STATUS_DOWN = 2, 1797 }; 1798 1799 /** 1800 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1801 * @opcode: Opcode 1802 * @attr: Attribute type (enum ionic_vf_attr) 1803 * @vf_index: VF index 1804 * @macaddr: mac address 1805 * @vlanid: vlan ID 1806 * @maxrate: max Tx rate in Mbps 1807 * @spoofchk: enable address spoof checking 1808 * @trust: enable VF trust 1809 * @linkstate: set link up or down 1810 * @stats_pa: set DMA address for VF stats 1811 */ 1812 struct ionic_vf_setattr_cmd { 1813 u8 opcode; 1814 u8 attr; 1815 __le16 vf_index; 1816 union { 1817 u8 macaddr[6]; 1818 __le16 vlanid; 1819 __le32 maxrate; 1820 u8 spoofchk; 1821 u8 trust; 1822 u8 linkstate; 1823 __le64 stats_pa; 1824 u8 pad[60]; 1825 } __packed; 1826 }; 1827 1828 struct ionic_vf_setattr_comp { 1829 u8 status; 1830 u8 attr; 1831 __le16 vf_index; 1832 __le16 comp_index; 1833 u8 rsvd[9]; 1834 u8 color; 1835 }; 1836 1837 /** 1838 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 1839 * @opcode: Opcode 1840 * @attr: Attribute type (enum ionic_vf_attr) 1841 * @vf_index: VF index 1842 */ 1843 struct ionic_vf_getattr_cmd { 1844 u8 opcode; 1845 u8 attr; 1846 __le16 vf_index; 1847 u8 rsvd[60]; 1848 }; 1849 1850 struct ionic_vf_getattr_comp { 1851 u8 status; 1852 u8 attr; 1853 __le16 vf_index; 1854 union { 1855 u8 macaddr[6]; 1856 __le16 vlanid; 1857 __le32 maxrate; 1858 u8 spoofchk; 1859 u8 trust; 1860 u8 linkstate; 1861 __le64 stats_pa; 1862 u8 pad[11]; 1863 } __packed; 1864 u8 color; 1865 }; 1866 1867 /** 1868 * struct ionic_qos_identify_cmd - QoS identify command 1869 * @opcode: opcode 1870 * @ver: Highest version of identify supported by driver 1871 * 1872 */ 1873 struct ionic_qos_identify_cmd { 1874 u8 opcode; 1875 u8 ver; 1876 u8 rsvd[62]; 1877 }; 1878 1879 /** 1880 * struct ionic_qos_identify_comp - QoS identify command completion 1881 * @status: Status of the command (enum ionic_status_code) 1882 * @ver: Version of identify returned by device 1883 */ 1884 struct ionic_qos_identify_comp { 1885 u8 status; 1886 u8 ver; 1887 u8 rsvd[14]; 1888 }; 1889 1890 #define IONIC_QOS_TC_MAX 8 1891 #define IONIC_QOS_ALL_TC 0xFF 1892 /* Capri max supported, should be renamed. */ 1893 #define IONIC_QOS_CLASS_MAX 7 1894 #define IONIC_QOS_PCP_MAX 8 1895 #define IONIC_QOS_CLASS_NAME_SZ 32 1896 #define IONIC_QOS_DSCP_MAX 64 1897 #define IONIC_QOS_ALL_PCP 0xFF 1898 #define IONIC_DSCP_BLOCK_SIZE 8 1899 1900 /** 1901 * enum ionic_qos_class 1902 */ 1903 enum ionic_qos_class { 1904 IONIC_QOS_CLASS_DEFAULT = 0, 1905 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1906 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1907 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1908 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1909 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1910 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1911 }; 1912 1913 /** 1914 * enum ionic_qos_class_type - Traffic classification criteria 1915 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 1916 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 1917 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 1918 */ 1919 enum ionic_qos_class_type { 1920 IONIC_QOS_CLASS_TYPE_NONE = 0, 1921 IONIC_QOS_CLASS_TYPE_PCP = 1, 1922 IONIC_QOS_CLASS_TYPE_DSCP = 2, 1923 }; 1924 1925 /** 1926 * enum ionic_qos_sched_type - QoS class scheduling type 1927 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 1928 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 1929 */ 1930 enum ionic_qos_sched_type { 1931 IONIC_QOS_SCHED_TYPE_STRICT = 0, 1932 IONIC_QOS_SCHED_TYPE_DWRR = 1, 1933 }; 1934 1935 /** 1936 * union ionic_qos_config - QoS configuration structure 1937 * @flags: Configuration flags 1938 * IONIC_QOS_CONFIG_F_ENABLE enable 1939 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 1940 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1941 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1942 * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 1943 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 1944 * @class_type: QoS class type (enum ionic_qos_class_type) 1945 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 1946 * @name: QoS class name 1947 * @mtu: MTU of the class 1948 * @pfc_cos: Priority-Flow Control class of service 1949 * @dwrr_weight: QoS class scheduling weight 1950 * @strict_rlmt: Rate limit for strict priority scheduling 1951 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) 1952 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) 1953 * @dot1q_pcp: Dot1q pcp value 1954 * @ndscp: Number of valid dscp values in the ip_dscp field 1955 * @ip_dscp: IP dscp values 1956 */ 1957 union ionic_qos_config { 1958 struct { 1959 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1960 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 1961 /* Used to rewrite PCP or DSCP value. */ 1962 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1963 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1964 /* Non-disruptive TC update */ 1965 #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 1966 u8 flags; 1967 u8 sched_type; 1968 u8 class_type; 1969 u8 pause_type; 1970 char name[IONIC_QOS_CLASS_NAME_SZ]; 1971 __le32 mtu; 1972 /* flow control */ 1973 u8 pfc_cos; 1974 /* scheduler */ 1975 union { 1976 u8 dwrr_weight; 1977 __le64 strict_rlmt; 1978 }; 1979 /* marking */ 1980 /* Used to rewrite PCP or DSCP value. */ 1981 union { 1982 u8 rw_dot1q_pcp; 1983 u8 rw_ip_dscp; 1984 }; 1985 /* classification */ 1986 union { 1987 u8 dot1q_pcp; 1988 struct { 1989 u8 ndscp; 1990 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 1991 }; 1992 }; 1993 }; 1994 __le32 words[64]; 1995 }; 1996 1997 /** 1998 * union ionic_qos_identity - QoS identity structure 1999 * @version: Version of the identify structure 2000 * @type: QoS system type 2001 * @nclasses: Number of usable QoS classes 2002 * @config: Current configuration of classes 2003 */ 2004 union ionic_qos_identity { 2005 struct { 2006 u8 version; 2007 u8 type; 2008 u8 rsvd[62]; 2009 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2010 }; 2011 __le32 words[478]; 2012 }; 2013 2014 /** 2015 * struct ionic_qos_init_cmd - QoS config init command 2016 * @opcode: Opcode 2017 * @group: QoS class id 2018 * @info_pa: destination address for qos info 2019 */ 2020 struct ionic_qos_init_cmd { 2021 u8 opcode; 2022 u8 group; 2023 u8 rsvd[6]; 2024 __le64 info_pa; 2025 u8 rsvd1[48]; 2026 }; 2027 2028 typedef struct ionic_admin_comp ionic_qos_init_comp; 2029 2030 /** 2031 * struct ionic_qos_reset_cmd - QoS config reset command 2032 * @opcode: Opcode 2033 * @group: QoS class id 2034 */ 2035 struct ionic_qos_reset_cmd { 2036 u8 opcode; 2037 u8 group; 2038 u8 rsvd[62]; 2039 }; 2040 2041 /** 2042 * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 2043 * @opcode: Opcode 2044 */ 2045 struct ionic_qos_clear_stats_cmd { 2046 u8 opcode; 2047 u8 group_bitmap; 2048 u8 rsvd[62]; 2049 }; 2050 2051 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2052 2053 /** 2054 * struct ionic_fw_download_cmd - Firmware download command 2055 * @opcode: opcode 2056 * @addr: dma address of the firmware buffer 2057 * @offset: offset of the firmware buffer within the full image 2058 * @length: number of valid bytes in the firmware buffer 2059 */ 2060 struct ionic_fw_download_cmd { 2061 u8 opcode; 2062 u8 rsvd[3]; 2063 __le32 offset; 2064 __le64 addr; 2065 __le32 length; 2066 }; 2067 2068 typedef struct ionic_admin_comp ionic_fw_download_comp; 2069 2070 /** 2071 * enum ionic_fw_control_oper - FW control operations 2072 * @IONIC_FW_RESET: Reset firmware 2073 * @IONIC_FW_INSTALL: Install firmware 2074 * @IONIC_FW_ACTIVATE: Activate firmware 2075 */ 2076 enum ionic_fw_control_oper { 2077 IONIC_FW_RESET = 0, 2078 IONIC_FW_INSTALL = 1, 2079 IONIC_FW_ACTIVATE = 2, 2080 }; 2081 2082 /** 2083 * struct ionic_fw_control_cmd - Firmware control command 2084 * @opcode: opcode 2085 * @oper: firmware control operation (enum ionic_fw_control_oper) 2086 * @slot: slot to activate 2087 */ 2088 struct ionic_fw_control_cmd { 2089 u8 opcode; 2090 u8 rsvd[3]; 2091 u8 oper; 2092 u8 slot; 2093 u8 rsvd1[58]; 2094 }; 2095 2096 /** 2097 * struct ionic_fw_control_comp - Firmware control copletion 2098 * @status: Status of the command (enum ionic_status_code) 2099 * @comp_index: Index in the descriptor ring for which this is the completion 2100 * @slot: Slot where the firmware was installed 2101 * @color: Color bit 2102 */ 2103 struct ionic_fw_control_comp { 2104 u8 status; 2105 u8 rsvd; 2106 __le16 comp_index; 2107 u8 slot; 2108 u8 rsvd1[10]; 2109 u8 color; 2110 }; 2111 2112 /****************************************************************** 2113 ******************* RDMA Commands ******************************** 2114 ******************************************************************/ 2115 2116 /** 2117 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2118 * @opcode: opcode 2119 * @lif_index: LIF index 2120 * 2121 * There is no RDMA specific dev command completion struct. Completion uses 2122 * the common struct ionic_admin_comp. Only the status is indicated. 2123 * Nonzero status means the LIF does not support RDMA. 2124 **/ 2125 struct ionic_rdma_reset_cmd { 2126 u8 opcode; 2127 u8 rsvd; 2128 __le16 lif_index; 2129 u8 rsvd2[60]; 2130 }; 2131 2132 /** 2133 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2134 * @opcode: opcode, 52, 53 2135 * @lif_index: LIF index 2136 * @qid_ver: (qid | (RDMA version << 24)) 2137 * @cid: intr, eq_id, or cq_id 2138 * @dbid: doorbell page id 2139 * @depth_log2: log base two of queue depth 2140 * @stride_log2: log base two of queue stride 2141 * @dma_addr: address of the queue memory 2142 * 2143 * The same command struct is used to create an RDMA event queue, completion 2144 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2145 * queue, an event queue id for a completion queue, or a completion queue id 2146 * for an RDMA admin queue. 2147 * 2148 * The queue created via a dev command must be contiguous in dma space. 2149 * 2150 * The dev commands are intended only to be used during driver initialization, 2151 * to create queues supporting the RDMA admin queue. Other queues, and other 2152 * types of RDMA resources like memory regions, will be created and registered 2153 * via the RDMA admin queue, and will support a more complete interface 2154 * providing scatter gather lists for larger, scattered queue buffers and 2155 * memory registration. 2156 * 2157 * There is no RDMA specific dev command completion struct. Completion uses 2158 * the common struct ionic_admin_comp. Only the status is indicated. 2159 **/ 2160 struct ionic_rdma_queue_cmd { 2161 u8 opcode; 2162 u8 rsvd; 2163 __le16 lif_index; 2164 __le32 qid_ver; 2165 __le32 cid; 2166 __le16 dbid; 2167 u8 depth_log2; 2168 u8 stride_log2; 2169 __le64 dma_addr; 2170 u8 rsvd2[40]; 2171 }; 2172 2173 /****************************************************************** 2174 ******************* Notify Events ******************************** 2175 ******************************************************************/ 2176 2177 /** 2178 * struct ionic_notifyq_event - Generic event reporting structure 2179 * @eid: event number 2180 * @ecode: event code 2181 * @data: unspecified data about the event 2182 * 2183 * This is the generic event report struct from which the other 2184 * actual events will be formed. 2185 */ 2186 struct ionic_notifyq_event { 2187 __le64 eid; 2188 __le16 ecode; 2189 u8 data[54]; 2190 }; 2191 2192 /** 2193 * struct ionic_link_change_event - Link change event notification 2194 * @eid: event number 2195 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2196 * @link_status: link up/down, with error bits (enum ionic_port_status) 2197 * @link_speed: speed of the network link 2198 * 2199 * Sent when the network link state changes between UP and DOWN 2200 */ 2201 struct ionic_link_change_event { 2202 __le64 eid; 2203 __le16 ecode; 2204 __le16 link_status; 2205 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2206 u8 rsvd[48]; 2207 }; 2208 2209 /** 2210 * struct ionic_reset_event - Reset event notification 2211 * @eid: event number 2212 * @ecode: event code = IONIC_EVENT_RESET 2213 * @reset_code: reset type 2214 * @state: 0=pending, 1=complete, 2=error 2215 * 2216 * Sent when the NIC or some subsystem is going to be or 2217 * has been reset. 2218 */ 2219 struct ionic_reset_event { 2220 __le64 eid; 2221 __le16 ecode; 2222 u8 reset_code; 2223 u8 state; 2224 u8 rsvd[52]; 2225 }; 2226 2227 /** 2228 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2229 * @eid: event number 2230 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2231 */ 2232 struct ionic_heartbeat_event { 2233 __le64 eid; 2234 __le16 ecode; 2235 u8 rsvd[54]; 2236 }; 2237 2238 /** 2239 * struct ionic_log_event - Sent to notify the driver of an internal error 2240 * @eid: event number 2241 * @ecode: event code = IONIC_EVENT_LOG 2242 * @data: log data 2243 */ 2244 struct ionic_log_event { 2245 __le64 eid; 2246 __le16 ecode; 2247 u8 data[54]; 2248 }; 2249 2250 /** 2251 * struct ionic_xcvr_event - Transceiver change event 2252 * @eid: event number 2253 * @ecode: event code = IONIC_EVENT_XCVR 2254 */ 2255 struct ionic_xcvr_event { 2256 __le64 eid; 2257 __le16 ecode; 2258 u8 rsvd[54]; 2259 }; 2260 2261 /** 2262 * struct ionic_port_stats - Port statistics structure 2263 */ 2264 struct ionic_port_stats { 2265 __le64 frames_rx_ok; 2266 __le64 frames_rx_all; 2267 __le64 frames_rx_bad_fcs; 2268 __le64 frames_rx_bad_all; 2269 __le64 octets_rx_ok; 2270 __le64 octets_rx_all; 2271 __le64 frames_rx_unicast; 2272 __le64 frames_rx_multicast; 2273 __le64 frames_rx_broadcast; 2274 __le64 frames_rx_pause; 2275 __le64 frames_rx_bad_length; 2276 __le64 frames_rx_undersized; 2277 __le64 frames_rx_oversized; 2278 __le64 frames_rx_fragments; 2279 __le64 frames_rx_jabber; 2280 __le64 frames_rx_pripause; 2281 __le64 frames_rx_stomped_crc; 2282 __le64 frames_rx_too_long; 2283 __le64 frames_rx_vlan_good; 2284 __le64 frames_rx_dropped; 2285 __le64 frames_rx_less_than_64b; 2286 __le64 frames_rx_64b; 2287 __le64 frames_rx_65b_127b; 2288 __le64 frames_rx_128b_255b; 2289 __le64 frames_rx_256b_511b; 2290 __le64 frames_rx_512b_1023b; 2291 __le64 frames_rx_1024b_1518b; 2292 __le64 frames_rx_1519b_2047b; 2293 __le64 frames_rx_2048b_4095b; 2294 __le64 frames_rx_4096b_8191b; 2295 __le64 frames_rx_8192b_9215b; 2296 __le64 frames_rx_other; 2297 __le64 frames_tx_ok; 2298 __le64 frames_tx_all; 2299 __le64 frames_tx_bad; 2300 __le64 octets_tx_ok; 2301 __le64 octets_tx_total; 2302 __le64 frames_tx_unicast; 2303 __le64 frames_tx_multicast; 2304 __le64 frames_tx_broadcast; 2305 __le64 frames_tx_pause; 2306 __le64 frames_tx_pripause; 2307 __le64 frames_tx_vlan; 2308 __le64 frames_tx_less_than_64b; 2309 __le64 frames_tx_64b; 2310 __le64 frames_tx_65b_127b; 2311 __le64 frames_tx_128b_255b; 2312 __le64 frames_tx_256b_511b; 2313 __le64 frames_tx_512b_1023b; 2314 __le64 frames_tx_1024b_1518b; 2315 __le64 frames_tx_1519b_2047b; 2316 __le64 frames_tx_2048b_4095b; 2317 __le64 frames_tx_4096b_8191b; 2318 __le64 frames_tx_8192b_9215b; 2319 __le64 frames_tx_other; 2320 __le64 frames_tx_pri_0; 2321 __le64 frames_tx_pri_1; 2322 __le64 frames_tx_pri_2; 2323 __le64 frames_tx_pri_3; 2324 __le64 frames_tx_pri_4; 2325 __le64 frames_tx_pri_5; 2326 __le64 frames_tx_pri_6; 2327 __le64 frames_tx_pri_7; 2328 __le64 frames_rx_pri_0; 2329 __le64 frames_rx_pri_1; 2330 __le64 frames_rx_pri_2; 2331 __le64 frames_rx_pri_3; 2332 __le64 frames_rx_pri_4; 2333 __le64 frames_rx_pri_5; 2334 __le64 frames_rx_pri_6; 2335 __le64 frames_rx_pri_7; 2336 __le64 tx_pripause_0_1us_count; 2337 __le64 tx_pripause_1_1us_count; 2338 __le64 tx_pripause_2_1us_count; 2339 __le64 tx_pripause_3_1us_count; 2340 __le64 tx_pripause_4_1us_count; 2341 __le64 tx_pripause_5_1us_count; 2342 __le64 tx_pripause_6_1us_count; 2343 __le64 tx_pripause_7_1us_count; 2344 __le64 rx_pripause_0_1us_count; 2345 __le64 rx_pripause_1_1us_count; 2346 __le64 rx_pripause_2_1us_count; 2347 __le64 rx_pripause_3_1us_count; 2348 __le64 rx_pripause_4_1us_count; 2349 __le64 rx_pripause_5_1us_count; 2350 __le64 rx_pripause_6_1us_count; 2351 __le64 rx_pripause_7_1us_count; 2352 __le64 rx_pause_1us_count; 2353 __le64 frames_tx_truncated; 2354 }; 2355 2356 struct ionic_mgmt_port_stats { 2357 __le64 frames_rx_ok; 2358 __le64 frames_rx_all; 2359 __le64 frames_rx_bad_fcs; 2360 __le64 frames_rx_bad_all; 2361 __le64 octets_rx_ok; 2362 __le64 octets_rx_all; 2363 __le64 frames_rx_unicast; 2364 __le64 frames_rx_multicast; 2365 __le64 frames_rx_broadcast; 2366 __le64 frames_rx_pause; 2367 __le64 frames_rx_bad_length; 2368 __le64 frames_rx_undersized; 2369 __le64 frames_rx_oversized; 2370 __le64 frames_rx_fragments; 2371 __le64 frames_rx_jabber; 2372 __le64 frames_rx_64b; 2373 __le64 frames_rx_65b_127b; 2374 __le64 frames_rx_128b_255b; 2375 __le64 frames_rx_256b_511b; 2376 __le64 frames_rx_512b_1023b; 2377 __le64 frames_rx_1024b_1518b; 2378 __le64 frames_rx_gt_1518b; 2379 __le64 frames_rx_fifo_full; 2380 __le64 frames_tx_ok; 2381 __le64 frames_tx_all; 2382 __le64 frames_tx_bad; 2383 __le64 octets_tx_ok; 2384 __le64 octets_tx_total; 2385 __le64 frames_tx_unicast; 2386 __le64 frames_tx_multicast; 2387 __le64 frames_tx_broadcast; 2388 __le64 frames_tx_pause; 2389 }; 2390 2391 enum ionic_pb_buffer_drop_stats { 2392 IONIC_BUFFER_INTRINSIC_DROP = 0, 2393 IONIC_BUFFER_DISCARDED, 2394 IONIC_BUFFER_ADMITTED, 2395 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2396 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2397 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2398 IONIC_BUFFER_TRUNCATION_DROP, 2399 IONIC_BUFFER_PORT_DISABLED_DROP, 2400 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2401 IONIC_BUFFER_SPAN_TAIL_DROP, 2402 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2403 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2404 IONIC_BUFFER_INVALID_PORT_DROP, 2405 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2406 IONIC_BUFFER_DROP_MAX, 2407 }; 2408 2409 enum ionic_oflow_drop_stats { 2410 IONIC_OFLOW_OCCUPANCY_DROP, 2411 IONIC_OFLOW_EMERGENCY_STOP_DROP, 2412 IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 2413 IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 2414 IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 2415 IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 2416 IONIC_OFLOW_DROP_MAX, 2417 }; 2418 2419 /** 2420 * struct port_pb_stats - packet buffers system stats 2421 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2422 */ 2423 struct ionic_port_pb_stats { 2424 __le64 sop_count_in; 2425 __le64 eop_count_in; 2426 __le64 sop_count_out; 2427 __le64 eop_count_out; 2428 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2429 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2430 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2431 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2432 __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 2433 __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 2434 __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 2435 __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 2436 __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 2437 __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 2438 __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 2439 __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2440 }; 2441 2442 /** 2443 * struct ionic_port_identity - port identity structure 2444 * @version: identity structure version 2445 * @type: type of port (enum ionic_port_type) 2446 * @num_lanes: number of lanes for the port 2447 * @autoneg: autoneg supported 2448 * @min_frame_size: minimum frame size supported 2449 * @max_frame_size: maximum frame size supported 2450 * @fec_type: supported fec types 2451 * @pause_type: supported pause types 2452 * @loopback_mode: supported loopback mode 2453 * @speeds: supported speeds 2454 * @config: current port configuration 2455 */ 2456 union ionic_port_identity { 2457 struct { 2458 u8 version; 2459 u8 type; 2460 u8 num_lanes; 2461 u8 autoneg; 2462 __le32 min_frame_size; 2463 __le32 max_frame_size; 2464 u8 fec_type[4]; 2465 u8 pause_type[2]; 2466 u8 loopback_mode[2]; 2467 __le32 speeds[16]; 2468 u8 rsvd2[44]; 2469 union ionic_port_config config; 2470 }; 2471 __le32 words[478]; 2472 }; 2473 2474 /** 2475 * struct ionic_port_info - port info structure 2476 * @config: Port configuration data 2477 * @status: Port status data 2478 * @stats: Port statistics data 2479 * @mgmt_stats: Port management statistics data 2480 * @port_pb_drop_stats: uplink pb drop stats 2481 */ 2482 struct ionic_port_info { 2483 union ionic_port_config config; 2484 struct ionic_port_status status; 2485 union { 2486 struct ionic_port_stats stats; 2487 struct ionic_mgmt_port_stats mgmt_stats; 2488 }; 2489 /* room for pb_stats to start at 2k offset */ 2490 u8 rsvd[760]; 2491 struct ionic_port_pb_stats pb_stats; 2492 }; 2493 2494 /** 2495 * struct ionic_lif_stats - LIF statistics structure 2496 */ 2497 struct ionic_lif_stats { 2498 /* RX */ 2499 __le64 rx_ucast_bytes; 2500 __le64 rx_ucast_packets; 2501 __le64 rx_mcast_bytes; 2502 __le64 rx_mcast_packets; 2503 __le64 rx_bcast_bytes; 2504 __le64 rx_bcast_packets; 2505 __le64 rsvd0; 2506 __le64 rsvd1; 2507 /* RX drops */ 2508 __le64 rx_ucast_drop_bytes; 2509 __le64 rx_ucast_drop_packets; 2510 __le64 rx_mcast_drop_bytes; 2511 __le64 rx_mcast_drop_packets; 2512 __le64 rx_bcast_drop_bytes; 2513 __le64 rx_bcast_drop_packets; 2514 __le64 rx_dma_error; 2515 __le64 rsvd2; 2516 /* TX */ 2517 __le64 tx_ucast_bytes; 2518 __le64 tx_ucast_packets; 2519 __le64 tx_mcast_bytes; 2520 __le64 tx_mcast_packets; 2521 __le64 tx_bcast_bytes; 2522 __le64 tx_bcast_packets; 2523 __le64 rsvd3; 2524 __le64 rsvd4; 2525 /* TX drops */ 2526 __le64 tx_ucast_drop_bytes; 2527 __le64 tx_ucast_drop_packets; 2528 __le64 tx_mcast_drop_bytes; 2529 __le64 tx_mcast_drop_packets; 2530 __le64 tx_bcast_drop_bytes; 2531 __le64 tx_bcast_drop_packets; 2532 __le64 tx_dma_error; 2533 __le64 rsvd5; 2534 /* Rx Queue/Ring drops */ 2535 __le64 rx_queue_disabled; 2536 __le64 rx_queue_empty; 2537 __le64 rx_queue_error; 2538 __le64 rx_desc_fetch_error; 2539 __le64 rx_desc_data_error; 2540 __le64 rsvd6; 2541 __le64 rsvd7; 2542 __le64 rsvd8; 2543 /* Tx Queue/Ring drops */ 2544 __le64 tx_queue_disabled; 2545 __le64 tx_queue_error; 2546 __le64 tx_desc_fetch_error; 2547 __le64 tx_desc_data_error; 2548 __le64 tx_queue_empty; 2549 __le64 rsvd10; 2550 __le64 rsvd11; 2551 __le64 rsvd12; 2552 2553 /* RDMA/ROCE TX */ 2554 __le64 tx_rdma_ucast_bytes; 2555 __le64 tx_rdma_ucast_packets; 2556 __le64 tx_rdma_mcast_bytes; 2557 __le64 tx_rdma_mcast_packets; 2558 __le64 tx_rdma_cnp_packets; 2559 __le64 rsvd13; 2560 __le64 rsvd14; 2561 __le64 rsvd15; 2562 2563 /* RDMA/ROCE RX */ 2564 __le64 rx_rdma_ucast_bytes; 2565 __le64 rx_rdma_ucast_packets; 2566 __le64 rx_rdma_mcast_bytes; 2567 __le64 rx_rdma_mcast_packets; 2568 __le64 rx_rdma_cnp_packets; 2569 __le64 rx_rdma_ecn_packets; 2570 __le64 rsvd16; 2571 __le64 rsvd17; 2572 2573 __le64 rsvd18; 2574 __le64 rsvd19; 2575 __le64 rsvd20; 2576 __le64 rsvd21; 2577 __le64 rsvd22; 2578 __le64 rsvd23; 2579 __le64 rsvd24; 2580 __le64 rsvd25; 2581 2582 __le64 rsvd26; 2583 __le64 rsvd27; 2584 __le64 rsvd28; 2585 __le64 rsvd29; 2586 __le64 rsvd30; 2587 __le64 rsvd31; 2588 __le64 rsvd32; 2589 __le64 rsvd33; 2590 2591 __le64 rsvd34; 2592 __le64 rsvd35; 2593 __le64 rsvd36; 2594 __le64 rsvd37; 2595 __le64 rsvd38; 2596 __le64 rsvd39; 2597 __le64 rsvd40; 2598 __le64 rsvd41; 2599 2600 __le64 rsvd42; 2601 __le64 rsvd43; 2602 __le64 rsvd44; 2603 __le64 rsvd45; 2604 __le64 rsvd46; 2605 __le64 rsvd47; 2606 __le64 rsvd48; 2607 __le64 rsvd49; 2608 2609 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2610 __le64 rdma_req_rx_pkt_seq_err; 2611 __le64 rdma_req_rx_rnr_retry_err; 2612 __le64 rdma_req_rx_remote_access_err; 2613 __le64 rdma_req_rx_remote_inv_req_err; 2614 __le64 rdma_req_rx_remote_oper_err; 2615 __le64 rdma_req_rx_implied_nak_seq_err; 2616 __le64 rdma_req_rx_cqe_err; 2617 __le64 rdma_req_rx_cqe_flush_err; 2618 2619 __le64 rdma_req_rx_dup_responses; 2620 __le64 rdma_req_rx_invalid_packets; 2621 __le64 rdma_req_tx_local_access_err; 2622 __le64 rdma_req_tx_local_oper_err; 2623 __le64 rdma_req_tx_memory_mgmt_err; 2624 __le64 rsvd52; 2625 __le64 rsvd53; 2626 __le64 rsvd54; 2627 2628 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2629 __le64 rdma_resp_rx_dup_requests; 2630 __le64 rdma_resp_rx_out_of_buffer; 2631 __le64 rdma_resp_rx_out_of_seq_pkts; 2632 __le64 rdma_resp_rx_cqe_err; 2633 __le64 rdma_resp_rx_cqe_flush_err; 2634 __le64 rdma_resp_rx_local_len_err; 2635 __le64 rdma_resp_rx_inv_request_err; 2636 __le64 rdma_resp_rx_local_qp_oper_err; 2637 2638 __le64 rdma_resp_rx_out_of_atomic_resource; 2639 __le64 rdma_resp_tx_pkt_seq_err; 2640 __le64 rdma_resp_tx_remote_inv_req_err; 2641 __le64 rdma_resp_tx_remote_access_err; 2642 __le64 rdma_resp_tx_remote_oper_err; 2643 __le64 rdma_resp_tx_rnr_retry_err; 2644 __le64 rsvd57; 2645 __le64 rsvd58; 2646 }; 2647 2648 /** 2649 * struct ionic_lif_info - LIF info structure 2650 * @config: LIF configuration structure 2651 * @status: LIF status structure 2652 * @stats: LIF statistics structure 2653 */ 2654 struct ionic_lif_info { 2655 union ionic_lif_config config; 2656 struct ionic_lif_status status; 2657 struct ionic_lif_stats stats; 2658 }; 2659 2660 union ionic_dev_cmd { 2661 u32 words[16]; 2662 struct ionic_admin_cmd cmd; 2663 struct ionic_nop_cmd nop; 2664 2665 struct ionic_dev_identify_cmd identify; 2666 struct ionic_dev_init_cmd init; 2667 struct ionic_dev_reset_cmd reset; 2668 struct ionic_dev_getattr_cmd getattr; 2669 struct ionic_dev_setattr_cmd setattr; 2670 2671 struct ionic_port_identify_cmd port_identify; 2672 struct ionic_port_init_cmd port_init; 2673 struct ionic_port_reset_cmd port_reset; 2674 struct ionic_port_getattr_cmd port_getattr; 2675 struct ionic_port_setattr_cmd port_setattr; 2676 2677 struct ionic_vf_setattr_cmd vf_setattr; 2678 struct ionic_vf_getattr_cmd vf_getattr; 2679 2680 struct ionic_lif_identify_cmd lif_identify; 2681 struct ionic_lif_init_cmd lif_init; 2682 struct ionic_lif_reset_cmd lif_reset; 2683 2684 struct ionic_qos_identify_cmd qos_identify; 2685 struct ionic_qos_init_cmd qos_init; 2686 struct ionic_qos_reset_cmd qos_reset; 2687 struct ionic_qos_clear_stats_cmd qos_clear_stats; 2688 2689 struct ionic_q_identify_cmd q_identify; 2690 struct ionic_q_init_cmd q_init; 2691 struct ionic_q_control_cmd q_control; 2692 }; 2693 2694 union ionic_dev_cmd_comp { 2695 u32 words[4]; 2696 u8 status; 2697 struct ionic_admin_comp comp; 2698 struct ionic_nop_comp nop; 2699 2700 struct ionic_dev_identify_comp identify; 2701 struct ionic_dev_init_comp init; 2702 struct ionic_dev_reset_comp reset; 2703 struct ionic_dev_getattr_comp getattr; 2704 struct ionic_dev_setattr_comp setattr; 2705 2706 struct ionic_port_identify_comp port_identify; 2707 struct ionic_port_init_comp port_init; 2708 struct ionic_port_reset_comp port_reset; 2709 struct ionic_port_getattr_comp port_getattr; 2710 struct ionic_port_setattr_comp port_setattr; 2711 2712 struct ionic_vf_setattr_comp vf_setattr; 2713 struct ionic_vf_getattr_comp vf_getattr; 2714 2715 struct ionic_lif_identify_comp lif_identify; 2716 struct ionic_lif_init_comp lif_init; 2717 ionic_lif_reset_comp lif_reset; 2718 2719 struct ionic_qos_identify_comp qos_identify; 2720 ionic_qos_init_comp qos_init; 2721 ionic_qos_reset_comp qos_reset; 2722 2723 struct ionic_q_identify_comp q_identify; 2724 struct ionic_q_init_comp q_init; 2725 }; 2726 2727 /** 2728 * union ionic_dev_info_regs - Device info register format (read-only) 2729 * @signature: Signature value of 0x44455649 ('DEVI') 2730 * @version: Current version of info 2731 * @asic_type: Asic type 2732 * @asic_rev: Asic revision 2733 * @fw_status: Firmware status 2734 * @fw_heartbeat: Firmware heartbeat counter 2735 * @serial_num: Serial number 2736 * @fw_version: Firmware version 2737 */ 2738 union ionic_dev_info_regs { 2739 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2740 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2741 struct { 2742 u32 signature; 2743 u8 version; 2744 u8 asic_type; 2745 u8 asic_rev; 2746 #define IONIC_FW_STS_F_RUNNING 0x1 2747 u8 fw_status; 2748 u32 fw_heartbeat; 2749 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2750 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2751 }; 2752 u32 words[512]; 2753 }; 2754 2755 /** 2756 * union ionic_dev_cmd_regs - Device command register format (read-write) 2757 * @doorbell: Device Cmd Doorbell, write-only 2758 * Write a 1 to signal device to process cmd, 2759 * poll done for completion. 2760 * @done: Done indicator, bit 0 == 1 when command is complete 2761 * @cmd: Opcode-specific command bytes 2762 * @comp: Opcode-specific response bytes 2763 * @data: Opcode-specific side-data 2764 */ 2765 union ionic_dev_cmd_regs { 2766 struct { 2767 u32 doorbell; 2768 u32 done; 2769 union ionic_dev_cmd cmd; 2770 union ionic_dev_cmd_comp comp; 2771 u8 rsvd[48]; 2772 u32 data[478]; 2773 } __packed; 2774 u32 words[512]; 2775 }; 2776 2777 /** 2778 * union ionic_dev_regs - Device register format for bar 0 page 0 2779 * @info: Device info registers 2780 * @devcmd: Device command registers 2781 */ 2782 union ionic_dev_regs { 2783 struct { 2784 union ionic_dev_info_regs info; 2785 union ionic_dev_cmd_regs devcmd; 2786 } __packed; 2787 __le32 words[1024]; 2788 }; 2789 2790 union ionic_adminq_cmd { 2791 struct ionic_admin_cmd cmd; 2792 struct ionic_nop_cmd nop; 2793 struct ionic_q_identify_cmd q_identify; 2794 struct ionic_q_init_cmd q_init; 2795 struct ionic_q_control_cmd q_control; 2796 struct ionic_lif_setattr_cmd lif_setattr; 2797 struct ionic_lif_getattr_cmd lif_getattr; 2798 struct ionic_rx_mode_set_cmd rx_mode_set; 2799 struct ionic_rx_filter_add_cmd rx_filter_add; 2800 struct ionic_rx_filter_del_cmd rx_filter_del; 2801 struct ionic_rdma_reset_cmd rdma_reset; 2802 struct ionic_rdma_queue_cmd rdma_queue; 2803 struct ionic_fw_download_cmd fw_download; 2804 struct ionic_fw_control_cmd fw_control; 2805 }; 2806 2807 union ionic_adminq_comp { 2808 struct ionic_admin_comp comp; 2809 struct ionic_nop_comp nop; 2810 struct ionic_q_identify_comp q_identify; 2811 struct ionic_q_init_comp q_init; 2812 struct ionic_lif_setattr_comp lif_setattr; 2813 struct ionic_lif_getattr_comp lif_getattr; 2814 struct ionic_rx_filter_add_comp rx_filter_add; 2815 struct ionic_fw_control_comp fw_control; 2816 }; 2817 2818 #define IONIC_BARS_MAX 6 2819 #define IONIC_PCI_BAR_DBELL 1 2820 2821 /* BAR0 */ 2822 #define IONIC_BAR0_SIZE 0x8000 2823 2824 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2825 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2826 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2827 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2828 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2829 #define IONIC_DEV_CMD_DONE 0x00000001 2830 2831 #define IONIC_ASIC_TYPE_CAPRI 0 2832 2833 /** 2834 * struct ionic_doorbell - Doorbell register layout 2835 * @p_index: Producer index 2836 * @ring: Selects the specific ring of the queue to update 2837 * Type-specific meaning: 2838 * ring=0: Default producer/consumer queue 2839 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2840 * send events to EQs when armed. EQs send 2841 * interrupts when armed. 2842 * @qid_lo: Queue destination for the producer index and flags (low bits) 2843 * @qid_hi: Queue destination for the producer index and flags (high bits) 2844 */ 2845 struct ionic_doorbell { 2846 __le16 p_index; 2847 u8 ring; 2848 u8 qid_lo; 2849 __le16 qid_hi; 2850 u16 rsvd2; 2851 }; 2852 2853 struct ionic_intr_status { 2854 u32 status[2]; 2855 }; 2856 2857 struct ionic_notifyq_cmd { 2858 __le32 data; /* Not used but needed for qcq structure */ 2859 }; 2860 2861 union ionic_notifyq_comp { 2862 struct ionic_notifyq_event event; 2863 struct ionic_link_change_event link_change; 2864 struct ionic_reset_event reset; 2865 struct ionic_heartbeat_event heartbeat; 2866 struct ionic_log_event log; 2867 }; 2868 2869 /* Deprecate */ 2870 struct ionic_identity { 2871 union ionic_drv_identity drv; 2872 union ionic_dev_identity dev; 2873 union ionic_lif_identity lif; 2874 union ionic_port_identity port; 2875 union ionic_qos_identity qos; 2876 union ionic_q_identity txq; 2877 }; 2878 2879 #endif /* _IONIC_IF_H_ */ 2880