1 /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2 /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3 4 #ifndef _IONIC_IF_H_ 5 #define _IONIC_IF_H_ 6 7 #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8 #define IONIC_DEV_INFO_VERSION 1 9 #define IONIC_IFNAMSIZ 16 10 11 /** 12 * enum ionic_cmd_opcode - Device commands 13 */ 14 enum ionic_cmd_opcode { 15 IONIC_CMD_NOP = 0, 16 17 /* Device commands */ 18 IONIC_CMD_IDENTIFY = 1, 19 IONIC_CMD_INIT = 2, 20 IONIC_CMD_RESET = 3, 21 IONIC_CMD_GETATTR = 4, 22 IONIC_CMD_SETATTR = 5, 23 24 /* Port commands */ 25 IONIC_CMD_PORT_IDENTIFY = 10, 26 IONIC_CMD_PORT_INIT = 11, 27 IONIC_CMD_PORT_RESET = 12, 28 IONIC_CMD_PORT_GETATTR = 13, 29 IONIC_CMD_PORT_SETATTR = 14, 30 31 /* LIF commands */ 32 IONIC_CMD_LIF_IDENTIFY = 20, 33 IONIC_CMD_LIF_INIT = 21, 34 IONIC_CMD_LIF_RESET = 22, 35 IONIC_CMD_LIF_GETATTR = 23, 36 IONIC_CMD_LIF_SETATTR = 24, 37 38 IONIC_CMD_RX_MODE_SET = 30, 39 IONIC_CMD_RX_FILTER_ADD = 31, 40 IONIC_CMD_RX_FILTER_DEL = 32, 41 42 /* Queue commands */ 43 IONIC_CMD_Q_IDENTIFY = 39, 44 IONIC_CMD_Q_INIT = 40, 45 IONIC_CMD_Q_CONTROL = 41, 46 47 /* RDMA commands */ 48 IONIC_CMD_RDMA_RESET_LIF = 50, 49 IONIC_CMD_RDMA_CREATE_EQ = 51, 50 IONIC_CMD_RDMA_CREATE_CQ = 52, 51 IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 52 53 /* SR/IOV commands */ 54 IONIC_CMD_VF_GETATTR = 60, 55 IONIC_CMD_VF_SETATTR = 61, 56 57 /* QoS commands */ 58 IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 59 IONIC_CMD_QOS_CLASS_INIT = 241, 60 IONIC_CMD_QOS_CLASS_RESET = 242, 61 IONIC_CMD_QOS_CLASS_UPDATE = 243, 62 63 /* Firmware commands */ 64 IONIC_CMD_FW_DOWNLOAD = 254, 65 IONIC_CMD_FW_CONTROL = 255, 66 }; 67 68 /** 69 * enum ionic_status_code - Device command return codes 70 */ 71 enum ionic_status_code { 72 IONIC_RC_SUCCESS = 0, /* Success */ 73 IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 74 IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 75 IONIC_RC_EIO = 3, /* I/O error */ 76 IONIC_RC_EPERM = 4, /* Permission denied */ 77 IONIC_RC_EQID = 5, /* Bad qid */ 78 IONIC_RC_EQTYPE = 6, /* Bad qtype */ 79 IONIC_RC_ENOENT = 7, /* No such element */ 80 IONIC_RC_EINTR = 8, /* operation interrupted */ 81 IONIC_RC_EAGAIN = 9, /* Try again */ 82 IONIC_RC_ENOMEM = 10, /* Out of memory */ 83 IONIC_RC_EFAULT = 11, /* Bad address */ 84 IONIC_RC_EBUSY = 12, /* Device or resource busy */ 85 IONIC_RC_EEXIST = 13, /* object already exists */ 86 IONIC_RC_EINVAL = 14, /* Invalid argument */ 87 IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 88 IONIC_RC_ERANGE = 16, /* Parameter out of range */ 89 IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 90 IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 91 IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 92 IONIC_RC_ERROR = 29, /* Generic error */ 93 94 IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 95 }; 96 97 enum ionic_notifyq_opcode { 98 IONIC_EVENT_LINK_CHANGE = 1, 99 IONIC_EVENT_RESET = 2, 100 IONIC_EVENT_HEARTBEAT = 3, 101 IONIC_EVENT_LOG = 4, 102 IONIC_EVENT_XCVR = 5, 103 }; 104 105 /** 106 * struct cmd - General admin command format 107 * @opcode: Opcode for the command 108 * @lif_index: LIF index 109 * @cmd_data: Opcode-specific command bytes 110 */ 111 struct ionic_admin_cmd { 112 u8 opcode; 113 u8 rsvd; 114 __le16 lif_index; 115 u8 cmd_data[60]; 116 }; 117 118 /** 119 * struct ionic_admin_comp - General admin command completion format 120 * @status: Status of the command (enum ionic_status_code) 121 * @comp_index: Index in the descriptor ring for which this is the completion 122 * @cmd_data: Command-specific bytes 123 * @color: Color bit (Always 0 for commands issued to the 124 * Device Cmd Registers) 125 */ 126 struct ionic_admin_comp { 127 u8 status; 128 u8 rsvd; 129 __le16 comp_index; 130 u8 cmd_data[11]; 131 u8 color; 132 #define IONIC_COMP_COLOR_MASK 0x80 133 }; 134 135 static inline u8 color_match(u8 color, u8 done_color) 136 { 137 return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 138 } 139 140 /** 141 * struct ionic_nop_cmd - NOP command 142 * @opcode: opcode 143 */ 144 struct ionic_nop_cmd { 145 u8 opcode; 146 u8 rsvd[63]; 147 }; 148 149 /** 150 * struct ionic_nop_comp - NOP command completion 151 * @status: Status of the command (enum ionic_status_code) 152 */ 153 struct ionic_nop_comp { 154 u8 status; 155 u8 rsvd[15]; 156 }; 157 158 /** 159 * struct ionic_dev_init_cmd - Device init command 160 * @opcode: opcode 161 * @type: Device type 162 */ 163 struct ionic_dev_init_cmd { 164 u8 opcode; 165 u8 type; 166 u8 rsvd[62]; 167 }; 168 169 /** 170 * struct init_comp - Device init command completion 171 * @status: Status of the command (enum ionic_status_code) 172 */ 173 struct ionic_dev_init_comp { 174 u8 status; 175 u8 rsvd[15]; 176 }; 177 178 /** 179 * struct ionic_dev_reset_cmd - Device reset command 180 * @opcode: opcode 181 */ 182 struct ionic_dev_reset_cmd { 183 u8 opcode; 184 u8 rsvd[63]; 185 }; 186 187 /** 188 * struct reset_comp - Reset command completion 189 * @status: Status of the command (enum ionic_status_code) 190 */ 191 struct ionic_dev_reset_comp { 192 u8 status; 193 u8 rsvd[15]; 194 }; 195 196 #define IONIC_IDENTITY_VERSION_1 1 197 198 /** 199 * struct ionic_dev_identify_cmd - Driver/device identify command 200 * @opcode: opcode 201 * @ver: Highest version of identify supported by driver 202 */ 203 struct ionic_dev_identify_cmd { 204 u8 opcode; 205 u8 ver; 206 u8 rsvd[62]; 207 }; 208 209 /** 210 * struct ionic_dev_identify_comp - Driver/device identify command completion 211 * @status: Status of the command (enum ionic_status_code) 212 * @ver: Version of identify returned by device 213 */ 214 struct ionic_dev_identify_comp { 215 u8 status; 216 u8 ver; 217 u8 rsvd[14]; 218 }; 219 220 enum ionic_os_type { 221 IONIC_OS_TYPE_LINUX = 1, 222 IONIC_OS_TYPE_WIN = 2, 223 IONIC_OS_TYPE_DPDK = 3, 224 IONIC_OS_TYPE_FREEBSD = 4, 225 IONIC_OS_TYPE_IPXE = 5, 226 IONIC_OS_TYPE_ESXI = 6, 227 }; 228 229 /** 230 * union ionic_drv_identity - driver identity information 231 * @os_type: OS type (see enum ionic_os_type) 232 * @os_dist: OS distribution, numeric format 233 * @os_dist_str: OS distribution, string format 234 * @kernel_ver: Kernel version, numeric format 235 * @kernel_ver_str: Kernel version, string format 236 * @driver_ver_str: Driver version, string format 237 */ 238 union ionic_drv_identity { 239 struct { 240 __le32 os_type; 241 __le32 os_dist; 242 char os_dist_str[128]; 243 __le32 kernel_ver; 244 char kernel_ver_str[32]; 245 char driver_ver_str[32]; 246 }; 247 __le32 words[478]; 248 }; 249 250 /** 251 * union ionic_dev_identity - device identity information 252 * @version: Version of device identify 253 * @type: Identify type (0 for now) 254 * @nports: Number of ports provisioned 255 * @nlifs: Number of LIFs provisioned 256 * @nintrs: Number of interrupts provisioned 257 * @ndbpgs_per_lif: Number of doorbell pages per LIF 258 * @intr_coal_mult: Interrupt coalescing multiplication factor 259 * Scale user-supplied interrupt coalescing 260 * value in usecs to device units using: 261 * device units = usecs * mult / div 262 * @intr_coal_div: Interrupt coalescing division factor 263 * Scale user-supplied interrupt coalescing 264 * value in usecs to device units using: 265 * device units = usecs * mult / div 266 * @eq_count: Number of shared event queues 267 */ 268 union ionic_dev_identity { 269 struct { 270 u8 version; 271 u8 type; 272 u8 rsvd[2]; 273 u8 nports; 274 u8 rsvd2[3]; 275 __le32 nlifs; 276 __le32 nintrs; 277 __le32 ndbpgs_per_lif; 278 __le32 intr_coal_mult; 279 __le32 intr_coal_div; 280 __le32 eq_count; 281 }; 282 __le32 words[478]; 283 }; 284 285 enum ionic_lif_type { 286 IONIC_LIF_TYPE_CLASSIC = 0, 287 IONIC_LIF_TYPE_MACVLAN = 1, 288 IONIC_LIF_TYPE_NETQUEUE = 2, 289 }; 290 291 /** 292 * struct ionic_lif_identify_cmd - LIF identify command 293 * @opcode: opcode 294 * @type: LIF type (enum ionic_lif_type) 295 * @ver: Version of identify returned by device 296 */ 297 struct ionic_lif_identify_cmd { 298 u8 opcode; 299 u8 type; 300 u8 ver; 301 u8 rsvd[61]; 302 }; 303 304 /** 305 * struct ionic_lif_identify_comp - LIF identify command completion 306 * @status: Status of the command (enum ionic_status_code) 307 * @ver: Version of identify returned by device 308 */ 309 struct ionic_lif_identify_comp { 310 u8 status; 311 u8 ver; 312 u8 rsvd2[14]; 313 }; 314 315 /** 316 * enum ionic_lif_capability - LIF capabilities 317 * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 318 * @IONIC_LIF_CAP_RDMA: LIF support RDMA 319 */ 320 enum ionic_lif_capability { 321 IONIC_LIF_CAP_ETH = BIT(0), 322 IONIC_LIF_CAP_RDMA = BIT(1), 323 }; 324 325 /** 326 * enum ionic_logical_qtype - Logical Queue Types 327 * @IONIC_QTYPE_ADMINQ: Administrative Queue 328 * @IONIC_QTYPE_NOTIFYQ: Notify Queue 329 * @IONIC_QTYPE_RXQ: Receive Queue 330 * @IONIC_QTYPE_TXQ: Transmit Queue 331 * @IONIC_QTYPE_EQ: Event Queue 332 * @IONIC_QTYPE_MAX: Max queue type supported 333 */ 334 enum ionic_logical_qtype { 335 IONIC_QTYPE_ADMINQ = 0, 336 IONIC_QTYPE_NOTIFYQ = 1, 337 IONIC_QTYPE_RXQ = 2, 338 IONIC_QTYPE_TXQ = 3, 339 IONIC_QTYPE_EQ = 4, 340 IONIC_QTYPE_MAX = 16, 341 }; 342 343 /** 344 * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 345 * @qtype: Hardware Queue Type 346 * @qid_count: Number of Queue IDs of the logical type 347 * @qid_base: Minimum Queue ID of the logical type 348 */ 349 struct ionic_lif_logical_qtype { 350 u8 qtype; 351 u8 rsvd[3]; 352 __le32 qid_count; 353 __le32 qid_base; 354 }; 355 356 /** 357 * enum ionic_lif_state - LIF state 358 * @IONIC_LIF_DISABLE: LIF disabled 359 * @IONIC_LIF_ENABLE: LIF enabled 360 * @IONIC_LIF_HANG_RESET: LIF hung, being reset 361 */ 362 enum ionic_lif_state { 363 IONIC_LIF_DISABLE = 0, 364 IONIC_LIF_ENABLE = 1, 365 IONIC_LIF_HANG_RESET = 2, 366 }; 367 368 /** 369 * union ionic_lif_config - LIF configuration 370 * @state: LIF state (enum ionic_lif_state) 371 * @name: LIF name 372 * @mtu: MTU 373 * @mac: Station MAC address 374 * @features: Features (enum ionic_eth_hw_features) 375 * @queue_count: Queue counts per queue-type 376 */ 377 union ionic_lif_config { 378 struct { 379 u8 state; 380 u8 rsvd[3]; 381 char name[IONIC_IFNAMSIZ]; 382 __le32 mtu; 383 u8 mac[6]; 384 u8 rsvd2[2]; 385 __le64 features; 386 __le32 queue_count[IONIC_QTYPE_MAX]; 387 } __packed; 388 __le32 words[64]; 389 }; 390 391 /** 392 * struct ionic_lif_identity - LIF identity information (type-specific) 393 * 394 * @capabilities: LIF capabilities 395 * 396 * @eth: Ethernet identify structure 397 * @version: Ethernet identify structure version 398 * @max_ucast_filters: Number of perfect unicast addresses supported 399 * @max_mcast_filters: Number of perfect multicast addresses supported 400 * @min_frame_size: Minimum size of frames to be sent 401 * @max_frame_size: Maximim size of frames to be sent 402 * @config: LIF config struct with features, mtu, mac, q counts 403 * 404 * @rdma: RDMA identify structure 405 * @version: RDMA version of opcodes and queue descriptors 406 * @qp_opcodes: Number of RDMA queue pair opcodes supported 407 * @admin_opcodes: Number of RDMA admin opcodes supported 408 * @npts_per_lif: Page table size per LIF 409 * @nmrs_per_lif: Number of memory regions per LIF 410 * @nahs_per_lif: Number of address handles per LIF 411 * @max_stride: Max work request stride 412 * @cl_stride: Cache line stride 413 * @pte_stride: Page table entry stride 414 * @rrq_stride: Remote RQ work request stride 415 * @rsq_stride: Remote SQ work request stride 416 * @dcqcn_profiles: Number of DCQCN profiles 417 * @aq_qtype: RDMA Admin Qtype 418 * @sq_qtype: RDMA Send Qtype 419 * @rq_qtype: RDMA Receive Qtype 420 * @cq_qtype: RDMA Completion Qtype 421 * @eq_qtype: RDMA Event Qtype 422 */ 423 union ionic_lif_identity { 424 struct { 425 __le64 capabilities; 426 427 struct { 428 u8 version; 429 u8 rsvd[3]; 430 __le32 max_ucast_filters; 431 __le32 max_mcast_filters; 432 __le16 rss_ind_tbl_sz; 433 __le32 min_frame_size; 434 __le32 max_frame_size; 435 u8 rsvd2[106]; 436 union ionic_lif_config config; 437 } __packed eth; 438 439 struct { 440 u8 version; 441 u8 qp_opcodes; 442 u8 admin_opcodes; 443 u8 rsvd; 444 __le32 npts_per_lif; 445 __le32 nmrs_per_lif; 446 __le32 nahs_per_lif; 447 u8 max_stride; 448 u8 cl_stride; 449 u8 pte_stride; 450 u8 rrq_stride; 451 u8 rsq_stride; 452 u8 dcqcn_profiles; 453 u8 rsvd_dimensions[10]; 454 struct ionic_lif_logical_qtype aq_qtype; 455 struct ionic_lif_logical_qtype sq_qtype; 456 struct ionic_lif_logical_qtype rq_qtype; 457 struct ionic_lif_logical_qtype cq_qtype; 458 struct ionic_lif_logical_qtype eq_qtype; 459 } __packed rdma; 460 } __packed; 461 __le32 words[478]; 462 }; 463 464 /** 465 * struct ionic_lif_init_cmd - LIF init command 466 * @opcode: Opcode 467 * @type: LIF type (enum ionic_lif_type) 468 * @index: LIF index 469 * @info_pa: Destination address for LIF info (struct ionic_lif_info) 470 */ 471 struct ionic_lif_init_cmd { 472 u8 opcode; 473 u8 type; 474 __le16 index; 475 __le32 rsvd; 476 __le64 info_pa; 477 u8 rsvd2[48]; 478 }; 479 480 /** 481 * struct ionic_lif_init_comp - LIF init command completion 482 * @status: Status of the command (enum ionic_status_code) 483 * @hw_index: Hardware index of the initialized LIF 484 */ 485 struct ionic_lif_init_comp { 486 u8 status; 487 u8 rsvd; 488 __le16 hw_index; 489 u8 rsvd2[12]; 490 }; 491 492 /** 493 * struct ionic_q_identify_cmd - queue identify command 494 * @opcode: opcode 495 * @lif_type: LIF type (enum ionic_lif_type) 496 * @type: Logical queue type (enum ionic_logical_qtype) 497 * @ver: Highest queue type version that the driver supports 498 */ 499 struct ionic_q_identify_cmd { 500 u8 opcode; 501 u8 rsvd; 502 __le16 lif_type; 503 u8 type; 504 u8 ver; 505 u8 rsvd2[58]; 506 }; 507 508 /** 509 * struct ionic_q_identify_comp - queue identify command completion 510 * @status: Status of the command (enum ionic_status_code) 511 * @comp_index: Index in the descriptor ring for which this is the completion 512 * @ver: Queue type version that can be used with FW 513 */ 514 struct ionic_q_identify_comp { 515 u8 status; 516 u8 rsvd; 517 __le16 comp_index; 518 u8 ver; 519 u8 rsvd2[11]; 520 }; 521 522 /** 523 * union ionic_q_identity - queue identity information 524 * @version: Queue type version that can be used with FW 525 * @supported: Bitfield of queue versions, first bit = ver 0 526 * @features: Queue features 527 * @desc_sz: Descriptor size 528 * @comp_sz: Completion descriptor size 529 * @sg_desc_sz: Scatter/Gather descriptor size 530 * @max_sg_elems: Maximum number of Scatter/Gather elements 531 * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 532 */ 533 union ionic_q_identity { 534 struct { 535 u8 version; 536 u8 supported; 537 u8 rsvd[6]; 538 #define IONIC_QIDENT_F_CQ 0x01 /* queue has completion ring */ 539 #define IONIC_QIDENT_F_SG 0x02 /* queue has scatter/gather ring */ 540 #define IONIC_QIDENT_F_EQ 0x04 /* queue can use event queue */ 541 #define IONIC_QIDENT_F_CMB 0x08 /* queue is in cmb bar */ 542 __le64 features; 543 __le16 desc_sz; 544 __le16 comp_sz; 545 __le16 sg_desc_sz; 546 __le16 max_sg_elems; 547 __le16 sg_desc_stride; 548 }; 549 __le32 words[478]; 550 }; 551 552 /** 553 * struct ionic_q_init_cmd - Queue init command 554 * @opcode: opcode 555 * @type: Logical queue type 556 * @ver: Queue type version 557 * @lif_index: LIF index 558 * @index: (LIF, qtype) relative admin queue index 559 * @intr_index: Interrupt control register index, or Event queue index 560 * @pid: Process ID 561 * @flags: 562 * IRQ: Interrupt requested on completion 563 * ENA: Enable the queue. If ENA=0 the queue is initialized 564 * but remains disabled, to be later enabled with the 565 * Queue Enable command. If ENA=1, then queue is 566 * initialized and then enabled. 567 * SG: Enable Scatter-Gather on the queue. 568 * in number of descs. The actual ring size is 569 * (1 << ring_size). For example, to 570 * select a ring size of 64 descriptors write 571 * ring_size = 6. The minimum ring_size value is 2 572 * for a ring size of 4 descriptors. The maximum 573 * ring_size value is 16 for a ring size of 64k 574 * descriptors. Values of ring_size <2 and >16 are 575 * reserved. 576 * EQ: Enable the Event Queue 577 * @cos: Class of service for this queue 578 * @ring_size: Queue ring size, encoded as a log2(size) 579 * @ring_base: Queue ring base address 580 * @cq_ring_base: Completion queue ring base address 581 * @sg_ring_base: Scatter/Gather ring base address 582 */ 583 struct ionic_q_init_cmd { 584 u8 opcode; 585 u8 rsvd; 586 __le16 lif_index; 587 u8 type; 588 u8 ver; 589 u8 rsvd1[2]; 590 __le32 index; 591 __le16 pid; 592 __le16 intr_index; 593 __le16 flags; 594 #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 595 #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 596 #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 597 #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 598 #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 599 #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 600 u8 cos; 601 u8 ring_size; 602 __le64 ring_base; 603 __le64 cq_ring_base; 604 __le64 sg_ring_base; 605 u8 rsvd2[20]; 606 } __packed; 607 608 /** 609 * struct ionic_q_init_comp - Queue init command completion 610 * @status: Status of the command (enum ionic_status_code) 611 * @comp_index: Index in the descriptor ring for which this is the completion 612 * @hw_index: Hardware Queue ID 613 * @hw_type: Hardware Queue type 614 * @color: Color 615 */ 616 struct ionic_q_init_comp { 617 u8 status; 618 u8 rsvd; 619 __le16 comp_index; 620 __le32 hw_index; 621 u8 hw_type; 622 u8 rsvd2[6]; 623 u8 color; 624 }; 625 626 /* the device's internal addressing uses up to 52 bits */ 627 #define IONIC_ADDR_LEN 52 628 #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 629 630 enum ionic_txq_desc_opcode { 631 IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 632 IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 633 IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 634 IONIC_TXQ_DESC_OPCODE_TSO = 3, 635 }; 636 637 /** 638 * struct ionic_txq_desc - Ethernet Tx queue descriptor format 639 * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 640 * 641 * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 642 * Non-offload send. No segmentation, 643 * fragmentation or checksum calc/insertion is 644 * performed by device; packet is prepared 645 * to send by software stack and requires 646 * no further manipulation from device. 647 * 648 * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 649 * Offload 16-bit L4 checksum 650 * calculation/insertion. The device will 651 * calculate the L4 checksum value and 652 * insert the result in the packet's L4 653 * header checksum field. The L4 checksum 654 * is calculated starting at @csum_start bytes 655 * into the packet to the end of the packet. 656 * The checksum insertion position is given 657 * in @csum_offset, which is the offset from 658 * @csum_start to the checksum field in the L4 659 * header. This feature is only applicable to 660 * protocols such as TCP, UDP and ICMP where a 661 * standard (i.e. the 'IP-style' checksum) 662 * one's complement 16-bit checksum is used, 663 * using an IP pseudo-header to seed the 664 * calculation. Software will preload the L4 665 * checksum field with the IP pseudo-header 666 * checksum. 667 * 668 * For tunnel encapsulation, @csum_start and 669 * @csum_offset refer to the inner L4 670 * header. Supported tunnels encapsulations 671 * are: IPIP, GRE, and UDP. If the @encap 672 * is clear, no further processing by the 673 * device is required; software will 674 * calculate the outer header checksums. If 675 * the @encap is set, the device will 676 * offload the outer header checksums using 677 * LCO (local checksum offload) (see 678 * Documentation/networking/checksum-offloads.rst 679 * for more info). 680 * 681 * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 682 * Offload 16-bit checksum computation to hardware. 683 * If @csum_l3 is set then the packet's L3 checksum is 684 * updated. Similarly, if @csum_l4 is set the the L4 685 * checksum is updated. If @encap is set then encap header 686 * checksums are also updated. 687 * 688 * IONIC_TXQ_DESC_OPCODE_TSO: 689 * Device preforms TCP segmentation offload 690 * (TSO). @hdr_len is the number of bytes 691 * to the end of TCP header (the offset to 692 * the TCP payload). @mss is the desired 693 * MSS, the TCP payload length for each 694 * segment. The device will calculate/ 695 * insert IP (IPv4 only) and TCP checksums 696 * for each segment. In the first data 697 * buffer containing the header template, 698 * the driver will set IPv4 checksum to 0 699 * and preload TCP checksum with the IP 700 * pseudo header calculated with IP length = 0. 701 * 702 * Supported tunnel encapsulations are IPIP, 703 * layer-3 GRE, and UDP. @hdr_len includes 704 * both outer and inner headers. The driver 705 * will set IPv4 checksum to zero and 706 * preload TCP checksum with IP pseudo 707 * header on the inner header. 708 * 709 * TCP ECN offload is supported. The device 710 * will set CWR flag in the first segment if 711 * CWR is set in the template header, and 712 * clear CWR in remaining segments. 713 * @flags: 714 * vlan: 715 * Insert an L2 VLAN header using @vlan_tci 716 * encap: 717 * Calculate encap header checksum 718 * csum_l3: 719 * Compute L3 header checksum 720 * csum_l4: 721 * Compute L4 header checksum 722 * tso_sot: 723 * TSO start 724 * tso_eot: 725 * TSO end 726 * @num_sg_elems: Number of scatter-gather elements in SG 727 * descriptor 728 * @addr: First data buffer's DMA address 729 * (Subsequent data buffers are on txq_sg_desc) 730 * @len: First data buffer's length, in bytes 731 * @vlan_tci: VLAN tag to insert in the packet (if requested 732 * by @V-bit). Includes .1p and .1q tags 733 * @hdr_len: Length of packet headers, including 734 * encapsulating outer header, if applicable 735 * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 736 * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 737 * all other modes. For 738 * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 739 * of headers up to inner-most L4 header. For 740 * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 741 * inner-most L4 payload, so inclusive of 742 * inner-most L4 header. 743 * @mss: Desired MSS value for TSO; only applicable for 744 * IONIC_TXQ_DESC_OPCODE_TSO 745 * @csum_start: Offset from packet to first byte checked in L4 checksum 746 * @csum_offset: Offset from csum_start to L4 checksum field 747 */ 748 struct ionic_txq_desc { 749 __le64 cmd; 750 #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 751 #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 752 #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 753 #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 754 #define IONIC_TXQ_DESC_NSGE_MASK 0xf 755 #define IONIC_TXQ_DESC_NSGE_SHIFT 8 756 #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 757 #define IONIC_TXQ_DESC_ADDR_SHIFT 12 758 759 /* common flags */ 760 #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 761 #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 762 763 /* flags for csum_hw opcode */ 764 #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 765 #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 766 767 /* flags for tso opcode */ 768 #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 769 #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 770 771 __le16 len; 772 union { 773 __le16 vlan_tci; 774 __le16 hword0; 775 }; 776 union { 777 __le16 csum_start; 778 __le16 hdr_len; 779 __le16 hword1; 780 }; 781 union { 782 __le16 csum_offset; 783 __le16 mss; 784 __le16 hword2; 785 }; 786 }; 787 788 static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 789 u8 nsge, u64 addr) 790 { 791 u64 cmd; 792 793 cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 794 cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 795 cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 796 cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 797 798 return cmd; 799 }; 800 801 static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 802 u8 *nsge, u64 *addr) 803 { 804 *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 805 *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 806 *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 807 *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 808 }; 809 810 /** 811 * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 812 * @addr: DMA address of SG element data buffer 813 * @len: Length of SG element data buffer, in bytes 814 */ 815 struct ionic_txq_sg_elem { 816 __le64 addr; 817 __le16 len; 818 __le16 rsvd[3]; 819 }; 820 821 /** 822 * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 823 * @elems: Scatter-gather elements 824 */ 825 struct ionic_txq_sg_desc { 826 #define IONIC_TX_MAX_SG_ELEMS 8 827 #define IONIC_TX_SG_DESC_STRIDE 8 828 struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 829 }; 830 831 struct ionic_txq_sg_desc_v1 { 832 #define IONIC_TX_MAX_SG_ELEMS_V1 15 833 #define IONIC_TX_SG_DESC_STRIDE_V1 16 834 struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 835 }; 836 837 /** 838 * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 839 * @status: Status of the command (enum ionic_status_code) 840 * @comp_index: Index in the descriptor ring for which this is the completion 841 * @color: Color bit 842 */ 843 struct ionic_txq_comp { 844 u8 status; 845 u8 rsvd; 846 __le16 comp_index; 847 u8 rsvd2[11]; 848 u8 color; 849 }; 850 851 enum ionic_rxq_desc_opcode { 852 IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 853 IONIC_RXQ_DESC_OPCODE_SG = 1, 854 }; 855 856 /** 857 * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 858 * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 859 * 860 * IONIC_RXQ_DESC_OPCODE_SIMPLE: 861 * Receive full packet into data buffer 862 * starting at @addr. Results of 863 * receive, including actual bytes received, 864 * are recorded in Rx completion descriptor. 865 * 866 * @len: Data buffer's length, in bytes 867 * @addr: Data buffer's DMA address 868 */ 869 struct ionic_rxq_desc { 870 u8 opcode; 871 u8 rsvd[5]; 872 __le16 len; 873 __le64 addr; 874 }; 875 876 /** 877 * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 878 * @addr: DMA address of SG element data buffer 879 * @len: Length of SG element data buffer, in bytes 880 */ 881 struct ionic_rxq_sg_elem { 882 __le64 addr; 883 __le16 len; 884 __le16 rsvd[3]; 885 }; 886 887 /** 888 * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 889 * @elems: Scatter-gather elements 890 */ 891 struct ionic_rxq_sg_desc { 892 #define IONIC_RX_MAX_SG_ELEMS 8 893 #define IONIC_RX_SG_DESC_STRIDE 8 894 struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 895 }; 896 897 /** 898 * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 899 * @status: Status of the command (enum ionic_status_code) 900 * @num_sg_elems: Number of SG elements used by this descriptor 901 * @comp_index: Index in the descriptor ring for which this is the completion 902 * @rss_hash: 32-bit RSS hash 903 * @csum: 16-bit sum of the packet's L2 payload 904 * If the packet's L2 payload is odd length, an extra 905 * zero-value byte is included in the @csum calculation but 906 * not included in @len. 907 * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 908 * set. Includes .1p and .1q tags. 909 * @len: Received packet length, in bytes. Excludes FCS. 910 * @csum_calc L2 payload checksum is computed or not 911 * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 912 * 913 * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 914 * The TCP checksum calculated by the device 915 * matched the checksum in the receive packet's 916 * TCP header. 917 * 918 * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 919 * The TCP checksum calculated by the device did 920 * not match the checksum in the receive packet's 921 * TCP header. 922 * 923 * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 924 * The UDP checksum calculated by the device 925 * matched the checksum in the receive packet's 926 * UDP header 927 * 928 * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 929 * The UDP checksum calculated by the device did 930 * not match the checksum in the receive packet's 931 * UDP header. 932 * 933 * IONIC_RXQ_COMP_CSUM_F_IP_OK: 934 * The IPv4 checksum calculated by the device 935 * matched the checksum in the receive packet's 936 * first IPv4 header. If the receive packet 937 * contains both a tunnel IPv4 header and a 938 * transport IPv4 header, the device validates the 939 * checksum for the both IPv4 headers. 940 * 941 * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 942 * The IPv4 checksum calculated by the device did 943 * not match the checksum in the receive packet's 944 * first IPv4 header. If the receive packet 945 * contains both a tunnel IPv4 header and a 946 * transport IPv4 header, the device validates the 947 * checksum for both IP headers. 948 * 949 * IONIC_RXQ_COMP_CSUM_F_VLAN: 950 * The VLAN header was stripped and placed in @vlan_tci. 951 * 952 * IONIC_RXQ_COMP_CSUM_F_CALC: 953 * The checksum was calculated by the device. 954 * 955 * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 956 */ 957 struct ionic_rxq_comp { 958 u8 status; 959 u8 num_sg_elems; 960 __le16 comp_index; 961 __le32 rss_hash; 962 __le16 csum; 963 __le16 vlan_tci; 964 __le16 len; 965 u8 csum_flags; 966 #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 967 #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 968 #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 969 #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 970 #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 971 #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 972 #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 973 #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 974 u8 pkt_type_color; 975 #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 976 }; 977 978 enum ionic_pkt_type { 979 IONIC_PKT_TYPE_NON_IP = 0x000, 980 IONIC_PKT_TYPE_IPV4 = 0x001, 981 IONIC_PKT_TYPE_IPV4_TCP = 0x003, 982 IONIC_PKT_TYPE_IPV4_UDP = 0x005, 983 IONIC_PKT_TYPE_IPV6 = 0x008, 984 IONIC_PKT_TYPE_IPV6_TCP = 0x018, 985 IONIC_PKT_TYPE_IPV6_UDP = 0x028, 986 }; 987 988 enum ionic_eth_hw_features { 989 IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 990 IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 991 IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 992 IONIC_ETH_HW_RX_HASH = BIT(3), 993 IONIC_ETH_HW_RX_CSUM = BIT(4), 994 IONIC_ETH_HW_TX_SG = BIT(5), 995 IONIC_ETH_HW_RX_SG = BIT(6), 996 IONIC_ETH_HW_TX_CSUM = BIT(7), 997 IONIC_ETH_HW_TSO = BIT(8), 998 IONIC_ETH_HW_TSO_IPV6 = BIT(9), 999 IONIC_ETH_HW_TSO_ECN = BIT(10), 1000 IONIC_ETH_HW_TSO_GRE = BIT(11), 1001 IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1002 IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1003 IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1004 IONIC_ETH_HW_TSO_UDP = BIT(15), 1005 IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 1006 }; 1007 1008 /** 1009 * struct ionic_q_control_cmd - Queue control command 1010 * @opcode: opcode 1011 * @type: Queue type 1012 * @lif_index: LIF index 1013 * @index: Queue index 1014 * @oper: Operation (enum q_control_oper) 1015 */ 1016 struct ionic_q_control_cmd { 1017 u8 opcode; 1018 u8 type; 1019 __le16 lif_index; 1020 __le32 index; 1021 u8 oper; 1022 u8 rsvd[55]; 1023 }; 1024 1025 typedef struct ionic_admin_comp ionic_q_control_comp; 1026 1027 enum q_control_oper { 1028 IONIC_Q_DISABLE = 0, 1029 IONIC_Q_ENABLE = 1, 1030 IONIC_Q_HANG_RESET = 2, 1031 }; 1032 1033 /** 1034 * enum ionic_phy_type - Physical connection type 1035 * @IONIC_PHY_TYPE_NONE: No PHY installed 1036 * @IONIC_PHY_TYPE_COPPER: Copper PHY 1037 * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1038 */ 1039 enum ionic_phy_type { 1040 IONIC_PHY_TYPE_NONE = 0, 1041 IONIC_PHY_TYPE_COPPER = 1, 1042 IONIC_PHY_TYPE_FIBER = 2, 1043 }; 1044 1045 /** 1046 * enum ionic_xcvr_state - Transceiver status 1047 * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1048 * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1049 * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1050 * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1051 * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1052 */ 1053 enum ionic_xcvr_state { 1054 IONIC_XCVR_STATE_REMOVED = 0, 1055 IONIC_XCVR_STATE_INSERTED = 1, 1056 IONIC_XCVR_STATE_PENDING = 2, 1057 IONIC_XCVR_STATE_SPROM_READ = 3, 1058 IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1059 }; 1060 1061 /** 1062 * enum ionic_xcvr_pid - Supported link modes 1063 */ 1064 enum ionic_xcvr_pid { 1065 IONIC_XCVR_PID_UNKNOWN = 0, 1066 1067 /* CU */ 1068 IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1069 IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1070 IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1071 IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1072 IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1073 1074 /* Fiber */ 1075 IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1076 IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1077 IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1078 IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1079 IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1080 IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1081 IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1082 IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1083 IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1084 IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1085 IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1086 IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1087 IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1088 IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1089 IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1090 IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1091 IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1092 IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1093 IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1094 IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1095 IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1096 IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1097 }; 1098 1099 /** 1100 * enum ionic_port_type - Port types 1101 * @IONIC_PORT_TYPE_NONE: Port type not configured 1102 * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1103 * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1104 */ 1105 enum ionic_port_type { 1106 IONIC_PORT_TYPE_NONE = 0, 1107 IONIC_PORT_TYPE_ETH = 1, 1108 IONIC_PORT_TYPE_MGMT = 2, 1109 }; 1110 1111 /** 1112 * enum ionic_port_admin_state - Port config state 1113 * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1114 * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1115 * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1116 */ 1117 enum ionic_port_admin_state { 1118 IONIC_PORT_ADMIN_STATE_NONE = 0, 1119 IONIC_PORT_ADMIN_STATE_DOWN = 1, 1120 IONIC_PORT_ADMIN_STATE_UP = 2, 1121 }; 1122 1123 /** 1124 * enum ionic_port_oper_status - Port operational status 1125 * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1126 * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1127 * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1128 */ 1129 enum ionic_port_oper_status { 1130 IONIC_PORT_OPER_STATUS_NONE = 0, 1131 IONIC_PORT_OPER_STATUS_UP = 1, 1132 IONIC_PORT_OPER_STATUS_DOWN = 2, 1133 }; 1134 1135 /** 1136 * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1137 * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1138 * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1139 * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1140 */ 1141 enum ionic_port_fec_type { 1142 IONIC_PORT_FEC_TYPE_NONE = 0, 1143 IONIC_PORT_FEC_TYPE_FC = 1, 1144 IONIC_PORT_FEC_TYPE_RS = 2, 1145 }; 1146 1147 /** 1148 * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1149 * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1150 * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1151 * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1152 */ 1153 enum ionic_port_pause_type { 1154 IONIC_PORT_PAUSE_TYPE_NONE = 0, 1155 IONIC_PORT_PAUSE_TYPE_LINK = 1, 1156 IONIC_PORT_PAUSE_TYPE_PFC = 2, 1157 }; 1158 1159 /** 1160 * enum ionic_port_loopback_mode - Loopback modes 1161 * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1162 * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1163 * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1164 */ 1165 enum ionic_port_loopback_mode { 1166 IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1167 IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1168 IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1169 }; 1170 1171 /** 1172 * struct ionic_xcvr_status - Transceiver Status information 1173 * @state: Transceiver status (enum ionic_xcvr_state) 1174 * @phy: Physical connection type (enum ionic_phy_type) 1175 * @pid: Transceiver link mode (enum pid) 1176 * @sprom: Transceiver sprom contents 1177 */ 1178 struct ionic_xcvr_status { 1179 u8 state; 1180 u8 phy; 1181 __le16 pid; 1182 u8 sprom[256]; 1183 }; 1184 1185 /** 1186 * union ionic_port_config - Port configuration 1187 * @speed: port speed (in Mbps) 1188 * @mtu: mtu 1189 * @state: port admin state (enum port_admin_state) 1190 * @an_enable: autoneg enable 1191 * @fec_type: fec type (enum ionic_port_fec_type) 1192 * @pause_type: pause type (enum ionic_port_pause_type) 1193 * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1194 */ 1195 union ionic_port_config { 1196 struct { 1197 #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1198 #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1199 #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1200 #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1201 #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1202 #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1203 __le32 speed; 1204 __le32 mtu; 1205 u8 state; 1206 u8 an_enable; 1207 u8 fec_type; 1208 #define IONIC_PAUSE_TYPE_MASK 0x0f 1209 #define IONIC_PAUSE_FLAGS_MASK 0xf0 1210 #define IONIC_PAUSE_F_TX 0x10 1211 #define IONIC_PAUSE_F_RX 0x20 1212 u8 pause_type; 1213 u8 loopback_mode; 1214 }; 1215 __le32 words[64]; 1216 }; 1217 1218 /** 1219 * struct ionic_port_status - Port Status information 1220 * @status: link status (enum ionic_port_oper_status) 1221 * @id: port id 1222 * @speed: link speed (in Mbps) 1223 * @link_down_count: number of times link went from from up to down 1224 * @fec_type: fec type (enum ionic_port_fec_type) 1225 * @xcvr: tranceiver status 1226 */ 1227 struct ionic_port_status { 1228 __le32 id; 1229 __le32 speed; 1230 u8 status; 1231 __le16 link_down_count; 1232 u8 fec_type; 1233 u8 rsvd[48]; 1234 struct ionic_xcvr_status xcvr; 1235 } __packed; 1236 1237 /** 1238 * struct ionic_port_identify_cmd - Port identify command 1239 * @opcode: opcode 1240 * @index: port index 1241 * @ver: Highest version of identify supported by driver 1242 */ 1243 struct ionic_port_identify_cmd { 1244 u8 opcode; 1245 u8 index; 1246 u8 ver; 1247 u8 rsvd[61]; 1248 }; 1249 1250 /** 1251 * struct ionic_port_identify_comp - Port identify command completion 1252 * @status: Status of the command (enum ionic_status_code) 1253 * @ver: Version of identify returned by device 1254 */ 1255 struct ionic_port_identify_comp { 1256 u8 status; 1257 u8 ver; 1258 u8 rsvd[14]; 1259 }; 1260 1261 /** 1262 * struct ionic_port_init_cmd - Port initialization command 1263 * @opcode: opcode 1264 * @index: port index 1265 * @info_pa: destination address for port info (struct ionic_port_info) 1266 */ 1267 struct ionic_port_init_cmd { 1268 u8 opcode; 1269 u8 index; 1270 u8 rsvd[6]; 1271 __le64 info_pa; 1272 u8 rsvd2[48]; 1273 }; 1274 1275 /** 1276 * struct ionic_port_init_comp - Port initialization command completion 1277 * @status: Status of the command (enum ionic_status_code) 1278 */ 1279 struct ionic_port_init_comp { 1280 u8 status; 1281 u8 rsvd[15]; 1282 }; 1283 1284 /** 1285 * struct ionic_port_reset_cmd - Port reset command 1286 * @opcode: opcode 1287 * @index: port index 1288 */ 1289 struct ionic_port_reset_cmd { 1290 u8 opcode; 1291 u8 index; 1292 u8 rsvd[62]; 1293 }; 1294 1295 /** 1296 * struct ionic_port_reset_comp - Port reset command completion 1297 * @status: Status of the command (enum ionic_status_code) 1298 */ 1299 struct ionic_port_reset_comp { 1300 u8 status; 1301 u8 rsvd[15]; 1302 }; 1303 1304 /** 1305 * enum ionic_stats_ctl_cmd - List of commands for stats control 1306 * @IONIC_STATS_CTL_RESET: Reset statistics 1307 */ 1308 enum ionic_stats_ctl_cmd { 1309 IONIC_STATS_CTL_RESET = 0, 1310 }; 1311 1312 /** 1313 * enum ionic_port_attr - List of device attributes 1314 * @IONIC_PORT_ATTR_STATE: Port state attribute 1315 * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1316 * @IONIC_PORT_ATTR_MTU: Port MTU attribute 1317 * @IONIC_PORT_ATTR_AUTONEG: Port autonegotation attribute 1318 * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1319 * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1320 * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1321 * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1322 */ 1323 enum ionic_port_attr { 1324 IONIC_PORT_ATTR_STATE = 0, 1325 IONIC_PORT_ATTR_SPEED = 1, 1326 IONIC_PORT_ATTR_MTU = 2, 1327 IONIC_PORT_ATTR_AUTONEG = 3, 1328 IONIC_PORT_ATTR_FEC = 4, 1329 IONIC_PORT_ATTR_PAUSE = 5, 1330 IONIC_PORT_ATTR_LOOPBACK = 6, 1331 IONIC_PORT_ATTR_STATS_CTRL = 7, 1332 }; 1333 1334 /** 1335 * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1336 * @opcode: Opcode 1337 * @index: Port index 1338 * @attr: Attribute type (enum ionic_port_attr) 1339 * @state: Port state 1340 * @speed: Port speed 1341 * @mtu: Port MTU 1342 * @an_enable: Port autonegotiation setting 1343 * @fec_type: Port FEC type setting 1344 * @pause_type: Port pause type setting 1345 * @loopback_mode: Port loopback mode 1346 * @stats_ctl: Port stats setting 1347 */ 1348 struct ionic_port_setattr_cmd { 1349 u8 opcode; 1350 u8 index; 1351 u8 attr; 1352 u8 rsvd; 1353 union { 1354 u8 state; 1355 __le32 speed; 1356 __le32 mtu; 1357 u8 an_enable; 1358 u8 fec_type; 1359 u8 pause_type; 1360 u8 loopback_mode; 1361 u8 stats_ctl; 1362 u8 rsvd2[60]; 1363 }; 1364 }; 1365 1366 /** 1367 * struct ionic_port_setattr_comp - Port set attr command completion 1368 * @status: Status of the command (enum ionic_status_code) 1369 * @color: Color bit 1370 */ 1371 struct ionic_port_setattr_comp { 1372 u8 status; 1373 u8 rsvd[14]; 1374 u8 color; 1375 }; 1376 1377 /** 1378 * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1379 * @opcode: Opcode 1380 * @index: port index 1381 * @attr: Attribute type (enum ionic_port_attr) 1382 */ 1383 struct ionic_port_getattr_cmd { 1384 u8 opcode; 1385 u8 index; 1386 u8 attr; 1387 u8 rsvd[61]; 1388 }; 1389 1390 /** 1391 * struct ionic_port_getattr_comp - Port get attr command completion 1392 * @status: Status of the command (enum ionic_status_code) 1393 * @state: Port state 1394 * @speed: Port speed 1395 * @mtu: Port MTU 1396 * @an_enable: Port autonegotiation setting 1397 * @fec_type: Port FEC type setting 1398 * @pause_type: Port pause type setting 1399 * @loopback_mode: Port loopback mode 1400 * @color: Color bit 1401 */ 1402 struct ionic_port_getattr_comp { 1403 u8 status; 1404 u8 rsvd[3]; 1405 union { 1406 u8 state; 1407 __le32 speed; 1408 __le32 mtu; 1409 u8 an_enable; 1410 u8 fec_type; 1411 u8 pause_type; 1412 u8 loopback_mode; 1413 u8 rsvd2[11]; 1414 } __packed; 1415 u8 color; 1416 }; 1417 1418 /** 1419 * struct ionic_lif_status - LIF status register 1420 * @eid: most recent NotifyQ event id 1421 * @port_num: port the LIF is connected to 1422 * @link_status: port status (enum ionic_port_oper_status) 1423 * @link_speed: speed of link in Mbps 1424 * @link_down_count: number of times link went from up to down 1425 */ 1426 struct ionic_lif_status { 1427 __le64 eid; 1428 u8 port_num; 1429 u8 rsvd; 1430 __le16 link_status; 1431 __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1432 __le16 link_down_count; 1433 u8 rsvd2[46]; 1434 }; 1435 1436 /** 1437 * struct ionic_lif_reset_cmd - LIF reset command 1438 * @opcode: opcode 1439 * @index: LIF index 1440 */ 1441 struct ionic_lif_reset_cmd { 1442 u8 opcode; 1443 u8 rsvd; 1444 __le16 index; 1445 __le32 rsvd2[15]; 1446 }; 1447 1448 typedef struct ionic_admin_comp ionic_lif_reset_comp; 1449 1450 enum ionic_dev_state { 1451 IONIC_DEV_DISABLE = 0, 1452 IONIC_DEV_ENABLE = 1, 1453 IONIC_DEV_HANG_RESET = 2, 1454 }; 1455 1456 /** 1457 * enum ionic_dev_attr - List of device attributes 1458 * @IONIC_DEV_ATTR_STATE: Device state attribute 1459 * @IONIC_DEV_ATTR_NAME: Device name attribute 1460 * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1461 */ 1462 enum ionic_dev_attr { 1463 IONIC_DEV_ATTR_STATE = 0, 1464 IONIC_DEV_ATTR_NAME = 1, 1465 IONIC_DEV_ATTR_FEATURES = 2, 1466 }; 1467 1468 /** 1469 * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1470 * @opcode: Opcode 1471 * @attr: Attribute type (enum ionic_dev_attr) 1472 * @state: Device state (enum ionic_dev_state) 1473 * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1474 * @features: Device features 1475 */ 1476 struct ionic_dev_setattr_cmd { 1477 u8 opcode; 1478 u8 attr; 1479 __le16 rsvd; 1480 union { 1481 u8 state; 1482 char name[IONIC_IFNAMSIZ]; 1483 __le64 features; 1484 u8 rsvd2[60]; 1485 } __packed; 1486 }; 1487 1488 /** 1489 * struct ionic_dev_setattr_comp - Device set attr command completion 1490 * @status: Status of the command (enum ionic_status_code) 1491 * @features: Device features 1492 * @color: Color bit 1493 */ 1494 struct ionic_dev_setattr_comp { 1495 u8 status; 1496 u8 rsvd[3]; 1497 union { 1498 __le64 features; 1499 u8 rsvd2[11]; 1500 } __packed; 1501 u8 color; 1502 }; 1503 1504 /** 1505 * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1506 * @opcode: opcode 1507 * @attr: Attribute type (enum ionic_dev_attr) 1508 */ 1509 struct ionic_dev_getattr_cmd { 1510 u8 opcode; 1511 u8 attr; 1512 u8 rsvd[62]; 1513 }; 1514 1515 /** 1516 * struct ionic_dev_setattr_comp - Device set attr command completion 1517 * @status: Status of the command (enum ionic_status_code) 1518 * @features: Device features 1519 * @color: Color bit 1520 */ 1521 struct ionic_dev_getattr_comp { 1522 u8 status; 1523 u8 rsvd[3]; 1524 union { 1525 __le64 features; 1526 u8 rsvd2[11]; 1527 } __packed; 1528 u8 color; 1529 }; 1530 1531 /** 1532 * RSS parameters 1533 */ 1534 #define IONIC_RSS_HASH_KEY_SIZE 40 1535 1536 enum ionic_rss_hash_types { 1537 IONIC_RSS_TYPE_IPV4 = BIT(0), 1538 IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1539 IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1540 IONIC_RSS_TYPE_IPV6 = BIT(3), 1541 IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1542 IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1543 }; 1544 1545 /** 1546 * enum ionic_lif_attr - List of LIF attributes 1547 * @IONIC_LIF_ATTR_STATE: LIF state attribute 1548 * @IONIC_LIF_ATTR_NAME: LIF name attribute 1549 * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1550 * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1551 * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1552 * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1553 * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 1554 */ 1555 enum ionic_lif_attr { 1556 IONIC_LIF_ATTR_STATE = 0, 1557 IONIC_LIF_ATTR_NAME = 1, 1558 IONIC_LIF_ATTR_MTU = 2, 1559 IONIC_LIF_ATTR_MAC = 3, 1560 IONIC_LIF_ATTR_FEATURES = 4, 1561 IONIC_LIF_ATTR_RSS = 5, 1562 IONIC_LIF_ATTR_STATS_CTRL = 6, 1563 }; 1564 1565 /** 1566 * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1567 * @opcode: Opcode 1568 * @attr: Attribute type (enum ionic_lif_attr) 1569 * @index: LIF index 1570 * @state: LIF state (enum ionic_lif_state) 1571 * @name: The netdev name string, 0 terminated 1572 * @mtu: Mtu 1573 * @mac: Station mac 1574 * @features: Features (enum ionic_eth_hw_features) 1575 * @rss: RSS properties 1576 * @types: The hash types to enable (see rss_hash_types) 1577 * @key: The hash secret key 1578 * @addr: Address for the indirection table shared memory 1579 * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 1580 */ 1581 struct ionic_lif_setattr_cmd { 1582 u8 opcode; 1583 u8 attr; 1584 __le16 index; 1585 union { 1586 u8 state; 1587 char name[IONIC_IFNAMSIZ]; 1588 __le32 mtu; 1589 u8 mac[6]; 1590 __le64 features; 1591 struct { 1592 __le16 types; 1593 u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1594 u8 rsvd[6]; 1595 __le64 addr; 1596 } rss; 1597 u8 stats_ctl; 1598 u8 rsvd[60]; 1599 } __packed; 1600 }; 1601 1602 /** 1603 * struct ionic_lif_setattr_comp - LIF set attr command completion 1604 * @status: Status of the command (enum ionic_status_code) 1605 * @comp_index: Index in the descriptor ring for which this is the completion 1606 * @features: features (enum ionic_eth_hw_features) 1607 * @color: Color bit 1608 */ 1609 struct ionic_lif_setattr_comp { 1610 u8 status; 1611 u8 rsvd; 1612 __le16 comp_index; 1613 union { 1614 __le64 features; 1615 u8 rsvd2[11]; 1616 } __packed; 1617 u8 color; 1618 }; 1619 1620 /** 1621 * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1622 * @opcode: Opcode 1623 * @attr: Attribute type (enum ionic_lif_attr) 1624 * @index: LIF index 1625 */ 1626 struct ionic_lif_getattr_cmd { 1627 u8 opcode; 1628 u8 attr; 1629 __le16 index; 1630 u8 rsvd[60]; 1631 }; 1632 1633 /** 1634 * struct ionic_lif_getattr_comp - LIF get attr command completion 1635 * @status: Status of the command (enum ionic_status_code) 1636 * @comp_index: Index in the descriptor ring for which this is the completion 1637 * @state: LIF state (enum ionic_lif_state) 1638 * @name: The netdev name string, 0 terminated 1639 * @mtu: Mtu 1640 * @mac: Station mac 1641 * @features: Features (enum ionic_eth_hw_features) 1642 * @color: Color bit 1643 */ 1644 struct ionic_lif_getattr_comp { 1645 u8 status; 1646 u8 rsvd; 1647 __le16 comp_index; 1648 union { 1649 u8 state; 1650 __le32 mtu; 1651 u8 mac[6]; 1652 __le64 features; 1653 u8 rsvd2[11]; 1654 } __packed; 1655 u8 color; 1656 }; 1657 1658 enum ionic_rx_mode { 1659 IONIC_RX_MODE_F_UNICAST = BIT(0), 1660 IONIC_RX_MODE_F_MULTICAST = BIT(1), 1661 IONIC_RX_MODE_F_BROADCAST = BIT(2), 1662 IONIC_RX_MODE_F_PROMISC = BIT(3), 1663 IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1664 IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1665 }; 1666 1667 /** 1668 * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1669 * @opcode: opcode 1670 * @lif_index: LIF index 1671 * @rx_mode: Rx mode flags: 1672 * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1673 * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1674 * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1675 * IONIC_RX_MODE_F_PROMISC: Accept any packets 1676 * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1677 * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1678 */ 1679 struct ionic_rx_mode_set_cmd { 1680 u8 opcode; 1681 u8 rsvd; 1682 __le16 lif_index; 1683 __le16 rx_mode; 1684 __le16 rsvd2[29]; 1685 }; 1686 1687 typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1688 1689 enum ionic_rx_filter_match_type { 1690 IONIC_RX_FILTER_MATCH_VLAN = 0, 1691 IONIC_RX_FILTER_MATCH_MAC, 1692 IONIC_RX_FILTER_MATCH_MAC_VLAN, 1693 }; 1694 1695 /** 1696 * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1697 * @opcode: opcode 1698 * @qtype: Queue type 1699 * @lif_index: LIF index 1700 * @qid: Queue ID 1701 * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1702 * @vlan: VLAN filter 1703 * @vlan: VLAN ID 1704 * @mac: MAC filter 1705 * @addr: MAC address (network-byte order) 1706 * @mac_vlan: MACVLAN filter 1707 * @vlan: VLAN ID 1708 * @addr: MAC address (network-byte order) 1709 */ 1710 struct ionic_rx_filter_add_cmd { 1711 u8 opcode; 1712 u8 qtype; 1713 __le16 lif_index; 1714 __le32 qid; 1715 __le16 match; 1716 union { 1717 struct { 1718 __le16 vlan; 1719 } vlan; 1720 struct { 1721 u8 addr[6]; 1722 } mac; 1723 struct { 1724 __le16 vlan; 1725 u8 addr[6]; 1726 } mac_vlan; 1727 u8 rsvd[54]; 1728 }; 1729 }; 1730 1731 /** 1732 * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1733 * @status: Status of the command (enum ionic_status_code) 1734 * @comp_index: Index in the descriptor ring for which this is the completion 1735 * @filter_id: Filter ID 1736 * @color: Color bit 1737 */ 1738 struct ionic_rx_filter_add_comp { 1739 u8 status; 1740 u8 rsvd; 1741 __le16 comp_index; 1742 __le32 filter_id; 1743 u8 rsvd2[7]; 1744 u8 color; 1745 }; 1746 1747 /** 1748 * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1749 * @opcode: opcode 1750 * @lif_index: LIF index 1751 * @filter_id: Filter ID 1752 */ 1753 struct ionic_rx_filter_del_cmd { 1754 u8 opcode; 1755 u8 rsvd; 1756 __le16 lif_index; 1757 __le32 filter_id; 1758 u8 rsvd2[56]; 1759 }; 1760 1761 typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1762 1763 enum ionic_vf_attr { 1764 IONIC_VF_ATTR_SPOOFCHK = 1, 1765 IONIC_VF_ATTR_TRUST = 2, 1766 IONIC_VF_ATTR_MAC = 3, 1767 IONIC_VF_ATTR_LINKSTATE = 4, 1768 IONIC_VF_ATTR_VLAN = 5, 1769 IONIC_VF_ATTR_RATE = 6, 1770 IONIC_VF_ATTR_STATSADDR = 7, 1771 }; 1772 1773 /** 1774 * enum ionic_vf_link_status - Virtual Function link status 1775 * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1776 * @IONIC_VF_LINK_STATUS_UP: Link always up 1777 * @IONIC_VF_LINK_STATUS_DOWN: Link always down 1778 */ 1779 enum ionic_vf_link_status { 1780 IONIC_VF_LINK_STATUS_AUTO = 0, 1781 IONIC_VF_LINK_STATUS_UP = 1, 1782 IONIC_VF_LINK_STATUS_DOWN = 2, 1783 }; 1784 1785 /** 1786 * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 1787 * @opcode: Opcode 1788 * @attr: Attribute type (enum ionic_vf_attr) 1789 * @vf_index: VF index 1790 * @macaddr: mac address 1791 * @vlanid: vlan ID 1792 * @maxrate: max Tx rate in Mbps 1793 * @spoofchk: enable address spoof checking 1794 * @trust: enable VF trust 1795 * @linkstate: set link up or down 1796 * @stats_pa: set DMA address for VF stats 1797 */ 1798 struct ionic_vf_setattr_cmd { 1799 u8 opcode; 1800 u8 attr; 1801 __le16 vf_index; 1802 union { 1803 u8 macaddr[6]; 1804 __le16 vlanid; 1805 __le32 maxrate; 1806 u8 spoofchk; 1807 u8 trust; 1808 u8 linkstate; 1809 __le64 stats_pa; 1810 u8 pad[60]; 1811 } __packed; 1812 }; 1813 1814 struct ionic_vf_setattr_comp { 1815 u8 status; 1816 u8 attr; 1817 __le16 vf_index; 1818 __le16 comp_index; 1819 u8 rsvd[9]; 1820 u8 color; 1821 }; 1822 1823 /** 1824 * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 1825 * @opcode: Opcode 1826 * @attr: Attribute type (enum ionic_vf_attr) 1827 * @vf_index: VF index 1828 */ 1829 struct ionic_vf_getattr_cmd { 1830 u8 opcode; 1831 u8 attr; 1832 __le16 vf_index; 1833 u8 rsvd[60]; 1834 }; 1835 1836 struct ionic_vf_getattr_comp { 1837 u8 status; 1838 u8 attr; 1839 __le16 vf_index; 1840 union { 1841 u8 macaddr[6]; 1842 __le16 vlanid; 1843 __le32 maxrate; 1844 u8 spoofchk; 1845 u8 trust; 1846 u8 linkstate; 1847 __le64 stats_pa; 1848 u8 pad[11]; 1849 } __packed; 1850 u8 color; 1851 }; 1852 1853 /** 1854 * struct ionic_qos_identify_cmd - QoS identify command 1855 * @opcode: opcode 1856 * @ver: Highest version of identify supported by driver 1857 * 1858 */ 1859 struct ionic_qos_identify_cmd { 1860 u8 opcode; 1861 u8 ver; 1862 u8 rsvd[62]; 1863 }; 1864 1865 /** 1866 * struct ionic_qos_identify_comp - QoS identify command completion 1867 * @status: Status of the command (enum ionic_status_code) 1868 * @ver: Version of identify returned by device 1869 */ 1870 struct ionic_qos_identify_comp { 1871 u8 status; 1872 u8 ver; 1873 u8 rsvd[14]; 1874 }; 1875 1876 #define IONIC_QOS_TC_MAX 8 1877 /* Capri max supported, should be renamed. */ 1878 #define IONIC_QOS_CLASS_MAX 7 1879 #define IONIC_QOS_PCP_MAX 8 1880 #define IONIC_QOS_CLASS_NAME_SZ 32 1881 #define IONIC_QOS_DSCP_MAX 64 1882 #define IONIC_QOS_ALL_PCP 0xFF 1883 1884 /** 1885 * enum ionic_qos_class 1886 */ 1887 enum ionic_qos_class { 1888 IONIC_QOS_CLASS_DEFAULT = 0, 1889 IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 1890 IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 1891 IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 1892 IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 1893 IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 1894 IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 1895 }; 1896 1897 /** 1898 * enum ionic_qos_class_type - Traffic classification criteria 1899 * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 1900 * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 1901 * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 1902 */ 1903 enum ionic_qos_class_type { 1904 IONIC_QOS_CLASS_TYPE_NONE = 0, 1905 IONIC_QOS_CLASS_TYPE_PCP = 1, 1906 IONIC_QOS_CLASS_TYPE_DSCP = 2, 1907 }; 1908 1909 /** 1910 * enum ionic_qos_sched_type - QoS class scheduling type 1911 * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 1912 * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 1913 */ 1914 enum ionic_qos_sched_type { 1915 IONIC_QOS_SCHED_TYPE_STRICT = 0, 1916 IONIC_QOS_SCHED_TYPE_DWRR = 1, 1917 }; 1918 1919 /** 1920 * union ionic_qos_config - QoS configuration structure 1921 * @flags: Configuration flags 1922 * IONIC_QOS_CONFIG_F_ENABLE enable 1923 * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 1924 * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 1925 * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 1926 * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 1927 * @class_type: QoS class type (enum ionic_qos_class_type) 1928 * @pause_type: QoS pause type (enum ionic_qos_pause_type) 1929 * @name: QoS class name 1930 * @mtu: MTU of the class 1931 * @pfc_cos: Priority-Flow Control class of service 1932 * @dwrr_weight: QoS class scheduling weight 1933 * @strict_rlmt: Rate limit for strict priority scheduling 1934 * @rw_dot1q_pcp: Rewrite dot1q pcp to this value (valid iff F_RW_DOT1Q_PCP) 1935 * @rw_ip_dscp: Rewrite ip dscp to this value (valid iff F_RW_IP_DSCP) 1936 * @dot1q_pcp: Dot1q pcp value 1937 * @ndscp: Number of valid dscp values in the ip_dscp field 1938 * @ip_dscp: IP dscp values 1939 */ 1940 union ionic_qos_config { 1941 struct { 1942 #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 1943 #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 1944 /* Used to rewrite PCP or DSCP value. */ 1945 #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 1946 #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 1947 u8 flags; 1948 u8 sched_type; 1949 u8 class_type; 1950 u8 pause_type; 1951 char name[IONIC_QOS_CLASS_NAME_SZ]; 1952 __le32 mtu; 1953 /* flow control */ 1954 u8 pfc_cos; 1955 /* scheduler */ 1956 union { 1957 u8 dwrr_weight; 1958 __le64 strict_rlmt; 1959 }; 1960 /* marking */ 1961 /* Used to rewrite PCP or DSCP value. */ 1962 union { 1963 u8 rw_dot1q_pcp; 1964 u8 rw_ip_dscp; 1965 }; 1966 /* classification */ 1967 union { 1968 u8 dot1q_pcp; 1969 struct { 1970 u8 ndscp; 1971 u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 1972 }; 1973 }; 1974 }; 1975 __le32 words[64]; 1976 }; 1977 1978 /** 1979 * union ionic_qos_identity - QoS identity structure 1980 * @version: Version of the identify structure 1981 * @type: QoS system type 1982 * @nclasses: Number of usable QoS classes 1983 * @config: Current configuration of classes 1984 */ 1985 union ionic_qos_identity { 1986 struct { 1987 u8 version; 1988 u8 type; 1989 u8 rsvd[62]; 1990 union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 1991 }; 1992 __le32 words[478]; 1993 }; 1994 1995 /** 1996 * struct ionic_qos_init_cmd - QoS config init command 1997 * @opcode: Opcode 1998 * @group: QoS class id 1999 * @info_pa: destination address for qos info 2000 */ 2001 struct ionic_qos_init_cmd { 2002 u8 opcode; 2003 u8 group; 2004 u8 rsvd[6]; 2005 __le64 info_pa; 2006 u8 rsvd1[48]; 2007 }; 2008 2009 typedef struct ionic_admin_comp ionic_qos_init_comp; 2010 2011 /** 2012 * struct ionic_qos_reset_cmd - QoS config reset command 2013 * @opcode: Opcode 2014 * @group: QoS class id 2015 */ 2016 struct ionic_qos_reset_cmd { 2017 u8 opcode; 2018 u8 group; 2019 u8 rsvd[62]; 2020 }; 2021 2022 typedef struct ionic_admin_comp ionic_qos_reset_comp; 2023 2024 /** 2025 * struct ionic_fw_download_cmd - Firmware download command 2026 * @opcode: opcode 2027 * @addr: dma address of the firmware buffer 2028 * @offset: offset of the firmware buffer within the full image 2029 * @length: number of valid bytes in the firmware buffer 2030 */ 2031 struct ionic_fw_download_cmd { 2032 u8 opcode; 2033 u8 rsvd[3]; 2034 __le32 offset; 2035 __le64 addr; 2036 __le32 length; 2037 }; 2038 2039 typedef struct ionic_admin_comp ionic_fw_download_comp; 2040 2041 /** 2042 * enum ionic_fw_control_oper - FW control operations 2043 * @IONIC_FW_RESET: Reset firmware 2044 * @IONIC_FW_INSTALL: Install firmware 2045 * @IONIC_FW_ACTIVATE: Activate firmware 2046 */ 2047 enum ionic_fw_control_oper { 2048 IONIC_FW_RESET = 0, 2049 IONIC_FW_INSTALL = 1, 2050 IONIC_FW_ACTIVATE = 2, 2051 }; 2052 2053 /** 2054 * struct ionic_fw_control_cmd - Firmware control command 2055 * @opcode: opcode 2056 * @oper: firmware control operation (enum ionic_fw_control_oper) 2057 * @slot: slot to activate 2058 */ 2059 struct ionic_fw_control_cmd { 2060 u8 opcode; 2061 u8 rsvd[3]; 2062 u8 oper; 2063 u8 slot; 2064 u8 rsvd1[58]; 2065 }; 2066 2067 /** 2068 * struct ionic_fw_control_comp - Firmware control copletion 2069 * @status: Status of the command (enum ionic_status_code) 2070 * @comp_index: Index in the descriptor ring for which this is the completion 2071 * @slot: Slot where the firmware was installed 2072 * @color: Color bit 2073 */ 2074 struct ionic_fw_control_comp { 2075 u8 status; 2076 u8 rsvd; 2077 __le16 comp_index; 2078 u8 slot; 2079 u8 rsvd1[10]; 2080 u8 color; 2081 }; 2082 2083 /****************************************************************** 2084 ******************* RDMA Commands ******************************** 2085 ******************************************************************/ 2086 2087 /** 2088 * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2089 * @opcode: opcode 2090 * @lif_index: LIF index 2091 * 2092 * There is no RDMA specific dev command completion struct. Completion uses 2093 * the common struct ionic_admin_comp. Only the status is indicated. 2094 * Nonzero status means the LIF does not support RDMA. 2095 **/ 2096 struct ionic_rdma_reset_cmd { 2097 u8 opcode; 2098 u8 rsvd; 2099 __le16 lif_index; 2100 u8 rsvd2[60]; 2101 }; 2102 2103 /** 2104 * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2105 * @opcode: opcode, 52, 53 2106 * @lif_index: LIF index 2107 * @qid_ver: (qid | (RDMA version << 24)) 2108 * @cid: intr, eq_id, or cq_id 2109 * @dbid: doorbell page id 2110 * @depth_log2: log base two of queue depth 2111 * @stride_log2: log base two of queue stride 2112 * @dma_addr: address of the queue memory 2113 * 2114 * The same command struct is used to create an RDMA event queue, completion 2115 * queue, or RDMA admin queue. The cid is an interrupt number for an event 2116 * queue, an event queue id for a completion queue, or a completion queue id 2117 * for an RDMA admin queue. 2118 * 2119 * The queue created via a dev command must be contiguous in dma space. 2120 * 2121 * The dev commands are intended only to be used during driver initialization, 2122 * to create queues supporting the RDMA admin queue. Other queues, and other 2123 * types of RDMA resources like memory regions, will be created and registered 2124 * via the RDMA admin queue, and will support a more complete interface 2125 * providing scatter gather lists for larger, scattered queue buffers and 2126 * memory registration. 2127 * 2128 * There is no RDMA specific dev command completion struct. Completion uses 2129 * the common struct ionic_admin_comp. Only the status is indicated. 2130 **/ 2131 struct ionic_rdma_queue_cmd { 2132 u8 opcode; 2133 u8 rsvd; 2134 __le16 lif_index; 2135 __le32 qid_ver; 2136 __le32 cid; 2137 __le16 dbid; 2138 u8 depth_log2; 2139 u8 stride_log2; 2140 __le64 dma_addr; 2141 u8 rsvd2[40]; 2142 }; 2143 2144 /****************************************************************** 2145 ******************* Notify Events ******************************** 2146 ******************************************************************/ 2147 2148 /** 2149 * struct ionic_notifyq_event - Generic event reporting structure 2150 * @eid: event number 2151 * @ecode: event code 2152 * @data: unspecified data about the event 2153 * 2154 * This is the generic event report struct from which the other 2155 * actual events will be formed. 2156 */ 2157 struct ionic_notifyq_event { 2158 __le64 eid; 2159 __le16 ecode; 2160 u8 data[54]; 2161 }; 2162 2163 /** 2164 * struct ionic_link_change_event - Link change event notification 2165 * @eid: event number 2166 * @ecode: event code = IONIC_EVENT_LINK_CHANGE 2167 * @link_status: link up or down, with error bits (enum port_status) 2168 * @link_speed: speed of the network link 2169 * 2170 * Sent when the network link state changes between UP and DOWN 2171 */ 2172 struct ionic_link_change_event { 2173 __le64 eid; 2174 __le16 ecode; 2175 __le16 link_status; 2176 __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2177 u8 rsvd[48]; 2178 }; 2179 2180 /** 2181 * struct ionic_reset_event - Reset event notification 2182 * @eid: event number 2183 * @ecode: event code = IONIC_EVENT_RESET 2184 * @reset_code: reset type 2185 * @state: 0=pending, 1=complete, 2=error 2186 * 2187 * Sent when the NIC or some subsystem is going to be or 2188 * has been reset. 2189 */ 2190 struct ionic_reset_event { 2191 __le64 eid; 2192 __le16 ecode; 2193 u8 reset_code; 2194 u8 state; 2195 u8 rsvd[52]; 2196 }; 2197 2198 /** 2199 * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2200 * @eid: event number 2201 * @ecode: event code = IONIC_EVENT_HEARTBEAT 2202 */ 2203 struct ionic_heartbeat_event { 2204 __le64 eid; 2205 __le16 ecode; 2206 u8 rsvd[54]; 2207 }; 2208 2209 /** 2210 * struct ionic_log_event - Sent to notify the driver of an internal error 2211 * @eid: event number 2212 * @ecode: event code = IONIC_EVENT_LOG 2213 * @data: log data 2214 */ 2215 struct ionic_log_event { 2216 __le64 eid; 2217 __le16 ecode; 2218 u8 data[54]; 2219 }; 2220 2221 /** 2222 * struct ionic_xcvr_event - Transceiver change event 2223 * @eid: event number 2224 * @ecode: event code = IONIC_EVENT_XCVR 2225 */ 2226 struct ionic_xcvr_event { 2227 __le64 eid; 2228 __le16 ecode; 2229 u8 rsvd[54]; 2230 }; 2231 2232 /** 2233 * struct ionic_port_stats - Port statistics structure 2234 */ 2235 struct ionic_port_stats { 2236 __le64 frames_rx_ok; 2237 __le64 frames_rx_all; 2238 __le64 frames_rx_bad_fcs; 2239 __le64 frames_rx_bad_all; 2240 __le64 octets_rx_ok; 2241 __le64 octets_rx_all; 2242 __le64 frames_rx_unicast; 2243 __le64 frames_rx_multicast; 2244 __le64 frames_rx_broadcast; 2245 __le64 frames_rx_pause; 2246 __le64 frames_rx_bad_length; 2247 __le64 frames_rx_undersized; 2248 __le64 frames_rx_oversized; 2249 __le64 frames_rx_fragments; 2250 __le64 frames_rx_jabber; 2251 __le64 frames_rx_pripause; 2252 __le64 frames_rx_stomped_crc; 2253 __le64 frames_rx_too_long; 2254 __le64 frames_rx_vlan_good; 2255 __le64 frames_rx_dropped; 2256 __le64 frames_rx_less_than_64b; 2257 __le64 frames_rx_64b; 2258 __le64 frames_rx_65b_127b; 2259 __le64 frames_rx_128b_255b; 2260 __le64 frames_rx_256b_511b; 2261 __le64 frames_rx_512b_1023b; 2262 __le64 frames_rx_1024b_1518b; 2263 __le64 frames_rx_1519b_2047b; 2264 __le64 frames_rx_2048b_4095b; 2265 __le64 frames_rx_4096b_8191b; 2266 __le64 frames_rx_8192b_9215b; 2267 __le64 frames_rx_other; 2268 __le64 frames_tx_ok; 2269 __le64 frames_tx_all; 2270 __le64 frames_tx_bad; 2271 __le64 octets_tx_ok; 2272 __le64 octets_tx_total; 2273 __le64 frames_tx_unicast; 2274 __le64 frames_tx_multicast; 2275 __le64 frames_tx_broadcast; 2276 __le64 frames_tx_pause; 2277 __le64 frames_tx_pripause; 2278 __le64 frames_tx_vlan; 2279 __le64 frames_tx_less_than_64b; 2280 __le64 frames_tx_64b; 2281 __le64 frames_tx_65b_127b; 2282 __le64 frames_tx_128b_255b; 2283 __le64 frames_tx_256b_511b; 2284 __le64 frames_tx_512b_1023b; 2285 __le64 frames_tx_1024b_1518b; 2286 __le64 frames_tx_1519b_2047b; 2287 __le64 frames_tx_2048b_4095b; 2288 __le64 frames_tx_4096b_8191b; 2289 __le64 frames_tx_8192b_9215b; 2290 __le64 frames_tx_other; 2291 __le64 frames_tx_pri_0; 2292 __le64 frames_tx_pri_1; 2293 __le64 frames_tx_pri_2; 2294 __le64 frames_tx_pri_3; 2295 __le64 frames_tx_pri_4; 2296 __le64 frames_tx_pri_5; 2297 __le64 frames_tx_pri_6; 2298 __le64 frames_tx_pri_7; 2299 __le64 frames_rx_pri_0; 2300 __le64 frames_rx_pri_1; 2301 __le64 frames_rx_pri_2; 2302 __le64 frames_rx_pri_3; 2303 __le64 frames_rx_pri_4; 2304 __le64 frames_rx_pri_5; 2305 __le64 frames_rx_pri_6; 2306 __le64 frames_rx_pri_7; 2307 __le64 tx_pripause_0_1us_count; 2308 __le64 tx_pripause_1_1us_count; 2309 __le64 tx_pripause_2_1us_count; 2310 __le64 tx_pripause_3_1us_count; 2311 __le64 tx_pripause_4_1us_count; 2312 __le64 tx_pripause_5_1us_count; 2313 __le64 tx_pripause_6_1us_count; 2314 __le64 tx_pripause_7_1us_count; 2315 __le64 rx_pripause_0_1us_count; 2316 __le64 rx_pripause_1_1us_count; 2317 __le64 rx_pripause_2_1us_count; 2318 __le64 rx_pripause_3_1us_count; 2319 __le64 rx_pripause_4_1us_count; 2320 __le64 rx_pripause_5_1us_count; 2321 __le64 rx_pripause_6_1us_count; 2322 __le64 rx_pripause_7_1us_count; 2323 __le64 rx_pause_1us_count; 2324 __le64 frames_tx_truncated; 2325 }; 2326 2327 struct ionic_mgmt_port_stats { 2328 __le64 frames_rx_ok; 2329 __le64 frames_rx_all; 2330 __le64 frames_rx_bad_fcs; 2331 __le64 frames_rx_bad_all; 2332 __le64 octets_rx_ok; 2333 __le64 octets_rx_all; 2334 __le64 frames_rx_unicast; 2335 __le64 frames_rx_multicast; 2336 __le64 frames_rx_broadcast; 2337 __le64 frames_rx_pause; 2338 __le64 frames_rx_bad_length; 2339 __le64 frames_rx_undersized; 2340 __le64 frames_rx_oversized; 2341 __le64 frames_rx_fragments; 2342 __le64 frames_rx_jabber; 2343 __le64 frames_rx_64b; 2344 __le64 frames_rx_65b_127b; 2345 __le64 frames_rx_128b_255b; 2346 __le64 frames_rx_256b_511b; 2347 __le64 frames_rx_512b_1023b; 2348 __le64 frames_rx_1024b_1518b; 2349 __le64 frames_rx_gt_1518b; 2350 __le64 frames_rx_fifo_full; 2351 __le64 frames_tx_ok; 2352 __le64 frames_tx_all; 2353 __le64 frames_tx_bad; 2354 __le64 octets_tx_ok; 2355 __le64 octets_tx_total; 2356 __le64 frames_tx_unicast; 2357 __le64 frames_tx_multicast; 2358 __le64 frames_tx_broadcast; 2359 __le64 frames_tx_pause; 2360 }; 2361 2362 enum ionic_pb_buffer_drop_stats { 2363 IONIC_BUFFER_INTRINSIC_DROP = 0, 2364 IONIC_BUFFER_DISCARDED, 2365 IONIC_BUFFER_ADMITTED, 2366 IONIC_BUFFER_OUT_OF_CELLS_DROP, 2367 IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2368 IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2369 IONIC_BUFFER_TRUNCATION_DROP, 2370 IONIC_BUFFER_PORT_DISABLED_DROP, 2371 IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2372 IONIC_BUFFER_SPAN_TAIL_DROP, 2373 IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2374 IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2375 IONIC_BUFFER_INVALID_PORT_DROP, 2376 IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2377 IONIC_BUFFER_DROP_MAX, 2378 }; 2379 2380 /** 2381 * struct port_pb_stats - packet buffers system stats 2382 * uses ionic_pb_buffer_drop_stats for drop_counts[] 2383 */ 2384 struct ionic_port_pb_stats { 2385 __le64 sop_count_in; 2386 __le64 eop_count_in; 2387 __le64 sop_count_out; 2388 __le64 eop_count_out; 2389 __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2390 __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2391 __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2392 __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 2393 }; 2394 2395 /** 2396 * struct ionic_port_identity - port identity structure 2397 * @version: identity structure version 2398 * @type: type of port (enum port_type) 2399 * @num_lanes: number of lanes for the port 2400 * @autoneg: autoneg supported 2401 * @min_frame_size: minimum frame size supported 2402 * @max_frame_size: maximum frame size supported 2403 * @fec_type: supported fec types 2404 * @pause_type: supported pause types 2405 * @loopback_mode: supported loopback mode 2406 * @speeds: supported speeds 2407 * @config: current port configuration 2408 */ 2409 union ionic_port_identity { 2410 struct { 2411 u8 version; 2412 u8 type; 2413 u8 num_lanes; 2414 u8 autoneg; 2415 __le32 min_frame_size; 2416 __le32 max_frame_size; 2417 u8 fec_type[4]; 2418 u8 pause_type[2]; 2419 u8 loopback_mode[2]; 2420 __le32 speeds[16]; 2421 u8 rsvd2[44]; 2422 union ionic_port_config config; 2423 }; 2424 __le32 words[478]; 2425 }; 2426 2427 /** 2428 * struct ionic_port_info - port info structure 2429 * @config: Port configuration data 2430 * @status: Port status data 2431 * @stats: Port statistics data 2432 * @mgmt_stats: Port management statistics data 2433 * @port_pb_drop_stats: uplink pb drop stats 2434 */ 2435 struct ionic_port_info { 2436 union ionic_port_config config; 2437 struct ionic_port_status status; 2438 union { 2439 struct ionic_port_stats stats; 2440 struct ionic_mgmt_port_stats mgmt_stats; 2441 }; 2442 /* room for pb_stats to start at 2k offset */ 2443 u8 rsvd[760]; 2444 struct ionic_port_pb_stats pb_stats; 2445 }; 2446 2447 /** 2448 * struct ionic_lif_stats - LIF statistics structure 2449 */ 2450 struct ionic_lif_stats { 2451 /* RX */ 2452 __le64 rx_ucast_bytes; 2453 __le64 rx_ucast_packets; 2454 __le64 rx_mcast_bytes; 2455 __le64 rx_mcast_packets; 2456 __le64 rx_bcast_bytes; 2457 __le64 rx_bcast_packets; 2458 __le64 rsvd0; 2459 __le64 rsvd1; 2460 /* RX drops */ 2461 __le64 rx_ucast_drop_bytes; 2462 __le64 rx_ucast_drop_packets; 2463 __le64 rx_mcast_drop_bytes; 2464 __le64 rx_mcast_drop_packets; 2465 __le64 rx_bcast_drop_bytes; 2466 __le64 rx_bcast_drop_packets; 2467 __le64 rx_dma_error; 2468 __le64 rsvd2; 2469 /* TX */ 2470 __le64 tx_ucast_bytes; 2471 __le64 tx_ucast_packets; 2472 __le64 tx_mcast_bytes; 2473 __le64 tx_mcast_packets; 2474 __le64 tx_bcast_bytes; 2475 __le64 tx_bcast_packets; 2476 __le64 rsvd3; 2477 __le64 rsvd4; 2478 /* TX drops */ 2479 __le64 tx_ucast_drop_bytes; 2480 __le64 tx_ucast_drop_packets; 2481 __le64 tx_mcast_drop_bytes; 2482 __le64 tx_mcast_drop_packets; 2483 __le64 tx_bcast_drop_bytes; 2484 __le64 tx_bcast_drop_packets; 2485 __le64 tx_dma_error; 2486 __le64 rsvd5; 2487 /* Rx Queue/Ring drops */ 2488 __le64 rx_queue_disabled; 2489 __le64 rx_queue_empty; 2490 __le64 rx_queue_error; 2491 __le64 rx_desc_fetch_error; 2492 __le64 rx_desc_data_error; 2493 __le64 rsvd6; 2494 __le64 rsvd7; 2495 __le64 rsvd8; 2496 /* Tx Queue/Ring drops */ 2497 __le64 tx_queue_disabled; 2498 __le64 tx_queue_error; 2499 __le64 tx_desc_fetch_error; 2500 __le64 tx_desc_data_error; 2501 __le64 tx_queue_empty; 2502 __le64 rsvd10; 2503 __le64 rsvd11; 2504 __le64 rsvd12; 2505 2506 /* RDMA/ROCE TX */ 2507 __le64 tx_rdma_ucast_bytes; 2508 __le64 tx_rdma_ucast_packets; 2509 __le64 tx_rdma_mcast_bytes; 2510 __le64 tx_rdma_mcast_packets; 2511 __le64 tx_rdma_cnp_packets; 2512 __le64 rsvd13; 2513 __le64 rsvd14; 2514 __le64 rsvd15; 2515 2516 /* RDMA/ROCE RX */ 2517 __le64 rx_rdma_ucast_bytes; 2518 __le64 rx_rdma_ucast_packets; 2519 __le64 rx_rdma_mcast_bytes; 2520 __le64 rx_rdma_mcast_packets; 2521 __le64 rx_rdma_cnp_packets; 2522 __le64 rx_rdma_ecn_packets; 2523 __le64 rsvd16; 2524 __le64 rsvd17; 2525 2526 __le64 rsvd18; 2527 __le64 rsvd19; 2528 __le64 rsvd20; 2529 __le64 rsvd21; 2530 __le64 rsvd22; 2531 __le64 rsvd23; 2532 __le64 rsvd24; 2533 __le64 rsvd25; 2534 2535 __le64 rsvd26; 2536 __le64 rsvd27; 2537 __le64 rsvd28; 2538 __le64 rsvd29; 2539 __le64 rsvd30; 2540 __le64 rsvd31; 2541 __le64 rsvd32; 2542 __le64 rsvd33; 2543 2544 __le64 rsvd34; 2545 __le64 rsvd35; 2546 __le64 rsvd36; 2547 __le64 rsvd37; 2548 __le64 rsvd38; 2549 __le64 rsvd39; 2550 __le64 rsvd40; 2551 __le64 rsvd41; 2552 2553 __le64 rsvd42; 2554 __le64 rsvd43; 2555 __le64 rsvd44; 2556 __le64 rsvd45; 2557 __le64 rsvd46; 2558 __le64 rsvd47; 2559 __le64 rsvd48; 2560 __le64 rsvd49; 2561 2562 /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2563 __le64 rdma_req_rx_pkt_seq_err; 2564 __le64 rdma_req_rx_rnr_retry_err; 2565 __le64 rdma_req_rx_remote_access_err; 2566 __le64 rdma_req_rx_remote_inv_req_err; 2567 __le64 rdma_req_rx_remote_oper_err; 2568 __le64 rdma_req_rx_implied_nak_seq_err; 2569 __le64 rdma_req_rx_cqe_err; 2570 __le64 rdma_req_rx_cqe_flush_err; 2571 2572 __le64 rdma_req_rx_dup_responses; 2573 __le64 rdma_req_rx_invalid_packets; 2574 __le64 rdma_req_tx_local_access_err; 2575 __le64 rdma_req_tx_local_oper_err; 2576 __le64 rdma_req_tx_memory_mgmt_err; 2577 __le64 rsvd52; 2578 __le64 rsvd53; 2579 __le64 rsvd54; 2580 2581 /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2582 __le64 rdma_resp_rx_dup_requests; 2583 __le64 rdma_resp_rx_out_of_buffer; 2584 __le64 rdma_resp_rx_out_of_seq_pkts; 2585 __le64 rdma_resp_rx_cqe_err; 2586 __le64 rdma_resp_rx_cqe_flush_err; 2587 __le64 rdma_resp_rx_local_len_err; 2588 __le64 rdma_resp_rx_inv_request_err; 2589 __le64 rdma_resp_rx_local_qp_oper_err; 2590 2591 __le64 rdma_resp_rx_out_of_atomic_resource; 2592 __le64 rdma_resp_tx_pkt_seq_err; 2593 __le64 rdma_resp_tx_remote_inv_req_err; 2594 __le64 rdma_resp_tx_remote_access_err; 2595 __le64 rdma_resp_tx_remote_oper_err; 2596 __le64 rdma_resp_tx_rnr_retry_err; 2597 __le64 rsvd57; 2598 __le64 rsvd58; 2599 }; 2600 2601 /** 2602 * struct ionic_lif_info - LIF info structure 2603 * @config: LIF configuration structure 2604 * @status: LIF status structure 2605 * @stats: LIF statistics structure 2606 */ 2607 struct ionic_lif_info { 2608 union ionic_lif_config config; 2609 struct ionic_lif_status status; 2610 struct ionic_lif_stats stats; 2611 }; 2612 2613 union ionic_dev_cmd { 2614 u32 words[16]; 2615 struct ionic_admin_cmd cmd; 2616 struct ionic_nop_cmd nop; 2617 2618 struct ionic_dev_identify_cmd identify; 2619 struct ionic_dev_init_cmd init; 2620 struct ionic_dev_reset_cmd reset; 2621 struct ionic_dev_getattr_cmd getattr; 2622 struct ionic_dev_setattr_cmd setattr; 2623 2624 struct ionic_port_identify_cmd port_identify; 2625 struct ionic_port_init_cmd port_init; 2626 struct ionic_port_reset_cmd port_reset; 2627 struct ionic_port_getattr_cmd port_getattr; 2628 struct ionic_port_setattr_cmd port_setattr; 2629 2630 struct ionic_vf_setattr_cmd vf_setattr; 2631 struct ionic_vf_getattr_cmd vf_getattr; 2632 2633 struct ionic_lif_identify_cmd lif_identify; 2634 struct ionic_lif_init_cmd lif_init; 2635 struct ionic_lif_reset_cmd lif_reset; 2636 2637 struct ionic_qos_identify_cmd qos_identify; 2638 struct ionic_qos_init_cmd qos_init; 2639 struct ionic_qos_reset_cmd qos_reset; 2640 2641 struct ionic_q_identify_cmd q_identify; 2642 struct ionic_q_init_cmd q_init; 2643 struct ionic_q_control_cmd q_control; 2644 }; 2645 2646 union ionic_dev_cmd_comp { 2647 u32 words[4]; 2648 u8 status; 2649 struct ionic_admin_comp comp; 2650 struct ionic_nop_comp nop; 2651 2652 struct ionic_dev_identify_comp identify; 2653 struct ionic_dev_init_comp init; 2654 struct ionic_dev_reset_comp reset; 2655 struct ionic_dev_getattr_comp getattr; 2656 struct ionic_dev_setattr_comp setattr; 2657 2658 struct ionic_port_identify_comp port_identify; 2659 struct ionic_port_init_comp port_init; 2660 struct ionic_port_reset_comp port_reset; 2661 struct ionic_port_getattr_comp port_getattr; 2662 struct ionic_port_setattr_comp port_setattr; 2663 2664 struct ionic_vf_setattr_comp vf_setattr; 2665 struct ionic_vf_getattr_comp vf_getattr; 2666 2667 struct ionic_lif_identify_comp lif_identify; 2668 struct ionic_lif_init_comp lif_init; 2669 ionic_lif_reset_comp lif_reset; 2670 2671 struct ionic_qos_identify_comp qos_identify; 2672 ionic_qos_init_comp qos_init; 2673 ionic_qos_reset_comp qos_reset; 2674 2675 struct ionic_q_identify_comp q_identify; 2676 struct ionic_q_init_comp q_init; 2677 }; 2678 2679 /** 2680 * union ionic_dev_info_regs - Device info register format (read-only) 2681 * @signature: Signature value of 0x44455649 ('DEVI') 2682 * @version: Current version of info 2683 * @asic_type: Asic type 2684 * @asic_rev: Asic revision 2685 * @fw_status: Firmware status 2686 * @fw_heartbeat: Firmware heartbeat counter 2687 * @serial_num: Serial number 2688 * @fw_version: Firmware version 2689 */ 2690 union ionic_dev_info_regs { 2691 #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2692 #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2693 struct { 2694 u32 signature; 2695 u8 version; 2696 u8 asic_type; 2697 u8 asic_rev; 2698 #define IONIC_FW_STS_F_RUNNING 0x1 2699 u8 fw_status; 2700 u32 fw_heartbeat; 2701 char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2702 char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 2703 }; 2704 u32 words[512]; 2705 }; 2706 2707 /** 2708 * union ionic_dev_cmd_regs - Device command register format (read-write) 2709 * @doorbell: Device Cmd Doorbell, write-only 2710 * Write a 1 to signal device to process cmd, 2711 * poll done for completion. 2712 * @done: Done indicator, bit 0 == 1 when command is complete 2713 * @cmd: Opcode-specific command bytes 2714 * @comp: Opcode-specific response bytes 2715 * @data: Opcode-specific side-data 2716 */ 2717 union ionic_dev_cmd_regs { 2718 struct { 2719 u32 doorbell; 2720 u32 done; 2721 union ionic_dev_cmd cmd; 2722 union ionic_dev_cmd_comp comp; 2723 u8 rsvd[48]; 2724 u32 data[478]; 2725 } __packed; 2726 u32 words[512]; 2727 }; 2728 2729 /** 2730 * union ionic_dev_regs - Device register format for bar 0 page 0 2731 * @info: Device info registers 2732 * @devcmd: Device command registers 2733 */ 2734 union ionic_dev_regs { 2735 struct { 2736 union ionic_dev_info_regs info; 2737 union ionic_dev_cmd_regs devcmd; 2738 } __packed; 2739 __le32 words[1024]; 2740 }; 2741 2742 union ionic_adminq_cmd { 2743 struct ionic_admin_cmd cmd; 2744 struct ionic_nop_cmd nop; 2745 struct ionic_q_identify_cmd q_identify; 2746 struct ionic_q_init_cmd q_init; 2747 struct ionic_q_control_cmd q_control; 2748 struct ionic_lif_setattr_cmd lif_setattr; 2749 struct ionic_lif_getattr_cmd lif_getattr; 2750 struct ionic_rx_mode_set_cmd rx_mode_set; 2751 struct ionic_rx_filter_add_cmd rx_filter_add; 2752 struct ionic_rx_filter_del_cmd rx_filter_del; 2753 struct ionic_rdma_reset_cmd rdma_reset; 2754 struct ionic_rdma_queue_cmd rdma_queue; 2755 struct ionic_fw_download_cmd fw_download; 2756 struct ionic_fw_control_cmd fw_control; 2757 }; 2758 2759 union ionic_adminq_comp { 2760 struct ionic_admin_comp comp; 2761 struct ionic_nop_comp nop; 2762 struct ionic_q_identify_comp q_identify; 2763 struct ionic_q_init_comp q_init; 2764 struct ionic_lif_setattr_comp lif_setattr; 2765 struct ionic_lif_getattr_comp lif_getattr; 2766 struct ionic_rx_filter_add_comp rx_filter_add; 2767 struct ionic_fw_control_comp fw_control; 2768 }; 2769 2770 #define IONIC_BARS_MAX 6 2771 #define IONIC_PCI_BAR_DBELL 1 2772 2773 /* BAR0 */ 2774 #define IONIC_BAR0_SIZE 0x8000 2775 2776 #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 2777 #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 2778 #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 2779 #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 2780 #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 2781 #define IONIC_DEV_CMD_DONE 0x00000001 2782 2783 #define IONIC_ASIC_TYPE_CAPRI 0 2784 2785 /** 2786 * struct ionic_doorbell - Doorbell register layout 2787 * @p_index: Producer index 2788 * @ring: Selects the specific ring of the queue to update 2789 * Type-specific meaning: 2790 * ring=0: Default producer/consumer queue 2791 * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 2792 * send events to EQs when armed. EQs send 2793 * interrupts when armed. 2794 * @qid_lo: Queue destination for the producer index and flags (low bits) 2795 * @qid_hi: Queue destination for the producer index and flags (high bits) 2796 */ 2797 struct ionic_doorbell { 2798 __le16 p_index; 2799 u8 ring; 2800 u8 qid_lo; 2801 __le16 qid_hi; 2802 u16 rsvd2; 2803 }; 2804 2805 struct ionic_intr_status { 2806 u32 status[2]; 2807 }; 2808 2809 struct ionic_notifyq_cmd { 2810 __le32 data; /* Not used but needed for qcq structure */ 2811 }; 2812 2813 union ionic_notifyq_comp { 2814 struct ionic_notifyq_event event; 2815 struct ionic_link_change_event link_change; 2816 struct ionic_reset_event reset; 2817 struct ionic_heartbeat_event heartbeat; 2818 struct ionic_log_event log; 2819 }; 2820 2821 /* Deprecate */ 2822 struct ionic_identity { 2823 union ionic_drv_identity drv; 2824 union ionic_dev_identity dev; 2825 union ionic_lif_identity lif; 2826 union ionic_port_identity port; 2827 union ionic_qos_identity qos; 2828 union ionic_q_identity txq; 2829 }; 2830 2831 #endif /* _IONIC_IF_H_ */ 2832