106e9bfc1SLukas Bulwahn /* SPDX-License-Identifier: (GPL-2.0 OR Linux-OpenIB) OR BSD-2-Clause */ 2c4e7a75aSShannon Nelson /* Copyright (c) 2017-2020 Pensando Systems, Inc. All rights reserved. */ 3fbfb8031SShannon Nelson 4fbfb8031SShannon Nelson #ifndef _IONIC_IF_H_ 5fbfb8031SShannon Nelson #define _IONIC_IF_H_ 6fbfb8031SShannon Nelson 7fbfb8031SShannon Nelson #define IONIC_DEV_INFO_SIGNATURE 0x44455649 /* 'DEVI' */ 8fbfb8031SShannon Nelson #define IONIC_DEV_INFO_VERSION 1 9fbfb8031SShannon Nelson #define IONIC_IFNAMSIZ 16 10fbfb8031SShannon Nelson 11fbfb8031SShannon Nelson /** 12c4e7a75aSShannon Nelson * enum ionic_cmd_opcode - Device commands 13fbfb8031SShannon Nelson */ 14fbfb8031SShannon Nelson enum ionic_cmd_opcode { 15fbfb8031SShannon Nelson IONIC_CMD_NOP = 0, 16fbfb8031SShannon Nelson 17fbfb8031SShannon Nelson /* Device commands */ 18fbfb8031SShannon Nelson IONIC_CMD_IDENTIFY = 1, 19fbfb8031SShannon Nelson IONIC_CMD_INIT = 2, 20fbfb8031SShannon Nelson IONIC_CMD_RESET = 3, 21fbfb8031SShannon Nelson IONIC_CMD_GETATTR = 4, 22fbfb8031SShannon Nelson IONIC_CMD_SETATTR = 5, 23fbfb8031SShannon Nelson 24fbfb8031SShannon Nelson /* Port commands */ 25fbfb8031SShannon Nelson IONIC_CMD_PORT_IDENTIFY = 10, 26fbfb8031SShannon Nelson IONIC_CMD_PORT_INIT = 11, 27fbfb8031SShannon Nelson IONIC_CMD_PORT_RESET = 12, 28fbfb8031SShannon Nelson IONIC_CMD_PORT_GETATTR = 13, 29fbfb8031SShannon Nelson IONIC_CMD_PORT_SETATTR = 14, 30fbfb8031SShannon Nelson 31fbfb8031SShannon Nelson /* LIF commands */ 32fbfb8031SShannon Nelson IONIC_CMD_LIF_IDENTIFY = 20, 33fbfb8031SShannon Nelson IONIC_CMD_LIF_INIT = 21, 34fbfb8031SShannon Nelson IONIC_CMD_LIF_RESET = 22, 35fbfb8031SShannon Nelson IONIC_CMD_LIF_GETATTR = 23, 36fbfb8031SShannon Nelson IONIC_CMD_LIF_SETATTR = 24, 373da25843SShannon Nelson IONIC_CMD_LIF_SETPHC = 25, 38fbfb8031SShannon Nelson 39fbfb8031SShannon Nelson IONIC_CMD_RX_MODE_SET = 30, 40fbfb8031SShannon Nelson IONIC_CMD_RX_FILTER_ADD = 31, 41fbfb8031SShannon Nelson IONIC_CMD_RX_FILTER_DEL = 32, 42fbfb8031SShannon Nelson 43fbfb8031SShannon Nelson /* Queue commands */ 445b3f3f2aSShannon Nelson IONIC_CMD_Q_IDENTIFY = 39, 45fbfb8031SShannon Nelson IONIC_CMD_Q_INIT = 40, 46fbfb8031SShannon Nelson IONIC_CMD_Q_CONTROL = 41, 47fbfb8031SShannon Nelson 48fbfb8031SShannon Nelson /* RDMA commands */ 49fbfb8031SShannon Nelson IONIC_CMD_RDMA_RESET_LIF = 50, 50fbfb8031SShannon Nelson IONIC_CMD_RDMA_CREATE_EQ = 51, 51fbfb8031SShannon Nelson IONIC_CMD_RDMA_CREATE_CQ = 52, 52fbfb8031SShannon Nelson IONIC_CMD_RDMA_CREATE_ADMINQ = 53, 53fbfb8031SShannon Nelson 543d462ce2SShannon Nelson /* SR/IOV commands */ 553d462ce2SShannon Nelson IONIC_CMD_VF_GETATTR = 60, 563d462ce2SShannon Nelson IONIC_CMD_VF_SETATTR = 61, 573d462ce2SShannon Nelson 58fbfb8031SShannon Nelson /* QoS commands */ 59fbfb8031SShannon Nelson IONIC_CMD_QOS_CLASS_IDENTIFY = 240, 60fbfb8031SShannon Nelson IONIC_CMD_QOS_CLASS_INIT = 241, 61fbfb8031SShannon Nelson IONIC_CMD_QOS_CLASS_RESET = 242, 62c4e7a75aSShannon Nelson IONIC_CMD_QOS_CLASS_UPDATE = 243, 631b897e7dSShannon Nelson IONIC_CMD_QOS_CLEAR_STATS = 244, 641b897e7dSShannon Nelson IONIC_CMD_QOS_RESET = 245, 65fbfb8031SShannon Nelson 66fbfb8031SShannon Nelson /* Firmware commands */ 6787c905d8SShannon Nelson IONIC_CMD_FW_DOWNLOAD = 252, 6887c905d8SShannon Nelson IONIC_CMD_FW_CONTROL = 253, 6987c905d8SShannon Nelson IONIC_CMD_FW_DOWNLOAD_V1 = 254, 7087c905d8SShannon Nelson IONIC_CMD_FW_CONTROL_V1 = 255, 71fbfb8031SShannon Nelson }; 72fbfb8031SShannon Nelson 73fbfb8031SShannon Nelson /** 74c4e7a75aSShannon Nelson * enum ionic_status_code - Device command return codes 75fbfb8031SShannon Nelson */ 76fbfb8031SShannon Nelson enum ionic_status_code { 77fbfb8031SShannon Nelson IONIC_RC_SUCCESS = 0, /* Success */ 78fbfb8031SShannon Nelson IONIC_RC_EVERSION = 1, /* Incorrect version for request */ 79fbfb8031SShannon Nelson IONIC_RC_EOPCODE = 2, /* Invalid cmd opcode */ 80fbfb8031SShannon Nelson IONIC_RC_EIO = 3, /* I/O error */ 81fbfb8031SShannon Nelson IONIC_RC_EPERM = 4, /* Permission denied */ 82fbfb8031SShannon Nelson IONIC_RC_EQID = 5, /* Bad qid */ 83fbfb8031SShannon Nelson IONIC_RC_EQTYPE = 6, /* Bad qtype */ 84fbfb8031SShannon Nelson IONIC_RC_ENOENT = 7, /* No such element */ 85fbfb8031SShannon Nelson IONIC_RC_EINTR = 8, /* operation interrupted */ 86fbfb8031SShannon Nelson IONIC_RC_EAGAIN = 9, /* Try again */ 87fbfb8031SShannon Nelson IONIC_RC_ENOMEM = 10, /* Out of memory */ 88fbfb8031SShannon Nelson IONIC_RC_EFAULT = 11, /* Bad address */ 89fbfb8031SShannon Nelson IONIC_RC_EBUSY = 12, /* Device or resource busy */ 90fbfb8031SShannon Nelson IONIC_RC_EEXIST = 13, /* object already exists */ 91fbfb8031SShannon Nelson IONIC_RC_EINVAL = 14, /* Invalid argument */ 92fbfb8031SShannon Nelson IONIC_RC_ENOSPC = 15, /* No space left or alloc failure */ 93fbfb8031SShannon Nelson IONIC_RC_ERANGE = 16, /* Parameter out of range */ 94fbfb8031SShannon Nelson IONIC_RC_BAD_ADDR = 17, /* Descriptor contains a bad ptr */ 95fbfb8031SShannon Nelson IONIC_RC_DEV_CMD = 18, /* Device cmd attempted on AdminQ */ 96fbfb8031SShannon Nelson IONIC_RC_ENOSUPP = 19, /* Operation not supported */ 97fbfb8031SShannon Nelson IONIC_RC_ERROR = 29, /* Generic error */ 98fbfb8031SShannon Nelson IONIC_RC_ERDMA = 30, /* Generic RDMA error */ 991b897e7dSShannon Nelson IONIC_RC_EVFID = 31, /* VF ID does not exist */ 1009e15410dSShannon Nelson IONIC_RC_EBAD_FW = 32, /* FW file is invalid or corrupted */ 101fbfb8031SShannon Nelson }; 102fbfb8031SShannon Nelson 103fbfb8031SShannon Nelson enum ionic_notifyq_opcode { 104fbfb8031SShannon Nelson IONIC_EVENT_LINK_CHANGE = 1, 105fbfb8031SShannon Nelson IONIC_EVENT_RESET = 2, 106fbfb8031SShannon Nelson IONIC_EVENT_HEARTBEAT = 3, 107fbfb8031SShannon Nelson IONIC_EVENT_LOG = 4, 108c4e7a75aSShannon Nelson IONIC_EVENT_XCVR = 5, 109fbfb8031SShannon Nelson }; 110fbfb8031SShannon Nelson 111fbfb8031SShannon Nelson /** 1121b897e7dSShannon Nelson * struct ionic_admin_cmd - General admin command format 113fbfb8031SShannon Nelson * @opcode: Opcode for the command 114fbfb8031SShannon Nelson * @lif_index: LIF index 115fbfb8031SShannon Nelson * @cmd_data: Opcode-specific command bytes 116fbfb8031SShannon Nelson */ 117fbfb8031SShannon Nelson struct ionic_admin_cmd { 118fbfb8031SShannon Nelson u8 opcode; 119fbfb8031SShannon Nelson u8 rsvd; 120fbfb8031SShannon Nelson __le16 lif_index; 121fbfb8031SShannon Nelson u8 cmd_data[60]; 122fbfb8031SShannon Nelson }; 123fbfb8031SShannon Nelson 124fbfb8031SShannon Nelson /** 1255c28f213SShannon Nelson * struct ionic_admin_comp - General admin command completion format 126c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 127c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 128c4e7a75aSShannon Nelson * @cmd_data: Command-specific bytes 129c4e7a75aSShannon Nelson * @color: Color bit (Always 0 for commands issued to the 130c4e7a75aSShannon Nelson * Device Cmd Registers) 131fbfb8031SShannon Nelson */ 132fbfb8031SShannon Nelson struct ionic_admin_comp { 133fbfb8031SShannon Nelson u8 status; 134fbfb8031SShannon Nelson u8 rsvd; 135fbfb8031SShannon Nelson __le16 comp_index; 136fbfb8031SShannon Nelson u8 cmd_data[11]; 137fbfb8031SShannon Nelson u8 color; 138fbfb8031SShannon Nelson #define IONIC_COMP_COLOR_MASK 0x80 139fbfb8031SShannon Nelson }; 140fbfb8031SShannon Nelson 141fbfb8031SShannon Nelson static inline u8 color_match(u8 color, u8 done_color) 142fbfb8031SShannon Nelson { 143fbfb8031SShannon Nelson return (!!(color & IONIC_COMP_COLOR_MASK)) == done_color; 144fbfb8031SShannon Nelson } 145fbfb8031SShannon Nelson 146fbfb8031SShannon Nelson /** 1475c28f213SShannon Nelson * struct ionic_nop_cmd - NOP command 148fbfb8031SShannon Nelson * @opcode: opcode 149fbfb8031SShannon Nelson */ 150fbfb8031SShannon Nelson struct ionic_nop_cmd { 151fbfb8031SShannon Nelson u8 opcode; 152fbfb8031SShannon Nelson u8 rsvd[63]; 153fbfb8031SShannon Nelson }; 154fbfb8031SShannon Nelson 155fbfb8031SShannon Nelson /** 1565c28f213SShannon Nelson * struct ionic_nop_comp - NOP command completion 157c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 158fbfb8031SShannon Nelson */ 159fbfb8031SShannon Nelson struct ionic_nop_comp { 160fbfb8031SShannon Nelson u8 status; 161fbfb8031SShannon Nelson u8 rsvd[15]; 162fbfb8031SShannon Nelson }; 163fbfb8031SShannon Nelson 164fbfb8031SShannon Nelson /** 1655c28f213SShannon Nelson * struct ionic_dev_init_cmd - Device init command 166fbfb8031SShannon Nelson * @opcode: opcode 167c4e7a75aSShannon Nelson * @type: Device type 168fbfb8031SShannon Nelson */ 169fbfb8031SShannon Nelson struct ionic_dev_init_cmd { 170fbfb8031SShannon Nelson u8 opcode; 171fbfb8031SShannon Nelson u8 type; 172fbfb8031SShannon Nelson u8 rsvd[62]; 173fbfb8031SShannon Nelson }; 174fbfb8031SShannon Nelson 175fbfb8031SShannon Nelson /** 1761b897e7dSShannon Nelson * struct ionic_dev_init_comp - Device init command completion 177c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 178fbfb8031SShannon Nelson */ 179fbfb8031SShannon Nelson struct ionic_dev_init_comp { 180fbfb8031SShannon Nelson u8 status; 181fbfb8031SShannon Nelson u8 rsvd[15]; 182fbfb8031SShannon Nelson }; 183fbfb8031SShannon Nelson 184fbfb8031SShannon Nelson /** 1855c28f213SShannon Nelson * struct ionic_dev_reset_cmd - Device reset command 186fbfb8031SShannon Nelson * @opcode: opcode 187fbfb8031SShannon Nelson */ 188fbfb8031SShannon Nelson struct ionic_dev_reset_cmd { 189fbfb8031SShannon Nelson u8 opcode; 190fbfb8031SShannon Nelson u8 rsvd[63]; 191fbfb8031SShannon Nelson }; 192fbfb8031SShannon Nelson 193fbfb8031SShannon Nelson /** 1941b897e7dSShannon Nelson * struct ionic_dev_reset_comp - Reset command completion 195c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 196fbfb8031SShannon Nelson */ 197fbfb8031SShannon Nelson struct ionic_dev_reset_comp { 198fbfb8031SShannon Nelson u8 status; 199fbfb8031SShannon Nelson u8 rsvd[15]; 200fbfb8031SShannon Nelson }; 201fbfb8031SShannon Nelson 202fbfb8031SShannon Nelson #define IONIC_IDENTITY_VERSION_1 1 203fbfb8031SShannon Nelson 204fbfb8031SShannon Nelson /** 2055c28f213SShannon Nelson * struct ionic_dev_identify_cmd - Driver/device identify command 206fbfb8031SShannon Nelson * @opcode: opcode 207fbfb8031SShannon Nelson * @ver: Highest version of identify supported by driver 208fbfb8031SShannon Nelson */ 209fbfb8031SShannon Nelson struct ionic_dev_identify_cmd { 210fbfb8031SShannon Nelson u8 opcode; 211fbfb8031SShannon Nelson u8 ver; 212fbfb8031SShannon Nelson u8 rsvd[62]; 213fbfb8031SShannon Nelson }; 214fbfb8031SShannon Nelson 215fbfb8031SShannon Nelson /** 216c4e7a75aSShannon Nelson * struct ionic_dev_identify_comp - Driver/device identify command completion 217c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 218fbfb8031SShannon Nelson * @ver: Version of identify returned by device 219fbfb8031SShannon Nelson */ 220fbfb8031SShannon Nelson struct ionic_dev_identify_comp { 221fbfb8031SShannon Nelson u8 status; 222fbfb8031SShannon Nelson u8 ver; 223fbfb8031SShannon Nelson u8 rsvd[14]; 224fbfb8031SShannon Nelson }; 225fbfb8031SShannon Nelson 226fbfb8031SShannon Nelson enum ionic_os_type { 227fbfb8031SShannon Nelson IONIC_OS_TYPE_LINUX = 1, 228fbfb8031SShannon Nelson IONIC_OS_TYPE_WIN = 2, 229fbfb8031SShannon Nelson IONIC_OS_TYPE_DPDK = 3, 230fbfb8031SShannon Nelson IONIC_OS_TYPE_FREEBSD = 4, 231fbfb8031SShannon Nelson IONIC_OS_TYPE_IPXE = 5, 232fbfb8031SShannon Nelson IONIC_OS_TYPE_ESXI = 6, 233fbfb8031SShannon Nelson }; 234fbfb8031SShannon Nelson 235fbfb8031SShannon Nelson /** 236c4e7a75aSShannon Nelson * union ionic_drv_identity - driver identity information 237c4e7a75aSShannon Nelson * @os_type: OS type (see enum ionic_os_type) 238fbfb8031SShannon Nelson * @os_dist: OS distribution, numeric format 239fbfb8031SShannon Nelson * @os_dist_str: OS distribution, string format 240fbfb8031SShannon Nelson * @kernel_ver: Kernel version, numeric format 241fbfb8031SShannon Nelson * @kernel_ver_str: Kernel version, string format 242fbfb8031SShannon Nelson * @driver_ver_str: Driver version, string format 243fbfb8031SShannon Nelson */ 244fbfb8031SShannon Nelson union ionic_drv_identity { 245fbfb8031SShannon Nelson struct { 246fbfb8031SShannon Nelson __le32 os_type; 247fbfb8031SShannon Nelson __le32 os_dist; 248fbfb8031SShannon Nelson char os_dist_str[128]; 249fbfb8031SShannon Nelson __le32 kernel_ver; 250fbfb8031SShannon Nelson char kernel_ver_str[32]; 251fbfb8031SShannon Nelson char driver_ver_str[32]; 252fbfb8031SShannon Nelson }; 253c4e7a75aSShannon Nelson __le32 words[478]; 254fbfb8031SShannon Nelson }; 255fbfb8031SShannon Nelson 256fbfb8031SShannon Nelson /** 257c4e7a75aSShannon Nelson * union ionic_dev_identity - device identity information 258fbfb8031SShannon Nelson * @version: Version of device identify 259fbfb8031SShannon Nelson * @type: Identify type (0 for now) 260fbfb8031SShannon Nelson * @nports: Number of ports provisioned 261fbfb8031SShannon Nelson * @nlifs: Number of LIFs provisioned 262fbfb8031SShannon Nelson * @nintrs: Number of interrupts provisioned 263fbfb8031SShannon Nelson * @ndbpgs_per_lif: Number of doorbell pages per LIF 264c4e7a75aSShannon Nelson * @intr_coal_mult: Interrupt coalescing multiplication factor 265fbfb8031SShannon Nelson * Scale user-supplied interrupt coalescing 266fbfb8031SShannon Nelson * value in usecs to device units using: 267fbfb8031SShannon Nelson * device units = usecs * mult / div 268c4e7a75aSShannon Nelson * @intr_coal_div: Interrupt coalescing division factor 269fbfb8031SShannon Nelson * Scale user-supplied interrupt coalescing 270fbfb8031SShannon Nelson * value in usecs to device units using: 271fbfb8031SShannon Nelson * device units = usecs * mult / div 272c4e7a75aSShannon Nelson * @eq_count: Number of shared event queues 2733da25843SShannon Nelson * @hwstamp_mask: Bitmask for subtraction of hardware tick values. 2743da25843SShannon Nelson * @hwstamp_mult: Hardware tick to nanosecond multiplier. 2753da25843SShannon Nelson * @hwstamp_shift: Hardware tick to nanosecond divisor (power of two). 276fbfb8031SShannon Nelson */ 277fbfb8031SShannon Nelson union ionic_dev_identity { 278fbfb8031SShannon Nelson struct { 279fbfb8031SShannon Nelson u8 version; 280fbfb8031SShannon Nelson u8 type; 281fbfb8031SShannon Nelson u8 rsvd[2]; 282fbfb8031SShannon Nelson u8 nports; 283fbfb8031SShannon Nelson u8 rsvd2[3]; 284fbfb8031SShannon Nelson __le32 nlifs; 285fbfb8031SShannon Nelson __le32 nintrs; 286fbfb8031SShannon Nelson __le32 ndbpgs_per_lif; 287fbfb8031SShannon Nelson __le32 intr_coal_mult; 288fbfb8031SShannon Nelson __le32 intr_coal_div; 289c4e7a75aSShannon Nelson __le32 eq_count; 2903da25843SShannon Nelson __le64 hwstamp_mask; 2913da25843SShannon Nelson __le32 hwstamp_mult; 2923da25843SShannon Nelson __le32 hwstamp_shift; 293fbfb8031SShannon Nelson }; 294c4e7a75aSShannon Nelson __le32 words[478]; 295fbfb8031SShannon Nelson }; 296fbfb8031SShannon Nelson 297fbfb8031SShannon Nelson enum ionic_lif_type { 298fbfb8031SShannon Nelson IONIC_LIF_TYPE_CLASSIC = 0, 299fbfb8031SShannon Nelson IONIC_LIF_TYPE_MACVLAN = 1, 300fbfb8031SShannon Nelson IONIC_LIF_TYPE_NETQUEUE = 2, 301fbfb8031SShannon Nelson }; 302fbfb8031SShannon Nelson 303fbfb8031SShannon Nelson /** 304c4e7a75aSShannon Nelson * struct ionic_lif_identify_cmd - LIF identify command 305fbfb8031SShannon Nelson * @opcode: opcode 306c4e7a75aSShannon Nelson * @type: LIF type (enum ionic_lif_type) 307c4e7a75aSShannon Nelson * @ver: Version of identify returned by device 308fbfb8031SShannon Nelson */ 309fbfb8031SShannon Nelson struct ionic_lif_identify_cmd { 310fbfb8031SShannon Nelson u8 opcode; 311fbfb8031SShannon Nelson u8 type; 312fbfb8031SShannon Nelson u8 ver; 313fbfb8031SShannon Nelson u8 rsvd[61]; 314fbfb8031SShannon Nelson }; 315fbfb8031SShannon Nelson 316fbfb8031SShannon Nelson /** 317c4e7a75aSShannon Nelson * struct ionic_lif_identify_comp - LIF identify command completion 318c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 319c4e7a75aSShannon Nelson * @ver: Version of identify returned by device 320fbfb8031SShannon Nelson */ 321fbfb8031SShannon Nelson struct ionic_lif_identify_comp { 322fbfb8031SShannon Nelson u8 status; 323fbfb8031SShannon Nelson u8 ver; 324fbfb8031SShannon Nelson u8 rsvd2[14]; 325fbfb8031SShannon Nelson }; 326fbfb8031SShannon Nelson 327c4e7a75aSShannon Nelson /** 328c4e7a75aSShannon Nelson * enum ionic_lif_capability - LIF capabilities 329c4e7a75aSShannon Nelson * @IONIC_LIF_CAP_ETH: LIF supports Ethernet 33025cc5a5fSShannon Nelson * @IONIC_LIF_CAP_RDMA: LIF supports RDMA 331c4e7a75aSShannon Nelson */ 332fbfb8031SShannon Nelson enum ionic_lif_capability { 333fbfb8031SShannon Nelson IONIC_LIF_CAP_ETH = BIT(0), 334fbfb8031SShannon Nelson IONIC_LIF_CAP_RDMA = BIT(1), 335fbfb8031SShannon Nelson }; 336fbfb8031SShannon Nelson 337fbfb8031SShannon Nelson /** 338c4e7a75aSShannon Nelson * enum ionic_logical_qtype - Logical Queue Types 339c4e7a75aSShannon Nelson * @IONIC_QTYPE_ADMINQ: Administrative Queue 340c4e7a75aSShannon Nelson * @IONIC_QTYPE_NOTIFYQ: Notify Queue 341c4e7a75aSShannon Nelson * @IONIC_QTYPE_RXQ: Receive Queue 342c4e7a75aSShannon Nelson * @IONIC_QTYPE_TXQ: Transmit Queue 343c4e7a75aSShannon Nelson * @IONIC_QTYPE_EQ: Event Queue 344c4e7a75aSShannon Nelson * @IONIC_QTYPE_MAX: Max queue type supported 345fbfb8031SShannon Nelson */ 346fbfb8031SShannon Nelson enum ionic_logical_qtype { 347fbfb8031SShannon Nelson IONIC_QTYPE_ADMINQ = 0, 348fbfb8031SShannon Nelson IONIC_QTYPE_NOTIFYQ = 1, 349fbfb8031SShannon Nelson IONIC_QTYPE_RXQ = 2, 350fbfb8031SShannon Nelson IONIC_QTYPE_TXQ = 3, 351fbfb8031SShannon Nelson IONIC_QTYPE_EQ = 4, 352fbfb8031SShannon Nelson IONIC_QTYPE_MAX = 16, 353fbfb8031SShannon Nelson }; 354fbfb8031SShannon Nelson 355fbfb8031SShannon Nelson /** 35657a3a98dSShannon Nelson * enum ionic_q_feature - Common Features for most queue types 35757a3a98dSShannon Nelson * 35857a3a98dSShannon Nelson * Common features use bits 0-15. Per-queue-type features use higher bits. 35957a3a98dSShannon Nelson * 36057a3a98dSShannon Nelson * @IONIC_QIDENT_F_CQ: Queue has completion ring 36157a3a98dSShannon Nelson * @IONIC_QIDENT_F_SG: Queue has scatter/gather ring 36257a3a98dSShannon Nelson * @IONIC_QIDENT_F_EQ: Queue can use event queue 36357a3a98dSShannon Nelson * @IONIC_QIDENT_F_CMB: Queue is in cmb bar 3640ec9f666SShannon Nelson * @IONIC_Q_F_2X_DESC: Double main descriptor size 3650ec9f666SShannon Nelson * @IONIC_Q_F_2X_CQ_DESC: Double cq descriptor size 3660ec9f666SShannon Nelson * @IONIC_Q_F_2X_SG_DESC: Double sg descriptor size 3670ec9f666SShannon Nelson * @IONIC_Q_F_4X_DESC: Quadruple main descriptor size 3680ec9f666SShannon Nelson * @IONIC_Q_F_4X_CQ_DESC: Quadruple cq descriptor size 3690ec9f666SShannon Nelson * @IONIC_Q_F_4X_SG_DESC: Quadruple sg descriptor size 37057a3a98dSShannon Nelson */ 37157a3a98dSShannon Nelson enum ionic_q_feature { 37257a3a98dSShannon Nelson IONIC_QIDENT_F_CQ = BIT_ULL(0), 37357a3a98dSShannon Nelson IONIC_QIDENT_F_SG = BIT_ULL(1), 37457a3a98dSShannon Nelson IONIC_QIDENT_F_EQ = BIT_ULL(2), 37557a3a98dSShannon Nelson IONIC_QIDENT_F_CMB = BIT_ULL(3), 3760ec9f666SShannon Nelson IONIC_Q_F_2X_DESC = BIT_ULL(4), 3770ec9f666SShannon Nelson IONIC_Q_F_2X_CQ_DESC = BIT_ULL(5), 3780ec9f666SShannon Nelson IONIC_Q_F_2X_SG_DESC = BIT_ULL(6), 3790ec9f666SShannon Nelson IONIC_Q_F_4X_DESC = BIT_ULL(7), 3800ec9f666SShannon Nelson IONIC_Q_F_4X_CQ_DESC = BIT_ULL(8), 3810ec9f666SShannon Nelson IONIC_Q_F_4X_SG_DESC = BIT_ULL(9), 38257a3a98dSShannon Nelson }; 38357a3a98dSShannon Nelson 38457a3a98dSShannon Nelson /** 3853da25843SShannon Nelson * enum ionic_rxq_feature - RXQ-specific Features 3863da25843SShannon Nelson * 3873da25843SShannon Nelson * Per-queue-type features use bits 16 and higher. 3883da25843SShannon Nelson * 3893da25843SShannon Nelson * @IONIC_RXQ_F_HWSTAMP: Queue supports Hardware Timestamping 3903da25843SShannon Nelson */ 3913da25843SShannon Nelson enum ionic_rxq_feature { 3923da25843SShannon Nelson IONIC_RXQ_F_HWSTAMP = BIT_ULL(16), 3933da25843SShannon Nelson }; 3943da25843SShannon Nelson 3953da25843SShannon Nelson /** 3963da25843SShannon Nelson * enum ionic_txq_feature - TXQ-specific Features 3973da25843SShannon Nelson * 3983da25843SShannon Nelson * Per-queue-type features use bits 16 and higher. 3993da25843SShannon Nelson * 4003da25843SShannon Nelson * @IONIC_TXQ_F_HWSTAMP: Queue supports Hardware Timestamping 4013da25843SShannon Nelson */ 4023da25843SShannon Nelson enum ionic_txq_feature { 4033da25843SShannon Nelson IONIC_TXQ_F_HWSTAMP = BIT(16), 4043da25843SShannon Nelson }; 4053da25843SShannon Nelson 4063da25843SShannon Nelson /** 4073da25843SShannon Nelson * struct ionic_hwstamp_bits - Hardware timestamp decoding bits 4083da25843SShannon Nelson * @IONIC_HWSTAMP_INVALID: Invalid hardware timestamp value 4093da25843SShannon Nelson * @IONIC_HWSTAMP_CQ_NEGOFFSET: Timestamp field negative offset 4103da25843SShannon Nelson * from the base cq descriptor. 4113da25843SShannon Nelson */ 4123da25843SShannon Nelson enum ionic_hwstamp_bits { 4133da25843SShannon Nelson IONIC_HWSTAMP_INVALID = ~0ull, 4143da25843SShannon Nelson IONIC_HWSTAMP_CQ_NEGOFFSET = 8, 4153da25843SShannon Nelson }; 4163da25843SShannon Nelson 4173da25843SShannon Nelson /** 418c4e7a75aSShannon Nelson * struct ionic_lif_logical_qtype - Descriptor of logical to HW queue type 419c4e7a75aSShannon Nelson * @qtype: Hardware Queue Type 420c4e7a75aSShannon Nelson * @qid_count: Number of Queue IDs of the logical type 421c4e7a75aSShannon Nelson * @qid_base: Minimum Queue ID of the logical type 422fbfb8031SShannon Nelson */ 423fbfb8031SShannon Nelson struct ionic_lif_logical_qtype { 424fbfb8031SShannon Nelson u8 qtype; 425fbfb8031SShannon Nelson u8 rsvd[3]; 426fbfb8031SShannon Nelson __le32 qid_count; 427fbfb8031SShannon Nelson __le32 qid_base; 428fbfb8031SShannon Nelson }; 429fbfb8031SShannon Nelson 430c4e7a75aSShannon Nelson /** 431c4e7a75aSShannon Nelson * enum ionic_lif_state - LIF state 432c4e7a75aSShannon Nelson * @IONIC_LIF_DISABLE: LIF disabled 433c4e7a75aSShannon Nelson * @IONIC_LIF_ENABLE: LIF enabled 4341b897e7dSShannon Nelson * @IONIC_LIF_QUIESCE: LIF Quiesced 435c4e7a75aSShannon Nelson */ 436fbfb8031SShannon Nelson enum ionic_lif_state { 4371b897e7dSShannon Nelson IONIC_LIF_QUIESCE = 0, 438fbfb8031SShannon Nelson IONIC_LIF_ENABLE = 1, 4391b897e7dSShannon Nelson IONIC_LIF_DISABLE = 2, 440fbfb8031SShannon Nelson }; 441fbfb8031SShannon Nelson 442fbfb8031SShannon Nelson /** 443c4e7a75aSShannon Nelson * union ionic_lif_config - LIF configuration 444c4e7a75aSShannon Nelson * @state: LIF state (enum ionic_lif_state) 445c4e7a75aSShannon Nelson * @name: LIF name 446c4e7a75aSShannon Nelson * @mtu: MTU 447c4e7a75aSShannon Nelson * @mac: Station MAC address 4481b897e7dSShannon Nelson * @vlan: Default Vlan ID 449c4e7a75aSShannon Nelson * @features: Features (enum ionic_eth_hw_features) 450c4e7a75aSShannon Nelson * @queue_count: Queue counts per queue-type 451fbfb8031SShannon Nelson */ 452fbfb8031SShannon Nelson union ionic_lif_config { 453fbfb8031SShannon Nelson struct { 454fbfb8031SShannon Nelson u8 state; 455fbfb8031SShannon Nelson u8 rsvd[3]; 456fbfb8031SShannon Nelson char name[IONIC_IFNAMSIZ]; 457fbfb8031SShannon Nelson __le32 mtu; 458fbfb8031SShannon Nelson u8 mac[6]; 4591b897e7dSShannon Nelson __le16 vlan; 460fbfb8031SShannon Nelson __le64 features; 461fbfb8031SShannon Nelson __le32 queue_count[IONIC_QTYPE_MAX]; 4625dca69c4SShannon Nelson } __packed; 463fbfb8031SShannon Nelson __le32 words[64]; 464fbfb8031SShannon Nelson }; 465fbfb8031SShannon Nelson 466fbfb8031SShannon Nelson /** 467c4e7a75aSShannon Nelson * struct ionic_lif_identity - LIF identity information (type-specific) 468fbfb8031SShannon Nelson * 469c4e7a75aSShannon Nelson * @capabilities: LIF capabilities 470fbfb8031SShannon Nelson * 471c4e7a75aSShannon Nelson * @eth: Ethernet identify structure 472c4e7a75aSShannon Nelson * @version: Ethernet identify structure version 473c4e7a75aSShannon Nelson * @max_ucast_filters: Number of perfect unicast addresses supported 474c4e7a75aSShannon Nelson * @max_mcast_filters: Number of perfect multicast addresses supported 475fbfb8031SShannon Nelson * @min_frame_size: Minimum size of frames to be sent 47625cc5a5fSShannon Nelson * @max_frame_size: Maximum size of frames to be sent 4773da25843SShannon Nelson * @hwstamp_tx_modes: Bitmask of BIT_ULL(enum ionic_txstamp_mode) 4783da25843SShannon Nelson * @hwstamp_rx_filters: Bitmask of enum ionic_pkt_class 479fbfb8031SShannon Nelson * @config: LIF config struct with features, mtu, mac, q counts 480fbfb8031SShannon Nelson * 481c4e7a75aSShannon Nelson * @rdma: RDMA identify structure 482c4e7a75aSShannon Nelson * @version: RDMA version of opcodes and queue descriptors 483c4e7a75aSShannon Nelson * @qp_opcodes: Number of RDMA queue pair opcodes supported 484c4e7a75aSShannon Nelson * @admin_opcodes: Number of RDMA admin opcodes supported 485c4e7a75aSShannon Nelson * @npts_per_lif: Page table size per LIF 486c4e7a75aSShannon Nelson * @nmrs_per_lif: Number of memory regions per LIF 487c4e7a75aSShannon Nelson * @nahs_per_lif: Number of address handles per LIF 488c4e7a75aSShannon Nelson * @max_stride: Max work request stride 489c4e7a75aSShannon Nelson * @cl_stride: Cache line stride 490c4e7a75aSShannon Nelson * @pte_stride: Page table entry stride 491c4e7a75aSShannon Nelson * @rrq_stride: Remote RQ work request stride 492c4e7a75aSShannon Nelson * @rsq_stride: Remote SQ work request stride 493fbfb8031SShannon Nelson * @dcqcn_profiles: Number of DCQCN profiles 494c4e7a75aSShannon Nelson * @aq_qtype: RDMA Admin Qtype 495c4e7a75aSShannon Nelson * @sq_qtype: RDMA Send Qtype 496c4e7a75aSShannon Nelson * @rq_qtype: RDMA Receive Qtype 497c4e7a75aSShannon Nelson * @cq_qtype: RDMA Completion Qtype 498c4e7a75aSShannon Nelson * @eq_qtype: RDMA Event Qtype 499fbfb8031SShannon Nelson */ 500fbfb8031SShannon Nelson union ionic_lif_identity { 501fbfb8031SShannon Nelson struct { 502fbfb8031SShannon Nelson __le64 capabilities; 503fbfb8031SShannon Nelson 504fbfb8031SShannon Nelson struct { 505fbfb8031SShannon Nelson u8 version; 506fbfb8031SShannon Nelson u8 rsvd[3]; 507fbfb8031SShannon Nelson __le32 max_ucast_filters; 508fbfb8031SShannon Nelson __le32 max_mcast_filters; 509fbfb8031SShannon Nelson __le16 rss_ind_tbl_sz; 510fbfb8031SShannon Nelson __le32 min_frame_size; 511fbfb8031SShannon Nelson __le32 max_frame_size; 5123da25843SShannon Nelson u8 rsvd2[2]; 5133da25843SShannon Nelson __le64 hwstamp_tx_modes; 5143da25843SShannon Nelson __le64 hwstamp_rx_filters; 5153da25843SShannon Nelson u8 rsvd3[88]; 516fbfb8031SShannon Nelson union ionic_lif_config config; 5175dca69c4SShannon Nelson } __packed eth; 518fbfb8031SShannon Nelson 519fbfb8031SShannon Nelson struct { 520fbfb8031SShannon Nelson u8 version; 521fbfb8031SShannon Nelson u8 qp_opcodes; 522fbfb8031SShannon Nelson u8 admin_opcodes; 523fbfb8031SShannon Nelson u8 rsvd; 524fbfb8031SShannon Nelson __le32 npts_per_lif; 525fbfb8031SShannon Nelson __le32 nmrs_per_lif; 526fbfb8031SShannon Nelson __le32 nahs_per_lif; 527fbfb8031SShannon Nelson u8 max_stride; 528fbfb8031SShannon Nelson u8 cl_stride; 529fbfb8031SShannon Nelson u8 pte_stride; 530fbfb8031SShannon Nelson u8 rrq_stride; 531fbfb8031SShannon Nelson u8 rsq_stride; 532fbfb8031SShannon Nelson u8 dcqcn_profiles; 533fbfb8031SShannon Nelson u8 rsvd_dimensions[10]; 534fbfb8031SShannon Nelson struct ionic_lif_logical_qtype aq_qtype; 535fbfb8031SShannon Nelson struct ionic_lif_logical_qtype sq_qtype; 536fbfb8031SShannon Nelson struct ionic_lif_logical_qtype rq_qtype; 537fbfb8031SShannon Nelson struct ionic_lif_logical_qtype cq_qtype; 538fbfb8031SShannon Nelson struct ionic_lif_logical_qtype eq_qtype; 5395dca69c4SShannon Nelson } __packed rdma; 5405dca69c4SShannon Nelson } __packed; 541c4e7a75aSShannon Nelson __le32 words[478]; 542fbfb8031SShannon Nelson }; 543fbfb8031SShannon Nelson 544fbfb8031SShannon Nelson /** 5455c28f213SShannon Nelson * struct ionic_lif_init_cmd - LIF init command 546c4e7a75aSShannon Nelson * @opcode: Opcode 547c4e7a75aSShannon Nelson * @type: LIF type (enum ionic_lif_type) 548fbfb8031SShannon Nelson * @index: LIF index 549c4e7a75aSShannon Nelson * @info_pa: Destination address for LIF info (struct ionic_lif_info) 550fbfb8031SShannon Nelson */ 551fbfb8031SShannon Nelson struct ionic_lif_init_cmd { 552fbfb8031SShannon Nelson u8 opcode; 553fbfb8031SShannon Nelson u8 type; 554fbfb8031SShannon Nelson __le16 index; 555fbfb8031SShannon Nelson __le32 rsvd; 556fbfb8031SShannon Nelson __le64 info_pa; 557fbfb8031SShannon Nelson u8 rsvd2[48]; 558fbfb8031SShannon Nelson }; 559fbfb8031SShannon Nelson 560fbfb8031SShannon Nelson /** 5615c28f213SShannon Nelson * struct ionic_lif_init_comp - LIF init command completion 562c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 563c4e7a75aSShannon Nelson * @hw_index: Hardware index of the initialized LIF 564fbfb8031SShannon Nelson */ 565fbfb8031SShannon Nelson struct ionic_lif_init_comp { 566fbfb8031SShannon Nelson u8 status; 567fbfb8031SShannon Nelson u8 rsvd; 568fbfb8031SShannon Nelson __le16 hw_index; 569fbfb8031SShannon Nelson u8 rsvd2[12]; 570fbfb8031SShannon Nelson }; 571fbfb8031SShannon Nelson 572fbfb8031SShannon Nelson /** 5735b3f3f2aSShannon Nelson * struct ionic_q_identify_cmd - queue identify command 5745b3f3f2aSShannon Nelson * @opcode: opcode 5755b3f3f2aSShannon Nelson * @lif_type: LIF type (enum ionic_lif_type) 5765b3f3f2aSShannon Nelson * @type: Logical queue type (enum ionic_logical_qtype) 5775b3f3f2aSShannon Nelson * @ver: Highest queue type version that the driver supports 5785b3f3f2aSShannon Nelson */ 5795b3f3f2aSShannon Nelson struct ionic_q_identify_cmd { 5805b3f3f2aSShannon Nelson u8 opcode; 5815b3f3f2aSShannon Nelson u8 rsvd; 5825b3f3f2aSShannon Nelson __le16 lif_type; 5835b3f3f2aSShannon Nelson u8 type; 5845b3f3f2aSShannon Nelson u8 ver; 5855b3f3f2aSShannon Nelson u8 rsvd2[58]; 5865b3f3f2aSShannon Nelson }; 5875b3f3f2aSShannon Nelson 5885b3f3f2aSShannon Nelson /** 5895b3f3f2aSShannon Nelson * struct ionic_q_identify_comp - queue identify command completion 5905b3f3f2aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 5915b3f3f2aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 5925b3f3f2aSShannon Nelson * @ver: Queue type version that can be used with FW 5935b3f3f2aSShannon Nelson */ 5945b3f3f2aSShannon Nelson struct ionic_q_identify_comp { 5955b3f3f2aSShannon Nelson u8 status; 5965b3f3f2aSShannon Nelson u8 rsvd; 5975b3f3f2aSShannon Nelson __le16 comp_index; 5985b3f3f2aSShannon Nelson u8 ver; 5995b3f3f2aSShannon Nelson u8 rsvd2[11]; 6005b3f3f2aSShannon Nelson }; 6015b3f3f2aSShannon Nelson 6025b3f3f2aSShannon Nelson /** 6035b3f3f2aSShannon Nelson * union ionic_q_identity - queue identity information 6045b3f3f2aSShannon Nelson * @version: Queue type version that can be used with FW 6055b3f3f2aSShannon Nelson * @supported: Bitfield of queue versions, first bit = ver 0 60657a3a98dSShannon Nelson * @features: Queue features (enum ionic_q_feature, etc) 6075b3f3f2aSShannon Nelson * @desc_sz: Descriptor size 6085b3f3f2aSShannon Nelson * @comp_sz: Completion descriptor size 6095b3f3f2aSShannon Nelson * @sg_desc_sz: Scatter/Gather descriptor size 6105b3f3f2aSShannon Nelson * @max_sg_elems: Maximum number of Scatter/Gather elements 6115b3f3f2aSShannon Nelson * @sg_desc_stride: Number of Scatter/Gather elements per descriptor 6125b3f3f2aSShannon Nelson */ 6135b3f3f2aSShannon Nelson union ionic_q_identity { 6145b3f3f2aSShannon Nelson struct { 6155b3f3f2aSShannon Nelson u8 version; 6165b3f3f2aSShannon Nelson u8 supported; 6175b3f3f2aSShannon Nelson u8 rsvd[6]; 6185b3f3f2aSShannon Nelson __le64 features; 6195b3f3f2aSShannon Nelson __le16 desc_sz; 6205b3f3f2aSShannon Nelson __le16 comp_sz; 6215b3f3f2aSShannon Nelson __le16 sg_desc_sz; 6225b3f3f2aSShannon Nelson __le16 max_sg_elems; 6235b3f3f2aSShannon Nelson __le16 sg_desc_stride; 6245b3f3f2aSShannon Nelson }; 6255b3f3f2aSShannon Nelson __le32 words[478]; 6265b3f3f2aSShannon Nelson }; 6275b3f3f2aSShannon Nelson 6285b3f3f2aSShannon Nelson /** 6295c28f213SShannon Nelson * struct ionic_q_init_cmd - Queue init command 630fbfb8031SShannon Nelson * @opcode: opcode 631fbfb8031SShannon Nelson * @type: Logical queue type 632c4e7a75aSShannon Nelson * @ver: Queue type version 633fbfb8031SShannon Nelson * @lif_index: LIF index 634c4e7a75aSShannon Nelson * @index: (LIF, qtype) relative admin queue index 635c4e7a75aSShannon Nelson * @intr_index: Interrupt control register index, or Event queue index 636fbfb8031SShannon Nelson * @pid: Process ID 637fbfb8031SShannon Nelson * @flags: 638fbfb8031SShannon Nelson * IRQ: Interrupt requested on completion 639fbfb8031SShannon Nelson * ENA: Enable the queue. If ENA=0 the queue is initialized 640fbfb8031SShannon Nelson * but remains disabled, to be later enabled with the 641fbfb8031SShannon Nelson * Queue Enable command. If ENA=1, then queue is 642fbfb8031SShannon Nelson * initialized and then enabled. 643fbfb8031SShannon Nelson * SG: Enable Scatter-Gather on the queue. 644fbfb8031SShannon Nelson * in number of descs. The actual ring size is 645fbfb8031SShannon Nelson * (1 << ring_size). For example, to 646fbfb8031SShannon Nelson * select a ring size of 64 descriptors write 647fbfb8031SShannon Nelson * ring_size = 6. The minimum ring_size value is 2 648fbfb8031SShannon Nelson * for a ring size of 4 descriptors. The maximum 649fbfb8031SShannon Nelson * ring_size value is 16 for a ring size of 64k 650fbfb8031SShannon Nelson * descriptors. Values of ring_size <2 and >16 are 651fbfb8031SShannon Nelson * reserved. 652fbfb8031SShannon Nelson * EQ: Enable the Event Queue 653c4e7a75aSShannon Nelson * @cos: Class of service for this queue 654fbfb8031SShannon Nelson * @ring_size: Queue ring size, encoded as a log2(size) 655fbfb8031SShannon Nelson * @ring_base: Queue ring base address 656fbfb8031SShannon Nelson * @cq_ring_base: Completion queue ring base address 657fbfb8031SShannon Nelson * @sg_ring_base: Scatter/Gather ring base address 65857a3a98dSShannon Nelson * @features: Mask of queue features to enable, if not in the flags above. 659fbfb8031SShannon Nelson */ 660fbfb8031SShannon Nelson struct ionic_q_init_cmd { 661fbfb8031SShannon Nelson u8 opcode; 662fbfb8031SShannon Nelson u8 rsvd; 663fbfb8031SShannon Nelson __le16 lif_index; 664fbfb8031SShannon Nelson u8 type; 665fbfb8031SShannon Nelson u8 ver; 666fbfb8031SShannon Nelson u8 rsvd1[2]; 667fbfb8031SShannon Nelson __le32 index; 668fbfb8031SShannon Nelson __le16 pid; 669fbfb8031SShannon Nelson __le16 intr_index; 670fbfb8031SShannon Nelson __le16 flags; 671fbfb8031SShannon Nelson #define IONIC_QINIT_F_IRQ 0x01 /* Request interrupt on completion */ 672fbfb8031SShannon Nelson #define IONIC_QINIT_F_ENA 0x02 /* Enable the queue */ 673fbfb8031SShannon Nelson #define IONIC_QINIT_F_SG 0x04 /* Enable scatter/gather on the queue */ 674fbfb8031SShannon Nelson #define IONIC_QINIT_F_EQ 0x08 /* Enable event queue */ 675c4e7a75aSShannon Nelson #define IONIC_QINIT_F_CMB 0x10 /* Enable cmb-based queue */ 676fbfb8031SShannon Nelson #define IONIC_QINIT_F_DEBUG 0x80 /* Enable queue debugging */ 677fbfb8031SShannon Nelson u8 cos; 678fbfb8031SShannon Nelson u8 ring_size; 679fbfb8031SShannon Nelson __le64 ring_base; 680fbfb8031SShannon Nelson __le64 cq_ring_base; 681fbfb8031SShannon Nelson __le64 sg_ring_base; 68257a3a98dSShannon Nelson u8 rsvd2[12]; 68357a3a98dSShannon Nelson __le64 features; 6845dca69c4SShannon Nelson } __packed; 685fbfb8031SShannon Nelson 686fbfb8031SShannon Nelson /** 6875c28f213SShannon Nelson * struct ionic_q_init_comp - Queue init command completion 688c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 689c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 690fbfb8031SShannon Nelson * @hw_index: Hardware Queue ID 691fbfb8031SShannon Nelson * @hw_type: Hardware Queue type 692fbfb8031SShannon Nelson * @color: Color 693fbfb8031SShannon Nelson */ 694fbfb8031SShannon Nelson struct ionic_q_init_comp { 695fbfb8031SShannon Nelson u8 status; 696c4e7a75aSShannon Nelson u8 rsvd; 697fbfb8031SShannon Nelson __le16 comp_index; 698fbfb8031SShannon Nelson __le32 hw_index; 699fbfb8031SShannon Nelson u8 hw_type; 700fbfb8031SShannon Nelson u8 rsvd2[6]; 701fbfb8031SShannon Nelson u8 color; 702fbfb8031SShannon Nelson }; 703fbfb8031SShannon Nelson 704fbfb8031SShannon Nelson /* the device's internal addressing uses up to 52 bits */ 705fbfb8031SShannon Nelson #define IONIC_ADDR_LEN 52 706fbfb8031SShannon Nelson #define IONIC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 707fbfb8031SShannon Nelson 708fbfb8031SShannon Nelson enum ionic_txq_desc_opcode { 709fbfb8031SShannon Nelson IONIC_TXQ_DESC_OPCODE_CSUM_NONE = 0, 710fbfb8031SShannon Nelson IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL = 1, 711fbfb8031SShannon Nelson IONIC_TXQ_DESC_OPCODE_CSUM_HW = 2, 712fbfb8031SShannon Nelson IONIC_TXQ_DESC_OPCODE_TSO = 3, 713fbfb8031SShannon Nelson }; 714fbfb8031SShannon Nelson 715fbfb8031SShannon Nelson /** 7165c28f213SShannon Nelson * struct ionic_txq_desc - Ethernet Tx queue descriptor format 717c4e7a75aSShannon Nelson * @cmd: Tx operation, see IONIC_TXQ_DESC_OPCODE_*: 718fbfb8031SShannon Nelson * 719fbfb8031SShannon Nelson * IONIC_TXQ_DESC_OPCODE_CSUM_NONE: 720fbfb8031SShannon Nelson * Non-offload send. No segmentation, 721fbfb8031SShannon Nelson * fragmentation or checksum calc/insertion is 722fbfb8031SShannon Nelson * performed by device; packet is prepared 723fbfb8031SShannon Nelson * to send by software stack and requires 724fbfb8031SShannon Nelson * no further manipulation from device. 725fbfb8031SShannon Nelson * 726fbfb8031SShannon Nelson * IONIC_TXQ_DESC_OPCODE_CSUM_PARTIAL: 727fbfb8031SShannon Nelson * Offload 16-bit L4 checksum 728fbfb8031SShannon Nelson * calculation/insertion. The device will 729fbfb8031SShannon Nelson * calculate the L4 checksum value and 730fbfb8031SShannon Nelson * insert the result in the packet's L4 731fbfb8031SShannon Nelson * header checksum field. The L4 checksum 732fbfb8031SShannon Nelson * is calculated starting at @csum_start bytes 733fbfb8031SShannon Nelson * into the packet to the end of the packet. 734fbfb8031SShannon Nelson * The checksum insertion position is given 735c4e7a75aSShannon Nelson * in @csum_offset, which is the offset from 736c4e7a75aSShannon Nelson * @csum_start to the checksum field in the L4 737c4e7a75aSShannon Nelson * header. This feature is only applicable to 738c4e7a75aSShannon Nelson * protocols such as TCP, UDP and ICMP where a 739c4e7a75aSShannon Nelson * standard (i.e. the 'IP-style' checksum) 740c4e7a75aSShannon Nelson * one's complement 16-bit checksum is used, 741c4e7a75aSShannon Nelson * using an IP pseudo-header to seed the 742c4e7a75aSShannon Nelson * calculation. Software will preload the L4 743c4e7a75aSShannon Nelson * checksum field with the IP pseudo-header 744c4e7a75aSShannon Nelson * checksum. 745fbfb8031SShannon Nelson * 746fbfb8031SShannon Nelson * For tunnel encapsulation, @csum_start and 747fbfb8031SShannon Nelson * @csum_offset refer to the inner L4 748fbfb8031SShannon Nelson * header. Supported tunnels encapsulations 749fbfb8031SShannon Nelson * are: IPIP, GRE, and UDP. If the @encap 750fbfb8031SShannon Nelson * is clear, no further processing by the 751fbfb8031SShannon Nelson * device is required; software will 752fbfb8031SShannon Nelson * calculate the outer header checksums. If 753fbfb8031SShannon Nelson * the @encap is set, the device will 754fbfb8031SShannon Nelson * offload the outer header checksums using 755fbfb8031SShannon Nelson * LCO (local checksum offload) (see 7560ac624f4SMauro Carvalho Chehab * Documentation/networking/checksum-offloads.rst 7570ac624f4SMauro Carvalho Chehab * for more info). 758fbfb8031SShannon Nelson * 759fbfb8031SShannon Nelson * IONIC_TXQ_DESC_OPCODE_CSUM_HW: 760fbfb8031SShannon Nelson * Offload 16-bit checksum computation to hardware. 761fbfb8031SShannon Nelson * If @csum_l3 is set then the packet's L3 checksum is 762*ecea8bb4SShannon Nelson * updated. Similarly, if @csum_l4 is set the L4 763fbfb8031SShannon Nelson * checksum is updated. If @encap is set then encap header 764fbfb8031SShannon Nelson * checksums are also updated. 765fbfb8031SShannon Nelson * 766fbfb8031SShannon Nelson * IONIC_TXQ_DESC_OPCODE_TSO: 76725cc5a5fSShannon Nelson * Device performs TCP segmentation offload 768fbfb8031SShannon Nelson * (TSO). @hdr_len is the number of bytes 769fbfb8031SShannon Nelson * to the end of TCP header (the offset to 770fbfb8031SShannon Nelson * the TCP payload). @mss is the desired 771fbfb8031SShannon Nelson * MSS, the TCP payload length for each 772fbfb8031SShannon Nelson * segment. The device will calculate/ 773fbfb8031SShannon Nelson * insert IP (IPv4 only) and TCP checksums 774fbfb8031SShannon Nelson * for each segment. In the first data 775fbfb8031SShannon Nelson * buffer containing the header template, 776fbfb8031SShannon Nelson * the driver will set IPv4 checksum to 0 777fbfb8031SShannon Nelson * and preload TCP checksum with the IP 778fbfb8031SShannon Nelson * pseudo header calculated with IP length = 0. 779fbfb8031SShannon Nelson * 780fbfb8031SShannon Nelson * Supported tunnel encapsulations are IPIP, 781fbfb8031SShannon Nelson * layer-3 GRE, and UDP. @hdr_len includes 782fbfb8031SShannon Nelson * both outer and inner headers. The driver 783fbfb8031SShannon Nelson * will set IPv4 checksum to zero and 784fbfb8031SShannon Nelson * preload TCP checksum with IP pseudo 785fbfb8031SShannon Nelson * header on the inner header. 786fbfb8031SShannon Nelson * 787fbfb8031SShannon Nelson * TCP ECN offload is supported. The device 788fbfb8031SShannon Nelson * will set CWR flag in the first segment if 789fbfb8031SShannon Nelson * CWR is set in the template header, and 790fbfb8031SShannon Nelson * clear CWR in remaining segments. 791fbfb8031SShannon Nelson * @flags: 792fbfb8031SShannon Nelson * vlan: 793c4e7a75aSShannon Nelson * Insert an L2 VLAN header using @vlan_tci 794fbfb8031SShannon Nelson * encap: 795c4e7a75aSShannon Nelson * Calculate encap header checksum 796fbfb8031SShannon Nelson * csum_l3: 797c4e7a75aSShannon Nelson * Compute L3 header checksum 798fbfb8031SShannon Nelson * csum_l4: 799c4e7a75aSShannon Nelson * Compute L4 header checksum 800fbfb8031SShannon Nelson * tso_sot: 801fbfb8031SShannon Nelson * TSO start 802fbfb8031SShannon Nelson * tso_eot: 803fbfb8031SShannon Nelson * TSO end 804fbfb8031SShannon Nelson * @num_sg_elems: Number of scatter-gather elements in SG 805fbfb8031SShannon Nelson * descriptor 806c4e7a75aSShannon Nelson * @addr: First data buffer's DMA address 807c4e7a75aSShannon Nelson * (Subsequent data buffers are on txq_sg_desc) 808fbfb8031SShannon Nelson * @len: First data buffer's length, in bytes 809fbfb8031SShannon Nelson * @vlan_tci: VLAN tag to insert in the packet (if requested 810fbfb8031SShannon Nelson * by @V-bit). Includes .1p and .1q tags 811fbfb8031SShannon Nelson * @hdr_len: Length of packet headers, including 812c4e7a75aSShannon Nelson * encapsulating outer header, if applicable 813c4e7a75aSShannon Nelson * Valid for opcodes IONIC_TXQ_DESC_OPCODE_CALC_CSUM and 814c4e7a75aSShannon Nelson * IONIC_TXQ_DESC_OPCODE_TSO. Should be set to zero for 815fbfb8031SShannon Nelson * all other modes. For 816c4e7a75aSShannon Nelson * IONIC_TXQ_DESC_OPCODE_CALC_CSUM, @hdr_len is length 817fbfb8031SShannon Nelson * of headers up to inner-most L4 header. For 818c4e7a75aSShannon Nelson * IONIC_TXQ_DESC_OPCODE_TSO, @hdr_len is up to 819fbfb8031SShannon Nelson * inner-most L4 payload, so inclusive of 820fbfb8031SShannon Nelson * inner-most L4 header. 821c4e7a75aSShannon Nelson * @mss: Desired MSS value for TSO; only applicable for 822c4e7a75aSShannon Nelson * IONIC_TXQ_DESC_OPCODE_TSO 823c4e7a75aSShannon Nelson * @csum_start: Offset from packet to first byte checked in L4 checksum 824c4e7a75aSShannon Nelson * @csum_offset: Offset from csum_start to L4 checksum field 825fbfb8031SShannon Nelson */ 826c4e7a75aSShannon Nelson struct ionic_txq_desc { 827c4e7a75aSShannon Nelson __le64 cmd; 828fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_OPCODE_MASK 0xf 829fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_OPCODE_SHIFT 4 830fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAGS_MASK 0xf 831fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAGS_SHIFT 0 832fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_NSGE_MASK 0xf 833fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_NSGE_SHIFT 8 834fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_ADDR_MASK (BIT_ULL(IONIC_ADDR_LEN) - 1) 835fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_ADDR_SHIFT 12 836fbfb8031SShannon Nelson 837fbfb8031SShannon Nelson /* common flags */ 838fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_VLAN 0x1 839fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_ENCAP 0x2 840fbfb8031SShannon Nelson 841fbfb8031SShannon Nelson /* flags for csum_hw opcode */ 842fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_CSUM_L3 0x4 843fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_CSUM_L4 0x8 844fbfb8031SShannon Nelson 845fbfb8031SShannon Nelson /* flags for tso opcode */ 846fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_TSO_SOT 0x4 847fbfb8031SShannon Nelson #define IONIC_TXQ_DESC_FLAG_TSO_EOT 0x8 848fbfb8031SShannon Nelson 849fbfb8031SShannon Nelson __le16 len; 850fbfb8031SShannon Nelson union { 851fbfb8031SShannon Nelson __le16 vlan_tci; 852fbfb8031SShannon Nelson __le16 hword0; 853fbfb8031SShannon Nelson }; 854fbfb8031SShannon Nelson union { 855fbfb8031SShannon Nelson __le16 csum_start; 856fbfb8031SShannon Nelson __le16 hdr_len; 857fbfb8031SShannon Nelson __le16 hword1; 858fbfb8031SShannon Nelson }; 859fbfb8031SShannon Nelson union { 860fbfb8031SShannon Nelson __le16 csum_offset; 861fbfb8031SShannon Nelson __le16 mss; 862fbfb8031SShannon Nelson __le16 hword2; 863fbfb8031SShannon Nelson }; 864fbfb8031SShannon Nelson }; 865fbfb8031SShannon Nelson 866fbfb8031SShannon Nelson static inline u64 encode_txq_desc_cmd(u8 opcode, u8 flags, 867fbfb8031SShannon Nelson u8 nsge, u64 addr) 868fbfb8031SShannon Nelson { 869fbfb8031SShannon Nelson u64 cmd; 870fbfb8031SShannon Nelson 871fbfb8031SShannon Nelson cmd = (opcode & IONIC_TXQ_DESC_OPCODE_MASK) << IONIC_TXQ_DESC_OPCODE_SHIFT; 872fbfb8031SShannon Nelson cmd |= (flags & IONIC_TXQ_DESC_FLAGS_MASK) << IONIC_TXQ_DESC_FLAGS_SHIFT; 873fbfb8031SShannon Nelson cmd |= (nsge & IONIC_TXQ_DESC_NSGE_MASK) << IONIC_TXQ_DESC_NSGE_SHIFT; 874fbfb8031SShannon Nelson cmd |= (addr & IONIC_TXQ_DESC_ADDR_MASK) << IONIC_TXQ_DESC_ADDR_SHIFT; 875fbfb8031SShannon Nelson 876fbfb8031SShannon Nelson return cmd; 877fbfb8031SShannon Nelson }; 878fbfb8031SShannon Nelson 879fbfb8031SShannon Nelson static inline void decode_txq_desc_cmd(u64 cmd, u8 *opcode, u8 *flags, 880fbfb8031SShannon Nelson u8 *nsge, u64 *addr) 881fbfb8031SShannon Nelson { 882fbfb8031SShannon Nelson *opcode = (cmd >> IONIC_TXQ_DESC_OPCODE_SHIFT) & IONIC_TXQ_DESC_OPCODE_MASK; 883fbfb8031SShannon Nelson *flags = (cmd >> IONIC_TXQ_DESC_FLAGS_SHIFT) & IONIC_TXQ_DESC_FLAGS_MASK; 884fbfb8031SShannon Nelson *nsge = (cmd >> IONIC_TXQ_DESC_NSGE_SHIFT) & IONIC_TXQ_DESC_NSGE_MASK; 885fbfb8031SShannon Nelson *addr = (cmd >> IONIC_TXQ_DESC_ADDR_SHIFT) & IONIC_TXQ_DESC_ADDR_MASK; 886fbfb8031SShannon Nelson }; 887fbfb8031SShannon Nelson 888fbfb8031SShannon Nelson /** 8895b3f3f2aSShannon Nelson * struct ionic_txq_sg_elem - Transmit scatter-gather (SG) descriptor element 890fbfb8031SShannon Nelson * @addr: DMA address of SG element data buffer 891fbfb8031SShannon Nelson * @len: Length of SG element data buffer, in bytes 892fbfb8031SShannon Nelson */ 893fbfb8031SShannon Nelson struct ionic_txq_sg_elem { 894fbfb8031SShannon Nelson __le64 addr; 895fbfb8031SShannon Nelson __le16 len; 896fbfb8031SShannon Nelson __le16 rsvd[3]; 8975b3f3f2aSShannon Nelson }; 8985b3f3f2aSShannon Nelson 8995b3f3f2aSShannon Nelson /** 9005b3f3f2aSShannon Nelson * struct ionic_txq_sg_desc - Transmit scatter-gather (SG) list 9015b3f3f2aSShannon Nelson * @elems: Scatter-gather elements 9025b3f3f2aSShannon Nelson */ 9035b3f3f2aSShannon Nelson struct ionic_txq_sg_desc { 9045b3f3f2aSShannon Nelson #define IONIC_TX_MAX_SG_ELEMS 8 9055b3f3f2aSShannon Nelson #define IONIC_TX_SG_DESC_STRIDE 8 9065b3f3f2aSShannon Nelson struct ionic_txq_sg_elem elems[IONIC_TX_MAX_SG_ELEMS]; 9075b3f3f2aSShannon Nelson }; 9085b3f3f2aSShannon Nelson 9095b3f3f2aSShannon Nelson struct ionic_txq_sg_desc_v1 { 9105b3f3f2aSShannon Nelson #define IONIC_TX_MAX_SG_ELEMS_V1 15 9115b3f3f2aSShannon Nelson #define IONIC_TX_SG_DESC_STRIDE_V1 16 9125b3f3f2aSShannon Nelson struct ionic_txq_sg_elem elems[IONIC_TX_SG_DESC_STRIDE_V1]; 913fbfb8031SShannon Nelson }; 914fbfb8031SShannon Nelson 915fbfb8031SShannon Nelson /** 9165c28f213SShannon Nelson * struct ionic_txq_comp - Ethernet transmit queue completion descriptor 917c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 918c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 919c4e7a75aSShannon Nelson * @color: Color bit 920fbfb8031SShannon Nelson */ 921fbfb8031SShannon Nelson struct ionic_txq_comp { 922fbfb8031SShannon Nelson u8 status; 923fbfb8031SShannon Nelson u8 rsvd; 924fbfb8031SShannon Nelson __le16 comp_index; 925fbfb8031SShannon Nelson u8 rsvd2[11]; 926fbfb8031SShannon Nelson u8 color; 927fbfb8031SShannon Nelson }; 928fbfb8031SShannon Nelson 929fbfb8031SShannon Nelson enum ionic_rxq_desc_opcode { 930fbfb8031SShannon Nelson IONIC_RXQ_DESC_OPCODE_SIMPLE = 0, 931fbfb8031SShannon Nelson IONIC_RXQ_DESC_OPCODE_SG = 1, 932fbfb8031SShannon Nelson }; 933fbfb8031SShannon Nelson 934fbfb8031SShannon Nelson /** 9355c28f213SShannon Nelson * struct ionic_rxq_desc - Ethernet Rx queue descriptor format 936c4e7a75aSShannon Nelson * @opcode: Rx operation, see IONIC_RXQ_DESC_OPCODE_*: 937fbfb8031SShannon Nelson * 938c4e7a75aSShannon Nelson * IONIC_RXQ_DESC_OPCODE_SIMPLE: 939fbfb8031SShannon Nelson * Receive full packet into data buffer 940fbfb8031SShannon Nelson * starting at @addr. Results of 941fbfb8031SShannon Nelson * receive, including actual bytes received, 942fbfb8031SShannon Nelson * are recorded in Rx completion descriptor. 943fbfb8031SShannon Nelson * 944c4e7a75aSShannon Nelson * @len: Data buffer's length, in bytes 945fbfb8031SShannon Nelson * @addr: Data buffer's DMA address 946fbfb8031SShannon Nelson */ 947fbfb8031SShannon Nelson struct ionic_rxq_desc { 948fbfb8031SShannon Nelson u8 opcode; 949fbfb8031SShannon Nelson u8 rsvd[5]; 950fbfb8031SShannon Nelson __le16 len; 951fbfb8031SShannon Nelson __le64 addr; 952fbfb8031SShannon Nelson }; 953fbfb8031SShannon Nelson 954fbfb8031SShannon Nelson /** 955c4e7a75aSShannon Nelson * struct ionic_rxq_sg_elem - Receive scatter-gather (SG) descriptor element 956fbfb8031SShannon Nelson * @addr: DMA address of SG element data buffer 957fbfb8031SShannon Nelson * @len: Length of SG element data buffer, in bytes 958fbfb8031SShannon Nelson */ 959fbfb8031SShannon Nelson struct ionic_rxq_sg_elem { 960fbfb8031SShannon Nelson __le64 addr; 961fbfb8031SShannon Nelson __le16 len; 962fbfb8031SShannon Nelson __le16 rsvd[3]; 9635b3f3f2aSShannon Nelson }; 9645b3f3f2aSShannon Nelson 9655b3f3f2aSShannon Nelson /** 9665b3f3f2aSShannon Nelson * struct ionic_rxq_sg_desc - Receive scatter-gather (SG) list 9675b3f3f2aSShannon Nelson * @elems: Scatter-gather elements 9685b3f3f2aSShannon Nelson */ 9695b3f3f2aSShannon Nelson struct ionic_rxq_sg_desc { 9705b3f3f2aSShannon Nelson #define IONIC_RX_MAX_SG_ELEMS 8 9715b3f3f2aSShannon Nelson #define IONIC_RX_SG_DESC_STRIDE 8 9725b3f3f2aSShannon Nelson struct ionic_rxq_sg_elem elems[IONIC_RX_SG_DESC_STRIDE]; 973fbfb8031SShannon Nelson }; 974fbfb8031SShannon Nelson 975fbfb8031SShannon Nelson /** 9765c28f213SShannon Nelson * struct ionic_rxq_comp - Ethernet receive queue completion descriptor 977c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 978fbfb8031SShannon Nelson * @num_sg_elems: Number of SG elements used by this descriptor 979c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 980fbfb8031SShannon Nelson * @rss_hash: 32-bit RSS hash 981c4e7a75aSShannon Nelson * @csum: 16-bit sum of the packet's L2 payload 982fbfb8031SShannon Nelson * If the packet's L2 payload is odd length, an extra 983fbfb8031SShannon Nelson * zero-value byte is included in the @csum calculation but 984fbfb8031SShannon Nelson * not included in @len. 985fbfb8031SShannon Nelson * @vlan_tci: VLAN tag stripped from the packet. Valid if @VLAN is 986fbfb8031SShannon Nelson * set. Includes .1p and .1q tags. 987fbfb8031SShannon Nelson * @len: Received packet length, in bytes. Excludes FCS. 988fbfb8031SShannon Nelson * @csum_calc L2 payload checksum is computed or not 989c4e7a75aSShannon Nelson * @csum_flags: See IONIC_RXQ_COMP_CSUM_F_*: 990c4e7a75aSShannon Nelson * 991c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_TCP_OK: 992c4e7a75aSShannon Nelson * The TCP checksum calculated by the device 993fbfb8031SShannon Nelson * matched the checksum in the receive packet's 994c4e7a75aSShannon Nelson * TCP header. 995c4e7a75aSShannon Nelson * 996c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_TCP_BAD: 997c4e7a75aSShannon Nelson * The TCP checksum calculated by the device did 998fbfb8031SShannon Nelson * not match the checksum in the receive packet's 999fbfb8031SShannon Nelson * TCP header. 1000c4e7a75aSShannon Nelson * 1001c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_UDP_OK: 1002c4e7a75aSShannon Nelson * The UDP checksum calculated by the device 1003fbfb8031SShannon Nelson * matched the checksum in the receive packet's 1004fbfb8031SShannon Nelson * UDP header 1005c4e7a75aSShannon Nelson * 1006c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_UDP_BAD: 1007c4e7a75aSShannon Nelson * The UDP checksum calculated by the device did 1008fbfb8031SShannon Nelson * not match the checksum in the receive packet's 1009fbfb8031SShannon Nelson * UDP header. 1010c4e7a75aSShannon Nelson * 1011c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_IP_OK: 1012c4e7a75aSShannon Nelson * The IPv4 checksum calculated by the device 1013fbfb8031SShannon Nelson * matched the checksum in the receive packet's 1014fbfb8031SShannon Nelson * first IPv4 header. If the receive packet 1015fbfb8031SShannon Nelson * contains both a tunnel IPv4 header and a 1016fbfb8031SShannon Nelson * transport IPv4 header, the device validates the 1017fbfb8031SShannon Nelson * checksum for the both IPv4 headers. 1018c4e7a75aSShannon Nelson * 1019c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_IP_BAD: 1020c4e7a75aSShannon Nelson * The IPv4 checksum calculated by the device did 1021fbfb8031SShannon Nelson * not match the checksum in the receive packet's 1022fbfb8031SShannon Nelson * first IPv4 header. If the receive packet 1023fbfb8031SShannon Nelson * contains both a tunnel IPv4 header and a 1024fbfb8031SShannon Nelson * transport IPv4 header, the device validates the 1025fbfb8031SShannon Nelson * checksum for both IP headers. 1026c4e7a75aSShannon Nelson * 1027c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_VLAN: 1028c4e7a75aSShannon Nelson * The VLAN header was stripped and placed in @vlan_tci. 1029c4e7a75aSShannon Nelson * 1030c4e7a75aSShannon Nelson * IONIC_RXQ_COMP_CSUM_F_CALC: 1031c4e7a75aSShannon Nelson * The checksum was calculated by the device. 1032c4e7a75aSShannon Nelson * 1033c4e7a75aSShannon Nelson * @pkt_type_color: Packet type and color bit; see IONIC_RXQ_COMP_PKT_TYPE_MASK 1034fbfb8031SShannon Nelson */ 1035fbfb8031SShannon Nelson struct ionic_rxq_comp { 1036fbfb8031SShannon Nelson u8 status; 1037fbfb8031SShannon Nelson u8 num_sg_elems; 1038fbfb8031SShannon Nelson __le16 comp_index; 1039fbfb8031SShannon Nelson __le32 rss_hash; 1040fbfb8031SShannon Nelson __le16 csum; 1041fbfb8031SShannon Nelson __le16 vlan_tci; 1042fbfb8031SShannon Nelson __le16 len; 1043fbfb8031SShannon Nelson u8 csum_flags; 1044fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_TCP_OK 0x01 1045fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_TCP_BAD 0x02 1046fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_UDP_OK 0x04 1047fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_UDP_BAD 0x08 1048fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_IP_OK 0x10 1049fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_IP_BAD 0x20 1050fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_VLAN 0x40 1051fbfb8031SShannon Nelson #define IONIC_RXQ_COMP_CSUM_F_CALC 0x80 1052fbfb8031SShannon Nelson u8 pkt_type_color; 1053b5ce31b5SShannon Nelson #define IONIC_RXQ_COMP_PKT_TYPE_MASK 0x7f 1054fbfb8031SShannon Nelson }; 1055fbfb8031SShannon Nelson 1056fbfb8031SShannon Nelson enum ionic_pkt_type { 105725cc5a5fSShannon Nelson IONIC_PKT_TYPE_NON_IP = 0x00, 105825cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV4 = 0x01, 105925cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV4_TCP = 0x03, 106025cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV4_UDP = 0x05, 106125cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV6 = 0x08, 106225cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV6_TCP = 0x18, 106325cc5a5fSShannon Nelson IONIC_PKT_TYPE_IPV6_UDP = 0x28, 10641b897e7dSShannon Nelson /* below types are only used if encap offloads are enabled on lif */ 10651b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_NON_IP = 0x40, 10661b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV4 = 0x41, 10671b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV4_TCP = 0x43, 10681b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV4_UDP = 0x45, 10691b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV6 = 0x48, 10701b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV6_TCP = 0x58, 10711b897e7dSShannon Nelson IONIC_PKT_TYPE_ENCAP_IPV6_UDP = 0x68, 1072fbfb8031SShannon Nelson }; 1073fbfb8031SShannon Nelson 1074fbfb8031SShannon Nelson enum ionic_eth_hw_features { 1075fbfb8031SShannon Nelson IONIC_ETH_HW_VLAN_TX_TAG = BIT(0), 1076fbfb8031SShannon Nelson IONIC_ETH_HW_VLAN_RX_STRIP = BIT(1), 1077fbfb8031SShannon Nelson IONIC_ETH_HW_VLAN_RX_FILTER = BIT(2), 1078fbfb8031SShannon Nelson IONIC_ETH_HW_RX_HASH = BIT(3), 1079fbfb8031SShannon Nelson IONIC_ETH_HW_RX_CSUM = BIT(4), 1080fbfb8031SShannon Nelson IONIC_ETH_HW_TX_SG = BIT(5), 1081fbfb8031SShannon Nelson IONIC_ETH_HW_RX_SG = BIT(6), 1082fbfb8031SShannon Nelson IONIC_ETH_HW_TX_CSUM = BIT(7), 1083fbfb8031SShannon Nelson IONIC_ETH_HW_TSO = BIT(8), 1084fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_IPV6 = BIT(9), 1085fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_ECN = BIT(10), 1086fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_GRE = BIT(11), 1087fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_GRE_CSUM = BIT(12), 1088fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_IPXIP4 = BIT(13), 1089fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_IPXIP6 = BIT(14), 1090fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_UDP = BIT(15), 1091fbfb8031SShannon Nelson IONIC_ETH_HW_TSO_UDP_CSUM = BIT(16), 10921b897e7dSShannon Nelson IONIC_ETH_HW_RX_CSUM_GENEVE = BIT(17), 10931b897e7dSShannon Nelson IONIC_ETH_HW_TX_CSUM_GENEVE = BIT(18), 10943da25843SShannon Nelson IONIC_ETH_HW_TSO_GENEVE = BIT(19), 10953da25843SShannon Nelson IONIC_ETH_HW_TIMESTAMP = BIT(20), 10963da25843SShannon Nelson }; 10973da25843SShannon Nelson 10983da25843SShannon Nelson /** 10993da25843SShannon Nelson * enum ionic_pkt_class - Packet classification mask. 11003da25843SShannon Nelson * 11013da25843SShannon Nelson * Used with rx steering filter, packets indicated by the mask can be steered 11023da25843SShannon Nelson * toward a specific receive queue. 11033da25843SShannon Nelson * 11043da25843SShannon Nelson * @IONIC_PKT_CLS_NTP_ALL: All NTP packets. 11053da25843SShannon Nelson * @IONIC_PKT_CLS_PTP1_SYNC: PTPv1 sync 11063da25843SShannon Nelson * @IONIC_PKT_CLS_PTP1_DREQ: PTPv1 delay-request 11073da25843SShannon Nelson * @IONIC_PKT_CLS_PTP1_ALL: PTPv1 all packets 11083da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L4_SYNC: PTPv2-UDP sync 11093da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L4_DREQ: PTPv2-UDP delay-request 11103da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L4_ALL: PTPv2-UDP all packets 11113da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L2_SYNC: PTPv2-ETH sync 11123da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L2_DREQ: PTPv2-ETH delay-request 11133da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_L2_ALL: PTPv2-ETH all packets 11143da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_SYNC: PTPv2 sync 11153da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_DREQ: PTPv2 delay-request 11163da25843SShannon Nelson * @IONIC_PKT_CLS_PTP2_ALL: PTPv2 all packets 11173da25843SShannon Nelson * @IONIC_PKT_CLS_PTP_SYNC: PTP sync 11183da25843SShannon Nelson * @IONIC_PKT_CLS_PTP_DREQ: PTP delay-request 11193da25843SShannon Nelson * @IONIC_PKT_CLS_PTP_ALL: PTP all packets 11203da25843SShannon Nelson */ 11213da25843SShannon Nelson enum ionic_pkt_class { 11223da25843SShannon Nelson IONIC_PKT_CLS_NTP_ALL = BIT(0), 11233da25843SShannon Nelson 11243da25843SShannon Nelson IONIC_PKT_CLS_PTP1_SYNC = BIT(1), 11253da25843SShannon Nelson IONIC_PKT_CLS_PTP1_DREQ = BIT(2), 11263da25843SShannon Nelson IONIC_PKT_CLS_PTP1_ALL = BIT(3) | 11273da25843SShannon Nelson IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP1_DREQ, 11283da25843SShannon Nelson 11293da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_SYNC = BIT(4), 11303da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_DREQ = BIT(5), 11313da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_ALL = BIT(6) | 11323da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L4_DREQ, 11333da25843SShannon Nelson 11343da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L2_SYNC = BIT(7), 11353da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L2_DREQ = BIT(8), 11363da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L2_ALL = BIT(9) | 11373da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L2_SYNC | IONIC_PKT_CLS_PTP2_L2_DREQ, 11383da25843SShannon Nelson 11393da25843SShannon Nelson IONIC_PKT_CLS_PTP2_SYNC = 11403da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_SYNC | IONIC_PKT_CLS_PTP2_L2_SYNC, 11413da25843SShannon Nelson IONIC_PKT_CLS_PTP2_DREQ = 11423da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_DREQ | IONIC_PKT_CLS_PTP2_L2_DREQ, 11433da25843SShannon Nelson IONIC_PKT_CLS_PTP2_ALL = 11443da25843SShannon Nelson IONIC_PKT_CLS_PTP2_L4_ALL | IONIC_PKT_CLS_PTP2_L2_ALL, 11453da25843SShannon Nelson 11463da25843SShannon Nelson IONIC_PKT_CLS_PTP_SYNC = 11473da25843SShannon Nelson IONIC_PKT_CLS_PTP1_SYNC | IONIC_PKT_CLS_PTP2_SYNC, 11483da25843SShannon Nelson IONIC_PKT_CLS_PTP_DREQ = 11493da25843SShannon Nelson IONIC_PKT_CLS_PTP1_DREQ | IONIC_PKT_CLS_PTP2_DREQ, 11503da25843SShannon Nelson IONIC_PKT_CLS_PTP_ALL = 11513da25843SShannon Nelson IONIC_PKT_CLS_PTP1_ALL | IONIC_PKT_CLS_PTP2_ALL, 1152fbfb8031SShannon Nelson }; 1153fbfb8031SShannon Nelson 1154fbfb8031SShannon Nelson /** 11555c28f213SShannon Nelson * struct ionic_q_control_cmd - Queue control command 1156fbfb8031SShannon Nelson * @opcode: opcode 1157fbfb8031SShannon Nelson * @type: Queue type 1158fbfb8031SShannon Nelson * @lif_index: LIF index 1159fbfb8031SShannon Nelson * @index: Queue index 11601b897e7dSShannon Nelson * @oper: Operation (enum ionic_q_control_oper) 1161fbfb8031SShannon Nelson */ 1162fbfb8031SShannon Nelson struct ionic_q_control_cmd { 1163fbfb8031SShannon Nelson u8 opcode; 1164fbfb8031SShannon Nelson u8 type; 1165fbfb8031SShannon Nelson __le16 lif_index; 1166fbfb8031SShannon Nelson __le32 index; 1167fbfb8031SShannon Nelson u8 oper; 1168fbfb8031SShannon Nelson u8 rsvd[55]; 1169fbfb8031SShannon Nelson }; 1170fbfb8031SShannon Nelson 1171fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_q_control_comp; 1172fbfb8031SShannon Nelson 1173fbfb8031SShannon Nelson enum q_control_oper { 1174fbfb8031SShannon Nelson IONIC_Q_DISABLE = 0, 1175fbfb8031SShannon Nelson IONIC_Q_ENABLE = 1, 1176fbfb8031SShannon Nelson IONIC_Q_HANG_RESET = 2, 1177fbfb8031SShannon Nelson }; 1178fbfb8031SShannon Nelson 1179fbfb8031SShannon Nelson /** 1180c4e7a75aSShannon Nelson * enum ionic_phy_type - Physical connection type 1181c4e7a75aSShannon Nelson * @IONIC_PHY_TYPE_NONE: No PHY installed 1182c4e7a75aSShannon Nelson * @IONIC_PHY_TYPE_COPPER: Copper PHY 1183c4e7a75aSShannon Nelson * @IONIC_PHY_TYPE_FIBER: Fiber PHY 1184fbfb8031SShannon Nelson */ 1185fbfb8031SShannon Nelson enum ionic_phy_type { 1186fbfb8031SShannon Nelson IONIC_PHY_TYPE_NONE = 0, 1187fbfb8031SShannon Nelson IONIC_PHY_TYPE_COPPER = 1, 1188fbfb8031SShannon Nelson IONIC_PHY_TYPE_FIBER = 2, 1189fbfb8031SShannon Nelson }; 1190fbfb8031SShannon Nelson 1191fbfb8031SShannon Nelson /** 1192c4e7a75aSShannon Nelson * enum ionic_xcvr_state - Transceiver status 1193c4e7a75aSShannon Nelson * @IONIC_XCVR_STATE_REMOVED: Transceiver removed 1194c4e7a75aSShannon Nelson * @IONIC_XCVR_STATE_INSERTED: Transceiver inserted 1195c4e7a75aSShannon Nelson * @IONIC_XCVR_STATE_PENDING: Transceiver pending 1196c4e7a75aSShannon Nelson * @IONIC_XCVR_STATE_SPROM_READ: Transceiver data read 1197c4e7a75aSShannon Nelson * @IONIC_XCVR_STATE_SPROM_READ_ERR: Transceiver data read error 1198fbfb8031SShannon Nelson */ 1199fbfb8031SShannon Nelson enum ionic_xcvr_state { 1200fbfb8031SShannon Nelson IONIC_XCVR_STATE_REMOVED = 0, 1201fbfb8031SShannon Nelson IONIC_XCVR_STATE_INSERTED = 1, 1202fbfb8031SShannon Nelson IONIC_XCVR_STATE_PENDING = 2, 1203fbfb8031SShannon Nelson IONIC_XCVR_STATE_SPROM_READ = 3, 1204fbfb8031SShannon Nelson IONIC_XCVR_STATE_SPROM_READ_ERR = 4, 1205fbfb8031SShannon Nelson }; 1206fbfb8031SShannon Nelson 1207fbfb8031SShannon Nelson /** 1208c4e7a75aSShannon Nelson * enum ionic_xcvr_pid - Supported link modes 1209fbfb8031SShannon Nelson */ 1210fbfb8031SShannon Nelson enum ionic_xcvr_pid { 1211fbfb8031SShannon Nelson IONIC_XCVR_PID_UNKNOWN = 0, 1212fbfb8031SShannon Nelson 1213fbfb8031SShannon Nelson /* CU */ 1214fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_CR4 = 1, 1215fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_40GBASE_CR4 = 2, 1216fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_CR_S = 3, 1217fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_CR_L = 4, 1218fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_CR_N = 5, 1219fbfb8031SShannon Nelson 1220fbfb8031SShannon Nelson /* Fiber */ 1221fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_AOC = 50, 1222fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_ACC = 51, 1223fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_SR4 = 52, 1224fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_LR4 = 53, 1225fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_ER4 = 54, 1226fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_40GBASE_ER4 = 55, 1227fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_40GBASE_SR4 = 56, 1228fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_40GBASE_LR4 = 57, 1229fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_40GBASE_AOC = 58, 1230fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_SR = 59, 1231fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_LR = 60, 1232fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_ER = 61, 1233fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_AOC = 62, 1234fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_SR = 63, 1235fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_LR = 64, 1236fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_LRM = 65, 1237fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_ER = 66, 1238fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_AOC = 67, 1239fbfb8031SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_CU = 68, 1240fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_CWDM4 = 69, 1241fbfb8031SShannon Nelson IONIC_XCVR_PID_QSFP_100G_PSM4 = 70, 1242c4e7a75aSShannon Nelson IONIC_XCVR_PID_SFP_25GBASE_ACC = 71, 1243acc606d3SShannon Nelson IONIC_XCVR_PID_SFP_10GBASE_T = 72, 1244acc606d3SShannon Nelson IONIC_XCVR_PID_SFP_1000BASE_T = 73, 1245fbfb8031SShannon Nelson }; 1246fbfb8031SShannon Nelson 1247fbfb8031SShannon Nelson /** 1248c4e7a75aSShannon Nelson * enum ionic_port_type - Port types 1249c4e7a75aSShannon Nelson * @IONIC_PORT_TYPE_NONE: Port type not configured 1250c4e7a75aSShannon Nelson * @IONIC_PORT_TYPE_ETH: Port carries ethernet traffic (inband) 1251c4e7a75aSShannon Nelson * @IONIC_PORT_TYPE_MGMT: Port carries mgmt traffic (out-of-band) 1252fbfb8031SShannon Nelson */ 1253fbfb8031SShannon Nelson enum ionic_port_type { 1254c4e7a75aSShannon Nelson IONIC_PORT_TYPE_NONE = 0, 1255c4e7a75aSShannon Nelson IONIC_PORT_TYPE_ETH = 1, 1256c4e7a75aSShannon Nelson IONIC_PORT_TYPE_MGMT = 2, 1257fbfb8031SShannon Nelson }; 1258fbfb8031SShannon Nelson 1259fbfb8031SShannon Nelson /** 1260c4e7a75aSShannon Nelson * enum ionic_port_admin_state - Port config state 1261c4e7a75aSShannon Nelson * @IONIC_PORT_ADMIN_STATE_NONE: Port admin state not configured 1262c4e7a75aSShannon Nelson * @IONIC_PORT_ADMIN_STATE_DOWN: Port admin disabled 1263c4e7a75aSShannon Nelson * @IONIC_PORT_ADMIN_STATE_UP: Port admin enabled 1264fbfb8031SShannon Nelson */ 1265fbfb8031SShannon Nelson enum ionic_port_admin_state { 1266c4e7a75aSShannon Nelson IONIC_PORT_ADMIN_STATE_NONE = 0, 1267c4e7a75aSShannon Nelson IONIC_PORT_ADMIN_STATE_DOWN = 1, 1268c4e7a75aSShannon Nelson IONIC_PORT_ADMIN_STATE_UP = 2, 1269fbfb8031SShannon Nelson }; 1270fbfb8031SShannon Nelson 1271fbfb8031SShannon Nelson /** 1272c4e7a75aSShannon Nelson * enum ionic_port_oper_status - Port operational status 1273c4e7a75aSShannon Nelson * @IONIC_PORT_OPER_STATUS_NONE: Port disabled 1274c4e7a75aSShannon Nelson * @IONIC_PORT_OPER_STATUS_UP: Port link status up 1275c4e7a75aSShannon Nelson * @IONIC_PORT_OPER_STATUS_DOWN: Port link status down 1276fbfb8031SShannon Nelson */ 1277fbfb8031SShannon Nelson enum ionic_port_oper_status { 1278c4e7a75aSShannon Nelson IONIC_PORT_OPER_STATUS_NONE = 0, 1279c4e7a75aSShannon Nelson IONIC_PORT_OPER_STATUS_UP = 1, 1280c4e7a75aSShannon Nelson IONIC_PORT_OPER_STATUS_DOWN = 2, 1281fbfb8031SShannon Nelson }; 1282fbfb8031SShannon Nelson 1283fbfb8031SShannon Nelson /** 1284c4e7a75aSShannon Nelson * enum ionic_port_fec_type - Ethernet Forward error correction (FEC) modes 1285c4e7a75aSShannon Nelson * @IONIC_PORT_FEC_TYPE_NONE: FEC Disabled 1286c4e7a75aSShannon Nelson * @IONIC_PORT_FEC_TYPE_FC: FireCode FEC 1287c4e7a75aSShannon Nelson * @IONIC_PORT_FEC_TYPE_RS: ReedSolomon FEC 1288fbfb8031SShannon Nelson */ 1289fbfb8031SShannon Nelson enum ionic_port_fec_type { 1290c4e7a75aSShannon Nelson IONIC_PORT_FEC_TYPE_NONE = 0, 1291c4e7a75aSShannon Nelson IONIC_PORT_FEC_TYPE_FC = 1, 1292c4e7a75aSShannon Nelson IONIC_PORT_FEC_TYPE_RS = 2, 1293fbfb8031SShannon Nelson }; 1294fbfb8031SShannon Nelson 1295fbfb8031SShannon Nelson /** 1296c4e7a75aSShannon Nelson * enum ionic_port_pause_type - Ethernet pause (flow control) modes 1297c4e7a75aSShannon Nelson * @IONIC_PORT_PAUSE_TYPE_NONE: Disable Pause 1298c4e7a75aSShannon Nelson * @IONIC_PORT_PAUSE_TYPE_LINK: Link level pause 1299c4e7a75aSShannon Nelson * @IONIC_PORT_PAUSE_TYPE_PFC: Priority-Flow Control 1300fbfb8031SShannon Nelson */ 1301fbfb8031SShannon Nelson enum ionic_port_pause_type { 1302c4e7a75aSShannon Nelson IONIC_PORT_PAUSE_TYPE_NONE = 0, 1303c4e7a75aSShannon Nelson IONIC_PORT_PAUSE_TYPE_LINK = 1, 1304c4e7a75aSShannon Nelson IONIC_PORT_PAUSE_TYPE_PFC = 2, 1305fbfb8031SShannon Nelson }; 1306fbfb8031SShannon Nelson 1307fbfb8031SShannon Nelson /** 1308c4e7a75aSShannon Nelson * enum ionic_port_loopback_mode - Loopback modes 1309c4e7a75aSShannon Nelson * @IONIC_PORT_LOOPBACK_MODE_NONE: Disable loopback 1310c4e7a75aSShannon Nelson * @IONIC_PORT_LOOPBACK_MODE_MAC: MAC loopback 1311c4e7a75aSShannon Nelson * @IONIC_PORT_LOOPBACK_MODE_PHY: PHY/SerDes loopback 1312fbfb8031SShannon Nelson */ 1313fbfb8031SShannon Nelson enum ionic_port_loopback_mode { 1314c4e7a75aSShannon Nelson IONIC_PORT_LOOPBACK_MODE_NONE = 0, 1315c4e7a75aSShannon Nelson IONIC_PORT_LOOPBACK_MODE_MAC = 1, 1316c4e7a75aSShannon Nelson IONIC_PORT_LOOPBACK_MODE_PHY = 2, 1317fbfb8031SShannon Nelson }; 1318fbfb8031SShannon Nelson 1319fbfb8031SShannon Nelson /** 1320c4e7a75aSShannon Nelson * struct ionic_xcvr_status - Transceiver Status information 13215c28f213SShannon Nelson * @state: Transceiver status (enum ionic_xcvr_state) 13225c28f213SShannon Nelson * @phy: Physical connection type (enum ionic_phy_type) 13231b897e7dSShannon Nelson * @pid: Transceiver link mode (enum ionic_xcvr_pid) 1324fbfb8031SShannon Nelson * @sprom: Transceiver sprom contents 1325fbfb8031SShannon Nelson */ 1326fbfb8031SShannon Nelson struct ionic_xcvr_status { 1327fbfb8031SShannon Nelson u8 state; 1328fbfb8031SShannon Nelson u8 phy; 1329fbfb8031SShannon Nelson __le16 pid; 1330fbfb8031SShannon Nelson u8 sprom[256]; 1331fbfb8031SShannon Nelson }; 1332fbfb8031SShannon Nelson 1333fbfb8031SShannon Nelson /** 1334c4e7a75aSShannon Nelson * union ionic_port_config - Port configuration 1335fbfb8031SShannon Nelson * @speed: port speed (in Mbps) 1336fbfb8031SShannon Nelson * @mtu: mtu 13371b897e7dSShannon Nelson * @state: port admin state (enum ionic_port_admin_state) 1338fbfb8031SShannon Nelson * @an_enable: autoneg enable 13395c28f213SShannon Nelson * @fec_type: fec type (enum ionic_port_fec_type) 13405c28f213SShannon Nelson * @pause_type: pause type (enum ionic_port_pause_type) 13415c28f213SShannon Nelson * @loopback_mode: loopback mode (enum ionic_port_loopback_mode) 1342fbfb8031SShannon Nelson */ 1343fbfb8031SShannon Nelson union ionic_port_config { 1344fbfb8031SShannon Nelson struct { 1345fbfb8031SShannon Nelson #define IONIC_SPEED_100G 100000 /* 100G in Mbps */ 1346fbfb8031SShannon Nelson #define IONIC_SPEED_50G 50000 /* 50G in Mbps */ 1347fbfb8031SShannon Nelson #define IONIC_SPEED_40G 40000 /* 40G in Mbps */ 1348fbfb8031SShannon Nelson #define IONIC_SPEED_25G 25000 /* 25G in Mbps */ 1349fbfb8031SShannon Nelson #define IONIC_SPEED_10G 10000 /* 10G in Mbps */ 1350fbfb8031SShannon Nelson #define IONIC_SPEED_1G 1000 /* 1G in Mbps */ 1351fbfb8031SShannon Nelson __le32 speed; 1352fbfb8031SShannon Nelson __le32 mtu; 1353fbfb8031SShannon Nelson u8 state; 1354fbfb8031SShannon Nelson u8 an_enable; 1355fbfb8031SShannon Nelson u8 fec_type; 1356fbfb8031SShannon Nelson #define IONIC_PAUSE_TYPE_MASK 0x0f 1357fbfb8031SShannon Nelson #define IONIC_PAUSE_FLAGS_MASK 0xf0 1358fbfb8031SShannon Nelson #define IONIC_PAUSE_F_TX 0x10 1359fbfb8031SShannon Nelson #define IONIC_PAUSE_F_RX 0x20 1360fbfb8031SShannon Nelson u8 pause_type; 1361fbfb8031SShannon Nelson u8 loopback_mode; 1362fbfb8031SShannon Nelson }; 1363fbfb8031SShannon Nelson __le32 words[64]; 1364fbfb8031SShannon Nelson }; 1365fbfb8031SShannon Nelson 1366fbfb8031SShannon Nelson /** 1367c4e7a75aSShannon Nelson * struct ionic_port_status - Port Status information 13685c28f213SShannon Nelson * @status: link status (enum ionic_port_oper_status) 1369fbfb8031SShannon Nelson * @id: port id 1370fbfb8031SShannon Nelson * @speed: link speed (in Mbps) 1371*ecea8bb4SShannon Nelson * @link_down_count: number of times link went from up to down 1372c4e7a75aSShannon Nelson * @fec_type: fec type (enum ionic_port_fec_type) 1373*ecea8bb4SShannon Nelson * @xcvr: transceiver status 1374fbfb8031SShannon Nelson */ 1375fbfb8031SShannon Nelson struct ionic_port_status { 1376fbfb8031SShannon Nelson __le32 id; 1377fbfb8031SShannon Nelson __le32 speed; 1378fbfb8031SShannon Nelson u8 status; 1379c4e7a75aSShannon Nelson __le16 link_down_count; 1380c4e7a75aSShannon Nelson u8 fec_type; 1381c4e7a75aSShannon Nelson u8 rsvd[48]; 1382fbfb8031SShannon Nelson struct ionic_xcvr_status xcvr; 13835dca69c4SShannon Nelson } __packed; 1384fbfb8031SShannon Nelson 1385fbfb8031SShannon Nelson /** 13865c28f213SShannon Nelson * struct ionic_port_identify_cmd - Port identify command 1387fbfb8031SShannon Nelson * @opcode: opcode 1388fbfb8031SShannon Nelson * @index: port index 1389fbfb8031SShannon Nelson * @ver: Highest version of identify supported by driver 1390fbfb8031SShannon Nelson */ 1391fbfb8031SShannon Nelson struct ionic_port_identify_cmd { 1392fbfb8031SShannon Nelson u8 opcode; 1393fbfb8031SShannon Nelson u8 index; 1394fbfb8031SShannon Nelson u8 ver; 1395fbfb8031SShannon Nelson u8 rsvd[61]; 1396fbfb8031SShannon Nelson }; 1397fbfb8031SShannon Nelson 1398fbfb8031SShannon Nelson /** 13995c28f213SShannon Nelson * struct ionic_port_identify_comp - Port identify command completion 1400c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1401fbfb8031SShannon Nelson * @ver: Version of identify returned by device 1402fbfb8031SShannon Nelson */ 1403fbfb8031SShannon Nelson struct ionic_port_identify_comp { 1404fbfb8031SShannon Nelson u8 status; 1405fbfb8031SShannon Nelson u8 ver; 1406fbfb8031SShannon Nelson u8 rsvd[14]; 1407fbfb8031SShannon Nelson }; 1408fbfb8031SShannon Nelson 1409fbfb8031SShannon Nelson /** 14105c28f213SShannon Nelson * struct ionic_port_init_cmd - Port initialization command 1411fbfb8031SShannon Nelson * @opcode: opcode 1412fbfb8031SShannon Nelson * @index: port index 14135c28f213SShannon Nelson * @info_pa: destination address for port info (struct ionic_port_info) 1414fbfb8031SShannon Nelson */ 1415fbfb8031SShannon Nelson struct ionic_port_init_cmd { 1416fbfb8031SShannon Nelson u8 opcode; 1417fbfb8031SShannon Nelson u8 index; 1418fbfb8031SShannon Nelson u8 rsvd[6]; 1419fbfb8031SShannon Nelson __le64 info_pa; 1420fbfb8031SShannon Nelson u8 rsvd2[48]; 1421fbfb8031SShannon Nelson }; 1422fbfb8031SShannon Nelson 1423fbfb8031SShannon Nelson /** 14245c28f213SShannon Nelson * struct ionic_port_init_comp - Port initialization command completion 1425c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1426fbfb8031SShannon Nelson */ 1427fbfb8031SShannon Nelson struct ionic_port_init_comp { 1428fbfb8031SShannon Nelson u8 status; 1429fbfb8031SShannon Nelson u8 rsvd[15]; 1430fbfb8031SShannon Nelson }; 1431fbfb8031SShannon Nelson 1432fbfb8031SShannon Nelson /** 14335c28f213SShannon Nelson * struct ionic_port_reset_cmd - Port reset command 1434fbfb8031SShannon Nelson * @opcode: opcode 1435fbfb8031SShannon Nelson * @index: port index 1436fbfb8031SShannon Nelson */ 1437fbfb8031SShannon Nelson struct ionic_port_reset_cmd { 1438fbfb8031SShannon Nelson u8 opcode; 1439fbfb8031SShannon Nelson u8 index; 1440fbfb8031SShannon Nelson u8 rsvd[62]; 1441fbfb8031SShannon Nelson }; 1442fbfb8031SShannon Nelson 1443fbfb8031SShannon Nelson /** 14445c28f213SShannon Nelson * struct ionic_port_reset_comp - Port reset command completion 1445c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1446fbfb8031SShannon Nelson */ 1447fbfb8031SShannon Nelson struct ionic_port_reset_comp { 1448fbfb8031SShannon Nelson u8 status; 1449fbfb8031SShannon Nelson u8 rsvd[15]; 1450fbfb8031SShannon Nelson }; 1451fbfb8031SShannon Nelson 1452fbfb8031SShannon Nelson /** 1453c4e7a75aSShannon Nelson * enum ionic_stats_ctl_cmd - List of commands for stats control 1454c4e7a75aSShannon Nelson * @IONIC_STATS_CTL_RESET: Reset statistics 1455fbfb8031SShannon Nelson */ 1456fbfb8031SShannon Nelson enum ionic_stats_ctl_cmd { 1457fbfb8031SShannon Nelson IONIC_STATS_CTL_RESET = 0, 1458fbfb8031SShannon Nelson }; 1459fbfb8031SShannon Nelson 1460fbfb8031SShannon Nelson /** 14613da25843SShannon Nelson * enum ionic_txstamp_mode - List of TX Timestamping Modes 14623da25843SShannon Nelson * @IONIC_TXSTAMP_OFF: Disable TX hardware timetamping. 14633da25843SShannon Nelson * @IONIC_TXSTAMP_ON: Enable local TX hardware timetamping. 14643da25843SShannon Nelson * @IONIC_TXSTAMP_ONESTEP_SYNC: Modify TX PTP Sync packets. 14653da25843SShannon Nelson * @IONIC_TXSTAMP_ONESTEP_P2P: Modify TX PTP Sync and PDelayResp. 14663da25843SShannon Nelson */ 14673da25843SShannon Nelson enum ionic_txstamp_mode { 14683da25843SShannon Nelson IONIC_TXSTAMP_OFF = 0, 14693da25843SShannon Nelson IONIC_TXSTAMP_ON = 1, 14703da25843SShannon Nelson IONIC_TXSTAMP_ONESTEP_SYNC = 2, 14713da25843SShannon Nelson IONIC_TXSTAMP_ONESTEP_P2P = 3, 14723da25843SShannon Nelson }; 14733da25843SShannon Nelson 14743da25843SShannon Nelson /** 1475fbfb8031SShannon Nelson * enum ionic_port_attr - List of device attributes 1476c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_STATE: Port state attribute 1477c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_SPEED: Port speed attribute 1478c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_MTU: Port MTU attribute 147925cc5a5fSShannon Nelson * @IONIC_PORT_ATTR_AUTONEG: Port autonegotiation attribute 1480c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_FEC: Port FEC attribute 1481c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_PAUSE: Port pause attribute 1482c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_LOOPBACK: Port loopback attribute 1483c4e7a75aSShannon Nelson * @IONIC_PORT_ATTR_STATS_CTRL: Port statistics control attribute 1484fbfb8031SShannon Nelson */ 1485fbfb8031SShannon Nelson enum ionic_port_attr { 1486fbfb8031SShannon Nelson IONIC_PORT_ATTR_STATE = 0, 1487fbfb8031SShannon Nelson IONIC_PORT_ATTR_SPEED = 1, 1488fbfb8031SShannon Nelson IONIC_PORT_ATTR_MTU = 2, 1489fbfb8031SShannon Nelson IONIC_PORT_ATTR_AUTONEG = 3, 1490fbfb8031SShannon Nelson IONIC_PORT_ATTR_FEC = 4, 1491fbfb8031SShannon Nelson IONIC_PORT_ATTR_PAUSE = 5, 1492fbfb8031SShannon Nelson IONIC_PORT_ATTR_LOOPBACK = 6, 1493fbfb8031SShannon Nelson IONIC_PORT_ATTR_STATS_CTRL = 7, 1494fbfb8031SShannon Nelson }; 1495fbfb8031SShannon Nelson 1496fbfb8031SShannon Nelson /** 14975c28f213SShannon Nelson * struct ionic_port_setattr_cmd - Set port attributes on the NIC 1498fbfb8031SShannon Nelson * @opcode: Opcode 1499c4e7a75aSShannon Nelson * @index: Port index 1500fbfb8031SShannon Nelson * @attr: Attribute type (enum ionic_port_attr) 1501c4e7a75aSShannon Nelson * @state: Port state 1502c4e7a75aSShannon Nelson * @speed: Port speed 1503c4e7a75aSShannon Nelson * @mtu: Port MTU 1504c4e7a75aSShannon Nelson * @an_enable: Port autonegotiation setting 1505c4e7a75aSShannon Nelson * @fec_type: Port FEC type setting 1506c4e7a75aSShannon Nelson * @pause_type: Port pause type setting 1507c4e7a75aSShannon Nelson * @loopback_mode: Port loopback mode 1508c4e7a75aSShannon Nelson * @stats_ctl: Port stats setting 1509fbfb8031SShannon Nelson */ 1510fbfb8031SShannon Nelson struct ionic_port_setattr_cmd { 1511fbfb8031SShannon Nelson u8 opcode; 1512fbfb8031SShannon Nelson u8 index; 1513fbfb8031SShannon Nelson u8 attr; 1514fbfb8031SShannon Nelson u8 rsvd; 1515fbfb8031SShannon Nelson union { 1516fbfb8031SShannon Nelson u8 state; 1517fbfb8031SShannon Nelson __le32 speed; 1518fbfb8031SShannon Nelson __le32 mtu; 1519fbfb8031SShannon Nelson u8 an_enable; 1520fbfb8031SShannon Nelson u8 fec_type; 1521fbfb8031SShannon Nelson u8 pause_type; 1522fbfb8031SShannon Nelson u8 loopback_mode; 1523fbfb8031SShannon Nelson u8 stats_ctl; 1524fbfb8031SShannon Nelson u8 rsvd2[60]; 1525fbfb8031SShannon Nelson }; 1526fbfb8031SShannon Nelson }; 1527fbfb8031SShannon Nelson 1528fbfb8031SShannon Nelson /** 15295c28f213SShannon Nelson * struct ionic_port_setattr_comp - Port set attr command completion 1530c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1531fbfb8031SShannon Nelson * @color: Color bit 1532fbfb8031SShannon Nelson */ 1533fbfb8031SShannon Nelson struct ionic_port_setattr_comp { 1534fbfb8031SShannon Nelson u8 status; 1535fbfb8031SShannon Nelson u8 rsvd[14]; 1536fbfb8031SShannon Nelson u8 color; 1537fbfb8031SShannon Nelson }; 1538fbfb8031SShannon Nelson 1539fbfb8031SShannon Nelson /** 15405c28f213SShannon Nelson * struct ionic_port_getattr_cmd - Get port attributes from the NIC 1541fbfb8031SShannon Nelson * @opcode: Opcode 1542fbfb8031SShannon Nelson * @index: port index 1543fbfb8031SShannon Nelson * @attr: Attribute type (enum ionic_port_attr) 1544fbfb8031SShannon Nelson */ 1545fbfb8031SShannon Nelson struct ionic_port_getattr_cmd { 1546fbfb8031SShannon Nelson u8 opcode; 1547fbfb8031SShannon Nelson u8 index; 1548fbfb8031SShannon Nelson u8 attr; 1549fbfb8031SShannon Nelson u8 rsvd[61]; 1550fbfb8031SShannon Nelson }; 1551fbfb8031SShannon Nelson 1552fbfb8031SShannon Nelson /** 15535c28f213SShannon Nelson * struct ionic_port_getattr_comp - Port get attr command completion 1554c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1555c4e7a75aSShannon Nelson * @state: Port state 1556c4e7a75aSShannon Nelson * @speed: Port speed 1557c4e7a75aSShannon Nelson * @mtu: Port MTU 1558c4e7a75aSShannon Nelson * @an_enable: Port autonegotiation setting 1559c4e7a75aSShannon Nelson * @fec_type: Port FEC type setting 1560c4e7a75aSShannon Nelson * @pause_type: Port pause type setting 1561c4e7a75aSShannon Nelson * @loopback_mode: Port loopback mode 1562fbfb8031SShannon Nelson * @color: Color bit 1563fbfb8031SShannon Nelson */ 1564fbfb8031SShannon Nelson struct ionic_port_getattr_comp { 1565fbfb8031SShannon Nelson u8 status; 1566fbfb8031SShannon Nelson u8 rsvd[3]; 1567fbfb8031SShannon Nelson union { 1568fbfb8031SShannon Nelson u8 state; 1569fbfb8031SShannon Nelson __le32 speed; 1570fbfb8031SShannon Nelson __le32 mtu; 1571fbfb8031SShannon Nelson u8 an_enable; 1572fbfb8031SShannon Nelson u8 fec_type; 1573fbfb8031SShannon Nelson u8 pause_type; 1574fbfb8031SShannon Nelson u8 loopback_mode; 1575fbfb8031SShannon Nelson u8 rsvd2[11]; 15765dca69c4SShannon Nelson } __packed; 1577fbfb8031SShannon Nelson u8 color; 1578fbfb8031SShannon Nelson }; 1579fbfb8031SShannon Nelson 1580fbfb8031SShannon Nelson /** 1581c4e7a75aSShannon Nelson * struct ionic_lif_status - LIF status register 1582fbfb8031SShannon Nelson * @eid: most recent NotifyQ event id 1583c4e7a75aSShannon Nelson * @port_num: port the LIF is connected to 15845c28f213SShannon Nelson * @link_status: port status (enum ionic_port_oper_status) 1585fbfb8031SShannon Nelson * @link_speed: speed of link in Mbps 1586c4e7a75aSShannon Nelson * @link_down_count: number of times link went from up to down 1587fbfb8031SShannon Nelson */ 1588fbfb8031SShannon Nelson struct ionic_lif_status { 1589fbfb8031SShannon Nelson __le64 eid; 1590fbfb8031SShannon Nelson u8 port_num; 1591fbfb8031SShannon Nelson u8 rsvd; 1592fbfb8031SShannon Nelson __le16 link_status; 1593fbfb8031SShannon Nelson __le32 link_speed; /* units of 1Mbps: eg 10000 = 10Gbps */ 1594fbfb8031SShannon Nelson __le16 link_down_count; 1595fbfb8031SShannon Nelson u8 rsvd2[46]; 1596fbfb8031SShannon Nelson }; 1597fbfb8031SShannon Nelson 1598fbfb8031SShannon Nelson /** 15995c28f213SShannon Nelson * struct ionic_lif_reset_cmd - LIF reset command 1600fbfb8031SShannon Nelson * @opcode: opcode 1601fbfb8031SShannon Nelson * @index: LIF index 1602fbfb8031SShannon Nelson */ 1603fbfb8031SShannon Nelson struct ionic_lif_reset_cmd { 1604fbfb8031SShannon Nelson u8 opcode; 1605fbfb8031SShannon Nelson u8 rsvd; 1606fbfb8031SShannon Nelson __le16 index; 1607fbfb8031SShannon Nelson __le32 rsvd2[15]; 1608fbfb8031SShannon Nelson }; 1609fbfb8031SShannon Nelson 1610fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_lif_reset_comp; 1611fbfb8031SShannon Nelson 1612fbfb8031SShannon Nelson enum ionic_dev_state { 1613fbfb8031SShannon Nelson IONIC_DEV_DISABLE = 0, 1614fbfb8031SShannon Nelson IONIC_DEV_ENABLE = 1, 1615fbfb8031SShannon Nelson IONIC_DEV_HANG_RESET = 2, 1616fbfb8031SShannon Nelson }; 1617fbfb8031SShannon Nelson 1618fbfb8031SShannon Nelson /** 16195c28f213SShannon Nelson * enum ionic_dev_attr - List of device attributes 1620c4e7a75aSShannon Nelson * @IONIC_DEV_ATTR_STATE: Device state attribute 1621c4e7a75aSShannon Nelson * @IONIC_DEV_ATTR_NAME: Device name attribute 1622c4e7a75aSShannon Nelson * @IONIC_DEV_ATTR_FEATURES: Device feature attributes 1623fbfb8031SShannon Nelson */ 1624fbfb8031SShannon Nelson enum ionic_dev_attr { 1625fbfb8031SShannon Nelson IONIC_DEV_ATTR_STATE = 0, 1626fbfb8031SShannon Nelson IONIC_DEV_ATTR_NAME = 1, 1627fbfb8031SShannon Nelson IONIC_DEV_ATTR_FEATURES = 2, 1628fbfb8031SShannon Nelson }; 1629fbfb8031SShannon Nelson 1630fbfb8031SShannon Nelson /** 16315c28f213SShannon Nelson * struct ionic_dev_setattr_cmd - Set Device attributes on the NIC 1632fbfb8031SShannon Nelson * @opcode: Opcode 16335c28f213SShannon Nelson * @attr: Attribute type (enum ionic_dev_attr) 16345c28f213SShannon Nelson * @state: Device state (enum ionic_dev_state) 1635fbfb8031SShannon Nelson * @name: The bus info, e.g. PCI slot-device-function, 0 terminated 1636fbfb8031SShannon Nelson * @features: Device features 1637fbfb8031SShannon Nelson */ 1638fbfb8031SShannon Nelson struct ionic_dev_setattr_cmd { 1639fbfb8031SShannon Nelson u8 opcode; 1640fbfb8031SShannon Nelson u8 attr; 1641fbfb8031SShannon Nelson __le16 rsvd; 1642fbfb8031SShannon Nelson union { 1643fbfb8031SShannon Nelson u8 state; 1644fbfb8031SShannon Nelson char name[IONIC_IFNAMSIZ]; 1645fbfb8031SShannon Nelson __le64 features; 1646fbfb8031SShannon Nelson u8 rsvd2[60]; 16475dca69c4SShannon Nelson } __packed; 1648fbfb8031SShannon Nelson }; 1649fbfb8031SShannon Nelson 1650fbfb8031SShannon Nelson /** 16515c28f213SShannon Nelson * struct ionic_dev_setattr_comp - Device set attr command completion 1652c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1653fbfb8031SShannon Nelson * @features: Device features 1654fbfb8031SShannon Nelson * @color: Color bit 1655fbfb8031SShannon Nelson */ 1656fbfb8031SShannon Nelson struct ionic_dev_setattr_comp { 1657fbfb8031SShannon Nelson u8 status; 1658fbfb8031SShannon Nelson u8 rsvd[3]; 1659fbfb8031SShannon Nelson union { 1660fbfb8031SShannon Nelson __le64 features; 1661fbfb8031SShannon Nelson u8 rsvd2[11]; 16625dca69c4SShannon Nelson } __packed; 1663fbfb8031SShannon Nelson u8 color; 1664fbfb8031SShannon Nelson }; 1665fbfb8031SShannon Nelson 1666fbfb8031SShannon Nelson /** 16675c28f213SShannon Nelson * struct ionic_dev_getattr_cmd - Get Device attributes from the NIC 1668fbfb8031SShannon Nelson * @opcode: opcode 16695c28f213SShannon Nelson * @attr: Attribute type (enum ionic_dev_attr) 1670fbfb8031SShannon Nelson */ 1671fbfb8031SShannon Nelson struct ionic_dev_getattr_cmd { 1672fbfb8031SShannon Nelson u8 opcode; 1673fbfb8031SShannon Nelson u8 attr; 1674fbfb8031SShannon Nelson u8 rsvd[62]; 1675fbfb8031SShannon Nelson }; 1676fbfb8031SShannon Nelson 1677fbfb8031SShannon Nelson /** 16785c28f213SShannon Nelson * struct ionic_dev_setattr_comp - Device set attr command completion 1679c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1680fbfb8031SShannon Nelson * @features: Device features 1681fbfb8031SShannon Nelson * @color: Color bit 1682fbfb8031SShannon Nelson */ 1683fbfb8031SShannon Nelson struct ionic_dev_getattr_comp { 1684fbfb8031SShannon Nelson u8 status; 1685fbfb8031SShannon Nelson u8 rsvd[3]; 1686fbfb8031SShannon Nelson union { 1687fbfb8031SShannon Nelson __le64 features; 1688fbfb8031SShannon Nelson u8 rsvd2[11]; 16895dca69c4SShannon Nelson } __packed; 1690fbfb8031SShannon Nelson u8 color; 1691fbfb8031SShannon Nelson }; 1692fbfb8031SShannon Nelson 1693fbfb8031SShannon Nelson /** 1694fbfb8031SShannon Nelson * RSS parameters 1695fbfb8031SShannon Nelson */ 1696fbfb8031SShannon Nelson #define IONIC_RSS_HASH_KEY_SIZE 40 1697fbfb8031SShannon Nelson 1698fbfb8031SShannon Nelson enum ionic_rss_hash_types { 1699fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV4 = BIT(0), 1700fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV4_TCP = BIT(1), 1701fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV4_UDP = BIT(2), 1702fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV6 = BIT(3), 1703fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV6_TCP = BIT(4), 1704fbfb8031SShannon Nelson IONIC_RSS_TYPE_IPV6_UDP = BIT(5), 1705fbfb8031SShannon Nelson }; 1706fbfb8031SShannon Nelson 1707fbfb8031SShannon Nelson /** 17085c28f213SShannon Nelson * enum ionic_lif_attr - List of LIF attributes 1709c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_STATE: LIF state attribute 1710c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_NAME: LIF name attribute 1711c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_MTU: LIF MTU attribute 1712c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_MAC: LIF MAC attribute 1713c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_FEATURES: LIF features attribute 1714c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_RSS: LIF RSS attribute 1715c4e7a75aSShannon Nelson * @IONIC_LIF_ATTR_STATS_CTRL: LIF statistics control attribute 17163da25843SShannon Nelson * @IONIC_LIF_ATTR_TXSTAMP: LIF TX timestamping mode 1717fbfb8031SShannon Nelson */ 1718fbfb8031SShannon Nelson enum ionic_lif_attr { 1719fbfb8031SShannon Nelson IONIC_LIF_ATTR_STATE = 0, 1720fbfb8031SShannon Nelson IONIC_LIF_ATTR_NAME = 1, 1721fbfb8031SShannon Nelson IONIC_LIF_ATTR_MTU = 2, 1722fbfb8031SShannon Nelson IONIC_LIF_ATTR_MAC = 3, 1723fbfb8031SShannon Nelson IONIC_LIF_ATTR_FEATURES = 4, 1724fbfb8031SShannon Nelson IONIC_LIF_ATTR_RSS = 5, 1725fbfb8031SShannon Nelson IONIC_LIF_ATTR_STATS_CTRL = 6, 17263da25843SShannon Nelson IONIC_LIF_ATTR_TXSTAMP = 7, 1727fbfb8031SShannon Nelson }; 1728fbfb8031SShannon Nelson 1729fbfb8031SShannon Nelson /** 17305c28f213SShannon Nelson * struct ionic_lif_setattr_cmd - Set LIF attributes on the NIC 1731fbfb8031SShannon Nelson * @opcode: Opcode 1732c4e7a75aSShannon Nelson * @attr: Attribute type (enum ionic_lif_attr) 1733fbfb8031SShannon Nelson * @index: LIF index 1734c4e7a75aSShannon Nelson * @state: LIF state (enum ionic_lif_state) 1735fbfb8031SShannon Nelson * @name: The netdev name string, 0 terminated 1736fbfb8031SShannon Nelson * @mtu: Mtu 1737fbfb8031SShannon Nelson * @mac: Station mac 17385c28f213SShannon Nelson * @features: Features (enum ionic_eth_hw_features) 1739fbfb8031SShannon Nelson * @rss: RSS properties 1740c4e7a75aSShannon Nelson * @types: The hash types to enable (see rss_hash_types) 1741c4e7a75aSShannon Nelson * @key: The hash secret key 1742c4e7a75aSShannon Nelson * @addr: Address for the indirection table shared memory 1743c4e7a75aSShannon Nelson * @stats_ctl: stats control commands (enum ionic_stats_ctl_cmd) 17443da25843SShannon Nelson * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1745fbfb8031SShannon Nelson */ 1746fbfb8031SShannon Nelson struct ionic_lif_setattr_cmd { 1747fbfb8031SShannon Nelson u8 opcode; 1748fbfb8031SShannon Nelson u8 attr; 1749fbfb8031SShannon Nelson __le16 index; 1750fbfb8031SShannon Nelson union { 1751fbfb8031SShannon Nelson u8 state; 1752fbfb8031SShannon Nelson char name[IONIC_IFNAMSIZ]; 1753fbfb8031SShannon Nelson __le32 mtu; 1754fbfb8031SShannon Nelson u8 mac[6]; 1755fbfb8031SShannon Nelson __le64 features; 1756fbfb8031SShannon Nelson struct { 1757fbfb8031SShannon Nelson __le16 types; 1758fbfb8031SShannon Nelson u8 key[IONIC_RSS_HASH_KEY_SIZE]; 1759fbfb8031SShannon Nelson u8 rsvd[6]; 1760fbfb8031SShannon Nelson __le64 addr; 1761fbfb8031SShannon Nelson } rss; 1762fbfb8031SShannon Nelson u8 stats_ctl; 17633da25843SShannon Nelson __le16 txstamp_mode; 1764fbfb8031SShannon Nelson u8 rsvd[60]; 17655dca69c4SShannon Nelson } __packed; 1766fbfb8031SShannon Nelson }; 1767fbfb8031SShannon Nelson 1768fbfb8031SShannon Nelson /** 17695c28f213SShannon Nelson * struct ionic_lif_setattr_comp - LIF set attr command completion 1770c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1771c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 17725c28f213SShannon Nelson * @features: features (enum ionic_eth_hw_features) 1773fbfb8031SShannon Nelson * @color: Color bit 1774fbfb8031SShannon Nelson */ 1775fbfb8031SShannon Nelson struct ionic_lif_setattr_comp { 1776fbfb8031SShannon Nelson u8 status; 1777fbfb8031SShannon Nelson u8 rsvd; 1778fbfb8031SShannon Nelson __le16 comp_index; 1779fbfb8031SShannon Nelson union { 1780fbfb8031SShannon Nelson __le64 features; 1781fbfb8031SShannon Nelson u8 rsvd2[11]; 17825dca69c4SShannon Nelson } __packed; 1783fbfb8031SShannon Nelson u8 color; 1784fbfb8031SShannon Nelson }; 1785fbfb8031SShannon Nelson 1786fbfb8031SShannon Nelson /** 17875c28f213SShannon Nelson * struct ionic_lif_getattr_cmd - Get LIF attributes from the NIC 1788fbfb8031SShannon Nelson * @opcode: Opcode 17895c28f213SShannon Nelson * @attr: Attribute type (enum ionic_lif_attr) 1790fbfb8031SShannon Nelson * @index: LIF index 1791fbfb8031SShannon Nelson */ 1792fbfb8031SShannon Nelson struct ionic_lif_getattr_cmd { 1793fbfb8031SShannon Nelson u8 opcode; 1794fbfb8031SShannon Nelson u8 attr; 1795fbfb8031SShannon Nelson __le16 index; 1796fbfb8031SShannon Nelson u8 rsvd[60]; 1797fbfb8031SShannon Nelson }; 1798fbfb8031SShannon Nelson 1799fbfb8031SShannon Nelson /** 18005c28f213SShannon Nelson * struct ionic_lif_getattr_comp - LIF get attr command completion 1801c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1802c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 1803c4e7a75aSShannon Nelson * @state: LIF state (enum ionic_lif_state) 1804fbfb8031SShannon Nelson * @name: The netdev name string, 0 terminated 1805fbfb8031SShannon Nelson * @mtu: Mtu 1806fbfb8031SShannon Nelson * @mac: Station mac 18075c28f213SShannon Nelson * @features: Features (enum ionic_eth_hw_features) 18083da25843SShannon Nelson * @txstamp: TX Timestamping Mode (enum ionic_txstamp_mode) 1809fbfb8031SShannon Nelson * @color: Color bit 1810fbfb8031SShannon Nelson */ 1811fbfb8031SShannon Nelson struct ionic_lif_getattr_comp { 1812fbfb8031SShannon Nelson u8 status; 1813fbfb8031SShannon Nelson u8 rsvd; 1814fbfb8031SShannon Nelson __le16 comp_index; 1815fbfb8031SShannon Nelson union { 1816fbfb8031SShannon Nelson u8 state; 1817fbfb8031SShannon Nelson __le32 mtu; 1818fbfb8031SShannon Nelson u8 mac[6]; 1819fbfb8031SShannon Nelson __le64 features; 18203da25843SShannon Nelson __le16 txstamp_mode; 1821fbfb8031SShannon Nelson u8 rsvd2[11]; 18225dca69c4SShannon Nelson } __packed; 1823fbfb8031SShannon Nelson u8 color; 1824fbfb8031SShannon Nelson }; 1825fbfb8031SShannon Nelson 18263da25843SShannon Nelson /** 18273da25843SShannon Nelson * struct ionic_lif_setphc_cmd - Set LIF PTP Hardware Clock 18283da25843SShannon Nelson * @opcode: Opcode 18293da25843SShannon Nelson * @lif_index: LIF index 18303da25843SShannon Nelson * @tick: Hardware stamp tick of an instant in time. 18313da25843SShannon Nelson * @nsec: Nanosecond stamp of the same instant. 18323da25843SShannon Nelson * @frac: Fractional nanoseconds at the same instant. 18333da25843SShannon Nelson * @mult: Cycle to nanosecond multiplier. 18343da25843SShannon Nelson * @shift: Cycle to nanosecond divisor (power of two). 18353da25843SShannon Nelson */ 18363da25843SShannon Nelson struct ionic_lif_setphc_cmd { 18373da25843SShannon Nelson u8 opcode; 18383da25843SShannon Nelson u8 rsvd1; 18393da25843SShannon Nelson __le16 lif_index; 18403da25843SShannon Nelson u8 rsvd2[4]; 18413da25843SShannon Nelson __le64 tick; 18423da25843SShannon Nelson __le64 nsec; 18433da25843SShannon Nelson __le64 frac; 18443da25843SShannon Nelson __le32 mult; 18453da25843SShannon Nelson __le32 shift; 18463da25843SShannon Nelson u8 rsvd3[24]; 18473da25843SShannon Nelson }; 18483da25843SShannon Nelson 1849fbfb8031SShannon Nelson enum ionic_rx_mode { 1850fbfb8031SShannon Nelson IONIC_RX_MODE_F_UNICAST = BIT(0), 1851fbfb8031SShannon Nelson IONIC_RX_MODE_F_MULTICAST = BIT(1), 1852fbfb8031SShannon Nelson IONIC_RX_MODE_F_BROADCAST = BIT(2), 1853fbfb8031SShannon Nelson IONIC_RX_MODE_F_PROMISC = BIT(3), 1854fbfb8031SShannon Nelson IONIC_RX_MODE_F_ALLMULTI = BIT(4), 1855c4e7a75aSShannon Nelson IONIC_RX_MODE_F_RDMA_SNIFFER = BIT(5), 1856fbfb8031SShannon Nelson }; 1857fbfb8031SShannon Nelson 1858fbfb8031SShannon Nelson /** 18595c28f213SShannon Nelson * struct ionic_rx_mode_set_cmd - Set LIF's Rx mode command 1860fbfb8031SShannon Nelson * @opcode: opcode 1861fbfb8031SShannon Nelson * @lif_index: LIF index 1862fbfb8031SShannon Nelson * @rx_mode: Rx mode flags: 1863c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_UNICAST: Accept known unicast packets 1864c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_MULTICAST: Accept known multicast packets 1865c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_BROADCAST: Accept broadcast packets 1866c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_PROMISC: Accept any packets 1867c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_ALLMULTI: Accept any multicast packets 1868c4e7a75aSShannon Nelson * IONIC_RX_MODE_F_RDMA_SNIFFER: Sniff RDMA packets 1869fbfb8031SShannon Nelson */ 1870fbfb8031SShannon Nelson struct ionic_rx_mode_set_cmd { 1871fbfb8031SShannon Nelson u8 opcode; 1872fbfb8031SShannon Nelson u8 rsvd; 1873fbfb8031SShannon Nelson __le16 lif_index; 1874fbfb8031SShannon Nelson __le16 rx_mode; 1875fbfb8031SShannon Nelson __le16 rsvd2[29]; 1876fbfb8031SShannon Nelson }; 1877fbfb8031SShannon Nelson 1878fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_rx_mode_set_comp; 1879fbfb8031SShannon Nelson 1880fbfb8031SShannon Nelson enum ionic_rx_filter_match_type { 18813da25843SShannon Nelson IONIC_RX_FILTER_MATCH_VLAN = 0x0, 18823da25843SShannon Nelson IONIC_RX_FILTER_MATCH_MAC = 0x1, 18833da25843SShannon Nelson IONIC_RX_FILTER_MATCH_MAC_VLAN = 0x2, 18843da25843SShannon Nelson IONIC_RX_FILTER_STEER_PKTCLASS = 0x10, 1885fbfb8031SShannon Nelson }; 1886fbfb8031SShannon Nelson 1887fbfb8031SShannon Nelson /** 18885c28f213SShannon Nelson * struct ionic_rx_filter_add_cmd - Add LIF Rx filter command 1889fbfb8031SShannon Nelson * @opcode: opcode 1890fbfb8031SShannon Nelson * @qtype: Queue type 1891fbfb8031SShannon Nelson * @lif_index: LIF index 1892fbfb8031SShannon Nelson * @qid: Queue ID 1893c4e7a75aSShannon Nelson * @match: Rx filter match type (see IONIC_RX_FILTER_MATCH_xxx) 1894c4e7a75aSShannon Nelson * @vlan: VLAN filter 1895c4e7a75aSShannon Nelson * @vlan: VLAN ID 1896c4e7a75aSShannon Nelson * @mac: MAC filter 1897c4e7a75aSShannon Nelson * @addr: MAC address (network-byte order) 1898c4e7a75aSShannon Nelson * @mac_vlan: MACVLAN filter 1899fbfb8031SShannon Nelson * @vlan: VLAN ID 1900fbfb8031SShannon Nelson * @addr: MAC address (network-byte order) 19013da25843SShannon Nelson * @pkt_class: Packet classification filter 1902fbfb8031SShannon Nelson */ 1903fbfb8031SShannon Nelson struct ionic_rx_filter_add_cmd { 1904fbfb8031SShannon Nelson u8 opcode; 1905fbfb8031SShannon Nelson u8 qtype; 1906fbfb8031SShannon Nelson __le16 lif_index; 1907fbfb8031SShannon Nelson __le32 qid; 1908fbfb8031SShannon Nelson __le16 match; 1909fbfb8031SShannon Nelson union { 1910fbfb8031SShannon Nelson struct { 1911fbfb8031SShannon Nelson __le16 vlan; 1912fbfb8031SShannon Nelson } vlan; 1913fbfb8031SShannon Nelson struct { 1914fbfb8031SShannon Nelson u8 addr[6]; 1915fbfb8031SShannon Nelson } mac; 1916fbfb8031SShannon Nelson struct { 1917fbfb8031SShannon Nelson __le16 vlan; 1918fbfb8031SShannon Nelson u8 addr[6]; 1919fbfb8031SShannon Nelson } mac_vlan; 19203da25843SShannon Nelson __le64 pkt_class; 1921fbfb8031SShannon Nelson u8 rsvd[54]; 19223da25843SShannon Nelson } __packed; 1923fbfb8031SShannon Nelson }; 1924fbfb8031SShannon Nelson 1925fbfb8031SShannon Nelson /** 19265c28f213SShannon Nelson * struct ionic_rx_filter_add_comp - Add LIF Rx filter command completion 1927c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 1928c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 1929fbfb8031SShannon Nelson * @filter_id: Filter ID 1930c4e7a75aSShannon Nelson * @color: Color bit 1931fbfb8031SShannon Nelson */ 1932fbfb8031SShannon Nelson struct ionic_rx_filter_add_comp { 1933fbfb8031SShannon Nelson u8 status; 1934fbfb8031SShannon Nelson u8 rsvd; 1935fbfb8031SShannon Nelson __le16 comp_index; 1936fbfb8031SShannon Nelson __le32 filter_id; 1937fbfb8031SShannon Nelson u8 rsvd2[7]; 1938fbfb8031SShannon Nelson u8 color; 1939fbfb8031SShannon Nelson }; 1940fbfb8031SShannon Nelson 1941fbfb8031SShannon Nelson /** 19425c28f213SShannon Nelson * struct ionic_rx_filter_del_cmd - Delete LIF Rx filter command 1943fbfb8031SShannon Nelson * @opcode: opcode 1944fbfb8031SShannon Nelson * @lif_index: LIF index 1945fbfb8031SShannon Nelson * @filter_id: Filter ID 1946fbfb8031SShannon Nelson */ 1947fbfb8031SShannon Nelson struct ionic_rx_filter_del_cmd { 1948fbfb8031SShannon Nelson u8 opcode; 1949fbfb8031SShannon Nelson u8 rsvd; 1950fbfb8031SShannon Nelson __le16 lif_index; 1951fbfb8031SShannon Nelson __le32 filter_id; 1952fbfb8031SShannon Nelson u8 rsvd2[56]; 1953fbfb8031SShannon Nelson }; 1954fbfb8031SShannon Nelson 1955fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_rx_filter_del_comp; 1956fbfb8031SShannon Nelson 19573d462ce2SShannon Nelson enum ionic_vf_attr { 19583d462ce2SShannon Nelson IONIC_VF_ATTR_SPOOFCHK = 1, 19593d462ce2SShannon Nelson IONIC_VF_ATTR_TRUST = 2, 19603d462ce2SShannon Nelson IONIC_VF_ATTR_MAC = 3, 19613d462ce2SShannon Nelson IONIC_VF_ATTR_LINKSTATE = 4, 19623d462ce2SShannon Nelson IONIC_VF_ATTR_VLAN = 5, 19633d462ce2SShannon Nelson IONIC_VF_ATTR_RATE = 6, 19643d462ce2SShannon Nelson IONIC_VF_ATTR_STATSADDR = 7, 19653d462ce2SShannon Nelson }; 19663d462ce2SShannon Nelson 19673d462ce2SShannon Nelson /** 1968c4e7a75aSShannon Nelson * enum ionic_vf_link_status - Virtual Function link status 1969c4e7a75aSShannon Nelson * @IONIC_VF_LINK_STATUS_AUTO: Use link state of the uplink 1970c4e7a75aSShannon Nelson * @IONIC_VF_LINK_STATUS_UP: Link always up 1971c4e7a75aSShannon Nelson * @IONIC_VF_LINK_STATUS_DOWN: Link always down 19723d462ce2SShannon Nelson */ 19733d462ce2SShannon Nelson enum ionic_vf_link_status { 1974c4e7a75aSShannon Nelson IONIC_VF_LINK_STATUS_AUTO = 0, 1975c4e7a75aSShannon Nelson IONIC_VF_LINK_STATUS_UP = 1, 1976c4e7a75aSShannon Nelson IONIC_VF_LINK_STATUS_DOWN = 2, 19773d462ce2SShannon Nelson }; 19783d462ce2SShannon Nelson 19793d462ce2SShannon Nelson /** 19803d462ce2SShannon Nelson * struct ionic_vf_setattr_cmd - Set VF attributes on the NIC 19813d462ce2SShannon Nelson * @opcode: Opcode 19823d462ce2SShannon Nelson * @attr: Attribute type (enum ionic_vf_attr) 1983c4e7a75aSShannon Nelson * @vf_index: VF index 1984c4e7a75aSShannon Nelson * @macaddr: mac address 1985c4e7a75aSShannon Nelson * @vlanid: vlan ID 1986c4e7a75aSShannon Nelson * @maxrate: max Tx rate in Mbps 1987c4e7a75aSShannon Nelson * @spoofchk: enable address spoof checking 1988c4e7a75aSShannon Nelson * @trust: enable VF trust 1989c4e7a75aSShannon Nelson * @linkstate: set link up or down 1990c4e7a75aSShannon Nelson * @stats_pa: set DMA address for VF stats 19913d462ce2SShannon Nelson */ 19923d462ce2SShannon Nelson struct ionic_vf_setattr_cmd { 19933d462ce2SShannon Nelson u8 opcode; 19943d462ce2SShannon Nelson u8 attr; 19953d462ce2SShannon Nelson __le16 vf_index; 19963d462ce2SShannon Nelson union { 19973d462ce2SShannon Nelson u8 macaddr[6]; 19983d462ce2SShannon Nelson __le16 vlanid; 19993d462ce2SShannon Nelson __le32 maxrate; 20003d462ce2SShannon Nelson u8 spoofchk; 20013d462ce2SShannon Nelson u8 trust; 20023d462ce2SShannon Nelson u8 linkstate; 20033d462ce2SShannon Nelson __le64 stats_pa; 20043d462ce2SShannon Nelson u8 pad[60]; 20055dca69c4SShannon Nelson } __packed; 20063d462ce2SShannon Nelson }; 20073d462ce2SShannon Nelson 20083d462ce2SShannon Nelson struct ionic_vf_setattr_comp { 20093d462ce2SShannon Nelson u8 status; 20103d462ce2SShannon Nelson u8 attr; 20113d462ce2SShannon Nelson __le16 vf_index; 20123d462ce2SShannon Nelson __le16 comp_index; 20133d462ce2SShannon Nelson u8 rsvd[9]; 20143d462ce2SShannon Nelson u8 color; 20153d462ce2SShannon Nelson }; 20163d462ce2SShannon Nelson 20173d462ce2SShannon Nelson /** 20183d462ce2SShannon Nelson * struct ionic_vf_getattr_cmd - Get VF attributes from the NIC 20193d462ce2SShannon Nelson * @opcode: Opcode 20203d462ce2SShannon Nelson * @attr: Attribute type (enum ionic_vf_attr) 2021c4e7a75aSShannon Nelson * @vf_index: VF index 20223d462ce2SShannon Nelson */ 20233d462ce2SShannon Nelson struct ionic_vf_getattr_cmd { 20243d462ce2SShannon Nelson u8 opcode; 20253d462ce2SShannon Nelson u8 attr; 20263d462ce2SShannon Nelson __le16 vf_index; 20273d462ce2SShannon Nelson u8 rsvd[60]; 20283d462ce2SShannon Nelson }; 20293d462ce2SShannon Nelson 20303d462ce2SShannon Nelson struct ionic_vf_getattr_comp { 20313d462ce2SShannon Nelson u8 status; 20323d462ce2SShannon Nelson u8 attr; 20333d462ce2SShannon Nelson __le16 vf_index; 20343d462ce2SShannon Nelson union { 20353d462ce2SShannon Nelson u8 macaddr[6]; 20363d462ce2SShannon Nelson __le16 vlanid; 20373d462ce2SShannon Nelson __le32 maxrate; 20383d462ce2SShannon Nelson u8 spoofchk; 20393d462ce2SShannon Nelson u8 trust; 20403d462ce2SShannon Nelson u8 linkstate; 20413d462ce2SShannon Nelson __le64 stats_pa; 20423d462ce2SShannon Nelson u8 pad[11]; 20435dca69c4SShannon Nelson } __packed; 20443d462ce2SShannon Nelson u8 color; 20453d462ce2SShannon Nelson }; 20463d462ce2SShannon Nelson 2047fbfb8031SShannon Nelson /** 2048c4e7a75aSShannon Nelson * struct ionic_qos_identify_cmd - QoS identify command 2049c4e7a75aSShannon Nelson * @opcode: opcode 2050c4e7a75aSShannon Nelson * @ver: Highest version of identify supported by driver 2051c4e7a75aSShannon Nelson * 2052c4e7a75aSShannon Nelson */ 2053c4e7a75aSShannon Nelson struct ionic_qos_identify_cmd { 2054c4e7a75aSShannon Nelson u8 opcode; 2055c4e7a75aSShannon Nelson u8 ver; 2056c4e7a75aSShannon Nelson u8 rsvd[62]; 2057c4e7a75aSShannon Nelson }; 2058c4e7a75aSShannon Nelson 2059c4e7a75aSShannon Nelson /** 2060c4e7a75aSShannon Nelson * struct ionic_qos_identify_comp - QoS identify command completion 2061c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 2062c4e7a75aSShannon Nelson * @ver: Version of identify returned by device 2063c4e7a75aSShannon Nelson */ 2064c4e7a75aSShannon Nelson struct ionic_qos_identify_comp { 2065c4e7a75aSShannon Nelson u8 status; 2066c4e7a75aSShannon Nelson u8 ver; 2067c4e7a75aSShannon Nelson u8 rsvd[14]; 2068c4e7a75aSShannon Nelson }; 2069c4e7a75aSShannon Nelson 2070c4e7a75aSShannon Nelson #define IONIC_QOS_TC_MAX 8 20711b897e7dSShannon Nelson #define IONIC_QOS_ALL_TC 0xFF 2072c4e7a75aSShannon Nelson /* Capri max supported, should be renamed. */ 2073c4e7a75aSShannon Nelson #define IONIC_QOS_CLASS_MAX 7 2074c4e7a75aSShannon Nelson #define IONIC_QOS_PCP_MAX 8 2075c4e7a75aSShannon Nelson #define IONIC_QOS_CLASS_NAME_SZ 32 2076c4e7a75aSShannon Nelson #define IONIC_QOS_DSCP_MAX 64 2077c4e7a75aSShannon Nelson #define IONIC_QOS_ALL_PCP 0xFF 20781b897e7dSShannon Nelson #define IONIC_DSCP_BLOCK_SIZE 8 2079c4e7a75aSShannon Nelson 2080c4e7a75aSShannon Nelson /** 2081c4e7a75aSShannon Nelson * enum ionic_qos_class 2082c4e7a75aSShannon Nelson */ 2083c4e7a75aSShannon Nelson enum ionic_qos_class { 2084c4e7a75aSShannon Nelson IONIC_QOS_CLASS_DEFAULT = 0, 2085c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_1 = 1, 2086c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_2 = 2, 2087c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_3 = 3, 2088c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_4 = 4, 2089c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_5 = 5, 2090c4e7a75aSShannon Nelson IONIC_QOS_CLASS_USER_DEFINED_6 = 6, 2091c4e7a75aSShannon Nelson }; 2092c4e7a75aSShannon Nelson 2093c4e7a75aSShannon Nelson /** 2094c4e7a75aSShannon Nelson * enum ionic_qos_class_type - Traffic classification criteria 2095c4e7a75aSShannon Nelson * @IONIC_QOS_CLASS_TYPE_NONE: No QoS 2096c4e7a75aSShannon Nelson * @IONIC_QOS_CLASS_TYPE_PCP: Dot1Q PCP 2097c4e7a75aSShannon Nelson * @IONIC_QOS_CLASS_TYPE_DSCP: IP DSCP 2098c4e7a75aSShannon Nelson */ 2099c4e7a75aSShannon Nelson enum ionic_qos_class_type { 2100c4e7a75aSShannon Nelson IONIC_QOS_CLASS_TYPE_NONE = 0, 2101c4e7a75aSShannon Nelson IONIC_QOS_CLASS_TYPE_PCP = 1, 2102c4e7a75aSShannon Nelson IONIC_QOS_CLASS_TYPE_DSCP = 2, 2103c4e7a75aSShannon Nelson }; 2104c4e7a75aSShannon Nelson 2105c4e7a75aSShannon Nelson /** 2106c4e7a75aSShannon Nelson * enum ionic_qos_sched_type - QoS class scheduling type 2107c4e7a75aSShannon Nelson * @IONIC_QOS_SCHED_TYPE_STRICT: Strict priority 2108c4e7a75aSShannon Nelson * @IONIC_QOS_SCHED_TYPE_DWRR: Deficit weighted round-robin 2109c4e7a75aSShannon Nelson */ 2110c4e7a75aSShannon Nelson enum ionic_qos_sched_type { 2111c4e7a75aSShannon Nelson IONIC_QOS_SCHED_TYPE_STRICT = 0, 2112c4e7a75aSShannon Nelson IONIC_QOS_SCHED_TYPE_DWRR = 1, 2113c4e7a75aSShannon Nelson }; 2114c4e7a75aSShannon Nelson 2115c4e7a75aSShannon Nelson /** 2116c4e7a75aSShannon Nelson * union ionic_qos_config - QoS configuration structure 2117fbfb8031SShannon Nelson * @flags: Configuration flags 2118fbfb8031SShannon Nelson * IONIC_QOS_CONFIG_F_ENABLE enable 2119c4e7a75aSShannon Nelson * IONIC_QOS_CONFIG_F_NO_DROP drop/nodrop 2120fbfb8031SShannon Nelson * IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP enable dot1q pcp rewrite 2121fbfb8031SShannon Nelson * IONIC_QOS_CONFIG_F_RW_IP_DSCP enable ip dscp rewrite 21221b897e7dSShannon Nelson * IONIC_QOS_CONFIG_F_NON_DISRUPTIVE Non-disruptive TC update 2123c4e7a75aSShannon Nelson * @sched_type: QoS class scheduling type (enum ionic_qos_sched_type) 2124c4e7a75aSShannon Nelson * @class_type: QoS class type (enum ionic_qos_class_type) 2125c4e7a75aSShannon Nelson * @pause_type: QoS pause type (enum ionic_qos_pause_type) 2126c4e7a75aSShannon Nelson * @name: QoS class name 2127fbfb8031SShannon Nelson * @mtu: MTU of the class 2128c4e7a75aSShannon Nelson * @pfc_cos: Priority-Flow Control class of service 2129c4e7a75aSShannon Nelson * @dwrr_weight: QoS class scheduling weight 2130fbfb8031SShannon Nelson * @strict_rlmt: Rate limit for strict priority scheduling 213125cc5a5fSShannon Nelson * @rw_dot1q_pcp: Rewrite dot1q pcp to value (valid iff F_RW_DOT1Q_PCP) 213225cc5a5fSShannon Nelson * @rw_ip_dscp: Rewrite ip dscp to value (valid iff F_RW_IP_DSCP) 2133fbfb8031SShannon Nelson * @dot1q_pcp: Dot1q pcp value 2134fbfb8031SShannon Nelson * @ndscp: Number of valid dscp values in the ip_dscp field 2135fbfb8031SShannon Nelson * @ip_dscp: IP dscp values 2136fbfb8031SShannon Nelson */ 2137fbfb8031SShannon Nelson union ionic_qos_config { 2138fbfb8031SShannon Nelson struct { 2139fbfb8031SShannon Nelson #define IONIC_QOS_CONFIG_F_ENABLE BIT(0) 2140c4e7a75aSShannon Nelson #define IONIC_QOS_CONFIG_F_NO_DROP BIT(1) 2141c4e7a75aSShannon Nelson /* Used to rewrite PCP or DSCP value. */ 2142fbfb8031SShannon Nelson #define IONIC_QOS_CONFIG_F_RW_DOT1Q_PCP BIT(2) 2143fbfb8031SShannon Nelson #define IONIC_QOS_CONFIG_F_RW_IP_DSCP BIT(3) 21441b897e7dSShannon Nelson /* Non-disruptive TC update */ 21451b897e7dSShannon Nelson #define IONIC_QOS_CONFIG_F_NON_DISRUPTIVE BIT(4) 2146fbfb8031SShannon Nelson u8 flags; 2147fbfb8031SShannon Nelson u8 sched_type; 2148fbfb8031SShannon Nelson u8 class_type; 2149fbfb8031SShannon Nelson u8 pause_type; 2150fbfb8031SShannon Nelson char name[IONIC_QOS_CLASS_NAME_SZ]; 2151fbfb8031SShannon Nelson __le32 mtu; 2152fbfb8031SShannon Nelson /* flow control */ 2153fbfb8031SShannon Nelson u8 pfc_cos; 2154fbfb8031SShannon Nelson /* scheduler */ 2155fbfb8031SShannon Nelson union { 2156fbfb8031SShannon Nelson u8 dwrr_weight; 2157fbfb8031SShannon Nelson __le64 strict_rlmt; 2158fbfb8031SShannon Nelson }; 2159fbfb8031SShannon Nelson /* marking */ 2160c4e7a75aSShannon Nelson /* Used to rewrite PCP or DSCP value. */ 2161fbfb8031SShannon Nelson union { 2162fbfb8031SShannon Nelson u8 rw_dot1q_pcp; 2163fbfb8031SShannon Nelson u8 rw_ip_dscp; 2164fbfb8031SShannon Nelson }; 2165fbfb8031SShannon Nelson /* classification */ 2166fbfb8031SShannon Nelson union { 2167fbfb8031SShannon Nelson u8 dot1q_pcp; 2168fbfb8031SShannon Nelson struct { 2169fbfb8031SShannon Nelson u8 ndscp; 2170c4e7a75aSShannon Nelson u8 ip_dscp[IONIC_QOS_DSCP_MAX]; 2171fbfb8031SShannon Nelson }; 2172fbfb8031SShannon Nelson }; 2173fbfb8031SShannon Nelson }; 2174fbfb8031SShannon Nelson __le32 words[64]; 2175fbfb8031SShannon Nelson }; 2176fbfb8031SShannon Nelson 2177fbfb8031SShannon Nelson /** 21785c28f213SShannon Nelson * union ionic_qos_identity - QoS identity structure 2179fbfb8031SShannon Nelson * @version: Version of the identify structure 2180fbfb8031SShannon Nelson * @type: QoS system type 2181fbfb8031SShannon Nelson * @nclasses: Number of usable QoS classes 2182fbfb8031SShannon Nelson * @config: Current configuration of classes 2183fbfb8031SShannon Nelson */ 2184fbfb8031SShannon Nelson union ionic_qos_identity { 2185fbfb8031SShannon Nelson struct { 2186fbfb8031SShannon Nelson u8 version; 2187fbfb8031SShannon Nelson u8 type; 2188fbfb8031SShannon Nelson u8 rsvd[62]; 2189fbfb8031SShannon Nelson union ionic_qos_config config[IONIC_QOS_CLASS_MAX]; 2190fbfb8031SShannon Nelson }; 2191c4e7a75aSShannon Nelson __le32 words[478]; 2192fbfb8031SShannon Nelson }; 2193fbfb8031SShannon Nelson 2194fbfb8031SShannon Nelson /** 2195c4e7a75aSShannon Nelson * struct ionic_qos_init_cmd - QoS config init command 2196fbfb8031SShannon Nelson * @opcode: Opcode 2197c4e7a75aSShannon Nelson * @group: QoS class id 2198fbfb8031SShannon Nelson * @info_pa: destination address for qos info 2199fbfb8031SShannon Nelson */ 2200fbfb8031SShannon Nelson struct ionic_qos_init_cmd { 2201fbfb8031SShannon Nelson u8 opcode; 2202fbfb8031SShannon Nelson u8 group; 2203fbfb8031SShannon Nelson u8 rsvd[6]; 2204fbfb8031SShannon Nelson __le64 info_pa; 2205fbfb8031SShannon Nelson u8 rsvd1[48]; 2206fbfb8031SShannon Nelson }; 2207fbfb8031SShannon Nelson 2208fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_qos_init_comp; 2209fbfb8031SShannon Nelson 2210fbfb8031SShannon Nelson /** 2211c4e7a75aSShannon Nelson * struct ionic_qos_reset_cmd - QoS config reset command 2212fbfb8031SShannon Nelson * @opcode: Opcode 2213c4e7a75aSShannon Nelson * @group: QoS class id 2214fbfb8031SShannon Nelson */ 2215fbfb8031SShannon Nelson struct ionic_qos_reset_cmd { 2216fbfb8031SShannon Nelson u8 opcode; 2217fbfb8031SShannon Nelson u8 group; 2218fbfb8031SShannon Nelson u8 rsvd[62]; 2219fbfb8031SShannon Nelson }; 2220fbfb8031SShannon Nelson 22211b897e7dSShannon Nelson /** 22221b897e7dSShannon Nelson * struct ionic_qos_clear_port_stats_cmd - Qos config reset command 22231b897e7dSShannon Nelson * @opcode: Opcode 22241b897e7dSShannon Nelson */ 22251b897e7dSShannon Nelson struct ionic_qos_clear_stats_cmd { 22261b897e7dSShannon Nelson u8 opcode; 22271b897e7dSShannon Nelson u8 group_bitmap; 22281b897e7dSShannon Nelson u8 rsvd[62]; 22291b897e7dSShannon Nelson }; 22301b897e7dSShannon Nelson 2231fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_qos_reset_comp; 2232fbfb8031SShannon Nelson 2233fbfb8031SShannon Nelson /** 22345c28f213SShannon Nelson * struct ionic_fw_download_cmd - Firmware download command 2235fbfb8031SShannon Nelson * @opcode: opcode 2236fbfb8031SShannon Nelson * @addr: dma address of the firmware buffer 2237fbfb8031SShannon Nelson * @offset: offset of the firmware buffer within the full image 2238fbfb8031SShannon Nelson * @length: number of valid bytes in the firmware buffer 2239fbfb8031SShannon Nelson */ 2240fbfb8031SShannon Nelson struct ionic_fw_download_cmd { 2241fbfb8031SShannon Nelson u8 opcode; 2242fbfb8031SShannon Nelson u8 rsvd[3]; 2243fbfb8031SShannon Nelson __le32 offset; 2244fbfb8031SShannon Nelson __le64 addr; 2245fbfb8031SShannon Nelson __le32 length; 2246fbfb8031SShannon Nelson }; 2247fbfb8031SShannon Nelson 2248fbfb8031SShannon Nelson typedef struct ionic_admin_comp ionic_fw_download_comp; 2249fbfb8031SShannon Nelson 2250c4e7a75aSShannon Nelson /** 2251c4e7a75aSShannon Nelson * enum ionic_fw_control_oper - FW control operations 2252c4e7a75aSShannon Nelson * @IONIC_FW_RESET: Reset firmware 2253c4e7a75aSShannon Nelson * @IONIC_FW_INSTALL: Install firmware 2254c4e7a75aSShannon Nelson * @IONIC_FW_ACTIVATE: Activate firmware 225587c905d8SShannon Nelson * @IONIC_FW_INSTALL_ASYNC: Install firmware asynchronously 225687c905d8SShannon Nelson * @IONIC_FW_INSTALL_STATUS: Firmware installation status 225787c905d8SShannon Nelson * @IONIC_FW_ACTIVATE_ASYNC: Activate firmware asynchronously 225887c905d8SShannon Nelson * @IONIC_FW_ACTIVATE_STATUS: Firmware activate status 2259c4e7a75aSShannon Nelson */ 2260fbfb8031SShannon Nelson enum ionic_fw_control_oper { 2261c4e7a75aSShannon Nelson IONIC_FW_RESET = 0, 2262c4e7a75aSShannon Nelson IONIC_FW_INSTALL = 1, 2263c4e7a75aSShannon Nelson IONIC_FW_ACTIVATE = 2, 226487c905d8SShannon Nelson IONIC_FW_INSTALL_ASYNC = 3, 226587c905d8SShannon Nelson IONIC_FW_INSTALL_STATUS = 4, 226687c905d8SShannon Nelson IONIC_FW_ACTIVATE_ASYNC = 5, 226787c905d8SShannon Nelson IONIC_FW_ACTIVATE_STATUS = 6, 226887c905d8SShannon Nelson IONIC_FW_UPDATE_CLEANUP = 7, 2269fbfb8031SShannon Nelson }; 2270fbfb8031SShannon Nelson 2271fbfb8031SShannon Nelson /** 22725c28f213SShannon Nelson * struct ionic_fw_control_cmd - Firmware control command 2273fbfb8031SShannon Nelson * @opcode: opcode 22745c28f213SShannon Nelson * @oper: firmware control operation (enum ionic_fw_control_oper) 2275fbfb8031SShannon Nelson * @slot: slot to activate 2276fbfb8031SShannon Nelson */ 2277fbfb8031SShannon Nelson struct ionic_fw_control_cmd { 2278fbfb8031SShannon Nelson u8 opcode; 2279fbfb8031SShannon Nelson u8 rsvd[3]; 2280fbfb8031SShannon Nelson u8 oper; 2281fbfb8031SShannon Nelson u8 slot; 2282fbfb8031SShannon Nelson u8 rsvd1[58]; 2283fbfb8031SShannon Nelson }; 2284fbfb8031SShannon Nelson 2285fbfb8031SShannon Nelson /** 22865c28f213SShannon Nelson * struct ionic_fw_control_comp - Firmware control copletion 2287c4e7a75aSShannon Nelson * @status: Status of the command (enum ionic_status_code) 2288c4e7a75aSShannon Nelson * @comp_index: Index in the descriptor ring for which this is the completion 2289c4e7a75aSShannon Nelson * @slot: Slot where the firmware was installed 2290c4e7a75aSShannon Nelson * @color: Color bit 2291fbfb8031SShannon Nelson */ 2292fbfb8031SShannon Nelson struct ionic_fw_control_comp { 2293fbfb8031SShannon Nelson u8 status; 2294fbfb8031SShannon Nelson u8 rsvd; 2295fbfb8031SShannon Nelson __le16 comp_index; 2296fbfb8031SShannon Nelson u8 slot; 2297fbfb8031SShannon Nelson u8 rsvd1[10]; 2298fbfb8031SShannon Nelson u8 color; 2299fbfb8031SShannon Nelson }; 2300fbfb8031SShannon Nelson 2301fbfb8031SShannon Nelson /****************************************************************** 2302fbfb8031SShannon Nelson ******************* RDMA Commands ******************************** 2303fbfb8031SShannon Nelson ******************************************************************/ 2304fbfb8031SShannon Nelson 2305fbfb8031SShannon Nelson /** 23065c28f213SShannon Nelson * struct ionic_rdma_reset_cmd - Reset RDMA LIF cmd 2307fbfb8031SShannon Nelson * @opcode: opcode 2308c4e7a75aSShannon Nelson * @lif_index: LIF index 2309fbfb8031SShannon Nelson * 2310c4e7a75aSShannon Nelson * There is no RDMA specific dev command completion struct. Completion uses 23115c28f213SShannon Nelson * the common struct ionic_admin_comp. Only the status is indicated. 2312c4e7a75aSShannon Nelson * Nonzero status means the LIF does not support RDMA. 2313fbfb8031SShannon Nelson **/ 2314fbfb8031SShannon Nelson struct ionic_rdma_reset_cmd { 2315fbfb8031SShannon Nelson u8 opcode; 2316fbfb8031SShannon Nelson u8 rsvd; 2317fbfb8031SShannon Nelson __le16 lif_index; 2318fbfb8031SShannon Nelson u8 rsvd2[60]; 2319fbfb8031SShannon Nelson }; 2320fbfb8031SShannon Nelson 2321fbfb8031SShannon Nelson /** 23225c28f213SShannon Nelson * struct ionic_rdma_queue_cmd - Create RDMA Queue command 2323fbfb8031SShannon Nelson * @opcode: opcode, 52, 53 2324c4e7a75aSShannon Nelson * @lif_index: LIF index 2325c4e7a75aSShannon Nelson * @qid_ver: (qid | (RDMA version << 24)) 2326fbfb8031SShannon Nelson * @cid: intr, eq_id, or cq_id 2327fbfb8031SShannon Nelson * @dbid: doorbell page id 2328fbfb8031SShannon Nelson * @depth_log2: log base two of queue depth 2329fbfb8031SShannon Nelson * @stride_log2: log base two of queue stride 2330fbfb8031SShannon Nelson * @dma_addr: address of the queue memory 2331fbfb8031SShannon Nelson * 2332c4e7a75aSShannon Nelson * The same command struct is used to create an RDMA event queue, completion 2333c4e7a75aSShannon Nelson * queue, or RDMA admin queue. The cid is an interrupt number for an event 2334fbfb8031SShannon Nelson * queue, an event queue id for a completion queue, or a completion queue id 2335c4e7a75aSShannon Nelson * for an RDMA admin queue. 2336fbfb8031SShannon Nelson * 2337fbfb8031SShannon Nelson * The queue created via a dev command must be contiguous in dma space. 2338fbfb8031SShannon Nelson * 2339fbfb8031SShannon Nelson * The dev commands are intended only to be used during driver initialization, 2340c4e7a75aSShannon Nelson * to create queues supporting the RDMA admin queue. Other queues, and other 2341c4e7a75aSShannon Nelson * types of RDMA resources like memory regions, will be created and registered 2342c4e7a75aSShannon Nelson * via the RDMA admin queue, and will support a more complete interface 2343fbfb8031SShannon Nelson * providing scatter gather lists for larger, scattered queue buffers and 2344fbfb8031SShannon Nelson * memory registration. 2345fbfb8031SShannon Nelson * 2346c4e7a75aSShannon Nelson * There is no RDMA specific dev command completion struct. Completion uses 23475c28f213SShannon Nelson * the common struct ionic_admin_comp. Only the status is indicated. 2348fbfb8031SShannon Nelson **/ 2349fbfb8031SShannon Nelson struct ionic_rdma_queue_cmd { 2350fbfb8031SShannon Nelson u8 opcode; 2351fbfb8031SShannon Nelson u8 rsvd; 2352fbfb8031SShannon Nelson __le16 lif_index; 2353fbfb8031SShannon Nelson __le32 qid_ver; 2354fbfb8031SShannon Nelson __le32 cid; 2355fbfb8031SShannon Nelson __le16 dbid; 2356fbfb8031SShannon Nelson u8 depth_log2; 2357fbfb8031SShannon Nelson u8 stride_log2; 2358fbfb8031SShannon Nelson __le64 dma_addr; 2359c4e7a75aSShannon Nelson u8 rsvd2[40]; 2360fbfb8031SShannon Nelson }; 2361fbfb8031SShannon Nelson 2362fbfb8031SShannon Nelson /****************************************************************** 2363fbfb8031SShannon Nelson ******************* Notify Events ******************************** 2364fbfb8031SShannon Nelson ******************************************************************/ 2365fbfb8031SShannon Nelson 2366fbfb8031SShannon Nelson /** 2367c4e7a75aSShannon Nelson * struct ionic_notifyq_event - Generic event reporting structure 2368fbfb8031SShannon Nelson * @eid: event number 2369fbfb8031SShannon Nelson * @ecode: event code 2370fbfb8031SShannon Nelson * @data: unspecified data about the event 2371fbfb8031SShannon Nelson * 2372fbfb8031SShannon Nelson * This is the generic event report struct from which the other 2373fbfb8031SShannon Nelson * actual events will be formed. 2374fbfb8031SShannon Nelson */ 2375fbfb8031SShannon Nelson struct ionic_notifyq_event { 2376fbfb8031SShannon Nelson __le64 eid; 2377fbfb8031SShannon Nelson __le16 ecode; 2378fbfb8031SShannon Nelson u8 data[54]; 2379fbfb8031SShannon Nelson }; 2380fbfb8031SShannon Nelson 2381fbfb8031SShannon Nelson /** 2382c4e7a75aSShannon Nelson * struct ionic_link_change_event - Link change event notification 2383fbfb8031SShannon Nelson * @eid: event number 2384c4e7a75aSShannon Nelson * @ecode: event code = IONIC_EVENT_LINK_CHANGE 23851b897e7dSShannon Nelson * @link_status: link up/down, with error bits (enum ionic_port_status) 2386fbfb8031SShannon Nelson * @link_speed: speed of the network link 2387fbfb8031SShannon Nelson * 2388fbfb8031SShannon Nelson * Sent when the network link state changes between UP and DOWN 2389fbfb8031SShannon Nelson */ 2390fbfb8031SShannon Nelson struct ionic_link_change_event { 2391fbfb8031SShannon Nelson __le64 eid; 2392fbfb8031SShannon Nelson __le16 ecode; 2393fbfb8031SShannon Nelson __le16 link_status; 2394fbfb8031SShannon Nelson __le32 link_speed; /* units of 1Mbps: e.g. 10000 = 10Gbps */ 2395fbfb8031SShannon Nelson u8 rsvd[48]; 2396fbfb8031SShannon Nelson }; 2397fbfb8031SShannon Nelson 2398fbfb8031SShannon Nelson /** 2399c4e7a75aSShannon Nelson * struct ionic_reset_event - Reset event notification 2400fbfb8031SShannon Nelson * @eid: event number 2401c4e7a75aSShannon Nelson * @ecode: event code = IONIC_EVENT_RESET 2402fbfb8031SShannon Nelson * @reset_code: reset type 2403fbfb8031SShannon Nelson * @state: 0=pending, 1=complete, 2=error 2404fbfb8031SShannon Nelson * 2405fbfb8031SShannon Nelson * Sent when the NIC or some subsystem is going to be or 2406fbfb8031SShannon Nelson * has been reset. 2407fbfb8031SShannon Nelson */ 2408fbfb8031SShannon Nelson struct ionic_reset_event { 2409fbfb8031SShannon Nelson __le64 eid; 2410fbfb8031SShannon Nelson __le16 ecode; 2411fbfb8031SShannon Nelson u8 reset_code; 2412fbfb8031SShannon Nelson u8 state; 2413fbfb8031SShannon Nelson u8 rsvd[52]; 2414fbfb8031SShannon Nelson }; 2415fbfb8031SShannon Nelson 2416fbfb8031SShannon Nelson /** 2417c4e7a75aSShannon Nelson * struct ionic_heartbeat_event - Sent periodically by NIC to indicate health 2418fbfb8031SShannon Nelson * @eid: event number 2419c4e7a75aSShannon Nelson * @ecode: event code = IONIC_EVENT_HEARTBEAT 2420fbfb8031SShannon Nelson */ 2421fbfb8031SShannon Nelson struct ionic_heartbeat_event { 2422fbfb8031SShannon Nelson __le64 eid; 2423fbfb8031SShannon Nelson __le16 ecode; 2424fbfb8031SShannon Nelson u8 rsvd[54]; 2425fbfb8031SShannon Nelson }; 2426fbfb8031SShannon Nelson 2427fbfb8031SShannon Nelson /** 2428c4e7a75aSShannon Nelson * struct ionic_log_event - Sent to notify the driver of an internal error 2429fbfb8031SShannon Nelson * @eid: event number 2430c4e7a75aSShannon Nelson * @ecode: event code = IONIC_EVENT_LOG 2431fbfb8031SShannon Nelson * @data: log data 2432fbfb8031SShannon Nelson */ 2433fbfb8031SShannon Nelson struct ionic_log_event { 2434fbfb8031SShannon Nelson __le64 eid; 2435fbfb8031SShannon Nelson __le16 ecode; 2436fbfb8031SShannon Nelson u8 data[54]; 2437fbfb8031SShannon Nelson }; 2438fbfb8031SShannon Nelson 2439fbfb8031SShannon Nelson /** 2440c4e7a75aSShannon Nelson * struct ionic_xcvr_event - Transceiver change event 2441c4e7a75aSShannon Nelson * @eid: event number 2442c4e7a75aSShannon Nelson * @ecode: event code = IONIC_EVENT_XCVR 2443c4e7a75aSShannon Nelson */ 2444c4e7a75aSShannon Nelson struct ionic_xcvr_event { 2445c4e7a75aSShannon Nelson __le64 eid; 2446c4e7a75aSShannon Nelson __le16 ecode; 2447c4e7a75aSShannon Nelson u8 rsvd[54]; 2448c4e7a75aSShannon Nelson }; 2449c4e7a75aSShannon Nelson 2450c4e7a75aSShannon Nelson /** 2451c4e7a75aSShannon Nelson * struct ionic_port_stats - Port statistics structure 2452fbfb8031SShannon Nelson */ 2453fbfb8031SShannon Nelson struct ionic_port_stats { 2454fbfb8031SShannon Nelson __le64 frames_rx_ok; 2455fbfb8031SShannon Nelson __le64 frames_rx_all; 2456fbfb8031SShannon Nelson __le64 frames_rx_bad_fcs; 2457fbfb8031SShannon Nelson __le64 frames_rx_bad_all; 2458fbfb8031SShannon Nelson __le64 octets_rx_ok; 2459fbfb8031SShannon Nelson __le64 octets_rx_all; 2460fbfb8031SShannon Nelson __le64 frames_rx_unicast; 2461fbfb8031SShannon Nelson __le64 frames_rx_multicast; 2462fbfb8031SShannon Nelson __le64 frames_rx_broadcast; 2463fbfb8031SShannon Nelson __le64 frames_rx_pause; 2464fbfb8031SShannon Nelson __le64 frames_rx_bad_length; 2465fbfb8031SShannon Nelson __le64 frames_rx_undersized; 2466fbfb8031SShannon Nelson __le64 frames_rx_oversized; 2467fbfb8031SShannon Nelson __le64 frames_rx_fragments; 2468fbfb8031SShannon Nelson __le64 frames_rx_jabber; 2469fbfb8031SShannon Nelson __le64 frames_rx_pripause; 2470fbfb8031SShannon Nelson __le64 frames_rx_stomped_crc; 2471fbfb8031SShannon Nelson __le64 frames_rx_too_long; 2472fbfb8031SShannon Nelson __le64 frames_rx_vlan_good; 2473fbfb8031SShannon Nelson __le64 frames_rx_dropped; 2474fbfb8031SShannon Nelson __le64 frames_rx_less_than_64b; 2475fbfb8031SShannon Nelson __le64 frames_rx_64b; 2476fbfb8031SShannon Nelson __le64 frames_rx_65b_127b; 2477fbfb8031SShannon Nelson __le64 frames_rx_128b_255b; 2478fbfb8031SShannon Nelson __le64 frames_rx_256b_511b; 2479fbfb8031SShannon Nelson __le64 frames_rx_512b_1023b; 2480fbfb8031SShannon Nelson __le64 frames_rx_1024b_1518b; 2481fbfb8031SShannon Nelson __le64 frames_rx_1519b_2047b; 2482fbfb8031SShannon Nelson __le64 frames_rx_2048b_4095b; 2483fbfb8031SShannon Nelson __le64 frames_rx_4096b_8191b; 2484fbfb8031SShannon Nelson __le64 frames_rx_8192b_9215b; 2485fbfb8031SShannon Nelson __le64 frames_rx_other; 2486fbfb8031SShannon Nelson __le64 frames_tx_ok; 2487fbfb8031SShannon Nelson __le64 frames_tx_all; 2488fbfb8031SShannon Nelson __le64 frames_tx_bad; 2489fbfb8031SShannon Nelson __le64 octets_tx_ok; 2490fbfb8031SShannon Nelson __le64 octets_tx_total; 2491fbfb8031SShannon Nelson __le64 frames_tx_unicast; 2492fbfb8031SShannon Nelson __le64 frames_tx_multicast; 2493fbfb8031SShannon Nelson __le64 frames_tx_broadcast; 2494fbfb8031SShannon Nelson __le64 frames_tx_pause; 2495fbfb8031SShannon Nelson __le64 frames_tx_pripause; 2496fbfb8031SShannon Nelson __le64 frames_tx_vlan; 2497fbfb8031SShannon Nelson __le64 frames_tx_less_than_64b; 2498fbfb8031SShannon Nelson __le64 frames_tx_64b; 2499fbfb8031SShannon Nelson __le64 frames_tx_65b_127b; 2500fbfb8031SShannon Nelson __le64 frames_tx_128b_255b; 2501fbfb8031SShannon Nelson __le64 frames_tx_256b_511b; 2502fbfb8031SShannon Nelson __le64 frames_tx_512b_1023b; 2503fbfb8031SShannon Nelson __le64 frames_tx_1024b_1518b; 2504fbfb8031SShannon Nelson __le64 frames_tx_1519b_2047b; 2505fbfb8031SShannon Nelson __le64 frames_tx_2048b_4095b; 2506fbfb8031SShannon Nelson __le64 frames_tx_4096b_8191b; 2507fbfb8031SShannon Nelson __le64 frames_tx_8192b_9215b; 2508fbfb8031SShannon Nelson __le64 frames_tx_other; 2509fbfb8031SShannon Nelson __le64 frames_tx_pri_0; 2510fbfb8031SShannon Nelson __le64 frames_tx_pri_1; 2511fbfb8031SShannon Nelson __le64 frames_tx_pri_2; 2512fbfb8031SShannon Nelson __le64 frames_tx_pri_3; 2513fbfb8031SShannon Nelson __le64 frames_tx_pri_4; 2514fbfb8031SShannon Nelson __le64 frames_tx_pri_5; 2515fbfb8031SShannon Nelson __le64 frames_tx_pri_6; 2516fbfb8031SShannon Nelson __le64 frames_tx_pri_7; 2517fbfb8031SShannon Nelson __le64 frames_rx_pri_0; 2518fbfb8031SShannon Nelson __le64 frames_rx_pri_1; 2519fbfb8031SShannon Nelson __le64 frames_rx_pri_2; 2520fbfb8031SShannon Nelson __le64 frames_rx_pri_3; 2521fbfb8031SShannon Nelson __le64 frames_rx_pri_4; 2522fbfb8031SShannon Nelson __le64 frames_rx_pri_5; 2523fbfb8031SShannon Nelson __le64 frames_rx_pri_6; 2524fbfb8031SShannon Nelson __le64 frames_rx_pri_7; 2525fbfb8031SShannon Nelson __le64 tx_pripause_0_1us_count; 2526fbfb8031SShannon Nelson __le64 tx_pripause_1_1us_count; 2527fbfb8031SShannon Nelson __le64 tx_pripause_2_1us_count; 2528fbfb8031SShannon Nelson __le64 tx_pripause_3_1us_count; 2529fbfb8031SShannon Nelson __le64 tx_pripause_4_1us_count; 2530fbfb8031SShannon Nelson __le64 tx_pripause_5_1us_count; 2531fbfb8031SShannon Nelson __le64 tx_pripause_6_1us_count; 2532fbfb8031SShannon Nelson __le64 tx_pripause_7_1us_count; 2533fbfb8031SShannon Nelson __le64 rx_pripause_0_1us_count; 2534fbfb8031SShannon Nelson __le64 rx_pripause_1_1us_count; 2535fbfb8031SShannon Nelson __le64 rx_pripause_2_1us_count; 2536fbfb8031SShannon Nelson __le64 rx_pripause_3_1us_count; 2537fbfb8031SShannon Nelson __le64 rx_pripause_4_1us_count; 2538fbfb8031SShannon Nelson __le64 rx_pripause_5_1us_count; 2539fbfb8031SShannon Nelson __le64 rx_pripause_6_1us_count; 2540fbfb8031SShannon Nelson __le64 rx_pripause_7_1us_count; 2541fbfb8031SShannon Nelson __le64 rx_pause_1us_count; 2542fbfb8031SShannon Nelson __le64 frames_tx_truncated; 2543fbfb8031SShannon Nelson }; 2544fbfb8031SShannon Nelson 2545fbfb8031SShannon Nelson struct ionic_mgmt_port_stats { 2546fbfb8031SShannon Nelson __le64 frames_rx_ok; 2547fbfb8031SShannon Nelson __le64 frames_rx_all; 2548fbfb8031SShannon Nelson __le64 frames_rx_bad_fcs; 2549fbfb8031SShannon Nelson __le64 frames_rx_bad_all; 2550fbfb8031SShannon Nelson __le64 octets_rx_ok; 2551fbfb8031SShannon Nelson __le64 octets_rx_all; 2552fbfb8031SShannon Nelson __le64 frames_rx_unicast; 2553fbfb8031SShannon Nelson __le64 frames_rx_multicast; 2554fbfb8031SShannon Nelson __le64 frames_rx_broadcast; 2555fbfb8031SShannon Nelson __le64 frames_rx_pause; 2556c4e7a75aSShannon Nelson __le64 frames_rx_bad_length; 2557c4e7a75aSShannon Nelson __le64 frames_rx_undersized; 2558c4e7a75aSShannon Nelson __le64 frames_rx_oversized; 2559c4e7a75aSShannon Nelson __le64 frames_rx_fragments; 2560c4e7a75aSShannon Nelson __le64 frames_rx_jabber; 2561c4e7a75aSShannon Nelson __le64 frames_rx_64b; 2562c4e7a75aSShannon Nelson __le64 frames_rx_65b_127b; 2563c4e7a75aSShannon Nelson __le64 frames_rx_128b_255b; 2564c4e7a75aSShannon Nelson __le64 frames_rx_256b_511b; 2565c4e7a75aSShannon Nelson __le64 frames_rx_512b_1023b; 2566c4e7a75aSShannon Nelson __le64 frames_rx_1024b_1518b; 2567c4e7a75aSShannon Nelson __le64 frames_rx_gt_1518b; 2568c4e7a75aSShannon Nelson __le64 frames_rx_fifo_full; 2569c4e7a75aSShannon Nelson __le64 frames_tx_ok; 2570c4e7a75aSShannon Nelson __le64 frames_tx_all; 2571c4e7a75aSShannon Nelson __le64 frames_tx_bad; 2572c4e7a75aSShannon Nelson __le64 octets_tx_ok; 2573c4e7a75aSShannon Nelson __le64 octets_tx_total; 2574c4e7a75aSShannon Nelson __le64 frames_tx_unicast; 2575c4e7a75aSShannon Nelson __le64 frames_tx_multicast; 2576c4e7a75aSShannon Nelson __le64 frames_tx_broadcast; 2577c4e7a75aSShannon Nelson __le64 frames_tx_pause; 2578c4e7a75aSShannon Nelson }; 2579c4e7a75aSShannon Nelson 2580c4e7a75aSShannon Nelson enum ionic_pb_buffer_drop_stats { 2581c4e7a75aSShannon Nelson IONIC_BUFFER_INTRINSIC_DROP = 0, 2582c4e7a75aSShannon Nelson IONIC_BUFFER_DISCARDED, 2583c4e7a75aSShannon Nelson IONIC_BUFFER_ADMITTED, 2584c4e7a75aSShannon Nelson IONIC_BUFFER_OUT_OF_CELLS_DROP, 2585c4e7a75aSShannon Nelson IONIC_BUFFER_OUT_OF_CELLS_DROP_2, 2586c4e7a75aSShannon Nelson IONIC_BUFFER_OUT_OF_CREDIT_DROP, 2587c4e7a75aSShannon Nelson IONIC_BUFFER_TRUNCATION_DROP, 2588c4e7a75aSShannon Nelson IONIC_BUFFER_PORT_DISABLED_DROP, 2589c4e7a75aSShannon Nelson IONIC_BUFFER_COPY_TO_CPU_TAIL_DROP, 2590c4e7a75aSShannon Nelson IONIC_BUFFER_SPAN_TAIL_DROP, 2591c4e7a75aSShannon Nelson IONIC_BUFFER_MIN_SIZE_VIOLATION_DROP, 2592c4e7a75aSShannon Nelson IONIC_BUFFER_ENQUEUE_ERROR_DROP, 2593c4e7a75aSShannon Nelson IONIC_BUFFER_INVALID_PORT_DROP, 2594c4e7a75aSShannon Nelson IONIC_BUFFER_INVALID_OUTPUT_QUEUE_DROP, 2595c4e7a75aSShannon Nelson IONIC_BUFFER_DROP_MAX, 2596c4e7a75aSShannon Nelson }; 2597c4e7a75aSShannon Nelson 25981b897e7dSShannon Nelson enum ionic_oflow_drop_stats { 25991b897e7dSShannon Nelson IONIC_OFLOW_OCCUPANCY_DROP, 26001b897e7dSShannon Nelson IONIC_OFLOW_EMERGENCY_STOP_DROP, 26011b897e7dSShannon Nelson IONIC_OFLOW_WRITE_BUFFER_ACK_FILL_UP_DROP, 26021b897e7dSShannon Nelson IONIC_OFLOW_WRITE_BUFFER_ACK_FULL_DROP, 26031b897e7dSShannon Nelson IONIC_OFLOW_WRITE_BUFFER_FULL_DROP, 26041b897e7dSShannon Nelson IONIC_OFLOW_CONTROL_FIFO_FULL_DROP, 26051b897e7dSShannon Nelson IONIC_OFLOW_DROP_MAX, 26061b897e7dSShannon Nelson }; 26071b897e7dSShannon Nelson 2608c4e7a75aSShannon Nelson /** 2609c4e7a75aSShannon Nelson * struct port_pb_stats - packet buffers system stats 2610c4e7a75aSShannon Nelson * uses ionic_pb_buffer_drop_stats for drop_counts[] 2611c4e7a75aSShannon Nelson */ 2612c4e7a75aSShannon Nelson struct ionic_port_pb_stats { 2613c4e7a75aSShannon Nelson __le64 sop_count_in; 2614c4e7a75aSShannon Nelson __le64 eop_count_in; 2615c4e7a75aSShannon Nelson __le64 sop_count_out; 2616c4e7a75aSShannon Nelson __le64 eop_count_out; 2617c4e7a75aSShannon Nelson __le64 drop_counts[IONIC_BUFFER_DROP_MAX]; 2618c4e7a75aSShannon Nelson __le64 input_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2619c4e7a75aSShannon Nelson __le64 input_queue_port_monitor[IONIC_QOS_TC_MAX]; 2620c4e7a75aSShannon Nelson __le64 output_queue_port_monitor[IONIC_QOS_TC_MAX]; 26211b897e7dSShannon Nelson __le64 oflow_drop_counts[IONIC_OFLOW_DROP_MAX]; 26221b897e7dSShannon Nelson __le64 input_queue_good_pkts_in[IONIC_QOS_TC_MAX]; 26231b897e7dSShannon Nelson __le64 input_queue_good_pkts_out[IONIC_QOS_TC_MAX]; 26241b897e7dSShannon Nelson __le64 input_queue_err_pkts_in[IONIC_QOS_TC_MAX]; 26251b897e7dSShannon Nelson __le64 input_queue_fifo_depth[IONIC_QOS_TC_MAX]; 26261b897e7dSShannon Nelson __le64 input_queue_max_fifo_depth[IONIC_QOS_TC_MAX]; 26271b897e7dSShannon Nelson __le64 input_queue_peak_occupancy[IONIC_QOS_TC_MAX]; 26281b897e7dSShannon Nelson __le64 output_queue_buffer_occupancy[IONIC_QOS_TC_MAX]; 2629fbfb8031SShannon Nelson }; 2630fbfb8031SShannon Nelson 2631fbfb8031SShannon Nelson /** 26325c28f213SShannon Nelson * struct ionic_port_identity - port identity structure 2633fbfb8031SShannon Nelson * @version: identity structure version 26341b897e7dSShannon Nelson * @type: type of port (enum ionic_port_type) 2635fbfb8031SShannon Nelson * @num_lanes: number of lanes for the port 2636fbfb8031SShannon Nelson * @autoneg: autoneg supported 2637fbfb8031SShannon Nelson * @min_frame_size: minimum frame size supported 2638fbfb8031SShannon Nelson * @max_frame_size: maximum frame size supported 2639fbfb8031SShannon Nelson * @fec_type: supported fec types 2640fbfb8031SShannon Nelson * @pause_type: supported pause types 2641fbfb8031SShannon Nelson * @loopback_mode: supported loopback mode 2642fbfb8031SShannon Nelson * @speeds: supported speeds 2643fbfb8031SShannon Nelson * @config: current port configuration 2644fbfb8031SShannon Nelson */ 2645fbfb8031SShannon Nelson union ionic_port_identity { 2646fbfb8031SShannon Nelson struct { 2647fbfb8031SShannon Nelson u8 version; 2648fbfb8031SShannon Nelson u8 type; 2649fbfb8031SShannon Nelson u8 num_lanes; 2650fbfb8031SShannon Nelson u8 autoneg; 2651fbfb8031SShannon Nelson __le32 min_frame_size; 2652fbfb8031SShannon Nelson __le32 max_frame_size; 2653fbfb8031SShannon Nelson u8 fec_type[4]; 2654fbfb8031SShannon Nelson u8 pause_type[2]; 2655fbfb8031SShannon Nelson u8 loopback_mode[2]; 2656fbfb8031SShannon Nelson __le32 speeds[16]; 2657fbfb8031SShannon Nelson u8 rsvd2[44]; 2658fbfb8031SShannon Nelson union ionic_port_config config; 2659fbfb8031SShannon Nelson }; 2660c4e7a75aSShannon Nelson __le32 words[478]; 2661fbfb8031SShannon Nelson }; 2662fbfb8031SShannon Nelson 2663fbfb8031SShannon Nelson /** 26645c28f213SShannon Nelson * struct ionic_port_info - port info structure 2665c4e7a75aSShannon Nelson * @config: Port configuration data 2666c4e7a75aSShannon Nelson * @status: Port status data 2667c4e7a75aSShannon Nelson * @stats: Port statistics data 2668c4e7a75aSShannon Nelson * @mgmt_stats: Port management statistics data 2669c4e7a75aSShannon Nelson * @port_pb_drop_stats: uplink pb drop stats 2670fbfb8031SShannon Nelson */ 2671fbfb8031SShannon Nelson struct ionic_port_info { 2672fbfb8031SShannon Nelson union ionic_port_config config; 2673fbfb8031SShannon Nelson struct ionic_port_status status; 2674c4e7a75aSShannon Nelson union { 2675fbfb8031SShannon Nelson struct ionic_port_stats stats; 2676c4e7a75aSShannon Nelson struct ionic_mgmt_port_stats mgmt_stats; 2677c4e7a75aSShannon Nelson }; 2678c4e7a75aSShannon Nelson /* room for pb_stats to start at 2k offset */ 2679c4e7a75aSShannon Nelson u8 rsvd[760]; 2680c4e7a75aSShannon Nelson struct ionic_port_pb_stats pb_stats; 2681fbfb8031SShannon Nelson }; 2682fbfb8031SShannon Nelson 2683fbfb8031SShannon Nelson /** 2684c4e7a75aSShannon Nelson * struct ionic_lif_stats - LIF statistics structure 2685fbfb8031SShannon Nelson */ 2686fbfb8031SShannon Nelson struct ionic_lif_stats { 2687fbfb8031SShannon Nelson /* RX */ 2688fbfb8031SShannon Nelson __le64 rx_ucast_bytes; 2689fbfb8031SShannon Nelson __le64 rx_ucast_packets; 2690fbfb8031SShannon Nelson __le64 rx_mcast_bytes; 2691fbfb8031SShannon Nelson __le64 rx_mcast_packets; 2692fbfb8031SShannon Nelson __le64 rx_bcast_bytes; 2693fbfb8031SShannon Nelson __le64 rx_bcast_packets; 2694fbfb8031SShannon Nelson __le64 rsvd0; 2695fbfb8031SShannon Nelson __le64 rsvd1; 2696fbfb8031SShannon Nelson /* RX drops */ 2697fbfb8031SShannon Nelson __le64 rx_ucast_drop_bytes; 2698fbfb8031SShannon Nelson __le64 rx_ucast_drop_packets; 2699fbfb8031SShannon Nelson __le64 rx_mcast_drop_bytes; 2700fbfb8031SShannon Nelson __le64 rx_mcast_drop_packets; 2701fbfb8031SShannon Nelson __le64 rx_bcast_drop_bytes; 2702fbfb8031SShannon Nelson __le64 rx_bcast_drop_packets; 2703fbfb8031SShannon Nelson __le64 rx_dma_error; 2704fbfb8031SShannon Nelson __le64 rsvd2; 2705fbfb8031SShannon Nelson /* TX */ 2706fbfb8031SShannon Nelson __le64 tx_ucast_bytes; 2707fbfb8031SShannon Nelson __le64 tx_ucast_packets; 2708fbfb8031SShannon Nelson __le64 tx_mcast_bytes; 2709fbfb8031SShannon Nelson __le64 tx_mcast_packets; 2710fbfb8031SShannon Nelson __le64 tx_bcast_bytes; 2711fbfb8031SShannon Nelson __le64 tx_bcast_packets; 2712fbfb8031SShannon Nelson __le64 rsvd3; 2713fbfb8031SShannon Nelson __le64 rsvd4; 2714fbfb8031SShannon Nelson /* TX drops */ 2715fbfb8031SShannon Nelson __le64 tx_ucast_drop_bytes; 2716fbfb8031SShannon Nelson __le64 tx_ucast_drop_packets; 2717fbfb8031SShannon Nelson __le64 tx_mcast_drop_bytes; 2718fbfb8031SShannon Nelson __le64 tx_mcast_drop_packets; 2719fbfb8031SShannon Nelson __le64 tx_bcast_drop_bytes; 2720fbfb8031SShannon Nelson __le64 tx_bcast_drop_packets; 2721fbfb8031SShannon Nelson __le64 tx_dma_error; 2722fbfb8031SShannon Nelson __le64 rsvd5; 2723fbfb8031SShannon Nelson /* Rx Queue/Ring drops */ 2724fbfb8031SShannon Nelson __le64 rx_queue_disabled; 2725fbfb8031SShannon Nelson __le64 rx_queue_empty; 2726fbfb8031SShannon Nelson __le64 rx_queue_error; 2727fbfb8031SShannon Nelson __le64 rx_desc_fetch_error; 2728fbfb8031SShannon Nelson __le64 rx_desc_data_error; 2729fbfb8031SShannon Nelson __le64 rsvd6; 2730fbfb8031SShannon Nelson __le64 rsvd7; 2731fbfb8031SShannon Nelson __le64 rsvd8; 2732fbfb8031SShannon Nelson /* Tx Queue/Ring drops */ 2733fbfb8031SShannon Nelson __le64 tx_queue_disabled; 2734fbfb8031SShannon Nelson __le64 tx_queue_error; 2735fbfb8031SShannon Nelson __le64 tx_desc_fetch_error; 2736fbfb8031SShannon Nelson __le64 tx_desc_data_error; 2737c4e7a75aSShannon Nelson __le64 tx_queue_empty; 2738fbfb8031SShannon Nelson __le64 rsvd10; 2739fbfb8031SShannon Nelson __le64 rsvd11; 2740fbfb8031SShannon Nelson __le64 rsvd12; 2741fbfb8031SShannon Nelson 2742fbfb8031SShannon Nelson /* RDMA/ROCE TX */ 2743fbfb8031SShannon Nelson __le64 tx_rdma_ucast_bytes; 2744fbfb8031SShannon Nelson __le64 tx_rdma_ucast_packets; 2745fbfb8031SShannon Nelson __le64 tx_rdma_mcast_bytes; 2746fbfb8031SShannon Nelson __le64 tx_rdma_mcast_packets; 2747fbfb8031SShannon Nelson __le64 tx_rdma_cnp_packets; 2748fbfb8031SShannon Nelson __le64 rsvd13; 2749fbfb8031SShannon Nelson __le64 rsvd14; 2750fbfb8031SShannon Nelson __le64 rsvd15; 2751fbfb8031SShannon Nelson 2752fbfb8031SShannon Nelson /* RDMA/ROCE RX */ 2753fbfb8031SShannon Nelson __le64 rx_rdma_ucast_bytes; 2754fbfb8031SShannon Nelson __le64 rx_rdma_ucast_packets; 2755fbfb8031SShannon Nelson __le64 rx_rdma_mcast_bytes; 2756fbfb8031SShannon Nelson __le64 rx_rdma_mcast_packets; 2757fbfb8031SShannon Nelson __le64 rx_rdma_cnp_packets; 2758fbfb8031SShannon Nelson __le64 rx_rdma_ecn_packets; 2759fbfb8031SShannon Nelson __le64 rsvd16; 2760fbfb8031SShannon Nelson __le64 rsvd17; 2761fbfb8031SShannon Nelson 2762fbfb8031SShannon Nelson __le64 rsvd18; 2763fbfb8031SShannon Nelson __le64 rsvd19; 2764fbfb8031SShannon Nelson __le64 rsvd20; 2765fbfb8031SShannon Nelson __le64 rsvd21; 2766fbfb8031SShannon Nelson __le64 rsvd22; 2767fbfb8031SShannon Nelson __le64 rsvd23; 2768fbfb8031SShannon Nelson __le64 rsvd24; 2769fbfb8031SShannon Nelson __le64 rsvd25; 2770fbfb8031SShannon Nelson 2771fbfb8031SShannon Nelson __le64 rsvd26; 2772fbfb8031SShannon Nelson __le64 rsvd27; 2773fbfb8031SShannon Nelson __le64 rsvd28; 2774fbfb8031SShannon Nelson __le64 rsvd29; 2775fbfb8031SShannon Nelson __le64 rsvd30; 2776fbfb8031SShannon Nelson __le64 rsvd31; 2777fbfb8031SShannon Nelson __le64 rsvd32; 2778fbfb8031SShannon Nelson __le64 rsvd33; 2779fbfb8031SShannon Nelson 2780fbfb8031SShannon Nelson __le64 rsvd34; 2781fbfb8031SShannon Nelson __le64 rsvd35; 2782fbfb8031SShannon Nelson __le64 rsvd36; 2783fbfb8031SShannon Nelson __le64 rsvd37; 2784fbfb8031SShannon Nelson __le64 rsvd38; 2785fbfb8031SShannon Nelson __le64 rsvd39; 2786fbfb8031SShannon Nelson __le64 rsvd40; 2787fbfb8031SShannon Nelson __le64 rsvd41; 2788fbfb8031SShannon Nelson 2789fbfb8031SShannon Nelson __le64 rsvd42; 2790fbfb8031SShannon Nelson __le64 rsvd43; 2791fbfb8031SShannon Nelson __le64 rsvd44; 2792fbfb8031SShannon Nelson __le64 rsvd45; 2793fbfb8031SShannon Nelson __le64 rsvd46; 2794fbfb8031SShannon Nelson __le64 rsvd47; 2795fbfb8031SShannon Nelson __le64 rsvd48; 2796fbfb8031SShannon Nelson __le64 rsvd49; 2797fbfb8031SShannon Nelson 2798fbfb8031SShannon Nelson /* RDMA/ROCE REQ Error/Debugs (768 - 895) */ 2799fbfb8031SShannon Nelson __le64 rdma_req_rx_pkt_seq_err; 2800fbfb8031SShannon Nelson __le64 rdma_req_rx_rnr_retry_err; 2801fbfb8031SShannon Nelson __le64 rdma_req_rx_remote_access_err; 2802fbfb8031SShannon Nelson __le64 rdma_req_rx_remote_inv_req_err; 2803fbfb8031SShannon Nelson __le64 rdma_req_rx_remote_oper_err; 2804fbfb8031SShannon Nelson __le64 rdma_req_rx_implied_nak_seq_err; 2805fbfb8031SShannon Nelson __le64 rdma_req_rx_cqe_err; 2806fbfb8031SShannon Nelson __le64 rdma_req_rx_cqe_flush_err; 2807fbfb8031SShannon Nelson 2808fbfb8031SShannon Nelson __le64 rdma_req_rx_dup_responses; 2809fbfb8031SShannon Nelson __le64 rdma_req_rx_invalid_packets; 2810fbfb8031SShannon Nelson __le64 rdma_req_tx_local_access_err; 2811fbfb8031SShannon Nelson __le64 rdma_req_tx_local_oper_err; 2812fbfb8031SShannon Nelson __le64 rdma_req_tx_memory_mgmt_err; 2813fbfb8031SShannon Nelson __le64 rsvd52; 2814fbfb8031SShannon Nelson __le64 rsvd53; 2815fbfb8031SShannon Nelson __le64 rsvd54; 2816fbfb8031SShannon Nelson 2817fbfb8031SShannon Nelson /* RDMA/ROCE RESP Error/Debugs (896 - 1023) */ 2818fbfb8031SShannon Nelson __le64 rdma_resp_rx_dup_requests; 2819fbfb8031SShannon Nelson __le64 rdma_resp_rx_out_of_buffer; 2820fbfb8031SShannon Nelson __le64 rdma_resp_rx_out_of_seq_pkts; 2821fbfb8031SShannon Nelson __le64 rdma_resp_rx_cqe_err; 2822fbfb8031SShannon Nelson __le64 rdma_resp_rx_cqe_flush_err; 2823fbfb8031SShannon Nelson __le64 rdma_resp_rx_local_len_err; 2824fbfb8031SShannon Nelson __le64 rdma_resp_rx_inv_request_err; 2825fbfb8031SShannon Nelson __le64 rdma_resp_rx_local_qp_oper_err; 2826fbfb8031SShannon Nelson 2827fbfb8031SShannon Nelson __le64 rdma_resp_rx_out_of_atomic_resource; 2828fbfb8031SShannon Nelson __le64 rdma_resp_tx_pkt_seq_err; 2829fbfb8031SShannon Nelson __le64 rdma_resp_tx_remote_inv_req_err; 2830fbfb8031SShannon Nelson __le64 rdma_resp_tx_remote_access_err; 2831fbfb8031SShannon Nelson __le64 rdma_resp_tx_remote_oper_err; 2832fbfb8031SShannon Nelson __le64 rdma_resp_tx_rnr_retry_err; 2833fbfb8031SShannon Nelson __le64 rsvd57; 2834fbfb8031SShannon Nelson __le64 rsvd58; 2835fbfb8031SShannon Nelson }; 2836fbfb8031SShannon Nelson 2837fbfb8031SShannon Nelson /** 2838c4e7a75aSShannon Nelson * struct ionic_lif_info - LIF info structure 2839c4e7a75aSShannon Nelson * @config: LIF configuration structure 2840c4e7a75aSShannon Nelson * @status: LIF status structure 2841c4e7a75aSShannon Nelson * @stats: LIF statistics structure 2842fbfb8031SShannon Nelson */ 2843fbfb8031SShannon Nelson struct ionic_lif_info { 2844fbfb8031SShannon Nelson union ionic_lif_config config; 2845fbfb8031SShannon Nelson struct ionic_lif_status status; 2846fbfb8031SShannon Nelson struct ionic_lif_stats stats; 2847fbfb8031SShannon Nelson }; 2848fbfb8031SShannon Nelson 2849fbfb8031SShannon Nelson union ionic_dev_cmd { 2850fbfb8031SShannon Nelson u32 words[16]; 2851fbfb8031SShannon Nelson struct ionic_admin_cmd cmd; 2852fbfb8031SShannon Nelson struct ionic_nop_cmd nop; 2853fbfb8031SShannon Nelson 2854fbfb8031SShannon Nelson struct ionic_dev_identify_cmd identify; 2855fbfb8031SShannon Nelson struct ionic_dev_init_cmd init; 2856fbfb8031SShannon Nelson struct ionic_dev_reset_cmd reset; 2857fbfb8031SShannon Nelson struct ionic_dev_getattr_cmd getattr; 2858fbfb8031SShannon Nelson struct ionic_dev_setattr_cmd setattr; 2859fbfb8031SShannon Nelson 2860fbfb8031SShannon Nelson struct ionic_port_identify_cmd port_identify; 2861fbfb8031SShannon Nelson struct ionic_port_init_cmd port_init; 2862fbfb8031SShannon Nelson struct ionic_port_reset_cmd port_reset; 2863fbfb8031SShannon Nelson struct ionic_port_getattr_cmd port_getattr; 2864fbfb8031SShannon Nelson struct ionic_port_setattr_cmd port_setattr; 2865fbfb8031SShannon Nelson 28663d462ce2SShannon Nelson struct ionic_vf_setattr_cmd vf_setattr; 28673d462ce2SShannon Nelson struct ionic_vf_getattr_cmd vf_getattr; 28683d462ce2SShannon Nelson 2869fbfb8031SShannon Nelson struct ionic_lif_identify_cmd lif_identify; 2870fbfb8031SShannon Nelson struct ionic_lif_init_cmd lif_init; 2871fbfb8031SShannon Nelson struct ionic_lif_reset_cmd lif_reset; 2872fbfb8031SShannon Nelson 2873fbfb8031SShannon Nelson struct ionic_qos_identify_cmd qos_identify; 2874fbfb8031SShannon Nelson struct ionic_qos_init_cmd qos_init; 2875fbfb8031SShannon Nelson struct ionic_qos_reset_cmd qos_reset; 28761b897e7dSShannon Nelson struct ionic_qos_clear_stats_cmd qos_clear_stats; 2877fbfb8031SShannon Nelson 28785b3f3f2aSShannon Nelson struct ionic_q_identify_cmd q_identify; 2879fbfb8031SShannon Nelson struct ionic_q_init_cmd q_init; 2880c4e7a75aSShannon Nelson struct ionic_q_control_cmd q_control; 288187c905d8SShannon Nelson 288287c905d8SShannon Nelson struct ionic_fw_download_cmd fw_download; 288387c905d8SShannon Nelson struct ionic_fw_control_cmd fw_control; 2884fbfb8031SShannon Nelson }; 2885fbfb8031SShannon Nelson 2886fbfb8031SShannon Nelson union ionic_dev_cmd_comp { 2887fbfb8031SShannon Nelson u32 words[4]; 2888fbfb8031SShannon Nelson u8 status; 2889fbfb8031SShannon Nelson struct ionic_admin_comp comp; 2890fbfb8031SShannon Nelson struct ionic_nop_comp nop; 2891fbfb8031SShannon Nelson 2892fbfb8031SShannon Nelson struct ionic_dev_identify_comp identify; 2893fbfb8031SShannon Nelson struct ionic_dev_init_comp init; 2894fbfb8031SShannon Nelson struct ionic_dev_reset_comp reset; 2895fbfb8031SShannon Nelson struct ionic_dev_getattr_comp getattr; 2896fbfb8031SShannon Nelson struct ionic_dev_setattr_comp setattr; 2897fbfb8031SShannon Nelson 2898fbfb8031SShannon Nelson struct ionic_port_identify_comp port_identify; 2899fbfb8031SShannon Nelson struct ionic_port_init_comp port_init; 2900fbfb8031SShannon Nelson struct ionic_port_reset_comp port_reset; 2901fbfb8031SShannon Nelson struct ionic_port_getattr_comp port_getattr; 2902fbfb8031SShannon Nelson struct ionic_port_setattr_comp port_setattr; 2903fbfb8031SShannon Nelson 29043d462ce2SShannon Nelson struct ionic_vf_setattr_comp vf_setattr; 29053d462ce2SShannon Nelson struct ionic_vf_getattr_comp vf_getattr; 29063d462ce2SShannon Nelson 2907fbfb8031SShannon Nelson struct ionic_lif_identify_comp lif_identify; 2908fbfb8031SShannon Nelson struct ionic_lif_init_comp lif_init; 2909fbfb8031SShannon Nelson ionic_lif_reset_comp lif_reset; 2910fbfb8031SShannon Nelson 2911fbfb8031SShannon Nelson struct ionic_qos_identify_comp qos_identify; 2912fbfb8031SShannon Nelson ionic_qos_init_comp qos_init; 2913fbfb8031SShannon Nelson ionic_qos_reset_comp qos_reset; 2914fbfb8031SShannon Nelson 29155b3f3f2aSShannon Nelson struct ionic_q_identify_comp q_identify; 2916fbfb8031SShannon Nelson struct ionic_q_init_comp q_init; 291787c905d8SShannon Nelson 291887c905d8SShannon Nelson ionic_fw_download_comp fw_download; 291987c905d8SShannon Nelson struct ionic_fw_control_comp fw_control; 2920fbfb8031SShannon Nelson }; 2921fbfb8031SShannon Nelson 2922fbfb8031SShannon Nelson /** 29233da25843SShannon Nelson * struct ionic_hwstamp_regs - Hardware current timestamp registers 29243da25843SShannon Nelson * @tick_low: Low 32 bits of hardware timestamp 29253da25843SShannon Nelson * @tick_high: High 32 bits of hardware timestamp 29263da25843SShannon Nelson */ 29273da25843SShannon Nelson struct ionic_hwstamp_regs { 29283da25843SShannon Nelson u32 tick_low; 29293da25843SShannon Nelson u32 tick_high; 29303da25843SShannon Nelson }; 29313da25843SShannon Nelson 29323da25843SShannon Nelson /** 2933c4e7a75aSShannon Nelson * union ionic_dev_info_regs - Device info register format (read-only) 2934c4e7a75aSShannon Nelson * @signature: Signature value of 0x44455649 ('DEVI') 2935c4e7a75aSShannon Nelson * @version: Current version of info 2936c4e7a75aSShannon Nelson * @asic_type: Asic type 2937c4e7a75aSShannon Nelson * @asic_rev: Asic revision 2938c4e7a75aSShannon Nelson * @fw_status: Firmware status 2939d2662072SShannon Nelson * bit 0 - 1 = fw running 2940d2662072SShannon Nelson * bit 4-7 - 4 bit generation number, changes on fw restart 2941c4e7a75aSShannon Nelson * @fw_heartbeat: Firmware heartbeat counter 2942c4e7a75aSShannon Nelson * @serial_num: Serial number 2943c4e7a75aSShannon Nelson * @fw_version: Firmware version 29443da25843SShannon Nelson * @hwstamp_regs: Hardware current timestamp registers 2945fbfb8031SShannon Nelson */ 2946fbfb8031SShannon Nelson union ionic_dev_info_regs { 2947fbfb8031SShannon Nelson #define IONIC_DEVINFO_FWVERS_BUFLEN 32 2948fbfb8031SShannon Nelson #define IONIC_DEVINFO_SERIAL_BUFLEN 32 2949fbfb8031SShannon Nelson struct { 2950fbfb8031SShannon Nelson u32 signature; 2951fbfb8031SShannon Nelson u8 version; 2952fbfb8031SShannon Nelson u8 asic_type; 2953fbfb8031SShannon Nelson u8 asic_rev; 2954d2662072SShannon Nelson #define IONIC_FW_STS_F_RUNNING 0x01 2955d2662072SShannon Nelson #define IONIC_FW_STS_F_GENERATION 0xF0 2956fbfb8031SShannon Nelson u8 fw_status; 2957fbfb8031SShannon Nelson u32 fw_heartbeat; 2958fbfb8031SShannon Nelson char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN]; 2959fbfb8031SShannon Nelson char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN]; 29603da25843SShannon Nelson u8 rsvd_pad1024[948]; 29613da25843SShannon Nelson struct ionic_hwstamp_regs hwstamp; 2962fbfb8031SShannon Nelson }; 2963fbfb8031SShannon Nelson u32 words[512]; 2964fbfb8031SShannon Nelson }; 2965fbfb8031SShannon Nelson 2966fbfb8031SShannon Nelson /** 29675c28f213SShannon Nelson * union ionic_dev_cmd_regs - Device command register format (read-write) 2968c4e7a75aSShannon Nelson * @doorbell: Device Cmd Doorbell, write-only 2969fbfb8031SShannon Nelson * Write a 1 to signal device to process cmd, 2970fbfb8031SShannon Nelson * poll done for completion. 2971c4e7a75aSShannon Nelson * @done: Done indicator, bit 0 == 1 when command is complete 2972fbfb8031SShannon Nelson * @cmd: Opcode-specific command bytes 2973fbfb8031SShannon Nelson * @comp: Opcode-specific response bytes 2974fbfb8031SShannon Nelson * @data: Opcode-specific side-data 2975fbfb8031SShannon Nelson */ 2976fbfb8031SShannon Nelson union ionic_dev_cmd_regs { 2977fbfb8031SShannon Nelson struct { 2978fbfb8031SShannon Nelson u32 doorbell; 2979fbfb8031SShannon Nelson u32 done; 2980fbfb8031SShannon Nelson union ionic_dev_cmd cmd; 2981fbfb8031SShannon Nelson union ionic_dev_cmd_comp comp; 2982fbfb8031SShannon Nelson u8 rsvd[48]; 2983fbfb8031SShannon Nelson u32 data[478]; 29845dca69c4SShannon Nelson } __packed; 2985fbfb8031SShannon Nelson u32 words[512]; 2986fbfb8031SShannon Nelson }; 2987fbfb8031SShannon Nelson 2988fbfb8031SShannon Nelson /** 2989c4e7a75aSShannon Nelson * union ionic_dev_regs - Device register format for bar 0 page 0 2990fbfb8031SShannon Nelson * @info: Device info registers 2991fbfb8031SShannon Nelson * @devcmd: Device command registers 2992fbfb8031SShannon Nelson */ 2993fbfb8031SShannon Nelson union ionic_dev_regs { 2994fbfb8031SShannon Nelson struct { 2995fbfb8031SShannon Nelson union ionic_dev_info_regs info; 2996fbfb8031SShannon Nelson union ionic_dev_cmd_regs devcmd; 29975dca69c4SShannon Nelson } __packed; 2998fbfb8031SShannon Nelson __le32 words[1024]; 2999fbfb8031SShannon Nelson }; 3000fbfb8031SShannon Nelson 3001fbfb8031SShannon Nelson union ionic_adminq_cmd { 3002fbfb8031SShannon Nelson struct ionic_admin_cmd cmd; 3003fbfb8031SShannon Nelson struct ionic_nop_cmd nop; 3004c4e7a75aSShannon Nelson struct ionic_q_identify_cmd q_identify; 3005fbfb8031SShannon Nelson struct ionic_q_init_cmd q_init; 3006fbfb8031SShannon Nelson struct ionic_q_control_cmd q_control; 3007fbfb8031SShannon Nelson struct ionic_lif_setattr_cmd lif_setattr; 3008fbfb8031SShannon Nelson struct ionic_lif_getattr_cmd lif_getattr; 30093da25843SShannon Nelson struct ionic_lif_setphc_cmd lif_setphc; 3010fbfb8031SShannon Nelson struct ionic_rx_mode_set_cmd rx_mode_set; 3011fbfb8031SShannon Nelson struct ionic_rx_filter_add_cmd rx_filter_add; 3012fbfb8031SShannon Nelson struct ionic_rx_filter_del_cmd rx_filter_del; 3013fbfb8031SShannon Nelson struct ionic_rdma_reset_cmd rdma_reset; 3014fbfb8031SShannon Nelson struct ionic_rdma_queue_cmd rdma_queue; 3015fbfb8031SShannon Nelson struct ionic_fw_download_cmd fw_download; 3016fbfb8031SShannon Nelson struct ionic_fw_control_cmd fw_control; 3017fbfb8031SShannon Nelson }; 3018fbfb8031SShannon Nelson 3019fbfb8031SShannon Nelson union ionic_adminq_comp { 3020fbfb8031SShannon Nelson struct ionic_admin_comp comp; 3021fbfb8031SShannon Nelson struct ionic_nop_comp nop; 3022c4e7a75aSShannon Nelson struct ionic_q_identify_comp q_identify; 3023fbfb8031SShannon Nelson struct ionic_q_init_comp q_init; 3024fbfb8031SShannon Nelson struct ionic_lif_setattr_comp lif_setattr; 3025fbfb8031SShannon Nelson struct ionic_lif_getattr_comp lif_getattr; 30263da25843SShannon Nelson struct ionic_admin_comp lif_setphc; 3027fbfb8031SShannon Nelson struct ionic_rx_filter_add_comp rx_filter_add; 3028fbfb8031SShannon Nelson struct ionic_fw_control_comp fw_control; 3029fbfb8031SShannon Nelson }; 3030fbfb8031SShannon Nelson 3031fbfb8031SShannon Nelson #define IONIC_BARS_MAX 6 3032fbfb8031SShannon Nelson #define IONIC_PCI_BAR_DBELL 1 3033fbfb8031SShannon Nelson 3034fbfb8031SShannon Nelson /* BAR0 */ 3035fbfb8031SShannon Nelson #define IONIC_BAR0_SIZE 0x8000 3036fbfb8031SShannon Nelson 3037fbfb8031SShannon Nelson #define IONIC_BAR0_DEV_INFO_REGS_OFFSET 0x0000 3038fbfb8031SShannon Nelson #define IONIC_BAR0_DEV_CMD_REGS_OFFSET 0x0800 3039fbfb8031SShannon Nelson #define IONIC_BAR0_DEV_CMD_DATA_REGS_OFFSET 0x0c00 3040fbfb8031SShannon Nelson #define IONIC_BAR0_INTR_STATUS_OFFSET 0x1000 3041fbfb8031SShannon Nelson #define IONIC_BAR0_INTR_CTRL_OFFSET 0x2000 3042fbfb8031SShannon Nelson #define IONIC_DEV_CMD_DONE 0x00000001 3043fbfb8031SShannon Nelson 3044fbfb8031SShannon Nelson #define IONIC_ASIC_TYPE_CAPRI 0 3045fbfb8031SShannon Nelson 3046fbfb8031SShannon Nelson /** 30475c28f213SShannon Nelson * struct ionic_doorbell - Doorbell register layout 3048fbfb8031SShannon Nelson * @p_index: Producer index 3049c4e7a75aSShannon Nelson * @ring: Selects the specific ring of the queue to update 3050fbfb8031SShannon Nelson * Type-specific meaning: 3051c4e7a75aSShannon Nelson * ring=0: Default producer/consumer queue 3052fbfb8031SShannon Nelson * ring=1: (CQ, EQ) Re-Arm queue. RDMA CQs 3053fbfb8031SShannon Nelson * send events to EQs when armed. EQs send 3054fbfb8031SShannon Nelson * interrupts when armed. 3055c4e7a75aSShannon Nelson * @qid_lo: Queue destination for the producer index and flags (low bits) 3056c4e7a75aSShannon Nelson * @qid_hi: Queue destination for the producer index and flags (high bits) 3057fbfb8031SShannon Nelson */ 3058fbfb8031SShannon Nelson struct ionic_doorbell { 3059fbfb8031SShannon Nelson __le16 p_index; 3060fbfb8031SShannon Nelson u8 ring; 3061fbfb8031SShannon Nelson u8 qid_lo; 3062fbfb8031SShannon Nelson __le16 qid_hi; 3063fbfb8031SShannon Nelson u16 rsvd2; 3064fbfb8031SShannon Nelson }; 3065fbfb8031SShannon Nelson 3066fbfb8031SShannon Nelson struct ionic_intr_status { 3067fbfb8031SShannon Nelson u32 status[2]; 3068fbfb8031SShannon Nelson }; 3069fbfb8031SShannon Nelson 3070fbfb8031SShannon Nelson struct ionic_notifyq_cmd { 3071fbfb8031SShannon Nelson __le32 data; /* Not used but needed for qcq structure */ 3072fbfb8031SShannon Nelson }; 3073fbfb8031SShannon Nelson 3074fbfb8031SShannon Nelson union ionic_notifyq_comp { 3075fbfb8031SShannon Nelson struct ionic_notifyq_event event; 3076fbfb8031SShannon Nelson struct ionic_link_change_event link_change; 3077fbfb8031SShannon Nelson struct ionic_reset_event reset; 3078fbfb8031SShannon Nelson struct ionic_heartbeat_event heartbeat; 3079fbfb8031SShannon Nelson struct ionic_log_event log; 3080fbfb8031SShannon Nelson }; 3081fbfb8031SShannon Nelson 3082fbfb8031SShannon Nelson /* Deprecate */ 3083fbfb8031SShannon Nelson struct ionic_identity { 3084fbfb8031SShannon Nelson union ionic_drv_identity drv; 3085fbfb8031SShannon Nelson union ionic_dev_identity dev; 3086fbfb8031SShannon Nelson union ionic_lif_identity lif; 3087fbfb8031SShannon Nelson union ionic_port_identity port; 3088fbfb8031SShannon Nelson union ionic_qos_identity qos; 3089c4e7a75aSShannon Nelson union ionic_q_identity txq; 3090fbfb8031SShannon Nelson }; 3091fbfb8031SShannon Nelson 3092fbfb8031SShannon Nelson #endif /* _IONIC_IF_H_ */ 3093