1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3 
4 #ifndef _IONIC_DEV_H_
5 #define _IONIC_DEV_H_
6 
7 #include <linux/atomic.h>
8 #include <linux/mutex.h>
9 #include <linux/workqueue.h>
10 
11 #include "ionic_if.h"
12 #include "ionic_regs.h"
13 
14 #define IONIC_MAX_TX_DESC		8192
15 #define IONIC_MAX_RX_DESC		16384
16 #define IONIC_MIN_TXRX_DESC		64
17 #define IONIC_DEF_TXRX_DESC		4096
18 #define IONIC_RX_FILL_THRESHOLD		16
19 #define IONIC_RX_FILL_DIV		8
20 #define IONIC_LIFS_MAX			1024
21 #define IONIC_WATCHDOG_SECS		5
22 #define IONIC_ITR_COAL_USEC_DEFAULT	64
23 
24 #define IONIC_DEV_CMD_REG_VERSION	1
25 #define IONIC_DEV_INFO_REG_COUNT	32
26 #define IONIC_DEV_CMD_REG_COUNT		32
27 
28 #define IONIC_NAPI_DEADLINE		(HZ / 200)	/* 5ms */
29 #define IONIC_ADMIN_DOORBELL_DEADLINE	(HZ / 2)	/* 500ms */
30 #define IONIC_TX_DOORBELL_DEADLINE	(HZ / 100)	/* 10ms */
31 #define IONIC_RX_MIN_DOORBELL_DEADLINE	(HZ / 100)	/* 10ms */
32 #define IONIC_RX_MAX_DOORBELL_DEADLINE	(HZ * 5)	/* 5s */
33 
34 struct ionic_dev_bar {
35 	void __iomem *vaddr;
36 	phys_addr_t bus_addr;
37 	unsigned long len;
38 	int res_index;
39 };
40 
41 #ifndef __CHECKER__
42 /* Registers */
43 static_assert(sizeof(struct ionic_intr) == 32);
44 
45 static_assert(sizeof(struct ionic_doorbell) == 8);
46 static_assert(sizeof(struct ionic_intr_status) == 8);
47 static_assert(sizeof(union ionic_dev_regs) == 4096);
48 static_assert(sizeof(union ionic_dev_info_regs) == 2048);
49 static_assert(sizeof(union ionic_dev_cmd_regs) == 2048);
50 static_assert(sizeof(struct ionic_lif_stats) == 1024);
51 
52 static_assert(sizeof(struct ionic_admin_cmd) == 64);
53 static_assert(sizeof(struct ionic_admin_comp) == 16);
54 static_assert(sizeof(struct ionic_nop_cmd) == 64);
55 static_assert(sizeof(struct ionic_nop_comp) == 16);
56 
57 /* Device commands */
58 static_assert(sizeof(struct ionic_dev_identify_cmd) == 64);
59 static_assert(sizeof(struct ionic_dev_identify_comp) == 16);
60 static_assert(sizeof(struct ionic_dev_init_cmd) == 64);
61 static_assert(sizeof(struct ionic_dev_init_comp) == 16);
62 static_assert(sizeof(struct ionic_dev_reset_cmd) == 64);
63 static_assert(sizeof(struct ionic_dev_reset_comp) == 16);
64 static_assert(sizeof(struct ionic_dev_getattr_cmd) == 64);
65 static_assert(sizeof(struct ionic_dev_getattr_comp) == 16);
66 static_assert(sizeof(struct ionic_dev_setattr_cmd) == 64);
67 static_assert(sizeof(struct ionic_dev_setattr_comp) == 16);
68 static_assert(sizeof(struct ionic_lif_setphc_cmd) == 64);
69 
70 /* Port commands */
71 static_assert(sizeof(struct ionic_port_identify_cmd) == 64);
72 static_assert(sizeof(struct ionic_port_identify_comp) == 16);
73 static_assert(sizeof(struct ionic_port_init_cmd) == 64);
74 static_assert(sizeof(struct ionic_port_init_comp) == 16);
75 static_assert(sizeof(struct ionic_port_reset_cmd) == 64);
76 static_assert(sizeof(struct ionic_port_reset_comp) == 16);
77 static_assert(sizeof(struct ionic_port_getattr_cmd) == 64);
78 static_assert(sizeof(struct ionic_port_getattr_comp) == 16);
79 static_assert(sizeof(struct ionic_port_setattr_cmd) == 64);
80 static_assert(sizeof(struct ionic_port_setattr_comp) == 16);
81 
82 /* LIF commands */
83 static_assert(sizeof(struct ionic_lif_init_cmd) == 64);
84 static_assert(sizeof(struct ionic_lif_init_comp) == 16);
85 static_assert(sizeof(struct ionic_lif_reset_cmd) == 64);
86 static_assert(sizeof(ionic_lif_reset_comp) == 16);
87 static_assert(sizeof(struct ionic_lif_getattr_cmd) == 64);
88 static_assert(sizeof(struct ionic_lif_getattr_comp) == 16);
89 static_assert(sizeof(struct ionic_lif_setattr_cmd) == 64);
90 static_assert(sizeof(struct ionic_lif_setattr_comp) == 16);
91 
92 static_assert(sizeof(struct ionic_q_init_cmd) == 64);
93 static_assert(sizeof(struct ionic_q_init_comp) == 16);
94 static_assert(sizeof(struct ionic_q_control_cmd) == 64);
95 static_assert(sizeof(ionic_q_control_comp) == 16);
96 static_assert(sizeof(struct ionic_q_identify_cmd) == 64);
97 static_assert(sizeof(struct ionic_q_identify_comp) == 16);
98 
99 static_assert(sizeof(struct ionic_rx_mode_set_cmd) == 64);
100 static_assert(sizeof(ionic_rx_mode_set_comp) == 16);
101 static_assert(sizeof(struct ionic_rx_filter_add_cmd) == 64);
102 static_assert(sizeof(struct ionic_rx_filter_add_comp) == 16);
103 static_assert(sizeof(struct ionic_rx_filter_del_cmd) == 64);
104 static_assert(sizeof(ionic_rx_filter_del_comp) == 16);
105 
106 /* RDMA commands */
107 static_assert(sizeof(struct ionic_rdma_reset_cmd) == 64);
108 static_assert(sizeof(struct ionic_rdma_queue_cmd) == 64);
109 
110 /* Events */
111 static_assert(sizeof(struct ionic_notifyq_cmd) == 4);
112 static_assert(sizeof(union ionic_notifyq_comp) == 64);
113 static_assert(sizeof(struct ionic_notifyq_event) == 64);
114 static_assert(sizeof(struct ionic_link_change_event) == 64);
115 static_assert(sizeof(struct ionic_reset_event) == 64);
116 static_assert(sizeof(struct ionic_heartbeat_event) == 64);
117 static_assert(sizeof(struct ionic_log_event) == 64);
118 
119 /* I/O */
120 static_assert(sizeof(struct ionic_txq_desc) == 16);
121 static_assert(sizeof(struct ionic_txq_sg_desc) == 128);
122 static_assert(sizeof(struct ionic_txq_comp) == 16);
123 
124 static_assert(sizeof(struct ionic_rxq_desc) == 16);
125 static_assert(sizeof(struct ionic_rxq_sg_desc) == 128);
126 static_assert(sizeof(struct ionic_rxq_comp) == 16);
127 
128 /* SR/IOV */
129 static_assert(sizeof(struct ionic_vf_setattr_cmd) == 64);
130 static_assert(sizeof(struct ionic_vf_setattr_comp) == 16);
131 static_assert(sizeof(struct ionic_vf_getattr_cmd) == 64);
132 static_assert(sizeof(struct ionic_vf_getattr_comp) == 16);
133 static_assert(sizeof(struct ionic_vf_ctrl_cmd) == 64);
134 static_assert(sizeof(struct ionic_vf_ctrl_comp) == 16);
135 #endif /* __CHECKER__ */
136 
137 struct ionic_devinfo {
138 	u8 asic_type;
139 	u8 asic_rev;
140 	char fw_version[IONIC_DEVINFO_FWVERS_BUFLEN + 1];
141 	char serial_num[IONIC_DEVINFO_SERIAL_BUFLEN + 1];
142 };
143 
144 struct ionic_dev {
145 	union ionic_dev_info_regs __iomem *dev_info_regs;
146 	union ionic_dev_cmd_regs __iomem *dev_cmd_regs;
147 	struct ionic_hwstamp_regs __iomem *hwstamp_regs;
148 
149 	atomic_long_t last_check_time;
150 	unsigned long last_hb_time;
151 	u32 last_fw_hb;
152 	bool fw_hb_ready;
153 	bool fw_status_ready;
154 	u8 fw_generation;
155 
156 	u64 __iomem *db_pages;
157 	dma_addr_t phy_db_pages;
158 
159 	struct ionic_intr __iomem *intr_ctrl;
160 	u64 __iomem *intr_status;
161 
162 	struct mutex cmb_inuse_lock; /* for cmb_inuse */
163 	unsigned long *cmb_inuse;
164 	dma_addr_t phy_cmb_pages;
165 	u32 cmb_npages;
166 
167 	u32 port_info_sz;
168 	struct ionic_port_info *port_info;
169 	dma_addr_t port_info_pa;
170 
171 	struct ionic_devinfo dev_info;
172 };
173 
174 struct ionic_cq_info {
175 	union {
176 		void *cq_desc;
177 		struct ionic_admin_comp *admincq;
178 		struct ionic_notifyq_event *notifyq;
179 	};
180 };
181 
182 struct ionic_queue;
183 struct ionic_qcq;
184 struct ionic_desc_info;
185 
186 typedef void (*ionic_desc_cb)(struct ionic_queue *q,
187 			      struct ionic_desc_info *desc_info,
188 			      struct ionic_cq_info *cq_info, void *cb_arg);
189 
190 #define IONIC_MAX_BUF_LEN			((u16)-1)
191 #define IONIC_PAGE_SIZE				PAGE_SIZE
192 #define IONIC_PAGE_SPLIT_SZ			(PAGE_SIZE / 2)
193 #define IONIC_PAGE_GFP_MASK			(GFP_ATOMIC | __GFP_NOWARN |\
194 						 __GFP_COMP | __GFP_MEMALLOC)
195 
196 struct ionic_buf_info {
197 	struct page *page;
198 	dma_addr_t dma_addr;
199 	u32 page_offset;
200 	u32 len;
201 };
202 
203 #define IONIC_MAX_FRAGS			(1 + IONIC_TX_MAX_SG_ELEMS_V1)
204 
205 struct ionic_desc_info {
206 	union {
207 		void *desc;
208 		struct ionic_txq_desc *txq_desc;
209 		struct ionic_rxq_desc *rxq_desc;
210 		struct ionic_admin_cmd *adminq_desc;
211 	};
212 	void __iomem *cmb_desc;
213 	union {
214 		void *sg_desc;
215 		struct ionic_txq_sg_desc *txq_sg_desc;
216 		struct ionic_rxq_sg_desc *rxq_sgl_desc;
217 	};
218 	unsigned int bytes;
219 	unsigned int nbufs;
220 	struct ionic_buf_info bufs[IONIC_MAX_FRAGS];
221 	ionic_desc_cb cb;
222 	void *cb_arg;
223 };
224 
225 #define IONIC_QUEUE_NAME_MAX_SZ		16
226 
227 struct ionic_queue {
228 	struct device *dev;
229 	struct ionic_lif *lif;
230 	struct ionic_desc_info *info;
231 	u64 dbval;
232 	unsigned long dbell_deadline;
233 	unsigned long dbell_jiffies;
234 	u16 head_idx;
235 	u16 tail_idx;
236 	unsigned int index;
237 	unsigned int num_descs;
238 	unsigned int max_sg_elems;
239 	u64 features;
240 	u64 drop;
241 	struct ionic_dev *idev;
242 	unsigned int type;
243 	unsigned int hw_index;
244 	unsigned int hw_type;
245 	union {
246 		void *base;
247 		struct ionic_txq_desc *txq;
248 		struct ionic_rxq_desc *rxq;
249 		struct ionic_admin_cmd *adminq;
250 	};
251 	void __iomem *cmb_base;
252 	union {
253 		void *sg_base;
254 		struct ionic_txq_sg_desc *txq_sgl;
255 		struct ionic_rxq_sg_desc *rxq_sgl;
256 	};
257 	dma_addr_t base_pa;
258 	dma_addr_t cmb_base_pa;
259 	dma_addr_t sg_base_pa;
260 	unsigned int desc_size;
261 	unsigned int sg_desc_size;
262 	unsigned int pid;
263 	char name[IONIC_QUEUE_NAME_MAX_SZ];
264 } ____cacheline_aligned_in_smp;
265 
266 #define IONIC_INTR_INDEX_NOT_ASSIGNED	-1
267 #define IONIC_INTR_NAME_MAX_SZ		32
268 
269 struct ionic_intr_info {
270 	char name[IONIC_INTR_NAME_MAX_SZ];
271 	unsigned int index;
272 	unsigned int vector;
273 	u64 rearm_count;
274 	unsigned int cpu;
275 	cpumask_t affinity_mask;
276 	u32 dim_coal_hw;
277 };
278 
279 struct ionic_cq {
280 	struct ionic_lif *lif;
281 	struct ionic_cq_info *info;
282 	struct ionic_queue *bound_q;
283 	struct ionic_intr_info *bound_intr;
284 	u16 tail_idx;
285 	bool done_color;
286 	unsigned int num_descs;
287 	unsigned int desc_size;
288 	void *base;
289 	dma_addr_t base_pa;
290 } ____cacheline_aligned_in_smp;
291 
292 struct ionic;
293 
294 static inline void ionic_intr_init(struct ionic_dev *idev,
295 				   struct ionic_intr_info *intr,
296 				   unsigned long index)
297 {
298 	ionic_intr_clean(idev->intr_ctrl, index);
299 	intr->index = index;
300 }
301 
302 static inline unsigned int ionic_q_space_avail(struct ionic_queue *q)
303 {
304 	unsigned int avail = q->tail_idx;
305 
306 	if (q->head_idx >= avail)
307 		avail += q->num_descs - q->head_idx - 1;
308 	else
309 		avail -= q->head_idx + 1;
310 
311 	return avail;
312 }
313 
314 static inline bool ionic_q_has_space(struct ionic_queue *q, unsigned int want)
315 {
316 	return ionic_q_space_avail(q) >= want;
317 }
318 
319 void ionic_init_devinfo(struct ionic *ionic);
320 int ionic_dev_setup(struct ionic *ionic);
321 void ionic_dev_teardown(struct ionic *ionic);
322 
323 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);
324 u8 ionic_dev_cmd_status(struct ionic_dev *idev);
325 bool ionic_dev_cmd_done(struct ionic_dev *idev);
326 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp);
327 
328 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver);
329 void ionic_dev_cmd_init(struct ionic_dev *idev);
330 void ionic_dev_cmd_reset(struct ionic_dev *idev);
331 
332 void ionic_dev_cmd_port_identify(struct ionic_dev *idev);
333 void ionic_dev_cmd_port_init(struct ionic_dev *idev);
334 void ionic_dev_cmd_port_reset(struct ionic_dev *idev);
335 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state);
336 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed);
337 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable);
338 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type);
339 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type);
340 
341 int ionic_set_vf_config(struct ionic *ionic, int vf,
342 			struct ionic_vf_setattr_cmd *vfc);
343 int ionic_dev_cmd_vf_getattr(struct ionic *ionic, int vf, u8 attr,
344 			     struct ionic_vf_getattr_comp *comp);
345 void ionic_dev_cmd_queue_identify(struct ionic_dev *idev,
346 				  u16 lif_type, u8 qtype, u8 qver);
347 void ionic_vf_start(struct ionic *ionic);
348 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver);
349 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
350 			    dma_addr_t addr);
351 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index);
352 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
353 			       u16 lif_index, u16 intr_index);
354 
355 int ionic_db_page_num(struct ionic_lif *lif, int pid);
356 
357 int ionic_get_cmb(struct ionic_lif *lif, u32 *pgid, phys_addr_t *pgaddr, int order);
358 void ionic_put_cmb(struct ionic_lif *lif, u32 pgid, int order);
359 
360 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
361 		  struct ionic_intr_info *intr,
362 		  unsigned int num_descs, size_t desc_size);
363 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa);
364 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q);
365 typedef bool (*ionic_cq_cb)(struct ionic_cq *cq, struct ionic_cq_info *cq_info);
366 typedef void (*ionic_cq_done_cb)(void *done_arg);
367 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
368 			      ionic_cq_cb cb, ionic_cq_done_cb done_cb,
369 			      void *done_arg);
370 
371 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
372 		 struct ionic_queue *q, unsigned int index, const char *name,
373 		 unsigned int num_descs, size_t desc_size,
374 		 size_t sg_desc_size, unsigned int pid);
375 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
376 void ionic_q_cmb_map(struct ionic_queue *q, void __iomem *base, dma_addr_t base_pa);
377 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa);
378 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
379 		  void *cb_arg);
380 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
381 		     unsigned int stop_index);
382 int ionic_heartbeat_check(struct ionic *ionic);
383 bool ionic_is_fw_running(struct ionic_dev *idev);
384 
385 bool ionic_adminq_poke_doorbell(struct ionic_queue *q);
386 bool ionic_txq_poke_doorbell(struct ionic_queue *q);
387 bool ionic_rxq_poke_doorbell(struct ionic_queue *q);
388 
389 #endif /* _IONIC_DEV_H_ */
390