1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/kernel.h> 5 #include <linux/types.h> 6 #include <linux/errno.h> 7 #include <linux/io.h> 8 #include <linux/slab.h> 9 #include <linux/etherdevice.h> 10 #include "ionic.h" 11 #include "ionic_dev.h" 12 #include "ionic_lif.h" 13 14 static void ionic_watchdog_cb(struct timer_list *t) 15 { 16 struct ionic *ionic = from_timer(ionic, t, watchdog_timer); 17 18 mod_timer(&ionic->watchdog_timer, 19 round_jiffies(jiffies + ionic->watchdog_period)); 20 21 ionic_heartbeat_check(ionic); 22 } 23 24 void ionic_init_devinfo(struct ionic *ionic) 25 { 26 struct ionic_dev *idev = &ionic->idev; 27 28 idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type); 29 idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev); 30 31 memcpy_fromio(idev->dev_info.fw_version, 32 idev->dev_info_regs->fw_version, 33 IONIC_DEVINFO_FWVERS_BUFLEN); 34 35 memcpy_fromio(idev->dev_info.serial_num, 36 idev->dev_info_regs->serial_num, 37 IONIC_DEVINFO_SERIAL_BUFLEN); 38 39 idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0; 40 idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0; 41 42 dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version); 43 } 44 45 int ionic_dev_setup(struct ionic *ionic) 46 { 47 struct ionic_dev_bar *bar = ionic->bars; 48 unsigned int num_bars = ionic->num_bars; 49 struct ionic_dev *idev = &ionic->idev; 50 struct device *dev = ionic->dev; 51 u32 sig; 52 53 /* BAR0: dev_cmd and interrupts */ 54 if (num_bars < 1) { 55 dev_err(dev, "No bars found, aborting\n"); 56 return -EFAULT; 57 } 58 59 if (bar->len < IONIC_BAR0_SIZE) { 60 dev_err(dev, "Resource bar size %lu too small, aborting\n", 61 bar->len); 62 return -EFAULT; 63 } 64 65 idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET; 66 idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET; 67 idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET; 68 idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET; 69 70 sig = ioread32(&idev->dev_info_regs->signature); 71 if (sig != IONIC_DEV_INFO_SIGNATURE) { 72 dev_err(dev, "Incompatible firmware signature %x", sig); 73 return -EFAULT; 74 } 75 76 ionic_init_devinfo(ionic); 77 78 /* BAR1: doorbells */ 79 bar++; 80 if (num_bars < 2) { 81 dev_err(dev, "Doorbell bar missing, aborting\n"); 82 return -EFAULT; 83 } 84 85 timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0); 86 ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ; 87 mod_timer(&ionic->watchdog_timer, 88 round_jiffies(jiffies + ionic->watchdog_period)); 89 90 idev->db_pages = bar->vaddr; 91 idev->phy_db_pages = bar->bus_addr; 92 93 return 0; 94 } 95 96 void ionic_dev_teardown(struct ionic *ionic) 97 { 98 del_timer_sync(&ionic->watchdog_timer); 99 } 100 101 /* Devcmd Interface */ 102 int ionic_heartbeat_check(struct ionic *ionic) 103 { 104 struct ionic_dev *idev = &ionic->idev; 105 unsigned long hb_time; 106 u32 fw_status; 107 u32 hb; 108 109 /* wait a little more than one second before testing again */ 110 hb_time = jiffies; 111 if (time_before(hb_time, (idev->last_hb_time + ionic->watchdog_period))) 112 return 0; 113 114 /* firmware is useful only if fw_status is non-zero */ 115 fw_status = ioread32(&idev->dev_info_regs->fw_status); 116 if (!fw_status) 117 return -ENXIO; 118 119 /* early FW has no heartbeat, else FW will return non-zero */ 120 hb = ioread32(&idev->dev_info_regs->fw_heartbeat); 121 if (!hb) 122 return 0; 123 124 /* are we stalled? */ 125 if (hb == idev->last_hb) { 126 /* only complain once for each stall seen */ 127 if (idev->last_hb_time != 1) { 128 dev_info(ionic->dev, "FW heartbeat stalled at %d\n", 129 idev->last_hb); 130 idev->last_hb_time = 1; 131 } 132 133 return -ENXIO; 134 } 135 136 if (idev->last_hb_time == 1) 137 dev_info(ionic->dev, "FW heartbeat restored at %d\n", hb); 138 139 idev->last_hb = hb; 140 idev->last_hb_time = hb_time; 141 142 return 0; 143 } 144 145 u8 ionic_dev_cmd_status(struct ionic_dev *idev) 146 { 147 return ioread8(&idev->dev_cmd_regs->comp.comp.status); 148 } 149 150 bool ionic_dev_cmd_done(struct ionic_dev *idev) 151 { 152 return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE; 153 } 154 155 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp) 156 { 157 memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp)); 158 } 159 160 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd) 161 { 162 memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd)); 163 iowrite32(0, &idev->dev_cmd_regs->done); 164 iowrite32(1, &idev->dev_cmd_regs->doorbell); 165 } 166 167 /* Device commands */ 168 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver) 169 { 170 union ionic_dev_cmd cmd = { 171 .identify.opcode = IONIC_CMD_IDENTIFY, 172 .identify.ver = ver, 173 }; 174 175 ionic_dev_cmd_go(idev, &cmd); 176 } 177 178 void ionic_dev_cmd_init(struct ionic_dev *idev) 179 { 180 union ionic_dev_cmd cmd = { 181 .init.opcode = IONIC_CMD_INIT, 182 .init.type = 0, 183 }; 184 185 ionic_dev_cmd_go(idev, &cmd); 186 } 187 188 void ionic_dev_cmd_reset(struct ionic_dev *idev) 189 { 190 union ionic_dev_cmd cmd = { 191 .reset.opcode = IONIC_CMD_RESET, 192 }; 193 194 ionic_dev_cmd_go(idev, &cmd); 195 } 196 197 /* Port commands */ 198 void ionic_dev_cmd_port_identify(struct ionic_dev *idev) 199 { 200 union ionic_dev_cmd cmd = { 201 .port_init.opcode = IONIC_CMD_PORT_IDENTIFY, 202 .port_init.index = 0, 203 }; 204 205 ionic_dev_cmd_go(idev, &cmd); 206 } 207 208 void ionic_dev_cmd_port_init(struct ionic_dev *idev) 209 { 210 union ionic_dev_cmd cmd = { 211 .port_init.opcode = IONIC_CMD_PORT_INIT, 212 .port_init.index = 0, 213 .port_init.info_pa = cpu_to_le64(idev->port_info_pa), 214 }; 215 216 ionic_dev_cmd_go(idev, &cmd); 217 } 218 219 void ionic_dev_cmd_port_reset(struct ionic_dev *idev) 220 { 221 union ionic_dev_cmd cmd = { 222 .port_reset.opcode = IONIC_CMD_PORT_RESET, 223 .port_reset.index = 0, 224 }; 225 226 ionic_dev_cmd_go(idev, &cmd); 227 } 228 229 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state) 230 { 231 union ionic_dev_cmd cmd = { 232 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 233 .port_setattr.index = 0, 234 .port_setattr.attr = IONIC_PORT_ATTR_STATE, 235 .port_setattr.state = state, 236 }; 237 238 ionic_dev_cmd_go(idev, &cmd); 239 } 240 241 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed) 242 { 243 union ionic_dev_cmd cmd = { 244 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 245 .port_setattr.index = 0, 246 .port_setattr.attr = IONIC_PORT_ATTR_SPEED, 247 .port_setattr.speed = cpu_to_le32(speed), 248 }; 249 250 ionic_dev_cmd_go(idev, &cmd); 251 } 252 253 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable) 254 { 255 union ionic_dev_cmd cmd = { 256 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 257 .port_setattr.index = 0, 258 .port_setattr.attr = IONIC_PORT_ATTR_AUTONEG, 259 .port_setattr.an_enable = an_enable, 260 }; 261 262 ionic_dev_cmd_go(idev, &cmd); 263 } 264 265 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type) 266 { 267 union ionic_dev_cmd cmd = { 268 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 269 .port_setattr.index = 0, 270 .port_setattr.attr = IONIC_PORT_ATTR_FEC, 271 .port_setattr.fec_type = fec_type, 272 }; 273 274 ionic_dev_cmd_go(idev, &cmd); 275 } 276 277 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type) 278 { 279 union ionic_dev_cmd cmd = { 280 .port_setattr.opcode = IONIC_CMD_PORT_SETATTR, 281 .port_setattr.index = 0, 282 .port_setattr.attr = IONIC_PORT_ATTR_PAUSE, 283 .port_setattr.pause_type = pause_type, 284 }; 285 286 ionic_dev_cmd_go(idev, &cmd); 287 } 288 289 /* VF commands */ 290 int ionic_set_vf_config(struct ionic *ionic, int vf, u8 attr, u8 *data) 291 { 292 union ionic_dev_cmd cmd = { 293 .vf_setattr.opcode = IONIC_CMD_VF_SETATTR, 294 .vf_setattr.attr = attr, 295 .vf_setattr.vf_index = vf, 296 }; 297 int err; 298 299 switch (attr) { 300 case IONIC_VF_ATTR_SPOOFCHK: 301 cmd.vf_setattr.spoofchk = *data; 302 dev_dbg(ionic->dev, "%s: vf %d spoof %d\n", 303 __func__, vf, *data); 304 break; 305 case IONIC_VF_ATTR_TRUST: 306 cmd.vf_setattr.trust = *data; 307 dev_dbg(ionic->dev, "%s: vf %d trust %d\n", 308 __func__, vf, *data); 309 break; 310 case IONIC_VF_ATTR_LINKSTATE: 311 cmd.vf_setattr.linkstate = *data; 312 dev_dbg(ionic->dev, "%s: vf %d linkstate %d\n", 313 __func__, vf, *data); 314 break; 315 case IONIC_VF_ATTR_MAC: 316 ether_addr_copy(cmd.vf_setattr.macaddr, data); 317 dev_dbg(ionic->dev, "%s: vf %d macaddr %pM\n", 318 __func__, vf, data); 319 break; 320 case IONIC_VF_ATTR_VLAN: 321 cmd.vf_setattr.vlanid = cpu_to_le16(*(u16 *)data); 322 dev_dbg(ionic->dev, "%s: vf %d vlan %d\n", 323 __func__, vf, *(u16 *)data); 324 break; 325 case IONIC_VF_ATTR_RATE: 326 cmd.vf_setattr.maxrate = cpu_to_le32(*(u32 *)data); 327 dev_dbg(ionic->dev, "%s: vf %d maxrate %d\n", 328 __func__, vf, *(u32 *)data); 329 break; 330 case IONIC_VF_ATTR_STATSADDR: 331 cmd.vf_setattr.stats_pa = cpu_to_le64(*(u64 *)data); 332 dev_dbg(ionic->dev, "%s: vf %d stats_pa 0x%08llx\n", 333 __func__, vf, *(u64 *)data); 334 break; 335 default: 336 return -EINVAL; 337 } 338 339 mutex_lock(&ionic->dev_cmd_lock); 340 ionic_dev_cmd_go(&ionic->idev, &cmd); 341 err = ionic_dev_cmd_wait(ionic, DEVCMD_TIMEOUT); 342 mutex_unlock(&ionic->dev_cmd_lock); 343 344 return err; 345 } 346 347 /* LIF commands */ 348 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver) 349 { 350 union ionic_dev_cmd cmd = { 351 .lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY, 352 .lif_identify.type = type, 353 .lif_identify.ver = ver, 354 }; 355 356 ionic_dev_cmd_go(idev, &cmd); 357 } 358 359 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index, 360 dma_addr_t info_pa) 361 { 362 union ionic_dev_cmd cmd = { 363 .lif_init.opcode = IONIC_CMD_LIF_INIT, 364 .lif_init.index = cpu_to_le16(lif_index), 365 .lif_init.info_pa = cpu_to_le64(info_pa), 366 }; 367 368 ionic_dev_cmd_go(idev, &cmd); 369 } 370 371 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index) 372 { 373 union ionic_dev_cmd cmd = { 374 .lif_init.opcode = IONIC_CMD_LIF_RESET, 375 .lif_init.index = cpu_to_le16(lif_index), 376 }; 377 378 ionic_dev_cmd_go(idev, &cmd); 379 } 380 381 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq, 382 u16 lif_index, u16 intr_index) 383 { 384 struct ionic_queue *q = &qcq->q; 385 struct ionic_cq *cq = &qcq->cq; 386 387 union ionic_dev_cmd cmd = { 388 .q_init.opcode = IONIC_CMD_Q_INIT, 389 .q_init.lif_index = cpu_to_le16(lif_index), 390 .q_init.type = q->type, 391 .q_init.index = cpu_to_le32(q->index), 392 .q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ | 393 IONIC_QINIT_F_ENA), 394 .q_init.pid = cpu_to_le16(q->pid), 395 .q_init.intr_index = cpu_to_le16(intr_index), 396 .q_init.ring_size = ilog2(q->num_descs), 397 .q_init.ring_base = cpu_to_le64(q->base_pa), 398 .q_init.cq_ring_base = cpu_to_le64(cq->base_pa), 399 }; 400 401 ionic_dev_cmd_go(idev, &cmd); 402 } 403 404 int ionic_db_page_num(struct ionic_lif *lif, int pid) 405 { 406 return (lif->hw_index * lif->dbid_count) + pid; 407 } 408 409 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq, 410 struct ionic_intr_info *intr, 411 unsigned int num_descs, size_t desc_size) 412 { 413 struct ionic_cq_info *cur; 414 unsigned int ring_size; 415 unsigned int i; 416 417 if (desc_size == 0 || !is_power_of_2(num_descs)) 418 return -EINVAL; 419 420 ring_size = ilog2(num_descs); 421 if (ring_size < 2 || ring_size > 16) 422 return -EINVAL; 423 424 cq->lif = lif; 425 cq->bound_intr = intr; 426 cq->num_descs = num_descs; 427 cq->desc_size = desc_size; 428 cq->tail = cq->info; 429 cq->done_color = 1; 430 431 cur = cq->info; 432 433 for (i = 0; i < num_descs; i++) { 434 if (i + 1 == num_descs) { 435 cur->next = cq->info; 436 cur->last = true; 437 } else { 438 cur->next = cur + 1; 439 } 440 cur->index = i; 441 cur++; 442 } 443 444 return 0; 445 } 446 447 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa) 448 { 449 struct ionic_cq_info *cur; 450 unsigned int i; 451 452 cq->base = base; 453 cq->base_pa = base_pa; 454 455 for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++) 456 cur->cq_desc = base + (i * cq->desc_size); 457 } 458 459 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q) 460 { 461 cq->bound_q = q; 462 } 463 464 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do, 465 ionic_cq_cb cb, ionic_cq_done_cb done_cb, 466 void *done_arg) 467 { 468 unsigned int work_done = 0; 469 470 if (work_to_do == 0) 471 return 0; 472 473 while (cb(cq, cq->tail)) { 474 if (cq->tail->last) 475 cq->done_color = !cq->done_color; 476 cq->tail = cq->tail->next; 477 DEBUG_STATS_CQE_CNT(cq); 478 479 if (++work_done >= work_to_do) 480 break; 481 } 482 483 if (work_done && done_cb) 484 done_cb(done_arg); 485 486 return work_done; 487 } 488 489 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev, 490 struct ionic_queue *q, unsigned int index, const char *name, 491 unsigned int num_descs, size_t desc_size, 492 size_t sg_desc_size, unsigned int pid) 493 { 494 struct ionic_desc_info *cur; 495 unsigned int ring_size; 496 unsigned int i; 497 498 if (desc_size == 0 || !is_power_of_2(num_descs)) 499 return -EINVAL; 500 501 ring_size = ilog2(num_descs); 502 if (ring_size < 2 || ring_size > 16) 503 return -EINVAL; 504 505 q->lif = lif; 506 q->idev = idev; 507 q->index = index; 508 q->num_descs = num_descs; 509 q->desc_size = desc_size; 510 q->sg_desc_size = sg_desc_size; 511 q->tail = q->info; 512 q->head = q->tail; 513 q->pid = pid; 514 515 snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index); 516 517 cur = q->info; 518 519 for (i = 0; i < num_descs; i++) { 520 if (i + 1 == num_descs) 521 cur->next = q->info; 522 else 523 cur->next = cur + 1; 524 cur->index = i; 525 cur->left = num_descs - i; 526 cur++; 527 } 528 529 return 0; 530 } 531 532 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 533 { 534 struct ionic_desc_info *cur; 535 unsigned int i; 536 537 q->base = base; 538 q->base_pa = base_pa; 539 540 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 541 cur->desc = base + (i * q->desc_size); 542 } 543 544 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa) 545 { 546 struct ionic_desc_info *cur; 547 unsigned int i; 548 549 q->sg_base = base; 550 q->sg_base_pa = base_pa; 551 552 for (i = 0, cur = q->info; i < q->num_descs; i++, cur++) 553 cur->sg_desc = base + (i * q->sg_desc_size); 554 } 555 556 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb, 557 void *cb_arg) 558 { 559 struct device *dev = q->lif->ionic->dev; 560 struct ionic_lif *lif = q->lif; 561 562 q->head->cb = cb; 563 q->head->cb_arg = cb_arg; 564 q->head = q->head->next; 565 566 dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n", 567 q->lif->index, q->name, q->hw_type, q->hw_index, 568 q->head->index, ring_doorbell); 569 570 if (ring_doorbell) 571 ionic_dbell_ring(lif->kern_dbpage, q->hw_type, 572 q->dbval | q->head->index); 573 } 574 575 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos) 576 { 577 unsigned int mask, tail, head; 578 579 mask = q->num_descs - 1; 580 tail = q->tail->index; 581 head = q->head->index; 582 583 return ((pos - tail) & mask) < ((head - tail) & mask); 584 } 585 586 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info, 587 unsigned int stop_index) 588 { 589 struct ionic_desc_info *desc_info; 590 ionic_desc_cb cb; 591 void *cb_arg; 592 593 /* check for empty queue */ 594 if (q->tail->index == q->head->index) 595 return; 596 597 /* stop index must be for a descriptor that is not yet completed */ 598 if (unlikely(!ionic_q_is_posted(q, stop_index))) 599 dev_err(q->lif->ionic->dev, 600 "ionic stop is not posted %s stop %u tail %u head %u\n", 601 q->name, stop_index, q->tail->index, q->head->index); 602 603 do { 604 desc_info = q->tail; 605 q->tail = desc_info->next; 606 607 cb = desc_info->cb; 608 cb_arg = desc_info->cb_arg; 609 610 desc_info->cb = NULL; 611 desc_info->cb_arg = NULL; 612 613 if (cb) 614 cb(q, desc_info, cq_info, cb_arg); 615 } while (desc_info->index != stop_index); 616 } 617