1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */
3 
4 #include <linux/kernel.h>
5 #include <linux/types.h>
6 #include <linux/errno.h>
7 #include <linux/io.h>
8 #include <linux/slab.h>
9 #include <linux/etherdevice.h>
10 #include "ionic.h"
11 #include "ionic_dev.h"
12 #include "ionic_lif.h"
13 
14 static void ionic_watchdog_cb(struct timer_list *t)
15 {
16 	struct ionic *ionic = from_timer(ionic, t, watchdog_timer);
17 
18 	mod_timer(&ionic->watchdog_timer,
19 		  round_jiffies(jiffies + ionic->watchdog_period));
20 
21 	ionic_heartbeat_check(ionic);
22 }
23 
24 void ionic_init_devinfo(struct ionic *ionic)
25 {
26 	struct ionic_dev *idev = &ionic->idev;
27 
28 	idev->dev_info.asic_type = ioread8(&idev->dev_info_regs->asic_type);
29 	idev->dev_info.asic_rev = ioread8(&idev->dev_info_regs->asic_rev);
30 
31 	memcpy_fromio(idev->dev_info.fw_version,
32 		      idev->dev_info_regs->fw_version,
33 		      IONIC_DEVINFO_FWVERS_BUFLEN);
34 
35 	memcpy_fromio(idev->dev_info.serial_num,
36 		      idev->dev_info_regs->serial_num,
37 		      IONIC_DEVINFO_SERIAL_BUFLEN);
38 
39 	idev->dev_info.fw_version[IONIC_DEVINFO_FWVERS_BUFLEN] = 0;
40 	idev->dev_info.serial_num[IONIC_DEVINFO_SERIAL_BUFLEN] = 0;
41 
42 	dev_dbg(ionic->dev, "fw_version %s\n", idev->dev_info.fw_version);
43 }
44 
45 int ionic_dev_setup(struct ionic *ionic)
46 {
47 	struct ionic_dev_bar *bar = ionic->bars;
48 	unsigned int num_bars = ionic->num_bars;
49 	struct ionic_dev *idev = &ionic->idev;
50 	struct device *dev = ionic->dev;
51 	u32 sig;
52 
53 	/* BAR0: dev_cmd and interrupts */
54 	if (num_bars < 1) {
55 		dev_err(dev, "No bars found, aborting\n");
56 		return -EFAULT;
57 	}
58 
59 	if (bar->len < IONIC_BAR0_SIZE) {
60 		dev_err(dev, "Resource bar size %lu too small, aborting\n",
61 			bar->len);
62 		return -EFAULT;
63 	}
64 
65 	idev->dev_info_regs = bar->vaddr + IONIC_BAR0_DEV_INFO_REGS_OFFSET;
66 	idev->dev_cmd_regs = bar->vaddr + IONIC_BAR0_DEV_CMD_REGS_OFFSET;
67 	idev->intr_status = bar->vaddr + IONIC_BAR0_INTR_STATUS_OFFSET;
68 	idev->intr_ctrl = bar->vaddr + IONIC_BAR0_INTR_CTRL_OFFSET;
69 
70 	sig = ioread32(&idev->dev_info_regs->signature);
71 	if (sig != IONIC_DEV_INFO_SIGNATURE) {
72 		dev_err(dev, "Incompatible firmware signature %x", sig);
73 		return -EFAULT;
74 	}
75 
76 	ionic_init_devinfo(ionic);
77 
78 	/* BAR1: doorbells */
79 	bar++;
80 	if (num_bars < 2) {
81 		dev_err(dev, "Doorbell bar missing, aborting\n");
82 		return -EFAULT;
83 	}
84 
85 	timer_setup(&ionic->watchdog_timer, ionic_watchdog_cb, 0);
86 	ionic->watchdog_period = IONIC_WATCHDOG_SECS * HZ;
87 	mod_timer(&ionic->watchdog_timer,
88 		  round_jiffies(jiffies + ionic->watchdog_period));
89 
90 	idev->db_pages = bar->vaddr;
91 	idev->phy_db_pages = bar->bus_addr;
92 
93 	return 0;
94 }
95 
96 void ionic_dev_teardown(struct ionic *ionic)
97 {
98 	del_timer_sync(&ionic->watchdog_timer);
99 }
100 
101 /* Devcmd Interface */
102 int ionic_heartbeat_check(struct ionic *ionic)
103 {
104 	struct ionic_dev *idev = &ionic->idev;
105 	unsigned long hb_time;
106 	u32 fw_status;
107 	u32 hb;
108 
109 	/* wait a little more than one second before testing again */
110 	hb_time = jiffies;
111 	if (time_before(hb_time, (idev->last_hb_time + ionic->watchdog_period)))
112 		return 0;
113 
114 	/* firmware is useful only if fw_status is non-zero */
115 	fw_status = ioread32(&idev->dev_info_regs->fw_status);
116 	if (!fw_status)
117 		return -ENXIO;
118 
119 	/* early FW has no heartbeat, else FW will return non-zero */
120 	hb = ioread32(&idev->dev_info_regs->fw_heartbeat);
121 	if (!hb)
122 		return 0;
123 
124 	/* are we stalled? */
125 	if (hb == idev->last_hb) {
126 		/* only complain once for each stall seen */
127 		if (idev->last_hb_time != 1) {
128 			dev_info(ionic->dev, "FW heartbeat stalled at %d\n",
129 				 idev->last_hb);
130 			idev->last_hb_time = 1;
131 		}
132 
133 		return -ENXIO;
134 	}
135 
136 	if (idev->last_hb_time == 1)
137 		dev_info(ionic->dev, "FW heartbeat restored at %d\n", hb);
138 
139 	idev->last_hb = hb;
140 	idev->last_hb_time = hb_time;
141 
142 	return 0;
143 }
144 
145 u8 ionic_dev_cmd_status(struct ionic_dev *idev)
146 {
147 	return ioread8(&idev->dev_cmd_regs->comp.comp.status);
148 }
149 
150 bool ionic_dev_cmd_done(struct ionic_dev *idev)
151 {
152 	return ioread32(&idev->dev_cmd_regs->done) & IONIC_DEV_CMD_DONE;
153 }
154 
155 void ionic_dev_cmd_comp(struct ionic_dev *idev, union ionic_dev_cmd_comp *comp)
156 {
157 	memcpy_fromio(comp, &idev->dev_cmd_regs->comp, sizeof(*comp));
158 }
159 
160 void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
161 {
162 	memcpy_toio(&idev->dev_cmd_regs->cmd, cmd, sizeof(*cmd));
163 	iowrite32(0, &idev->dev_cmd_regs->done);
164 	iowrite32(1, &idev->dev_cmd_regs->doorbell);
165 }
166 
167 /* Device commands */
168 void ionic_dev_cmd_identify(struct ionic_dev *idev, u8 ver)
169 {
170 	union ionic_dev_cmd cmd = {
171 		.identify.opcode = IONIC_CMD_IDENTIFY,
172 		.identify.ver = ver,
173 	};
174 
175 	ionic_dev_cmd_go(idev, &cmd);
176 }
177 
178 void ionic_dev_cmd_init(struct ionic_dev *idev)
179 {
180 	union ionic_dev_cmd cmd = {
181 		.init.opcode = IONIC_CMD_INIT,
182 		.init.type = 0,
183 	};
184 
185 	ionic_dev_cmd_go(idev, &cmd);
186 }
187 
188 void ionic_dev_cmd_reset(struct ionic_dev *idev)
189 {
190 	union ionic_dev_cmd cmd = {
191 		.reset.opcode = IONIC_CMD_RESET,
192 	};
193 
194 	ionic_dev_cmd_go(idev, &cmd);
195 }
196 
197 /* Port commands */
198 void ionic_dev_cmd_port_identify(struct ionic_dev *idev)
199 {
200 	union ionic_dev_cmd cmd = {
201 		.port_init.opcode = IONIC_CMD_PORT_IDENTIFY,
202 		.port_init.index = 0,
203 	};
204 
205 	ionic_dev_cmd_go(idev, &cmd);
206 }
207 
208 void ionic_dev_cmd_port_init(struct ionic_dev *idev)
209 {
210 	union ionic_dev_cmd cmd = {
211 		.port_init.opcode = IONIC_CMD_PORT_INIT,
212 		.port_init.index = 0,
213 		.port_init.info_pa = cpu_to_le64(idev->port_info_pa),
214 	};
215 
216 	ionic_dev_cmd_go(idev, &cmd);
217 }
218 
219 void ionic_dev_cmd_port_reset(struct ionic_dev *idev)
220 {
221 	union ionic_dev_cmd cmd = {
222 		.port_reset.opcode = IONIC_CMD_PORT_RESET,
223 		.port_reset.index = 0,
224 	};
225 
226 	ionic_dev_cmd_go(idev, &cmd);
227 }
228 
229 void ionic_dev_cmd_port_state(struct ionic_dev *idev, u8 state)
230 {
231 	union ionic_dev_cmd cmd = {
232 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
233 		.port_setattr.index = 0,
234 		.port_setattr.attr = IONIC_PORT_ATTR_STATE,
235 		.port_setattr.state = state,
236 	};
237 
238 	ionic_dev_cmd_go(idev, &cmd);
239 }
240 
241 void ionic_dev_cmd_port_speed(struct ionic_dev *idev, u32 speed)
242 {
243 	union ionic_dev_cmd cmd = {
244 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
245 		.port_setattr.index = 0,
246 		.port_setattr.attr = IONIC_PORT_ATTR_SPEED,
247 		.port_setattr.speed = cpu_to_le32(speed),
248 	};
249 
250 	ionic_dev_cmd_go(idev, &cmd);
251 }
252 
253 void ionic_dev_cmd_port_autoneg(struct ionic_dev *idev, u8 an_enable)
254 {
255 	union ionic_dev_cmd cmd = {
256 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
257 		.port_setattr.index = 0,
258 		.port_setattr.attr = IONIC_PORT_ATTR_AUTONEG,
259 		.port_setattr.an_enable = an_enable,
260 	};
261 
262 	ionic_dev_cmd_go(idev, &cmd);
263 }
264 
265 void ionic_dev_cmd_port_fec(struct ionic_dev *idev, u8 fec_type)
266 {
267 	union ionic_dev_cmd cmd = {
268 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
269 		.port_setattr.index = 0,
270 		.port_setattr.attr = IONIC_PORT_ATTR_FEC,
271 		.port_setattr.fec_type = fec_type,
272 	};
273 
274 	ionic_dev_cmd_go(idev, &cmd);
275 }
276 
277 void ionic_dev_cmd_port_pause(struct ionic_dev *idev, u8 pause_type)
278 {
279 	union ionic_dev_cmd cmd = {
280 		.port_setattr.opcode = IONIC_CMD_PORT_SETATTR,
281 		.port_setattr.index = 0,
282 		.port_setattr.attr = IONIC_PORT_ATTR_PAUSE,
283 		.port_setattr.pause_type = pause_type,
284 	};
285 
286 	ionic_dev_cmd_go(idev, &cmd);
287 }
288 
289 /* LIF commands */
290 void ionic_dev_cmd_lif_identify(struct ionic_dev *idev, u8 type, u8 ver)
291 {
292 	union ionic_dev_cmd cmd = {
293 		.lif_identify.opcode = IONIC_CMD_LIF_IDENTIFY,
294 		.lif_identify.type = type,
295 		.lif_identify.ver = ver,
296 	};
297 
298 	ionic_dev_cmd_go(idev, &cmd);
299 }
300 
301 void ionic_dev_cmd_lif_init(struct ionic_dev *idev, u16 lif_index,
302 			    dma_addr_t info_pa)
303 {
304 	union ionic_dev_cmd cmd = {
305 		.lif_init.opcode = IONIC_CMD_LIF_INIT,
306 		.lif_init.index = cpu_to_le16(lif_index),
307 		.lif_init.info_pa = cpu_to_le64(info_pa),
308 	};
309 
310 	ionic_dev_cmd_go(idev, &cmd);
311 }
312 
313 void ionic_dev_cmd_lif_reset(struct ionic_dev *idev, u16 lif_index)
314 {
315 	union ionic_dev_cmd cmd = {
316 		.lif_init.opcode = IONIC_CMD_LIF_RESET,
317 		.lif_init.index = cpu_to_le16(lif_index),
318 	};
319 
320 	ionic_dev_cmd_go(idev, &cmd);
321 }
322 
323 void ionic_dev_cmd_adminq_init(struct ionic_dev *idev, struct ionic_qcq *qcq,
324 			       u16 lif_index, u16 intr_index)
325 {
326 	struct ionic_queue *q = &qcq->q;
327 	struct ionic_cq *cq = &qcq->cq;
328 
329 	union ionic_dev_cmd cmd = {
330 		.q_init.opcode = IONIC_CMD_Q_INIT,
331 		.q_init.lif_index = cpu_to_le16(lif_index),
332 		.q_init.type = q->type,
333 		.q_init.index = cpu_to_le32(q->index),
334 		.q_init.flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
335 					    IONIC_QINIT_F_ENA),
336 		.q_init.pid = cpu_to_le16(q->pid),
337 		.q_init.intr_index = cpu_to_le16(intr_index),
338 		.q_init.ring_size = ilog2(q->num_descs),
339 		.q_init.ring_base = cpu_to_le64(q->base_pa),
340 		.q_init.cq_ring_base = cpu_to_le64(cq->base_pa),
341 	};
342 
343 	ionic_dev_cmd_go(idev, &cmd);
344 }
345 
346 int ionic_db_page_num(struct ionic_lif *lif, int pid)
347 {
348 	return (lif->hw_index * lif->dbid_count) + pid;
349 }
350 
351 int ionic_cq_init(struct ionic_lif *lif, struct ionic_cq *cq,
352 		  struct ionic_intr_info *intr,
353 		  unsigned int num_descs, size_t desc_size)
354 {
355 	struct ionic_cq_info *cur;
356 	unsigned int ring_size;
357 	unsigned int i;
358 
359 	if (desc_size == 0 || !is_power_of_2(num_descs))
360 		return -EINVAL;
361 
362 	ring_size = ilog2(num_descs);
363 	if (ring_size < 2 || ring_size > 16)
364 		return -EINVAL;
365 
366 	cq->lif = lif;
367 	cq->bound_intr = intr;
368 	cq->num_descs = num_descs;
369 	cq->desc_size = desc_size;
370 	cq->tail = cq->info;
371 	cq->done_color = 1;
372 
373 	cur = cq->info;
374 
375 	for (i = 0; i < num_descs; i++) {
376 		if (i + 1 == num_descs) {
377 			cur->next = cq->info;
378 			cur->last = true;
379 		} else {
380 			cur->next = cur + 1;
381 		}
382 		cur->index = i;
383 		cur++;
384 	}
385 
386 	return 0;
387 }
388 
389 void ionic_cq_map(struct ionic_cq *cq, void *base, dma_addr_t base_pa)
390 {
391 	struct ionic_cq_info *cur;
392 	unsigned int i;
393 
394 	cq->base = base;
395 	cq->base_pa = base_pa;
396 
397 	for (i = 0, cur = cq->info; i < cq->num_descs; i++, cur++)
398 		cur->cq_desc = base + (i * cq->desc_size);
399 }
400 
401 void ionic_cq_bind(struct ionic_cq *cq, struct ionic_queue *q)
402 {
403 	cq->bound_q = q;
404 }
405 
406 unsigned int ionic_cq_service(struct ionic_cq *cq, unsigned int work_to_do,
407 			      ionic_cq_cb cb, ionic_cq_done_cb done_cb,
408 			      void *done_arg)
409 {
410 	unsigned int work_done = 0;
411 
412 	if (work_to_do == 0)
413 		return 0;
414 
415 	while (cb(cq, cq->tail)) {
416 		if (cq->tail->last)
417 			cq->done_color = !cq->done_color;
418 		cq->tail = cq->tail->next;
419 		DEBUG_STATS_CQE_CNT(cq);
420 
421 		if (++work_done >= work_to_do)
422 			break;
423 	}
424 
425 	if (work_done && done_cb)
426 		done_cb(done_arg);
427 
428 	return work_done;
429 }
430 
431 int ionic_q_init(struct ionic_lif *lif, struct ionic_dev *idev,
432 		 struct ionic_queue *q, unsigned int index, const char *name,
433 		 unsigned int num_descs, size_t desc_size,
434 		 size_t sg_desc_size, unsigned int pid)
435 {
436 	struct ionic_desc_info *cur;
437 	unsigned int ring_size;
438 	unsigned int i;
439 
440 	if (desc_size == 0 || !is_power_of_2(num_descs))
441 		return -EINVAL;
442 
443 	ring_size = ilog2(num_descs);
444 	if (ring_size < 2 || ring_size > 16)
445 		return -EINVAL;
446 
447 	q->lif = lif;
448 	q->idev = idev;
449 	q->index = index;
450 	q->num_descs = num_descs;
451 	q->desc_size = desc_size;
452 	q->sg_desc_size = sg_desc_size;
453 	q->tail = q->info;
454 	q->head = q->tail;
455 	q->pid = pid;
456 
457 	snprintf(q->name, sizeof(q->name), "L%d-%s%u", lif->index, name, index);
458 
459 	cur = q->info;
460 
461 	for (i = 0; i < num_descs; i++) {
462 		if (i + 1 == num_descs)
463 			cur->next = q->info;
464 		else
465 			cur->next = cur + 1;
466 		cur->index = i;
467 		cur->left = num_descs - i;
468 		cur++;
469 	}
470 
471 	return 0;
472 }
473 
474 void ionic_q_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
475 {
476 	struct ionic_desc_info *cur;
477 	unsigned int i;
478 
479 	q->base = base;
480 	q->base_pa = base_pa;
481 
482 	for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
483 		cur->desc = base + (i * q->desc_size);
484 }
485 
486 void ionic_q_sg_map(struct ionic_queue *q, void *base, dma_addr_t base_pa)
487 {
488 	struct ionic_desc_info *cur;
489 	unsigned int i;
490 
491 	q->sg_base = base;
492 	q->sg_base_pa = base_pa;
493 
494 	for (i = 0, cur = q->info; i < q->num_descs; i++, cur++)
495 		cur->sg_desc = base + (i * q->sg_desc_size);
496 }
497 
498 void ionic_q_post(struct ionic_queue *q, bool ring_doorbell, ionic_desc_cb cb,
499 		  void *cb_arg)
500 {
501 	struct device *dev = q->lif->ionic->dev;
502 	struct ionic_lif *lif = q->lif;
503 
504 	q->head->cb = cb;
505 	q->head->cb_arg = cb_arg;
506 	q->head = q->head->next;
507 
508 	dev_dbg(dev, "lif=%d qname=%s qid=%d qtype=%d p_index=%d ringdb=%d\n",
509 		q->lif->index, q->name, q->hw_type, q->hw_index,
510 		q->head->index, ring_doorbell);
511 
512 	if (ring_doorbell)
513 		ionic_dbell_ring(lif->kern_dbpage, q->hw_type,
514 				 q->dbval | q->head->index);
515 }
516 
517 static bool ionic_q_is_posted(struct ionic_queue *q, unsigned int pos)
518 {
519 	unsigned int mask, tail, head;
520 
521 	mask = q->num_descs - 1;
522 	tail = q->tail->index;
523 	head = q->head->index;
524 
525 	return ((pos - tail) & mask) < ((head - tail) & mask);
526 }
527 
528 void ionic_q_service(struct ionic_queue *q, struct ionic_cq_info *cq_info,
529 		     unsigned int stop_index)
530 {
531 	struct ionic_desc_info *desc_info;
532 	ionic_desc_cb cb;
533 	void *cb_arg;
534 
535 	/* check for empty queue */
536 	if (q->tail->index == q->head->index)
537 		return;
538 
539 	/* stop index must be for a descriptor that is not yet completed */
540 	if (unlikely(!ionic_q_is_posted(q, stop_index)))
541 		dev_err(q->lif->ionic->dev,
542 			"ionic stop is not posted %s stop %u tail %u head %u\n",
543 			q->name, stop_index, q->tail->index, q->head->index);
544 
545 	do {
546 		desc_info = q->tail;
547 		q->tail = desc_info->next;
548 
549 		cb = desc_info->cb;
550 		cb_arg = desc_info->cb_arg;
551 
552 		desc_info->cb = NULL;
553 		desc_info->cb_arg = NULL;
554 
555 		if (cb)
556 			cb(q, desc_info, cq_info, cb_arg);
557 	} while (desc_info->index != stop_index);
558 }
559