1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/etherdevice.h> 7 #include <linux/pci.h> 8 9 #include "ionic.h" 10 #include "ionic_bus.h" 11 #include "ionic_lif.h" 12 #include "ionic_debugfs.h" 13 14 /* Supported devices */ 15 static const struct pci_device_id ionic_id_table[] = { 16 { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF) }, 17 { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF) }, 18 { 0, } /* end of table */ 19 }; 20 MODULE_DEVICE_TABLE(pci, ionic_id_table); 21 22 int ionic_bus_get_irq(struct ionic *ionic, unsigned int num) 23 { 24 return pci_irq_vector(ionic->pdev, num); 25 } 26 27 const char *ionic_bus_info(struct ionic *ionic) 28 { 29 return pci_name(ionic->pdev); 30 } 31 32 int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs) 33 { 34 return pci_alloc_irq_vectors(ionic->pdev, nintrs, nintrs, 35 PCI_IRQ_MSIX); 36 } 37 38 void ionic_bus_free_irq_vectors(struct ionic *ionic) 39 { 40 if (!ionic->nintrs) 41 return; 42 43 pci_free_irq_vectors(ionic->pdev); 44 } 45 46 static int ionic_map_bars(struct ionic *ionic) 47 { 48 struct pci_dev *pdev = ionic->pdev; 49 struct device *dev = ionic->dev; 50 struct ionic_dev_bar *bars; 51 unsigned int i, j; 52 53 bars = ionic->bars; 54 ionic->num_bars = 0; 55 56 for (i = 0, j = 0; i < IONIC_BARS_MAX; i++) { 57 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) 58 continue; 59 bars[j].len = pci_resource_len(pdev, i); 60 61 /* only map the whole bar 0 */ 62 if (j > 0) { 63 bars[j].vaddr = NULL; 64 } else { 65 bars[j].vaddr = pci_iomap(pdev, i, bars[j].len); 66 if (!bars[j].vaddr) { 67 dev_err(dev, 68 "Cannot memory-map BAR %d, aborting\n", 69 i); 70 return -ENODEV; 71 } 72 } 73 74 bars[j].bus_addr = pci_resource_start(pdev, i); 75 bars[j].res_index = i; 76 ionic->num_bars++; 77 j++; 78 } 79 80 return 0; 81 } 82 83 static void ionic_unmap_bars(struct ionic *ionic) 84 { 85 struct ionic_dev_bar *bars = ionic->bars; 86 unsigned int i; 87 88 for (i = 0; i < IONIC_BARS_MAX; i++) { 89 if (bars[i].vaddr) { 90 iounmap(bars[i].vaddr); 91 bars[i].bus_addr = 0; 92 bars[i].vaddr = NULL; 93 bars[i].len = 0; 94 } 95 } 96 } 97 98 void __iomem *ionic_bus_map_dbpage(struct ionic *ionic, int page_num) 99 { 100 return pci_iomap_range(ionic->pdev, 101 ionic->bars[IONIC_PCI_BAR_DBELL].res_index, 102 (u64)page_num << PAGE_SHIFT, PAGE_SIZE); 103 } 104 105 void ionic_bus_unmap_dbpage(struct ionic *ionic, void __iomem *page) 106 { 107 iounmap(page); 108 } 109 110 static void ionic_vf_dealloc_locked(struct ionic *ionic) 111 { 112 struct ionic_vf *v; 113 dma_addr_t dma = 0; 114 int i; 115 116 if (!ionic->vfs) 117 return; 118 119 for (i = ionic->num_vfs - 1; i >= 0; i--) { 120 v = &ionic->vfs[i]; 121 122 if (v->stats_pa) { 123 (void)ionic_set_vf_config(ionic, i, 124 IONIC_VF_ATTR_STATSADDR, 125 (u8 *)&dma); 126 dma_unmap_single(ionic->dev, v->stats_pa, 127 sizeof(v->stats), DMA_FROM_DEVICE); 128 v->stats_pa = 0; 129 } 130 } 131 132 kfree(ionic->vfs); 133 ionic->vfs = NULL; 134 ionic->num_vfs = 0; 135 } 136 137 static void ionic_vf_dealloc(struct ionic *ionic) 138 { 139 down_write(&ionic->vf_op_lock); 140 ionic_vf_dealloc_locked(ionic); 141 up_write(&ionic->vf_op_lock); 142 } 143 144 static int ionic_vf_alloc(struct ionic *ionic, int num_vfs) 145 { 146 struct ionic_vf *v; 147 int err = 0; 148 int i; 149 150 down_write(&ionic->vf_op_lock); 151 152 ionic->vfs = kcalloc(num_vfs, sizeof(struct ionic_vf), GFP_KERNEL); 153 if (!ionic->vfs) { 154 err = -ENOMEM; 155 goto out; 156 } 157 158 for (i = 0; i < num_vfs; i++) { 159 v = &ionic->vfs[i]; 160 v->stats_pa = dma_map_single(ionic->dev, &v->stats, 161 sizeof(v->stats), DMA_FROM_DEVICE); 162 if (dma_mapping_error(ionic->dev, v->stats_pa)) { 163 v->stats_pa = 0; 164 err = -ENODEV; 165 goto out; 166 } 167 168 /* ignore failures from older FW, we just won't get stats */ 169 (void)ionic_set_vf_config(ionic, i, IONIC_VF_ATTR_STATSADDR, 170 (u8 *)&v->stats_pa); 171 ionic->num_vfs++; 172 } 173 174 out: 175 if (err) 176 ionic_vf_dealloc_locked(ionic); 177 up_write(&ionic->vf_op_lock); 178 return err; 179 } 180 181 static int ionic_sriov_configure(struct pci_dev *pdev, int num_vfs) 182 { 183 struct ionic *ionic = pci_get_drvdata(pdev); 184 struct device *dev = ionic->dev; 185 int ret = 0; 186 187 if (num_vfs > 0) { 188 ret = pci_enable_sriov(pdev, num_vfs); 189 if (ret) { 190 dev_err(dev, "Cannot enable SRIOV: %d\n", ret); 191 goto out; 192 } 193 194 ret = ionic_vf_alloc(ionic, num_vfs); 195 if (ret) { 196 dev_err(dev, "Cannot alloc VFs: %d\n", ret); 197 pci_disable_sriov(pdev); 198 goto out; 199 } 200 201 ret = num_vfs; 202 } else { 203 pci_disable_sriov(pdev); 204 ionic_vf_dealloc(ionic); 205 } 206 207 out: 208 return ret; 209 } 210 211 static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 212 { 213 struct device *dev = &pdev->dev; 214 struct ionic *ionic; 215 int num_vfs; 216 int err; 217 218 ionic = ionic_devlink_alloc(dev); 219 if (!ionic) 220 return -ENOMEM; 221 222 ionic->pdev = pdev; 223 ionic->dev = dev; 224 pci_set_drvdata(pdev, ionic); 225 mutex_init(&ionic->dev_cmd_lock); 226 227 /* Query system for DMA addressing limitation for the device. */ 228 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IONIC_ADDR_LEN)); 229 if (err) { 230 dev_err(dev, "Unable to obtain 64-bit DMA for consistent allocations, aborting. err=%d\n", 231 err); 232 goto err_out_clear_drvdata; 233 } 234 235 ionic_debugfs_add_dev(ionic); 236 237 /* Setup PCI device */ 238 err = pci_enable_device_mem(pdev); 239 if (err) { 240 dev_err(dev, "Cannot enable PCI device: %d, aborting\n", err); 241 goto err_out_debugfs_del_dev; 242 } 243 244 err = pci_request_regions(pdev, IONIC_DRV_NAME); 245 if (err) { 246 dev_err(dev, "Cannot request PCI regions: %d, aborting\n", err); 247 goto err_out_pci_disable_device; 248 } 249 250 pci_set_master(pdev); 251 pcie_print_link_status(pdev); 252 253 err = ionic_map_bars(ionic); 254 if (err) 255 goto err_out_pci_clear_master; 256 257 /* Configure the device */ 258 err = ionic_setup(ionic); 259 if (err) { 260 dev_err(dev, "Cannot setup device: %d, aborting\n", err); 261 goto err_out_unmap_bars; 262 } 263 264 err = ionic_identify(ionic); 265 if (err) { 266 dev_err(dev, "Cannot identify device: %d, aborting\n", err); 267 goto err_out_teardown; 268 } 269 270 err = ionic_init(ionic); 271 if (err) { 272 dev_err(dev, "Cannot init device: %d, aborting\n", err); 273 goto err_out_teardown; 274 } 275 276 /* Configure the ports */ 277 err = ionic_port_identify(ionic); 278 if (err) { 279 dev_err(dev, "Cannot identify port: %d, aborting\n", err); 280 goto err_out_reset; 281 } 282 283 err = ionic_port_init(ionic); 284 if (err) { 285 dev_err(dev, "Cannot init port: %d, aborting\n", err); 286 goto err_out_reset; 287 } 288 289 /* Configure LIFs */ 290 err = ionic_lif_identify(ionic, IONIC_LIF_TYPE_CLASSIC, 291 &ionic->ident.lif); 292 if (err) { 293 dev_err(dev, "Cannot identify LIFs: %d, aborting\n", err); 294 goto err_out_port_reset; 295 } 296 297 err = ionic_lifs_size(ionic); 298 if (err) { 299 dev_err(dev, "Cannot size LIFs: %d, aborting\n", err); 300 goto err_out_port_reset; 301 } 302 303 err = ionic_lifs_alloc(ionic); 304 if (err) { 305 dev_err(dev, "Cannot allocate LIFs: %d, aborting\n", err); 306 goto err_out_free_irqs; 307 } 308 309 err = ionic_lifs_init(ionic); 310 if (err) { 311 dev_err(dev, "Cannot init LIFs: %d, aborting\n", err); 312 goto err_out_free_lifs; 313 } 314 315 init_rwsem(&ionic->vf_op_lock); 316 num_vfs = pci_num_vf(pdev); 317 if (num_vfs) { 318 dev_info(dev, "%d VFs found already enabled\n", num_vfs); 319 err = ionic_vf_alloc(ionic, num_vfs); 320 if (err) 321 dev_err(dev, "Cannot enable existing VFs: %d\n", err); 322 } 323 324 err = ionic_lifs_register(ionic); 325 if (err) { 326 dev_err(dev, "Cannot register LIFs: %d, aborting\n", err); 327 goto err_out_deinit_lifs; 328 } 329 330 err = ionic_devlink_register(ionic); 331 if (err) { 332 dev_err(dev, "Cannot register devlink: %d\n", err); 333 goto err_out_deregister_lifs; 334 } 335 336 return 0; 337 338 err_out_deregister_lifs: 339 ionic_lifs_unregister(ionic); 340 err_out_deinit_lifs: 341 ionic_vf_dealloc(ionic); 342 ionic_lifs_deinit(ionic); 343 err_out_free_lifs: 344 ionic_lifs_free(ionic); 345 err_out_free_irqs: 346 ionic_bus_free_irq_vectors(ionic); 347 err_out_port_reset: 348 ionic_port_reset(ionic); 349 err_out_reset: 350 ionic_reset(ionic); 351 err_out_teardown: 352 ionic_dev_teardown(ionic); 353 /* Don't fail the probe for these errors, keep 354 * the hw interface around for inspection 355 */ 356 return 0; 357 358 err_out_unmap_bars: 359 ionic_unmap_bars(ionic); 360 pci_release_regions(pdev); 361 err_out_pci_clear_master: 362 pci_clear_master(pdev); 363 err_out_pci_disable_device: 364 pci_disable_device(pdev); 365 err_out_debugfs_del_dev: 366 ionic_debugfs_del_dev(ionic); 367 err_out_clear_drvdata: 368 mutex_destroy(&ionic->dev_cmd_lock); 369 ionic_devlink_free(ionic); 370 371 return err; 372 } 373 374 static void ionic_remove(struct pci_dev *pdev) 375 { 376 struct ionic *ionic = pci_get_drvdata(pdev); 377 378 if (!ionic) 379 return; 380 381 if (ionic->master_lif) { 382 ionic_devlink_unregister(ionic); 383 ionic_lifs_unregister(ionic); 384 ionic_lifs_deinit(ionic); 385 ionic_lifs_free(ionic); 386 ionic_bus_free_irq_vectors(ionic); 387 } 388 389 ionic_port_reset(ionic); 390 ionic_reset(ionic); 391 ionic_dev_teardown(ionic); 392 ionic_unmap_bars(ionic); 393 pci_release_regions(pdev); 394 pci_clear_master(pdev); 395 pci_disable_device(pdev); 396 ionic_debugfs_del_dev(ionic); 397 mutex_destroy(&ionic->dev_cmd_lock); 398 ionic_devlink_free(ionic); 399 } 400 401 static struct pci_driver ionic_driver = { 402 .name = IONIC_DRV_NAME, 403 .id_table = ionic_id_table, 404 .probe = ionic_probe, 405 .remove = ionic_remove, 406 .sriov_configure = ionic_sriov_configure, 407 }; 408 409 int ionic_bus_register_driver(void) 410 { 411 return pci_register_driver(&ionic_driver); 412 } 413 414 void ionic_bus_unregister_driver(void) 415 { 416 pci_unregister_driver(&ionic_driver); 417 } 418