1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright(c) 2017 - 2019 Pensando Systems, Inc */ 3 4 #include <linux/module.h> 5 #include <linux/netdevice.h> 6 #include <linux/etherdevice.h> 7 #include <linux/pci.h> 8 9 #include "ionic.h" 10 #include "ionic_bus.h" 11 #include "ionic_lif.h" 12 #include "ionic_debugfs.h" 13 14 /* Supported devices */ 15 static const struct pci_device_id ionic_id_table[] = { 16 { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_PF) }, 17 { PCI_VDEVICE(PENSANDO, PCI_DEVICE_ID_PENSANDO_IONIC_ETH_VF) }, 18 { 0, } /* end of table */ 19 }; 20 MODULE_DEVICE_TABLE(pci, ionic_id_table); 21 22 int ionic_bus_get_irq(struct ionic *ionic, unsigned int num) 23 { 24 return pci_irq_vector(ionic->pdev, num); 25 } 26 27 const char *ionic_bus_info(struct ionic *ionic) 28 { 29 return pci_name(ionic->pdev); 30 } 31 32 int ionic_bus_alloc_irq_vectors(struct ionic *ionic, unsigned int nintrs) 33 { 34 return pci_alloc_irq_vectors(ionic->pdev, nintrs, nintrs, 35 PCI_IRQ_MSIX); 36 } 37 38 void ionic_bus_free_irq_vectors(struct ionic *ionic) 39 { 40 pci_free_irq_vectors(ionic->pdev); 41 } 42 43 static int ionic_map_bars(struct ionic *ionic) 44 { 45 struct pci_dev *pdev = ionic->pdev; 46 struct device *dev = ionic->dev; 47 struct ionic_dev_bar *bars; 48 unsigned int i, j; 49 50 bars = ionic->bars; 51 ionic->num_bars = 0; 52 53 for (i = 0, j = 0; i < IONIC_BARS_MAX; i++) { 54 if (!(pci_resource_flags(pdev, i) & IORESOURCE_MEM)) 55 continue; 56 bars[j].len = pci_resource_len(pdev, i); 57 58 /* only map the whole bar 0 */ 59 if (j > 0) { 60 bars[j].vaddr = NULL; 61 } else { 62 bars[j].vaddr = pci_iomap(pdev, i, bars[j].len); 63 if (!bars[j].vaddr) { 64 dev_err(dev, 65 "Cannot memory-map BAR %d, aborting\n", 66 i); 67 return -ENODEV; 68 } 69 } 70 71 bars[j].bus_addr = pci_resource_start(pdev, i); 72 bars[j].res_index = i; 73 ionic->num_bars++; 74 j++; 75 } 76 77 return 0; 78 } 79 80 static void ionic_unmap_bars(struct ionic *ionic) 81 { 82 struct ionic_dev_bar *bars = ionic->bars; 83 unsigned int i; 84 85 for (i = 0; i < IONIC_BARS_MAX; i++) { 86 if (bars[i].vaddr) { 87 iounmap(bars[i].vaddr); 88 bars[i].bus_addr = 0; 89 bars[i].vaddr = NULL; 90 bars[i].len = 0; 91 } 92 } 93 } 94 95 void __iomem *ionic_bus_map_dbpage(struct ionic *ionic, int page_num) 96 { 97 return pci_iomap_range(ionic->pdev, 98 ionic->bars[IONIC_PCI_BAR_DBELL].res_index, 99 (u64)page_num << PAGE_SHIFT, PAGE_SIZE); 100 } 101 102 void ionic_bus_unmap_dbpage(struct ionic *ionic, void __iomem *page) 103 { 104 iounmap(page); 105 } 106 107 static void ionic_vf_dealloc_locked(struct ionic *ionic) 108 { 109 struct ionic_vf *v; 110 dma_addr_t dma = 0; 111 int i; 112 113 if (!ionic->vfs) 114 return; 115 116 for (i = ionic->num_vfs - 1; i >= 0; i--) { 117 v = &ionic->vfs[i]; 118 119 if (v->stats_pa) { 120 (void)ionic_set_vf_config(ionic, i, 121 IONIC_VF_ATTR_STATSADDR, 122 (u8 *)&dma); 123 dma_unmap_single(ionic->dev, v->stats_pa, 124 sizeof(v->stats), DMA_FROM_DEVICE); 125 v->stats_pa = 0; 126 } 127 } 128 129 kfree(ionic->vfs); 130 ionic->vfs = NULL; 131 ionic->num_vfs = 0; 132 } 133 134 static void ionic_vf_dealloc(struct ionic *ionic) 135 { 136 down_write(&ionic->vf_op_lock); 137 ionic_vf_dealloc_locked(ionic); 138 up_write(&ionic->vf_op_lock); 139 } 140 141 static int ionic_vf_alloc(struct ionic *ionic, int num_vfs) 142 { 143 struct ionic_vf *v; 144 int err = 0; 145 int i; 146 147 down_write(&ionic->vf_op_lock); 148 149 ionic->vfs = kcalloc(num_vfs, sizeof(struct ionic_vf), GFP_KERNEL); 150 if (!ionic->vfs) { 151 err = -ENOMEM; 152 goto out; 153 } 154 155 for (i = 0; i < num_vfs; i++) { 156 v = &ionic->vfs[i]; 157 v->stats_pa = dma_map_single(ionic->dev, &v->stats, 158 sizeof(v->stats), DMA_FROM_DEVICE); 159 if (dma_mapping_error(ionic->dev, v->stats_pa)) { 160 v->stats_pa = 0; 161 err = -ENODEV; 162 goto out; 163 } 164 165 /* ignore failures from older FW, we just won't get stats */ 166 (void)ionic_set_vf_config(ionic, i, IONIC_VF_ATTR_STATSADDR, 167 (u8 *)&v->stats_pa); 168 ionic->num_vfs++; 169 } 170 171 out: 172 if (err) 173 ionic_vf_dealloc_locked(ionic); 174 up_write(&ionic->vf_op_lock); 175 return err; 176 } 177 178 static int ionic_sriov_configure(struct pci_dev *pdev, int num_vfs) 179 { 180 struct ionic *ionic = pci_get_drvdata(pdev); 181 struct device *dev = ionic->dev; 182 int ret = 0; 183 184 if (num_vfs > 0) { 185 ret = pci_enable_sriov(pdev, num_vfs); 186 if (ret) { 187 dev_err(dev, "Cannot enable SRIOV: %d\n", ret); 188 goto out; 189 } 190 191 ret = ionic_vf_alloc(ionic, num_vfs); 192 if (ret) { 193 dev_err(dev, "Cannot alloc VFs: %d\n", ret); 194 pci_disable_sriov(pdev); 195 goto out; 196 } 197 198 ret = num_vfs; 199 } else { 200 pci_disable_sriov(pdev); 201 ionic_vf_dealloc(ionic); 202 } 203 204 out: 205 return ret; 206 } 207 208 static int ionic_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 209 { 210 struct device *dev = &pdev->dev; 211 struct ionic *ionic; 212 int num_vfs; 213 int err; 214 215 ionic = ionic_devlink_alloc(dev); 216 if (!ionic) 217 return -ENOMEM; 218 219 ionic->pdev = pdev; 220 ionic->dev = dev; 221 pci_set_drvdata(pdev, ionic); 222 mutex_init(&ionic->dev_cmd_lock); 223 224 /* Query system for DMA addressing limitation for the device. */ 225 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(IONIC_ADDR_LEN)); 226 if (err) { 227 dev_err(dev, "Unable to obtain 64-bit DMA for consistent allocations, aborting. err=%d\n", 228 err); 229 goto err_out_clear_drvdata; 230 } 231 232 ionic_debugfs_add_dev(ionic); 233 234 /* Setup PCI device */ 235 err = pci_enable_device_mem(pdev); 236 if (err) { 237 dev_err(dev, "Cannot enable PCI device: %d, aborting\n", err); 238 goto err_out_debugfs_del_dev; 239 } 240 241 err = pci_request_regions(pdev, IONIC_DRV_NAME); 242 if (err) { 243 dev_err(dev, "Cannot request PCI regions: %d, aborting\n", err); 244 goto err_out_pci_disable_device; 245 } 246 247 pci_set_master(pdev); 248 249 err = ionic_map_bars(ionic); 250 if (err) 251 goto err_out_pci_clear_master; 252 253 /* Configure the device */ 254 err = ionic_setup(ionic); 255 if (err) { 256 dev_err(dev, "Cannot setup device: %d, aborting\n", err); 257 goto err_out_unmap_bars; 258 } 259 260 err = ionic_identify(ionic); 261 if (err) { 262 dev_err(dev, "Cannot identify device: %d, aborting\n", err); 263 goto err_out_teardown; 264 } 265 266 err = ionic_init(ionic); 267 if (err) { 268 dev_err(dev, "Cannot init device: %d, aborting\n", err); 269 goto err_out_teardown; 270 } 271 272 /* Configure the ports */ 273 err = ionic_port_identify(ionic); 274 if (err) { 275 dev_err(dev, "Cannot identify port: %d, aborting\n", err); 276 goto err_out_reset; 277 } 278 279 err = ionic_port_init(ionic); 280 if (err) { 281 dev_err(dev, "Cannot init port: %d, aborting\n", err); 282 goto err_out_reset; 283 } 284 285 /* Configure LIFs */ 286 err = ionic_lif_identify(ionic, IONIC_LIF_TYPE_CLASSIC, 287 &ionic->ident.lif); 288 if (err) { 289 dev_err(dev, "Cannot identify LIFs: %d, aborting\n", err); 290 goto err_out_port_reset; 291 } 292 293 err = ionic_lifs_size(ionic); 294 if (err) { 295 dev_err(dev, "Cannot size LIFs: %d, aborting\n", err); 296 goto err_out_port_reset; 297 } 298 299 err = ionic_lifs_alloc(ionic); 300 if (err) { 301 dev_err(dev, "Cannot allocate LIFs: %d, aborting\n", err); 302 goto err_out_free_irqs; 303 } 304 305 err = ionic_lifs_init(ionic); 306 if (err) { 307 dev_err(dev, "Cannot init LIFs: %d, aborting\n", err); 308 goto err_out_free_lifs; 309 } 310 311 init_rwsem(&ionic->vf_op_lock); 312 num_vfs = pci_num_vf(pdev); 313 if (num_vfs) { 314 dev_info(dev, "%d VFs found already enabled\n", num_vfs); 315 err = ionic_vf_alloc(ionic, num_vfs); 316 if (err) 317 dev_err(dev, "Cannot enable existing VFs: %d\n", err); 318 } 319 320 err = ionic_lifs_register(ionic); 321 if (err) { 322 dev_err(dev, "Cannot register LIFs: %d, aborting\n", err); 323 goto err_out_deinit_lifs; 324 } 325 326 err = ionic_devlink_register(ionic); 327 if (err) { 328 dev_err(dev, "Cannot register devlink: %d\n", err); 329 goto err_out_deregister_lifs; 330 } 331 332 return 0; 333 334 err_out_deregister_lifs: 335 ionic_lifs_unregister(ionic); 336 err_out_deinit_lifs: 337 ionic_vf_dealloc(ionic); 338 ionic_lifs_deinit(ionic); 339 err_out_free_lifs: 340 ionic_lifs_free(ionic); 341 err_out_free_irqs: 342 ionic_bus_free_irq_vectors(ionic); 343 err_out_port_reset: 344 ionic_port_reset(ionic); 345 err_out_reset: 346 ionic_reset(ionic); 347 err_out_teardown: 348 ionic_dev_teardown(ionic); 349 err_out_unmap_bars: 350 ionic_unmap_bars(ionic); 351 pci_release_regions(pdev); 352 err_out_pci_clear_master: 353 pci_clear_master(pdev); 354 err_out_pci_disable_device: 355 pci_disable_device(pdev); 356 err_out_debugfs_del_dev: 357 ionic_debugfs_del_dev(ionic); 358 err_out_clear_drvdata: 359 mutex_destroy(&ionic->dev_cmd_lock); 360 ionic_devlink_free(ionic); 361 362 return err; 363 } 364 365 static void ionic_remove(struct pci_dev *pdev) 366 { 367 struct ionic *ionic = pci_get_drvdata(pdev); 368 369 if (!ionic) 370 return; 371 372 ionic_devlink_unregister(ionic); 373 ionic_lifs_unregister(ionic); 374 ionic_lifs_deinit(ionic); 375 ionic_lifs_free(ionic); 376 ionic_bus_free_irq_vectors(ionic); 377 ionic_port_reset(ionic); 378 ionic_reset(ionic); 379 ionic_dev_teardown(ionic); 380 ionic_unmap_bars(ionic); 381 pci_release_regions(pdev); 382 pci_clear_master(pdev); 383 pci_disable_device(pdev); 384 ionic_debugfs_del_dev(ionic); 385 mutex_destroy(&ionic->dev_cmd_lock); 386 ionic_devlink_free(ionic); 387 } 388 389 static struct pci_driver ionic_driver = { 390 .name = IONIC_DRV_NAME, 391 .id_table = ionic_id_table, 392 .probe = ionic_probe, 393 .remove = ionic_remove, 394 .sriov_configure = ionic_sriov_configure, 395 }; 396 397 int ionic_bus_register_driver(void) 398 { 399 return pci_register_driver(&ionic_driver); 400 } 401 402 void ionic_bus_unregister_driver(void) 403 { 404 pci_unregister_driver(&ionic_driver); 405 } 406