1 /*
2  * Copyright (C) 2006-2007 PA Semi, Inc
3  *
4  * Driver for the PA Semi PWRficient onchip 1G/10G Ethernet MACs
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  * You should have received a copy of the GNU General Public License
16  * along with this program; if not, see <http://www.gnu.org/licenses/>.
17  */
18 
19 #include <linux/module.h>
20 #include <linux/pci.h>
21 #include <linux/slab.h>
22 #include <linux/interrupt.h>
23 #include <linux/dmaengine.h>
24 #include <linux/delay.h>
25 #include <linux/netdevice.h>
26 #include <linux/of_mdio.h>
27 #include <linux/etherdevice.h>
28 #include <asm/dma-mapping.h>
29 #include <linux/in.h>
30 #include <linux/skbuff.h>
31 
32 #include <linux/ip.h>
33 #include <linux/tcp.h>
34 #include <net/checksum.h>
35 #include <linux/inet_lro.h>
36 #include <linux/prefetch.h>
37 
38 #include <asm/irq.h>
39 #include <asm/firmware.h>
40 #include <asm/pasemi_dma.h>
41 
42 #include "pasemi_mac.h"
43 
44 /* We have our own align, since ppc64 in general has it at 0 because
45  * of design flaws in some of the server bridge chips. However, for
46  * PWRficient doing the unaligned copies is more expensive than doing
47  * unaligned DMA, so make sure the data is aligned instead.
48  */
49 #define LOCAL_SKB_ALIGN	2
50 
51 /* TODO list
52  *
53  * - Multicast support
54  * - Large MTU support
55  * - SW LRO
56  * - Multiqueue RX/TX
57  */
58 
59 #define LRO_MAX_AGGR 64
60 
61 #define PE_MIN_MTU	64
62 #define PE_MAX_MTU	9000
63 #define PE_DEF_MTU	ETH_DATA_LEN
64 
65 #define DEFAULT_MSG_ENABLE	  \
66 	(NETIF_MSG_DRV		| \
67 	 NETIF_MSG_PROBE	| \
68 	 NETIF_MSG_LINK		| \
69 	 NETIF_MSG_TIMER	| \
70 	 NETIF_MSG_IFDOWN	| \
71 	 NETIF_MSG_IFUP		| \
72 	 NETIF_MSG_RX_ERR	| \
73 	 NETIF_MSG_TX_ERR)
74 
75 MODULE_LICENSE("GPL");
76 MODULE_AUTHOR ("Olof Johansson <olof@lixom.net>");
77 MODULE_DESCRIPTION("PA Semi PWRficient Ethernet driver");
78 
79 static int debug = -1;	/* -1 == use DEFAULT_MSG_ENABLE as value */
80 module_param(debug, int, 0);
81 MODULE_PARM_DESC(debug, "PA Semi MAC bitmapped debugging message enable value");
82 
83 extern const struct ethtool_ops pasemi_mac_ethtool_ops;
84 
85 static int translation_enabled(void)
86 {
87 #if defined(CONFIG_PPC_PASEMI_IOMMU_DMA_FORCE)
88 	return 1;
89 #else
90 	return firmware_has_feature(FW_FEATURE_LPAR);
91 #endif
92 }
93 
94 static void write_iob_reg(unsigned int reg, unsigned int val)
95 {
96 	pasemi_write_iob_reg(reg, val);
97 }
98 
99 static unsigned int read_mac_reg(const struct pasemi_mac *mac, unsigned int reg)
100 {
101 	return pasemi_read_mac_reg(mac->dma_if, reg);
102 }
103 
104 static void write_mac_reg(const struct pasemi_mac *mac, unsigned int reg,
105 			  unsigned int val)
106 {
107 	pasemi_write_mac_reg(mac->dma_if, reg, val);
108 }
109 
110 static unsigned int read_dma_reg(unsigned int reg)
111 {
112 	return pasemi_read_dma_reg(reg);
113 }
114 
115 static void write_dma_reg(unsigned int reg, unsigned int val)
116 {
117 	pasemi_write_dma_reg(reg, val);
118 }
119 
120 static struct pasemi_mac_rxring *rx_ring(const struct pasemi_mac *mac)
121 {
122 	return mac->rx;
123 }
124 
125 static struct pasemi_mac_txring *tx_ring(const struct pasemi_mac *mac)
126 {
127 	return mac->tx;
128 }
129 
130 static inline void prefetch_skb(const struct sk_buff *skb)
131 {
132 	const void *d = skb;
133 
134 	prefetch(d);
135 	prefetch(d+64);
136 	prefetch(d+128);
137 	prefetch(d+192);
138 }
139 
140 static int mac_to_intf(struct pasemi_mac *mac)
141 {
142 	struct pci_dev *pdev = mac->pdev;
143 	u32 tmp;
144 	int nintf, off, i, j;
145 	int devfn = pdev->devfn;
146 
147 	tmp = read_dma_reg(PAS_DMA_CAP_IFI);
148 	nintf = (tmp & PAS_DMA_CAP_IFI_NIN_M) >> PAS_DMA_CAP_IFI_NIN_S;
149 	off = (tmp & PAS_DMA_CAP_IFI_IOFF_M) >> PAS_DMA_CAP_IFI_IOFF_S;
150 
151 	/* IOFF contains the offset to the registers containing the
152 	 * DMA interface-to-MAC-pci-id mappings, and NIN contains number
153 	 * of total interfaces. Each register contains 4 devfns.
154 	 * Just do a linear search until we find the devfn of the MAC
155 	 * we're trying to look up.
156 	 */
157 
158 	for (i = 0; i < (nintf+3)/4; i++) {
159 		tmp = read_dma_reg(off+4*i);
160 		for (j = 0; j < 4; j++) {
161 			if (((tmp >> (8*j)) & 0xff) == devfn)
162 				return i*4 + j;
163 		}
164 	}
165 	return -1;
166 }
167 
168 static void pasemi_mac_intf_disable(struct pasemi_mac *mac)
169 {
170 	unsigned int flags;
171 
172 	flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
173 	flags &= ~PAS_MAC_CFG_PCFG_PE;
174 	write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
175 }
176 
177 static void pasemi_mac_intf_enable(struct pasemi_mac *mac)
178 {
179 	unsigned int flags;
180 
181 	flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
182 	flags |= PAS_MAC_CFG_PCFG_PE;
183 	write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
184 }
185 
186 static int pasemi_get_mac_addr(struct pasemi_mac *mac)
187 {
188 	struct pci_dev *pdev = mac->pdev;
189 	struct device_node *dn = pci_device_to_OF_node(pdev);
190 	int len;
191 	const u8 *maddr;
192 	u8 addr[ETH_ALEN];
193 
194 	if (!dn) {
195 		dev_dbg(&pdev->dev,
196 			  "No device node for mac, not configuring\n");
197 		return -ENOENT;
198 	}
199 
200 	maddr = of_get_property(dn, "local-mac-address", &len);
201 
202 	if (maddr && len == ETH_ALEN) {
203 		memcpy(mac->mac_addr, maddr, ETH_ALEN);
204 		return 0;
205 	}
206 
207 	/* Some old versions of firmware mistakenly uses mac-address
208 	 * (and as a string) instead of a byte array in local-mac-address.
209 	 */
210 
211 	if (maddr == NULL)
212 		maddr = of_get_property(dn, "mac-address", NULL);
213 
214 	if (maddr == NULL) {
215 		dev_warn(&pdev->dev,
216 			 "no mac address in device tree, not configuring\n");
217 		return -ENOENT;
218 	}
219 
220 	if (sscanf(maddr, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx",
221 		   &addr[0], &addr[1], &addr[2], &addr[3], &addr[4], &addr[5])
222 	    != ETH_ALEN) {
223 		dev_warn(&pdev->dev,
224 			 "can't parse mac address, not configuring\n");
225 		return -EINVAL;
226 	}
227 
228 	memcpy(mac->mac_addr, addr, ETH_ALEN);
229 
230 	return 0;
231 }
232 
233 static int pasemi_mac_set_mac_addr(struct net_device *dev, void *p)
234 {
235 	struct pasemi_mac *mac = netdev_priv(dev);
236 	struct sockaddr *addr = p;
237 	unsigned int adr0, adr1;
238 
239 	if (!is_valid_ether_addr(addr->sa_data))
240 		return -EADDRNOTAVAIL;
241 
242 	memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
243 
244 	adr0 = dev->dev_addr[2] << 24 |
245 	       dev->dev_addr[3] << 16 |
246 	       dev->dev_addr[4] << 8 |
247 	       dev->dev_addr[5];
248 	adr1 = read_mac_reg(mac, PAS_MAC_CFG_ADR1);
249 	adr1 &= ~0xffff;
250 	adr1 |= dev->dev_addr[0] << 8 | dev->dev_addr[1];
251 
252 	pasemi_mac_intf_disable(mac);
253 	write_mac_reg(mac, PAS_MAC_CFG_ADR0, adr0);
254 	write_mac_reg(mac, PAS_MAC_CFG_ADR1, adr1);
255 	pasemi_mac_intf_enable(mac);
256 
257 	return 0;
258 }
259 
260 static int get_skb_hdr(struct sk_buff *skb, void **iphdr,
261 		       void **tcph, u64 *hdr_flags, void *data)
262 {
263 	u64 macrx = (u64) data;
264 	unsigned int ip_len;
265 	struct iphdr *iph;
266 
267 	/* IPv4 header checksum failed */
268 	if ((macrx & XCT_MACRX_HTY_M) != XCT_MACRX_HTY_IPV4_OK)
269 		return -1;
270 
271 	/* non tcp packet */
272 	skb_reset_network_header(skb);
273 	iph = ip_hdr(skb);
274 	if (iph->protocol != IPPROTO_TCP)
275 		return -1;
276 
277 	ip_len = ip_hdrlen(skb);
278 	skb_set_transport_header(skb, ip_len);
279 	*tcph = tcp_hdr(skb);
280 
281 	/* check if ip header and tcp header are complete */
282 	if (ntohs(iph->tot_len) < ip_len + tcp_hdrlen(skb))
283 		return -1;
284 
285 	*hdr_flags = LRO_IPV4 | LRO_TCP;
286 	*iphdr = iph;
287 
288 	return 0;
289 }
290 
291 static int pasemi_mac_unmap_tx_skb(struct pasemi_mac *mac,
292 				    const int nfrags,
293 				    struct sk_buff *skb,
294 				    const dma_addr_t *dmas)
295 {
296 	int f;
297 	struct pci_dev *pdev = mac->dma_pdev;
298 
299 	pci_unmap_single(pdev, dmas[0], skb_headlen(skb), PCI_DMA_TODEVICE);
300 
301 	for (f = 0; f < nfrags; f++) {
302 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
303 
304 		pci_unmap_page(pdev, dmas[f+1], skb_frag_size(frag), PCI_DMA_TODEVICE);
305 	}
306 	dev_kfree_skb_irq(skb);
307 
308 	/* Freed descriptor slot + main SKB ptr + nfrags additional ptrs,
309 	 * aligned up to a power of 2
310 	 */
311 	return (nfrags + 3) & ~1;
312 }
313 
314 static struct pasemi_mac_csring *pasemi_mac_setup_csring(struct pasemi_mac *mac)
315 {
316 	struct pasemi_mac_csring *ring;
317 	u32 val;
318 	unsigned int cfg;
319 	int chno;
320 
321 	ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_csring),
322 				       offsetof(struct pasemi_mac_csring, chan));
323 
324 	if (!ring) {
325 		dev_err(&mac->pdev->dev, "Can't allocate checksum channel\n");
326 		goto out_chan;
327 	}
328 
329 	chno = ring->chan.chno;
330 
331 	ring->size = CS_RING_SIZE;
332 	ring->next_to_fill = 0;
333 
334 	/* Allocate descriptors */
335 	if (pasemi_dma_alloc_ring(&ring->chan, CS_RING_SIZE))
336 		goto out_ring_desc;
337 
338 	write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
339 		      PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
340 	val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
341 	val |= PAS_DMA_TXCHAN_BASEU_SIZ(CS_RING_SIZE >> 3);
342 
343 	write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
344 
345 	ring->events[0] = pasemi_dma_alloc_flag();
346 	ring->events[1] = pasemi_dma_alloc_flag();
347 	if (ring->events[0] < 0 || ring->events[1] < 0)
348 		goto out_flags;
349 
350 	pasemi_dma_clear_flag(ring->events[0]);
351 	pasemi_dma_clear_flag(ring->events[1]);
352 
353 	ring->fun = pasemi_dma_alloc_fun();
354 	if (ring->fun < 0)
355 		goto out_fun;
356 
357 	cfg = PAS_DMA_TXCHAN_CFG_TY_FUNC | PAS_DMA_TXCHAN_CFG_UP |
358 	      PAS_DMA_TXCHAN_CFG_TATTR(ring->fun) |
359 	      PAS_DMA_TXCHAN_CFG_LPSQ | PAS_DMA_TXCHAN_CFG_LPDQ;
360 
361 	if (translation_enabled())
362 		cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
363 
364 	write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
365 
366 	/* enable channel */
367 	pasemi_dma_start_chan(&ring->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
368 					   PAS_DMA_TXCHAN_TCMDSTA_DB |
369 					   PAS_DMA_TXCHAN_TCMDSTA_DE |
370 					   PAS_DMA_TXCHAN_TCMDSTA_DA);
371 
372 	return ring;
373 
374 out_fun:
375 out_flags:
376 	if (ring->events[0] >= 0)
377 		pasemi_dma_free_flag(ring->events[0]);
378 	if (ring->events[1] >= 0)
379 		pasemi_dma_free_flag(ring->events[1]);
380 	pasemi_dma_free_ring(&ring->chan);
381 out_ring_desc:
382 	pasemi_dma_free_chan(&ring->chan);
383 out_chan:
384 
385 	return NULL;
386 }
387 
388 static void pasemi_mac_setup_csrings(struct pasemi_mac *mac)
389 {
390 	int i;
391 	mac->cs[0] = pasemi_mac_setup_csring(mac);
392 	if (mac->type == MAC_TYPE_XAUI)
393 		mac->cs[1] = pasemi_mac_setup_csring(mac);
394 	else
395 		mac->cs[1] = 0;
396 
397 	for (i = 0; i < MAX_CS; i++)
398 		if (mac->cs[i])
399 			mac->num_cs++;
400 }
401 
402 static void pasemi_mac_free_csring(struct pasemi_mac_csring *csring)
403 {
404 	pasemi_dma_stop_chan(&csring->chan);
405 	pasemi_dma_free_flag(csring->events[0]);
406 	pasemi_dma_free_flag(csring->events[1]);
407 	pasemi_dma_free_ring(&csring->chan);
408 	pasemi_dma_free_chan(&csring->chan);
409 	pasemi_dma_free_fun(csring->fun);
410 }
411 
412 static int pasemi_mac_setup_rx_resources(const struct net_device *dev)
413 {
414 	struct pasemi_mac_rxring *ring;
415 	struct pasemi_mac *mac = netdev_priv(dev);
416 	int chno;
417 	unsigned int cfg;
418 
419 	ring = pasemi_dma_alloc_chan(RXCHAN, sizeof(struct pasemi_mac_rxring),
420 				     offsetof(struct pasemi_mac_rxring, chan));
421 
422 	if (!ring) {
423 		dev_err(&mac->pdev->dev, "Can't allocate RX channel\n");
424 		goto out_chan;
425 	}
426 	chno = ring->chan.chno;
427 
428 	spin_lock_init(&ring->lock);
429 
430 	ring->size = RX_RING_SIZE;
431 	ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
432 				  RX_RING_SIZE, GFP_KERNEL);
433 
434 	if (!ring->ring_info)
435 		goto out_ring_info;
436 
437 	/* Allocate descriptors */
438 	if (pasemi_dma_alloc_ring(&ring->chan, RX_RING_SIZE))
439 		goto out_ring_desc;
440 
441 	ring->buffers = dma_zalloc_coherent(&mac->dma_pdev->dev,
442 					    RX_RING_SIZE * sizeof(u64),
443 					    &ring->buf_dma, GFP_KERNEL);
444 	if (!ring->buffers)
445 		goto out_ring_desc;
446 
447 	write_dma_reg(PAS_DMA_RXCHAN_BASEL(chno),
448 		      PAS_DMA_RXCHAN_BASEL_BRBL(ring->chan.ring_dma));
449 
450 	write_dma_reg(PAS_DMA_RXCHAN_BASEU(chno),
451 		      PAS_DMA_RXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32) |
452 		      PAS_DMA_RXCHAN_BASEU_SIZ(RX_RING_SIZE >> 3));
453 
454 	cfg = PAS_DMA_RXCHAN_CFG_HBU(2);
455 
456 	if (translation_enabled())
457 		cfg |= PAS_DMA_RXCHAN_CFG_CTR;
458 
459 	write_dma_reg(PAS_DMA_RXCHAN_CFG(chno), cfg);
460 
461 	write_dma_reg(PAS_DMA_RXINT_BASEL(mac->dma_if),
462 		      PAS_DMA_RXINT_BASEL_BRBL(ring->buf_dma));
463 
464 	write_dma_reg(PAS_DMA_RXINT_BASEU(mac->dma_if),
465 		      PAS_DMA_RXINT_BASEU_BRBH(ring->buf_dma >> 32) |
466 		      PAS_DMA_RXINT_BASEU_SIZ(RX_RING_SIZE >> 3));
467 
468 	cfg = PAS_DMA_RXINT_CFG_DHL(2) | PAS_DMA_RXINT_CFG_L2 |
469 	      PAS_DMA_RXINT_CFG_LW | PAS_DMA_RXINT_CFG_RBP |
470 	      PAS_DMA_RXINT_CFG_HEN;
471 
472 	if (translation_enabled())
473 		cfg |= PAS_DMA_RXINT_CFG_ITRR | PAS_DMA_RXINT_CFG_ITR;
474 
475 	write_dma_reg(PAS_DMA_RXINT_CFG(mac->dma_if), cfg);
476 
477 	ring->next_to_fill = 0;
478 	ring->next_to_clean = 0;
479 	ring->mac = mac;
480 	mac->rx = ring;
481 
482 	return 0;
483 
484 out_ring_desc:
485 	kfree(ring->ring_info);
486 out_ring_info:
487 	pasemi_dma_free_chan(&ring->chan);
488 out_chan:
489 	return -ENOMEM;
490 }
491 
492 static struct pasemi_mac_txring *
493 pasemi_mac_setup_tx_resources(const struct net_device *dev)
494 {
495 	struct pasemi_mac *mac = netdev_priv(dev);
496 	u32 val;
497 	struct pasemi_mac_txring *ring;
498 	unsigned int cfg;
499 	int chno;
500 
501 	ring = pasemi_dma_alloc_chan(TXCHAN, sizeof(struct pasemi_mac_txring),
502 				     offsetof(struct pasemi_mac_txring, chan));
503 
504 	if (!ring) {
505 		dev_err(&mac->pdev->dev, "Can't allocate TX channel\n");
506 		goto out_chan;
507 	}
508 
509 	chno = ring->chan.chno;
510 
511 	spin_lock_init(&ring->lock);
512 
513 	ring->size = TX_RING_SIZE;
514 	ring->ring_info = kzalloc(sizeof(struct pasemi_mac_buffer) *
515 				  TX_RING_SIZE, GFP_KERNEL);
516 	if (!ring->ring_info)
517 		goto out_ring_info;
518 
519 	/* Allocate descriptors */
520 	if (pasemi_dma_alloc_ring(&ring->chan, TX_RING_SIZE))
521 		goto out_ring_desc;
522 
523 	write_dma_reg(PAS_DMA_TXCHAN_BASEL(chno),
524 		      PAS_DMA_TXCHAN_BASEL_BRBL(ring->chan.ring_dma));
525 	val = PAS_DMA_TXCHAN_BASEU_BRBH(ring->chan.ring_dma >> 32);
526 	val |= PAS_DMA_TXCHAN_BASEU_SIZ(TX_RING_SIZE >> 3);
527 
528 	write_dma_reg(PAS_DMA_TXCHAN_BASEU(chno), val);
529 
530 	cfg = PAS_DMA_TXCHAN_CFG_TY_IFACE |
531 	      PAS_DMA_TXCHAN_CFG_TATTR(mac->dma_if) |
532 	      PAS_DMA_TXCHAN_CFG_UP |
533 	      PAS_DMA_TXCHAN_CFG_WT(4);
534 
535 	if (translation_enabled())
536 		cfg |= PAS_DMA_TXCHAN_CFG_TRD | PAS_DMA_TXCHAN_CFG_TRR;
537 
538 	write_dma_reg(PAS_DMA_TXCHAN_CFG(chno), cfg);
539 
540 	ring->next_to_fill = 0;
541 	ring->next_to_clean = 0;
542 	ring->mac = mac;
543 
544 	return ring;
545 
546 out_ring_desc:
547 	kfree(ring->ring_info);
548 out_ring_info:
549 	pasemi_dma_free_chan(&ring->chan);
550 out_chan:
551 	return NULL;
552 }
553 
554 static void pasemi_mac_free_tx_resources(struct pasemi_mac *mac)
555 {
556 	struct pasemi_mac_txring *txring = tx_ring(mac);
557 	unsigned int i, j;
558 	struct pasemi_mac_buffer *info;
559 	dma_addr_t dmas[MAX_SKB_FRAGS+1];
560 	int freed, nfrags;
561 	int start, limit;
562 
563 	start = txring->next_to_clean;
564 	limit = txring->next_to_fill;
565 
566 	/* Compensate for when fill has wrapped and clean has not */
567 	if (start > limit)
568 		limit += TX_RING_SIZE;
569 
570 	for (i = start; i < limit; i += freed) {
571 		info = &txring->ring_info[(i+1) & (TX_RING_SIZE-1)];
572 		if (info->dma && info->skb) {
573 			nfrags = skb_shinfo(info->skb)->nr_frags;
574 			for (j = 0; j <= nfrags; j++)
575 				dmas[j] = txring->ring_info[(i+1+j) &
576 						(TX_RING_SIZE-1)].dma;
577 			freed = pasemi_mac_unmap_tx_skb(mac, nfrags,
578 							info->skb, dmas);
579 		} else {
580 			freed = 2;
581 		}
582 	}
583 
584 	kfree(txring->ring_info);
585 	pasemi_dma_free_chan(&txring->chan);
586 
587 }
588 
589 static void pasemi_mac_free_rx_buffers(struct pasemi_mac *mac)
590 {
591 	struct pasemi_mac_rxring *rx = rx_ring(mac);
592 	unsigned int i;
593 	struct pasemi_mac_buffer *info;
594 
595 	for (i = 0; i < RX_RING_SIZE; i++) {
596 		info = &RX_DESC_INFO(rx, i);
597 		if (info->skb && info->dma) {
598 			pci_unmap_single(mac->dma_pdev,
599 					 info->dma,
600 					 info->skb->len,
601 					 PCI_DMA_FROMDEVICE);
602 			dev_kfree_skb_any(info->skb);
603 		}
604 		info->dma = 0;
605 		info->skb = NULL;
606 	}
607 
608 	for (i = 0; i < RX_RING_SIZE; i++)
609 		RX_BUFF(rx, i) = 0;
610 }
611 
612 static void pasemi_mac_free_rx_resources(struct pasemi_mac *mac)
613 {
614 	pasemi_mac_free_rx_buffers(mac);
615 
616 	dma_free_coherent(&mac->dma_pdev->dev, RX_RING_SIZE * sizeof(u64),
617 			  rx_ring(mac)->buffers, rx_ring(mac)->buf_dma);
618 
619 	kfree(rx_ring(mac)->ring_info);
620 	pasemi_dma_free_chan(&rx_ring(mac)->chan);
621 	mac->rx = NULL;
622 }
623 
624 static void pasemi_mac_replenish_rx_ring(struct net_device *dev,
625 					 const int limit)
626 {
627 	const struct pasemi_mac *mac = netdev_priv(dev);
628 	struct pasemi_mac_rxring *rx = rx_ring(mac);
629 	int fill, count;
630 
631 	if (limit <= 0)
632 		return;
633 
634 	fill = rx_ring(mac)->next_to_fill;
635 	for (count = 0; count < limit; count++) {
636 		struct pasemi_mac_buffer *info = &RX_DESC_INFO(rx, fill);
637 		u64 *buff = &RX_BUFF(rx, fill);
638 		struct sk_buff *skb;
639 		dma_addr_t dma;
640 
641 		/* Entry in use? */
642 		WARN_ON(*buff);
643 
644 		skb = netdev_alloc_skb(dev, mac->bufsz);
645 		skb_reserve(skb, LOCAL_SKB_ALIGN);
646 
647 		if (unlikely(!skb))
648 			break;
649 
650 		dma = pci_map_single(mac->dma_pdev, skb->data,
651 				     mac->bufsz - LOCAL_SKB_ALIGN,
652 				     PCI_DMA_FROMDEVICE);
653 
654 		if (unlikely(pci_dma_mapping_error(mac->dma_pdev, dma))) {
655 			dev_kfree_skb_irq(info->skb);
656 			break;
657 		}
658 
659 		info->skb = skb;
660 		info->dma = dma;
661 		*buff = XCT_RXB_LEN(mac->bufsz) | XCT_RXB_ADDR(dma);
662 		fill++;
663 	}
664 
665 	wmb();
666 
667 	write_dma_reg(PAS_DMA_RXINT_INCR(mac->dma_if), count);
668 
669 	rx_ring(mac)->next_to_fill = (rx_ring(mac)->next_to_fill + count) &
670 				(RX_RING_SIZE - 1);
671 }
672 
673 static void pasemi_mac_restart_rx_intr(const struct pasemi_mac *mac)
674 {
675 	struct pasemi_mac_rxring *rx = rx_ring(mac);
676 	unsigned int reg, pcnt;
677 	/* Re-enable packet count interrupts: finally
678 	 * ack the packet count interrupt we got in rx_intr.
679 	 */
680 
681 	pcnt = *rx->chan.status & PAS_STATUS_PCNT_M;
682 
683 	reg = PAS_IOB_DMA_RXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_RXCH_RESET_PINTC;
684 
685 	if (*rx->chan.status & PAS_STATUS_TIMER)
686 		reg |= PAS_IOB_DMA_RXCH_RESET_TINTC;
687 
688 	write_iob_reg(PAS_IOB_DMA_RXCH_RESET(mac->rx->chan.chno), reg);
689 }
690 
691 static void pasemi_mac_restart_tx_intr(const struct pasemi_mac *mac)
692 {
693 	unsigned int reg, pcnt;
694 
695 	/* Re-enable packet count interrupts */
696 	pcnt = *tx_ring(mac)->chan.status & PAS_STATUS_PCNT_M;
697 
698 	reg = PAS_IOB_DMA_TXCH_RESET_PCNT(pcnt) | PAS_IOB_DMA_TXCH_RESET_PINTC;
699 
700 	write_iob_reg(PAS_IOB_DMA_TXCH_RESET(tx_ring(mac)->chan.chno), reg);
701 }
702 
703 
704 static inline void pasemi_mac_rx_error(const struct pasemi_mac *mac,
705 				       const u64 macrx)
706 {
707 	unsigned int rcmdsta, ccmdsta;
708 	struct pasemi_dmachan *chan = &rx_ring(mac)->chan;
709 
710 	if (!netif_msg_rx_err(mac))
711 		return;
712 
713 	rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
714 	ccmdsta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(chan->chno));
715 
716 	printk(KERN_ERR "pasemi_mac: rx error. macrx %016llx, rx status %llx\n",
717 		macrx, *chan->status);
718 
719 	printk(KERN_ERR "pasemi_mac: rcmdsta %08x ccmdsta %08x\n",
720 		rcmdsta, ccmdsta);
721 }
722 
723 static inline void pasemi_mac_tx_error(const struct pasemi_mac *mac,
724 				       const u64 mactx)
725 {
726 	unsigned int cmdsta;
727 	struct pasemi_dmachan *chan = &tx_ring(mac)->chan;
728 
729 	if (!netif_msg_tx_err(mac))
730 		return;
731 
732 	cmdsta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(chan->chno));
733 
734 	printk(KERN_ERR "pasemi_mac: tx error. mactx 0x%016llx, "\
735 		"tx status 0x%016llx\n", mactx, *chan->status);
736 
737 	printk(KERN_ERR "pasemi_mac: tcmdsta 0x%08x\n", cmdsta);
738 }
739 
740 static int pasemi_mac_clean_rx(struct pasemi_mac_rxring *rx,
741 			       const int limit)
742 {
743 	const struct pasemi_dmachan *chan = &rx->chan;
744 	struct pasemi_mac *mac = rx->mac;
745 	struct pci_dev *pdev = mac->dma_pdev;
746 	unsigned int n;
747 	int count, buf_index, tot_bytes, packets;
748 	struct pasemi_mac_buffer *info;
749 	struct sk_buff *skb;
750 	unsigned int len;
751 	u64 macrx, eval;
752 	dma_addr_t dma;
753 
754 	tot_bytes = 0;
755 	packets = 0;
756 
757 	spin_lock(&rx->lock);
758 
759 	n = rx->next_to_clean;
760 
761 	prefetch(&RX_DESC(rx, n));
762 
763 	for (count = 0; count < limit; count++) {
764 		macrx = RX_DESC(rx, n);
765 		prefetch(&RX_DESC(rx, n+4));
766 
767 		if ((macrx & XCT_MACRX_E) ||
768 		    (*chan->status & PAS_STATUS_ERROR))
769 			pasemi_mac_rx_error(mac, macrx);
770 
771 		if (!(macrx & XCT_MACRX_O))
772 			break;
773 
774 		info = NULL;
775 
776 		BUG_ON(!(macrx & XCT_MACRX_RR_8BRES));
777 
778 		eval = (RX_DESC(rx, n+1) & XCT_RXRES_8B_EVAL_M) >>
779 			XCT_RXRES_8B_EVAL_S;
780 		buf_index = eval-1;
781 
782 		dma = (RX_DESC(rx, n+2) & XCT_PTR_ADDR_M);
783 		info = &RX_DESC_INFO(rx, buf_index);
784 
785 		skb = info->skb;
786 
787 		prefetch_skb(skb);
788 
789 		len = (macrx & XCT_MACRX_LLEN_M) >> XCT_MACRX_LLEN_S;
790 
791 		pci_unmap_single(pdev, dma, mac->bufsz - LOCAL_SKB_ALIGN,
792 				 PCI_DMA_FROMDEVICE);
793 
794 		if (macrx & XCT_MACRX_CRC) {
795 			/* CRC error flagged */
796 			mac->netdev->stats.rx_errors++;
797 			mac->netdev->stats.rx_crc_errors++;
798 			/* No need to free skb, it'll be reused */
799 			goto next;
800 		}
801 
802 		info->skb = NULL;
803 		info->dma = 0;
804 
805 		if (likely((macrx & XCT_MACRX_HTY_M) == XCT_MACRX_HTY_IPV4_OK)) {
806 			skb->ip_summed = CHECKSUM_UNNECESSARY;
807 			skb->csum = (macrx & XCT_MACRX_CSUM_M) >>
808 					   XCT_MACRX_CSUM_S;
809 		} else {
810 			skb_checksum_none_assert(skb);
811 		}
812 
813 		packets++;
814 		tot_bytes += len;
815 
816 		/* Don't include CRC */
817 		skb_put(skb, len-4);
818 
819 		skb->protocol = eth_type_trans(skb, mac->netdev);
820 		lro_receive_skb(&mac->lro_mgr, skb, (void *)macrx);
821 
822 next:
823 		RX_DESC(rx, n) = 0;
824 		RX_DESC(rx, n+1) = 0;
825 
826 		/* Need to zero it out since hardware doesn't, since the
827 		 * replenish loop uses it to tell when it's done.
828 		 */
829 		RX_BUFF(rx, buf_index) = 0;
830 
831 		n += 4;
832 	}
833 
834 	if (n > RX_RING_SIZE) {
835 		/* Errata 5971 workaround: L2 target of headers */
836 		write_iob_reg(PAS_IOB_COM_PKTHDRCNT, 0);
837 		n &= (RX_RING_SIZE-1);
838 	}
839 
840 	rx_ring(mac)->next_to_clean = n;
841 
842 	lro_flush_all(&mac->lro_mgr);
843 
844 	/* Increase is in number of 16-byte entries, and since each descriptor
845 	 * with an 8BRES takes up 3x8 bytes (padded to 4x8), increase with
846 	 * count*2.
847 	 */
848 	write_dma_reg(PAS_DMA_RXCHAN_INCR(mac->rx->chan.chno), count << 1);
849 
850 	pasemi_mac_replenish_rx_ring(mac->netdev, count);
851 
852 	mac->netdev->stats.rx_bytes += tot_bytes;
853 	mac->netdev->stats.rx_packets += packets;
854 
855 	spin_unlock(&rx_ring(mac)->lock);
856 
857 	return count;
858 }
859 
860 /* Can't make this too large or we blow the kernel stack limits */
861 #define TX_CLEAN_BATCHSIZE (128/MAX_SKB_FRAGS)
862 
863 static int pasemi_mac_clean_tx(struct pasemi_mac_txring *txring)
864 {
865 	struct pasemi_dmachan *chan = &txring->chan;
866 	struct pasemi_mac *mac = txring->mac;
867 	int i, j;
868 	unsigned int start, descr_count, buf_count, batch_limit;
869 	unsigned int ring_limit;
870 	unsigned int total_count;
871 	unsigned long flags;
872 	struct sk_buff *skbs[TX_CLEAN_BATCHSIZE];
873 	dma_addr_t dmas[TX_CLEAN_BATCHSIZE][MAX_SKB_FRAGS+1];
874 	int nf[TX_CLEAN_BATCHSIZE];
875 	int nr_frags;
876 
877 	total_count = 0;
878 	batch_limit = TX_CLEAN_BATCHSIZE;
879 restart:
880 	spin_lock_irqsave(&txring->lock, flags);
881 
882 	start = txring->next_to_clean;
883 	ring_limit = txring->next_to_fill;
884 
885 	prefetch(&TX_DESC_INFO(txring, start+1).skb);
886 
887 	/* Compensate for when fill has wrapped but clean has not */
888 	if (start > ring_limit)
889 		ring_limit += TX_RING_SIZE;
890 
891 	buf_count = 0;
892 	descr_count = 0;
893 
894 	for (i = start;
895 	     descr_count < batch_limit && i < ring_limit;
896 	     i += buf_count) {
897 		u64 mactx = TX_DESC(txring, i);
898 		struct sk_buff *skb;
899 
900 		if ((mactx  & XCT_MACTX_E) ||
901 		    (*chan->status & PAS_STATUS_ERROR))
902 			pasemi_mac_tx_error(mac, mactx);
903 
904 		/* Skip over control descriptors */
905 		if (!(mactx & XCT_MACTX_LLEN_M)) {
906 			TX_DESC(txring, i) = 0;
907 			TX_DESC(txring, i+1) = 0;
908 			buf_count = 2;
909 			continue;
910 		}
911 
912 		skb = TX_DESC_INFO(txring, i+1).skb;
913 		nr_frags = TX_DESC_INFO(txring, i).dma;
914 
915 		if (unlikely(mactx & XCT_MACTX_O))
916 			/* Not yet transmitted */
917 			break;
918 
919 		buf_count = 2 + nr_frags;
920 		/* Since we always fill with an even number of entries, make
921 		 * sure we skip any unused one at the end as well.
922 		 */
923 		if (buf_count & 1)
924 			buf_count++;
925 
926 		for (j = 0; j <= nr_frags; j++)
927 			dmas[descr_count][j] = TX_DESC_INFO(txring, i+1+j).dma;
928 
929 		skbs[descr_count] = skb;
930 		nf[descr_count] = nr_frags;
931 
932 		TX_DESC(txring, i) = 0;
933 		TX_DESC(txring, i+1) = 0;
934 
935 		descr_count++;
936 	}
937 	txring->next_to_clean = i & (TX_RING_SIZE-1);
938 
939 	spin_unlock_irqrestore(&txring->lock, flags);
940 	netif_wake_queue(mac->netdev);
941 
942 	for (i = 0; i < descr_count; i++)
943 		pasemi_mac_unmap_tx_skb(mac, nf[i], skbs[i], dmas[i]);
944 
945 	total_count += descr_count;
946 
947 	/* If the batch was full, try to clean more */
948 	if (descr_count == batch_limit)
949 		goto restart;
950 
951 	return total_count;
952 }
953 
954 
955 static irqreturn_t pasemi_mac_rx_intr(int irq, void *data)
956 {
957 	const struct pasemi_mac_rxring *rxring = data;
958 	struct pasemi_mac *mac = rxring->mac;
959 	const struct pasemi_dmachan *chan = &rxring->chan;
960 	unsigned int reg;
961 
962 	if (!(*chan->status & PAS_STATUS_CAUSE_M))
963 		return IRQ_NONE;
964 
965 	/* Don't reset packet count so it won't fire again but clear
966 	 * all others.
967 	 */
968 
969 	reg = 0;
970 	if (*chan->status & PAS_STATUS_SOFT)
971 		reg |= PAS_IOB_DMA_RXCH_RESET_SINTC;
972 	if (*chan->status & PAS_STATUS_ERROR)
973 		reg |= PAS_IOB_DMA_RXCH_RESET_DINTC;
974 
975 	napi_schedule(&mac->napi);
976 
977 	write_iob_reg(PAS_IOB_DMA_RXCH_RESET(chan->chno), reg);
978 
979 	return IRQ_HANDLED;
980 }
981 
982 #define TX_CLEAN_INTERVAL HZ
983 
984 static void pasemi_mac_tx_timer(unsigned long data)
985 {
986 	struct pasemi_mac_txring *txring = (struct pasemi_mac_txring *)data;
987 	struct pasemi_mac *mac = txring->mac;
988 
989 	pasemi_mac_clean_tx(txring);
990 
991 	mod_timer(&txring->clean_timer, jiffies + TX_CLEAN_INTERVAL);
992 
993 	pasemi_mac_restart_tx_intr(mac);
994 }
995 
996 static irqreturn_t pasemi_mac_tx_intr(int irq, void *data)
997 {
998 	struct pasemi_mac_txring *txring = data;
999 	const struct pasemi_dmachan *chan = &txring->chan;
1000 	struct pasemi_mac *mac = txring->mac;
1001 	unsigned int reg;
1002 
1003 	if (!(*chan->status & PAS_STATUS_CAUSE_M))
1004 		return IRQ_NONE;
1005 
1006 	reg = 0;
1007 
1008 	if (*chan->status & PAS_STATUS_SOFT)
1009 		reg |= PAS_IOB_DMA_TXCH_RESET_SINTC;
1010 	if (*chan->status & PAS_STATUS_ERROR)
1011 		reg |= PAS_IOB_DMA_TXCH_RESET_DINTC;
1012 
1013 	mod_timer(&txring->clean_timer, jiffies + (TX_CLEAN_INTERVAL)*2);
1014 
1015 	napi_schedule(&mac->napi);
1016 
1017 	if (reg)
1018 		write_iob_reg(PAS_IOB_DMA_TXCH_RESET(chan->chno), reg);
1019 
1020 	return IRQ_HANDLED;
1021 }
1022 
1023 static void pasemi_adjust_link(struct net_device *dev)
1024 {
1025 	struct pasemi_mac *mac = netdev_priv(dev);
1026 	int msg;
1027 	unsigned int flags;
1028 	unsigned int new_flags;
1029 
1030 	if (!mac->phydev->link) {
1031 		/* If no link, MAC speed settings don't matter. Just report
1032 		 * link down and return.
1033 		 */
1034 		if (mac->link && netif_msg_link(mac))
1035 			printk(KERN_INFO "%s: Link is down.\n", dev->name);
1036 
1037 		netif_carrier_off(dev);
1038 		pasemi_mac_intf_disable(mac);
1039 		mac->link = 0;
1040 
1041 		return;
1042 	} else {
1043 		pasemi_mac_intf_enable(mac);
1044 		netif_carrier_on(dev);
1045 	}
1046 
1047 	flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1048 	new_flags = flags & ~(PAS_MAC_CFG_PCFG_HD | PAS_MAC_CFG_PCFG_SPD_M |
1049 			      PAS_MAC_CFG_PCFG_TSR_M);
1050 
1051 	if (!mac->phydev->duplex)
1052 		new_flags |= PAS_MAC_CFG_PCFG_HD;
1053 
1054 	switch (mac->phydev->speed) {
1055 	case 1000:
1056 		new_flags |= PAS_MAC_CFG_PCFG_SPD_1G |
1057 			     PAS_MAC_CFG_PCFG_TSR_1G;
1058 		break;
1059 	case 100:
1060 		new_flags |= PAS_MAC_CFG_PCFG_SPD_100M |
1061 			     PAS_MAC_CFG_PCFG_TSR_100M;
1062 		break;
1063 	case 10:
1064 		new_flags |= PAS_MAC_CFG_PCFG_SPD_10M |
1065 			     PAS_MAC_CFG_PCFG_TSR_10M;
1066 		break;
1067 	default:
1068 		printk("Unsupported speed %d\n", mac->phydev->speed);
1069 	}
1070 
1071 	/* Print on link or speed/duplex change */
1072 	msg = mac->link != mac->phydev->link || flags != new_flags;
1073 
1074 	mac->duplex = mac->phydev->duplex;
1075 	mac->speed = mac->phydev->speed;
1076 	mac->link = mac->phydev->link;
1077 
1078 	if (new_flags != flags)
1079 		write_mac_reg(mac, PAS_MAC_CFG_PCFG, new_flags);
1080 
1081 	if (msg && netif_msg_link(mac))
1082 		printk(KERN_INFO "%s: Link is up at %d Mbps, %s duplex.\n",
1083 		       dev->name, mac->speed, mac->duplex ? "full" : "half");
1084 }
1085 
1086 static int pasemi_mac_phy_init(struct net_device *dev)
1087 {
1088 	struct pasemi_mac *mac = netdev_priv(dev);
1089 	struct device_node *dn, *phy_dn;
1090 	struct phy_device *phydev;
1091 
1092 	dn = pci_device_to_OF_node(mac->pdev);
1093 	phy_dn = of_parse_phandle(dn, "phy-handle", 0);
1094 	of_node_put(phy_dn);
1095 
1096 	mac->link = 0;
1097 	mac->speed = 0;
1098 	mac->duplex = -1;
1099 
1100 	phydev = of_phy_connect(dev, phy_dn, &pasemi_adjust_link, 0,
1101 				PHY_INTERFACE_MODE_SGMII);
1102 
1103 	if (!phydev) {
1104 		printk(KERN_ERR "%s: Could not attach to phy\n", dev->name);
1105 		return -ENODEV;
1106 	}
1107 
1108 	mac->phydev = phydev;
1109 
1110 	return 0;
1111 }
1112 
1113 
1114 static int pasemi_mac_open(struct net_device *dev)
1115 {
1116 	struct pasemi_mac *mac = netdev_priv(dev);
1117 	unsigned int flags;
1118 	int i, ret;
1119 
1120 	flags = PAS_MAC_CFG_TXP_FCE | PAS_MAC_CFG_TXP_FPC(3) |
1121 		PAS_MAC_CFG_TXP_SL(3) | PAS_MAC_CFG_TXP_COB(0xf) |
1122 		PAS_MAC_CFG_TXP_TIFT(8) | PAS_MAC_CFG_TXP_TIFG(12);
1123 
1124 	write_mac_reg(mac, PAS_MAC_CFG_TXP, flags);
1125 
1126 	ret = pasemi_mac_setup_rx_resources(dev);
1127 	if (ret)
1128 		goto out_rx_resources;
1129 
1130 	mac->tx = pasemi_mac_setup_tx_resources(dev);
1131 
1132 	if (!mac->tx)
1133 		goto out_tx_ring;
1134 
1135 	/* We might already have allocated rings in case mtu was changed
1136 	 * before interface was brought up.
1137 	 */
1138 	if (dev->mtu > 1500 && !mac->num_cs) {
1139 		pasemi_mac_setup_csrings(mac);
1140 		if (!mac->num_cs)
1141 			goto out_tx_ring;
1142 	}
1143 
1144 	/* Zero out rmon counters */
1145 	for (i = 0; i < 32; i++)
1146 		write_mac_reg(mac, PAS_MAC_RMON(i), 0);
1147 
1148 	/* 0x3ff with 33MHz clock is about 31us */
1149 	write_iob_reg(PAS_IOB_DMA_COM_TIMEOUTCFG,
1150 		      PAS_IOB_DMA_COM_TIMEOUTCFG_TCNT(0x3ff));
1151 
1152 	write_iob_reg(PAS_IOB_DMA_RXCH_CFG(mac->rx->chan.chno),
1153 		      PAS_IOB_DMA_RXCH_CFG_CNTTH(256));
1154 
1155 	write_iob_reg(PAS_IOB_DMA_TXCH_CFG(mac->tx->chan.chno),
1156 		      PAS_IOB_DMA_TXCH_CFG_CNTTH(32));
1157 
1158 	write_mac_reg(mac, PAS_MAC_IPC_CHNL,
1159 		      PAS_MAC_IPC_CHNL_DCHNO(mac->rx->chan.chno) |
1160 		      PAS_MAC_IPC_CHNL_BCH(mac->rx->chan.chno));
1161 
1162 	/* enable rx if */
1163 	write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1164 		      PAS_DMA_RXINT_RCMDSTA_EN |
1165 		      PAS_DMA_RXINT_RCMDSTA_DROPS_M |
1166 		      PAS_DMA_RXINT_RCMDSTA_BP |
1167 		      PAS_DMA_RXINT_RCMDSTA_OO |
1168 		      PAS_DMA_RXINT_RCMDSTA_BT);
1169 
1170 	/* enable rx channel */
1171 	pasemi_dma_start_chan(&rx_ring(mac)->chan, PAS_DMA_RXCHAN_CCMDSTA_DU |
1172 						   PAS_DMA_RXCHAN_CCMDSTA_OD |
1173 						   PAS_DMA_RXCHAN_CCMDSTA_FD |
1174 						   PAS_DMA_RXCHAN_CCMDSTA_DT);
1175 
1176 	/* enable tx channel */
1177 	pasemi_dma_start_chan(&tx_ring(mac)->chan, PAS_DMA_TXCHAN_TCMDSTA_SZ |
1178 						   PAS_DMA_TXCHAN_TCMDSTA_DB |
1179 						   PAS_DMA_TXCHAN_TCMDSTA_DE |
1180 						   PAS_DMA_TXCHAN_TCMDSTA_DA);
1181 
1182 	pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE);
1183 
1184 	write_dma_reg(PAS_DMA_RXCHAN_INCR(rx_ring(mac)->chan.chno),
1185 		      RX_RING_SIZE>>1);
1186 
1187 	/* Clear out any residual packet count state from firmware */
1188 	pasemi_mac_restart_rx_intr(mac);
1189 	pasemi_mac_restart_tx_intr(mac);
1190 
1191 	flags = PAS_MAC_CFG_PCFG_S1 | PAS_MAC_CFG_PCFG_PR | PAS_MAC_CFG_PCFG_CE;
1192 
1193 	if (mac->type == MAC_TYPE_GMAC)
1194 		flags |= PAS_MAC_CFG_PCFG_TSR_1G | PAS_MAC_CFG_PCFG_SPD_1G;
1195 	else
1196 		flags |= PAS_MAC_CFG_PCFG_TSR_10G | PAS_MAC_CFG_PCFG_SPD_10G;
1197 
1198 	/* Enable interface in MAC */
1199 	write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1200 
1201 	ret = pasemi_mac_phy_init(dev);
1202 	if (ret) {
1203 		/* Since we won't get link notification, just enable RX */
1204 		pasemi_mac_intf_enable(mac);
1205 		if (mac->type == MAC_TYPE_GMAC) {
1206 			/* Warn for missing PHY on SGMII (1Gig) ports */
1207 			dev_warn(&mac->pdev->dev,
1208 				 "PHY init failed: %d.\n", ret);
1209 			dev_warn(&mac->pdev->dev,
1210 				 "Defaulting to 1Gbit full duplex\n");
1211 		}
1212 	}
1213 
1214 	netif_start_queue(dev);
1215 	napi_enable(&mac->napi);
1216 
1217 	snprintf(mac->tx_irq_name, sizeof(mac->tx_irq_name), "%s tx",
1218 		 dev->name);
1219 
1220 	ret = request_irq(mac->tx->chan.irq, pasemi_mac_tx_intr, 0,
1221 			  mac->tx_irq_name, mac->tx);
1222 	if (ret) {
1223 		dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1224 			mac->tx->chan.irq, ret);
1225 		goto out_tx_int;
1226 	}
1227 
1228 	snprintf(mac->rx_irq_name, sizeof(mac->rx_irq_name), "%s rx",
1229 		 dev->name);
1230 
1231 	ret = request_irq(mac->rx->chan.irq, pasemi_mac_rx_intr, 0,
1232 			  mac->rx_irq_name, mac->rx);
1233 	if (ret) {
1234 		dev_err(&mac->pdev->dev, "request_irq of irq %d failed: %d\n",
1235 			mac->rx->chan.irq, ret);
1236 		goto out_rx_int;
1237 	}
1238 
1239 	if (mac->phydev)
1240 		phy_start(mac->phydev);
1241 
1242 	init_timer(&mac->tx->clean_timer);
1243 	mac->tx->clean_timer.function = pasemi_mac_tx_timer;
1244 	mac->tx->clean_timer.data = (unsigned long)mac->tx;
1245 	mac->tx->clean_timer.expires = jiffies+HZ;
1246 	add_timer(&mac->tx->clean_timer);
1247 
1248 	return 0;
1249 
1250 out_rx_int:
1251 	free_irq(mac->tx->chan.irq, mac->tx);
1252 out_tx_int:
1253 	napi_disable(&mac->napi);
1254 	netif_stop_queue(dev);
1255 out_tx_ring:
1256 	if (mac->tx)
1257 		pasemi_mac_free_tx_resources(mac);
1258 	pasemi_mac_free_rx_resources(mac);
1259 out_rx_resources:
1260 
1261 	return ret;
1262 }
1263 
1264 #define MAX_RETRIES 5000
1265 
1266 static void pasemi_mac_pause_txchan(struct pasemi_mac *mac)
1267 {
1268 	unsigned int sta, retries;
1269 	int txch = tx_ring(mac)->chan.chno;
1270 
1271 	write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch),
1272 		      PAS_DMA_TXCHAN_TCMDSTA_ST);
1273 
1274 	for (retries = 0; retries < MAX_RETRIES; retries++) {
1275 		sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1276 		if (!(sta & PAS_DMA_TXCHAN_TCMDSTA_ACT))
1277 			break;
1278 		cond_resched();
1279 	}
1280 
1281 	if (sta & PAS_DMA_TXCHAN_TCMDSTA_ACT)
1282 		dev_err(&mac->dma_pdev->dev,
1283 			"Failed to stop tx channel, tcmdsta %08x\n", sta);
1284 
1285 	write_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch), 0);
1286 }
1287 
1288 static void pasemi_mac_pause_rxchan(struct pasemi_mac *mac)
1289 {
1290 	unsigned int sta, retries;
1291 	int rxch = rx_ring(mac)->chan.chno;
1292 
1293 	write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch),
1294 		      PAS_DMA_RXCHAN_CCMDSTA_ST);
1295 	for (retries = 0; retries < MAX_RETRIES; retries++) {
1296 		sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1297 		if (!(sta & PAS_DMA_RXCHAN_CCMDSTA_ACT))
1298 			break;
1299 		cond_resched();
1300 	}
1301 
1302 	if (sta & PAS_DMA_RXCHAN_CCMDSTA_ACT)
1303 		dev_err(&mac->dma_pdev->dev,
1304 			"Failed to stop rx channel, ccmdsta 08%x\n", sta);
1305 	write_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch), 0);
1306 }
1307 
1308 static void pasemi_mac_pause_rxint(struct pasemi_mac *mac)
1309 {
1310 	unsigned int sta, retries;
1311 
1312 	write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1313 		      PAS_DMA_RXINT_RCMDSTA_ST);
1314 	for (retries = 0; retries < MAX_RETRIES; retries++) {
1315 		sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1316 		if (!(sta & PAS_DMA_RXINT_RCMDSTA_ACT))
1317 			break;
1318 		cond_resched();
1319 	}
1320 
1321 	if (sta & PAS_DMA_RXINT_RCMDSTA_ACT)
1322 		dev_err(&mac->dma_pdev->dev,
1323 			"Failed to stop rx interface, rcmdsta %08x\n", sta);
1324 	write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if), 0);
1325 }
1326 
1327 static int pasemi_mac_close(struct net_device *dev)
1328 {
1329 	struct pasemi_mac *mac = netdev_priv(dev);
1330 	unsigned int sta;
1331 	int rxch, txch, i;
1332 
1333 	rxch = rx_ring(mac)->chan.chno;
1334 	txch = tx_ring(mac)->chan.chno;
1335 
1336 	if (mac->phydev) {
1337 		phy_stop(mac->phydev);
1338 		phy_disconnect(mac->phydev);
1339 	}
1340 
1341 	del_timer_sync(&mac->tx->clean_timer);
1342 
1343 	netif_stop_queue(dev);
1344 	napi_disable(&mac->napi);
1345 
1346 	sta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1347 	if (sta & (PAS_DMA_RXINT_RCMDSTA_BP |
1348 		      PAS_DMA_RXINT_RCMDSTA_OO |
1349 		      PAS_DMA_RXINT_RCMDSTA_BT))
1350 		printk(KERN_DEBUG "pasemi_mac: rcmdsta error: 0x%08x\n", sta);
1351 
1352 	sta = read_dma_reg(PAS_DMA_RXCHAN_CCMDSTA(rxch));
1353 	if (sta & (PAS_DMA_RXCHAN_CCMDSTA_DU |
1354 		     PAS_DMA_RXCHAN_CCMDSTA_OD |
1355 		     PAS_DMA_RXCHAN_CCMDSTA_FD |
1356 		     PAS_DMA_RXCHAN_CCMDSTA_DT))
1357 		printk(KERN_DEBUG "pasemi_mac: ccmdsta error: 0x%08x\n", sta);
1358 
1359 	sta = read_dma_reg(PAS_DMA_TXCHAN_TCMDSTA(txch));
1360 	if (sta & (PAS_DMA_TXCHAN_TCMDSTA_SZ | PAS_DMA_TXCHAN_TCMDSTA_DB |
1361 		      PAS_DMA_TXCHAN_TCMDSTA_DE | PAS_DMA_TXCHAN_TCMDSTA_DA))
1362 		printk(KERN_DEBUG "pasemi_mac: tcmdsta error: 0x%08x\n", sta);
1363 
1364 	/* Clean out any pending buffers */
1365 	pasemi_mac_clean_tx(tx_ring(mac));
1366 	pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1367 
1368 	pasemi_mac_pause_txchan(mac);
1369 	pasemi_mac_pause_rxint(mac);
1370 	pasemi_mac_pause_rxchan(mac);
1371 	pasemi_mac_intf_disable(mac);
1372 
1373 	free_irq(mac->tx->chan.irq, mac->tx);
1374 	free_irq(mac->rx->chan.irq, mac->rx);
1375 
1376 	for (i = 0; i < mac->num_cs; i++) {
1377 		pasemi_mac_free_csring(mac->cs[i]);
1378 		mac->cs[i] = NULL;
1379 	}
1380 
1381 	mac->num_cs = 0;
1382 
1383 	/* Free resources */
1384 	pasemi_mac_free_rx_resources(mac);
1385 	pasemi_mac_free_tx_resources(mac);
1386 
1387 	return 0;
1388 }
1389 
1390 static void pasemi_mac_queue_csdesc(const struct sk_buff *skb,
1391 				    const dma_addr_t *map,
1392 				    const unsigned int *map_size,
1393 				    struct pasemi_mac_txring *txring,
1394 				    struct pasemi_mac_csring *csring)
1395 {
1396 	u64 fund;
1397 	dma_addr_t cs_dest;
1398 	const int nh_off = skb_network_offset(skb);
1399 	const int nh_len = skb_network_header_len(skb);
1400 	const int nfrags = skb_shinfo(skb)->nr_frags;
1401 	int cs_size, i, fill, hdr, cpyhdr, evt;
1402 	dma_addr_t csdma;
1403 
1404 	fund = XCT_FUN_ST | XCT_FUN_RR_8BRES |
1405 	       XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1406 	       XCT_FUN_CRM_SIG | XCT_FUN_LLEN(skb->len - nh_off) |
1407 	       XCT_FUN_SHL(nh_len >> 2) | XCT_FUN_SE;
1408 
1409 	switch (ip_hdr(skb)->protocol) {
1410 	case IPPROTO_TCP:
1411 		fund |= XCT_FUN_SIG_TCP4;
1412 		/* TCP checksum is 16 bytes into the header */
1413 		cs_dest = map[0] + skb_transport_offset(skb) + 16;
1414 		break;
1415 	case IPPROTO_UDP:
1416 		fund |= XCT_FUN_SIG_UDP4;
1417 		/* UDP checksum is 6 bytes into the header */
1418 		cs_dest = map[0] + skb_transport_offset(skb) + 6;
1419 		break;
1420 	default:
1421 		BUG();
1422 	}
1423 
1424 	/* Do the checksum offloaded */
1425 	fill = csring->next_to_fill;
1426 	hdr = fill;
1427 
1428 	CS_DESC(csring, fill++) = fund;
1429 	/* Room for 8BRES. Checksum result is really 2 bytes into it */
1430 	csdma = csring->chan.ring_dma + (fill & (CS_RING_SIZE-1)) * 8 + 2;
1431 	CS_DESC(csring, fill++) = 0;
1432 
1433 	CS_DESC(csring, fill) = XCT_PTR_LEN(map_size[0]-nh_off) | XCT_PTR_ADDR(map[0]+nh_off);
1434 	for (i = 1; i <= nfrags; i++)
1435 		CS_DESC(csring, fill+i) = XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1436 
1437 	fill += i;
1438 	if (fill & 1)
1439 		fill++;
1440 
1441 	/* Copy the result into the TCP packet */
1442 	cpyhdr = fill;
1443 	CS_DESC(csring, fill++) = XCT_FUN_O | XCT_FUN_FUN(csring->fun) |
1444 				  XCT_FUN_LLEN(2) | XCT_FUN_SE;
1445 	CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(cs_dest) | XCT_PTR_T;
1446 	CS_DESC(csring, fill++) = XCT_PTR_LEN(2) | XCT_PTR_ADDR(csdma);
1447 	fill++;
1448 
1449 	evt = !csring->last_event;
1450 	csring->last_event = evt;
1451 
1452 	/* Event handshaking with MAC TX */
1453 	CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1454 				  CTRL_CMD_ETYPE_SET | CTRL_CMD_REG(csring->events[evt]);
1455 	CS_DESC(csring, fill++) = 0;
1456 	CS_DESC(csring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1457 				  CTRL_CMD_ETYPE_WCLR | CTRL_CMD_REG(csring->events[!evt]);
1458 	CS_DESC(csring, fill++) = 0;
1459 	csring->next_to_fill = fill & (CS_RING_SIZE-1);
1460 
1461 	cs_size = fill - hdr;
1462 	write_dma_reg(PAS_DMA_TXCHAN_INCR(csring->chan.chno), (cs_size) >> 1);
1463 
1464 	/* TX-side event handshaking */
1465 	fill = txring->next_to_fill;
1466 	TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1467 				  CTRL_CMD_ETYPE_WSET | CTRL_CMD_REG(csring->events[evt]);
1468 	TX_DESC(txring, fill++) = 0;
1469 	TX_DESC(txring, fill++) = CTRL_CMD_T | CTRL_CMD_META_EVT | CTRL_CMD_O |
1470 				  CTRL_CMD_ETYPE_CLR | CTRL_CMD_REG(csring->events[!evt]);
1471 	TX_DESC(txring, fill++) = 0;
1472 	txring->next_to_fill = fill;
1473 
1474 	write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), 2);
1475 }
1476 
1477 static int pasemi_mac_start_tx(struct sk_buff *skb, struct net_device *dev)
1478 {
1479 	struct pasemi_mac * const mac = netdev_priv(dev);
1480 	struct pasemi_mac_txring * const txring = tx_ring(mac);
1481 	struct pasemi_mac_csring *csring;
1482 	u64 dflags = 0;
1483 	u64 mactx;
1484 	dma_addr_t map[MAX_SKB_FRAGS+1];
1485 	unsigned int map_size[MAX_SKB_FRAGS+1];
1486 	unsigned long flags;
1487 	int i, nfrags;
1488 	int fill;
1489 	const int nh_off = skb_network_offset(skb);
1490 	const int nh_len = skb_network_header_len(skb);
1491 
1492 	prefetch(&txring->ring_info);
1493 
1494 	dflags = XCT_MACTX_O | XCT_MACTX_ST | XCT_MACTX_CRC_PAD;
1495 
1496 	nfrags = skb_shinfo(skb)->nr_frags;
1497 
1498 	map[0] = pci_map_single(mac->dma_pdev, skb->data, skb_headlen(skb),
1499 				PCI_DMA_TODEVICE);
1500 	map_size[0] = skb_headlen(skb);
1501 	if (pci_dma_mapping_error(mac->dma_pdev, map[0]))
1502 		goto out_err_nolock;
1503 
1504 	for (i = 0; i < nfrags; i++) {
1505 		skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1506 
1507 		map[i + 1] = skb_frag_dma_map(&mac->dma_pdev->dev, frag, 0,
1508 					      skb_frag_size(frag), DMA_TO_DEVICE);
1509 		map_size[i+1] = skb_frag_size(frag);
1510 		if (dma_mapping_error(&mac->dma_pdev->dev, map[i + 1])) {
1511 			nfrags = i;
1512 			goto out_err_nolock;
1513 		}
1514 	}
1515 
1516 	if (skb->ip_summed == CHECKSUM_PARTIAL && skb->len <= 1540) {
1517 		switch (ip_hdr(skb)->protocol) {
1518 		case IPPROTO_TCP:
1519 			dflags |= XCT_MACTX_CSUM_TCP;
1520 			dflags |= XCT_MACTX_IPH(nh_len >> 2);
1521 			dflags |= XCT_MACTX_IPO(nh_off);
1522 			break;
1523 		case IPPROTO_UDP:
1524 			dflags |= XCT_MACTX_CSUM_UDP;
1525 			dflags |= XCT_MACTX_IPH(nh_len >> 2);
1526 			dflags |= XCT_MACTX_IPO(nh_off);
1527 			break;
1528 		default:
1529 			WARN_ON(1);
1530 		}
1531 	}
1532 
1533 	mactx = dflags | XCT_MACTX_LLEN(skb->len);
1534 
1535 	spin_lock_irqsave(&txring->lock, flags);
1536 
1537 	/* Avoid stepping on the same cache line that the DMA controller
1538 	 * is currently about to send, so leave at least 8 words available.
1539 	 * Total free space needed is mactx + fragments + 8
1540 	 */
1541 	if (RING_AVAIL(txring) < nfrags + 14) {
1542 		/* no room -- stop the queue and wait for tx intr */
1543 		netif_stop_queue(dev);
1544 		goto out_err;
1545 	}
1546 
1547 	/* Queue up checksum + event descriptors, if needed */
1548 	if (mac->num_cs && skb->ip_summed == CHECKSUM_PARTIAL && skb->len > 1540) {
1549 		csring = mac->cs[mac->last_cs];
1550 		mac->last_cs = (mac->last_cs + 1) % mac->num_cs;
1551 
1552 		pasemi_mac_queue_csdesc(skb, map, map_size, txring, csring);
1553 	}
1554 
1555 	fill = txring->next_to_fill;
1556 	TX_DESC(txring, fill) = mactx;
1557 	TX_DESC_INFO(txring, fill).dma = nfrags;
1558 	fill++;
1559 	TX_DESC_INFO(txring, fill).skb = skb;
1560 	for (i = 0; i <= nfrags; i++) {
1561 		TX_DESC(txring, fill+i) =
1562 			XCT_PTR_LEN(map_size[i]) | XCT_PTR_ADDR(map[i]);
1563 		TX_DESC_INFO(txring, fill+i).dma = map[i];
1564 	}
1565 
1566 	/* We have to add an even number of 8-byte entries to the ring
1567 	 * even if the last one is unused. That means always an odd number
1568 	 * of pointers + one mactx descriptor.
1569 	 */
1570 	if (nfrags & 1)
1571 		nfrags++;
1572 
1573 	txring->next_to_fill = (fill + nfrags + 1) & (TX_RING_SIZE-1);
1574 
1575 	dev->stats.tx_packets++;
1576 	dev->stats.tx_bytes += skb->len;
1577 
1578 	spin_unlock_irqrestore(&txring->lock, flags);
1579 
1580 	write_dma_reg(PAS_DMA_TXCHAN_INCR(txring->chan.chno), (nfrags+2) >> 1);
1581 
1582 	return NETDEV_TX_OK;
1583 
1584 out_err:
1585 	spin_unlock_irqrestore(&txring->lock, flags);
1586 out_err_nolock:
1587 	while (nfrags--)
1588 		pci_unmap_single(mac->dma_pdev, map[nfrags], map_size[nfrags],
1589 				 PCI_DMA_TODEVICE);
1590 
1591 	return NETDEV_TX_BUSY;
1592 }
1593 
1594 static void pasemi_mac_set_rx_mode(struct net_device *dev)
1595 {
1596 	const struct pasemi_mac *mac = netdev_priv(dev);
1597 	unsigned int flags;
1598 
1599 	flags = read_mac_reg(mac, PAS_MAC_CFG_PCFG);
1600 
1601 	/* Set promiscuous */
1602 	if (dev->flags & IFF_PROMISC)
1603 		flags |= PAS_MAC_CFG_PCFG_PR;
1604 	else
1605 		flags &= ~PAS_MAC_CFG_PCFG_PR;
1606 
1607 	write_mac_reg(mac, PAS_MAC_CFG_PCFG, flags);
1608 }
1609 
1610 
1611 static int pasemi_mac_poll(struct napi_struct *napi, int budget)
1612 {
1613 	struct pasemi_mac *mac = container_of(napi, struct pasemi_mac, napi);
1614 	int pkts;
1615 
1616 	pasemi_mac_clean_tx(tx_ring(mac));
1617 	pkts = pasemi_mac_clean_rx(rx_ring(mac), budget);
1618 	if (pkts < budget) {
1619 		/* all done, no more packets present */
1620 		napi_complete(napi);
1621 
1622 		pasemi_mac_restart_rx_intr(mac);
1623 		pasemi_mac_restart_tx_intr(mac);
1624 	}
1625 	return pkts;
1626 }
1627 
1628 #ifdef CONFIG_NET_POLL_CONTROLLER
1629 /*
1630  * Polling 'interrupt' - used by things like netconsole to send skbs
1631  * without having to re-enable interrupts. It's not called while
1632  * the interrupt routine is executing.
1633  */
1634 static void pasemi_mac_netpoll(struct net_device *dev)
1635 {
1636 	const struct pasemi_mac *mac = netdev_priv(dev);
1637 
1638 	disable_irq(mac->tx->chan.irq);
1639 	pasemi_mac_tx_intr(mac->tx->chan.irq, mac->tx);
1640 	enable_irq(mac->tx->chan.irq);
1641 
1642 	disable_irq(mac->rx->chan.irq);
1643 	pasemi_mac_rx_intr(mac->rx->chan.irq, mac->rx);
1644 	enable_irq(mac->rx->chan.irq);
1645 }
1646 #endif
1647 
1648 static int pasemi_mac_change_mtu(struct net_device *dev, int new_mtu)
1649 {
1650 	struct pasemi_mac *mac = netdev_priv(dev);
1651 	unsigned int reg;
1652 	unsigned int rcmdsta = 0;
1653 	int running;
1654 	int ret = 0;
1655 
1656 	if (new_mtu < PE_MIN_MTU || new_mtu > PE_MAX_MTU)
1657 		return -EINVAL;
1658 
1659 	running = netif_running(dev);
1660 
1661 	if (running) {
1662 		/* Need to stop the interface, clean out all already
1663 		 * received buffers, free all unused buffers on the RX
1664 		 * interface ring, then finally re-fill the rx ring with
1665 		 * the new-size buffers and restart.
1666 		 */
1667 
1668 		napi_disable(&mac->napi);
1669 		netif_tx_disable(dev);
1670 		pasemi_mac_intf_disable(mac);
1671 
1672 		rcmdsta = read_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if));
1673 		pasemi_mac_pause_rxint(mac);
1674 		pasemi_mac_clean_rx(rx_ring(mac), RX_RING_SIZE);
1675 		pasemi_mac_free_rx_buffers(mac);
1676 
1677 	}
1678 
1679 	/* Setup checksum channels if large MTU and none already allocated */
1680 	if (new_mtu > 1500 && !mac->num_cs) {
1681 		pasemi_mac_setup_csrings(mac);
1682 		if (!mac->num_cs) {
1683 			ret = -ENOMEM;
1684 			goto out;
1685 		}
1686 	}
1687 
1688 	/* Change maxf, i.e. what size frames are accepted.
1689 	 * Need room for ethernet header and CRC word
1690 	 */
1691 	reg = read_mac_reg(mac, PAS_MAC_CFG_MACCFG);
1692 	reg &= ~PAS_MAC_CFG_MACCFG_MAXF_M;
1693 	reg |= PAS_MAC_CFG_MACCFG_MAXF(new_mtu + ETH_HLEN + 4);
1694 	write_mac_reg(mac, PAS_MAC_CFG_MACCFG, reg);
1695 
1696 	dev->mtu = new_mtu;
1697 	/* MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1698 	mac->bufsz = new_mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1699 
1700 out:
1701 	if (running) {
1702 		write_dma_reg(PAS_DMA_RXINT_RCMDSTA(mac->dma_if),
1703 			      rcmdsta | PAS_DMA_RXINT_RCMDSTA_EN);
1704 
1705 		rx_ring(mac)->next_to_fill = 0;
1706 		pasemi_mac_replenish_rx_ring(dev, RX_RING_SIZE-1);
1707 
1708 		napi_enable(&mac->napi);
1709 		netif_start_queue(dev);
1710 		pasemi_mac_intf_enable(mac);
1711 	}
1712 
1713 	return ret;
1714 }
1715 
1716 static const struct net_device_ops pasemi_netdev_ops = {
1717 	.ndo_open		= pasemi_mac_open,
1718 	.ndo_stop		= pasemi_mac_close,
1719 	.ndo_start_xmit		= pasemi_mac_start_tx,
1720 	.ndo_set_rx_mode	= pasemi_mac_set_rx_mode,
1721 	.ndo_set_mac_address	= pasemi_mac_set_mac_addr,
1722 	.ndo_change_mtu		= pasemi_mac_change_mtu,
1723 	.ndo_validate_addr	= eth_validate_addr,
1724 #ifdef CONFIG_NET_POLL_CONTROLLER
1725 	.ndo_poll_controller	= pasemi_mac_netpoll,
1726 #endif
1727 };
1728 
1729 static int
1730 pasemi_mac_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1731 {
1732 	struct net_device *dev;
1733 	struct pasemi_mac *mac;
1734 	int err, ret;
1735 
1736 	err = pci_enable_device(pdev);
1737 	if (err)
1738 		return err;
1739 
1740 	dev = alloc_etherdev(sizeof(struct pasemi_mac));
1741 	if (dev == NULL) {
1742 		err = -ENOMEM;
1743 		goto out_disable_device;
1744 	}
1745 
1746 	pci_set_drvdata(pdev, dev);
1747 	SET_NETDEV_DEV(dev, &pdev->dev);
1748 
1749 	mac = netdev_priv(dev);
1750 
1751 	mac->pdev = pdev;
1752 	mac->netdev = dev;
1753 
1754 	netif_napi_add(dev, &mac->napi, pasemi_mac_poll, 64);
1755 
1756 	dev->features = NETIF_F_IP_CSUM | NETIF_F_LLTX | NETIF_F_SG |
1757 			NETIF_F_HIGHDMA | NETIF_F_GSO;
1758 
1759 	mac->lro_mgr.max_aggr = LRO_MAX_AGGR;
1760 	mac->lro_mgr.max_desc = MAX_LRO_DESCRIPTORS;
1761 	mac->lro_mgr.lro_arr = mac->lro_desc;
1762 	mac->lro_mgr.get_skb_header = get_skb_hdr;
1763 	mac->lro_mgr.features = LRO_F_NAPI | LRO_F_EXTRACT_VLAN_ID;
1764 	mac->lro_mgr.dev = mac->netdev;
1765 	mac->lro_mgr.ip_summed = CHECKSUM_UNNECESSARY;
1766 	mac->lro_mgr.ip_summed_aggr = CHECKSUM_UNNECESSARY;
1767 
1768 
1769 	mac->dma_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa007, NULL);
1770 	if (!mac->dma_pdev) {
1771 		dev_err(&mac->pdev->dev, "Can't find DMA Controller\n");
1772 		err = -ENODEV;
1773 		goto out;
1774 	}
1775 
1776 	mac->iob_pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa001, NULL);
1777 	if (!mac->iob_pdev) {
1778 		dev_err(&mac->pdev->dev, "Can't find I/O Bridge\n");
1779 		err = -ENODEV;
1780 		goto out;
1781 	}
1782 
1783 	/* get mac addr from device tree */
1784 	if (pasemi_get_mac_addr(mac) || !is_valid_ether_addr(mac->mac_addr)) {
1785 		err = -ENODEV;
1786 		goto out;
1787 	}
1788 	memcpy(dev->dev_addr, mac->mac_addr, sizeof(mac->mac_addr));
1789 
1790 	ret = mac_to_intf(mac);
1791 	if (ret < 0) {
1792 		dev_err(&mac->pdev->dev, "Can't map DMA interface\n");
1793 		err = -ENODEV;
1794 		goto out;
1795 	}
1796 	mac->dma_if = ret;
1797 
1798 	switch (pdev->device) {
1799 	case 0xa005:
1800 		mac->type = MAC_TYPE_GMAC;
1801 		break;
1802 	case 0xa006:
1803 		mac->type = MAC_TYPE_XAUI;
1804 		break;
1805 	default:
1806 		err = -ENODEV;
1807 		goto out;
1808 	}
1809 
1810 	dev->netdev_ops = &pasemi_netdev_ops;
1811 	dev->mtu = PE_DEF_MTU;
1812 	/* 1500 MTU + ETH_HLEN + VLAN_HLEN + 2 64B cachelines */
1813 	mac->bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + LOCAL_SKB_ALIGN + 128;
1814 
1815 	dev->ethtool_ops = &pasemi_mac_ethtool_ops;
1816 
1817 	if (err)
1818 		goto out;
1819 
1820 	mac->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1821 
1822 	/* Enable most messages by default */
1823 	mac->msg_enable = (NETIF_MSG_IFUP << 1 ) - 1;
1824 
1825 	err = register_netdev(dev);
1826 
1827 	if (err) {
1828 		dev_err(&mac->pdev->dev, "register_netdev failed with error %d\n",
1829 			err);
1830 		goto out;
1831 	} else if (netif_msg_probe(mac)) {
1832 		printk(KERN_INFO "%s: PA Semi %s: intf %d, hw addr %pM\n",
1833 		       dev->name, mac->type == MAC_TYPE_GMAC ? "GMAC" : "XAUI",
1834 		       mac->dma_if, dev->dev_addr);
1835 	}
1836 
1837 	return err;
1838 
1839 out:
1840 	if (mac->iob_pdev)
1841 		pci_dev_put(mac->iob_pdev);
1842 	if (mac->dma_pdev)
1843 		pci_dev_put(mac->dma_pdev);
1844 
1845 	free_netdev(dev);
1846 out_disable_device:
1847 	pci_disable_device(pdev);
1848 	return err;
1849 
1850 }
1851 
1852 static void pasemi_mac_remove(struct pci_dev *pdev)
1853 {
1854 	struct net_device *netdev = pci_get_drvdata(pdev);
1855 	struct pasemi_mac *mac;
1856 
1857 	if (!netdev)
1858 		return;
1859 
1860 	mac = netdev_priv(netdev);
1861 
1862 	unregister_netdev(netdev);
1863 
1864 	pci_disable_device(pdev);
1865 	pci_dev_put(mac->dma_pdev);
1866 	pci_dev_put(mac->iob_pdev);
1867 
1868 	pasemi_dma_free_chan(&mac->tx->chan);
1869 	pasemi_dma_free_chan(&mac->rx->chan);
1870 
1871 	free_netdev(netdev);
1872 }
1873 
1874 static DEFINE_PCI_DEVICE_TABLE(pasemi_mac_pci_tbl) = {
1875 	{ PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa005) },
1876 	{ PCI_DEVICE(PCI_VENDOR_ID_PASEMI, 0xa006) },
1877 	{ },
1878 };
1879 
1880 MODULE_DEVICE_TABLE(pci, pasemi_mac_pci_tbl);
1881 
1882 static struct pci_driver pasemi_mac_driver = {
1883 	.name		= "pasemi_mac",
1884 	.id_table	= pasemi_mac_pci_tbl,
1885 	.probe		= pasemi_mac_probe,
1886 	.remove		= pasemi_mac_remove,
1887 };
1888 
1889 static void __exit pasemi_mac_cleanup_module(void)
1890 {
1891 	pci_unregister_driver(&pasemi_mac_driver);
1892 }
1893 
1894 int pasemi_mac_init_module(void)
1895 {
1896 	int err;
1897 
1898 	err = pasemi_dma_init();
1899 	if (err)
1900 		return err;
1901 
1902 	return pci_register_driver(&pasemi_mac_driver);
1903 }
1904 
1905 module_init(pasemi_mac_init_module);
1906 module_exit(pasemi_mac_cleanup_module);
1907