1 /* 2 * Copyright (C) 1999 - 2010 Intel Corporation. 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 * 5 * This code was derived from the Intel e1000e Linux driver. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; version 2 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #include "pch_gbe.h" 22 #include "pch_gbe_phy.h" 23 24 #define PHY_MAX_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 25 26 /* PHY 1000 MII Register/Bit Definitions */ 27 /* PHY Registers defined by IEEE */ 28 #define PHY_CONTROL 0x00 /* Control Register */ 29 #define PHY_STATUS 0x01 /* Status Regiser */ 30 #define PHY_ID1 0x02 /* Phy Id Register (word 1) */ 31 #define PHY_ID2 0x03 /* Phy Id Register (word 2) */ 32 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 33 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 34 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Register */ 35 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 36 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 37 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Register */ 38 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Register */ 39 #define PHY_EXT_STATUS 0x0F /* Extended Status Register */ 40 #define PHY_PHYSP_CONTROL 0x10 /* PHY Specific Control Register */ 41 #define PHY_EXT_PHYSP_CONTROL 0x14 /* Extended PHY Specific Control Register */ 42 #define PHY_LED_CONTROL 0x18 /* LED Control Register */ 43 #define PHY_EXT_PHYSP_STATUS 0x1B /* Extended PHY Specific Status Register */ 44 45 /* PHY Control Register */ 46 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 47 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 48 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 49 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 50 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 51 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 52 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 53 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 54 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 55 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 56 #define MII_CR_SPEED_1000 0x0040 57 #define MII_CR_SPEED_100 0x2000 58 #define MII_CR_SPEED_10 0x0000 59 60 /* PHY Status Register */ 61 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 62 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 63 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 64 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 65 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 66 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 67 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 68 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 69 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 70 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 71 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 72 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 73 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 74 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 75 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 76 77 /* AR8031 PHY Debug Registers */ 78 #define PHY_AR803X_ID 0x00001374 79 #define PHY_AR8031_DBG_OFF 0x1D 80 #define PHY_AR8031_DBG_DAT 0x1E 81 #define PHY_AR8031_SERDES 0x05 82 #define PHY_AR8031_HIBERNATE 0x0B 83 #define PHY_AR8031_SERDES_TX_CLK_DLY 0x0100 /* TX clock delay of 2.0ns */ 84 #define PHY_AR8031_PS_HIB_EN 0x8000 /* Hibernate enable */ 85 86 /* Phy Id Register (word 2) */ 87 #define PHY_REVISION_MASK 0x000F 88 89 /* PHY Specific Control Register */ 90 #define PHYSP_CTRL_ASSERT_CRS_TX 0x0800 91 92 93 /* Default value of PHY register */ 94 #define PHY_CONTROL_DEFAULT 0x1140 /* Control Register */ 95 #define PHY_AUTONEG_ADV_DEFAULT 0x01e0 /* Autoneg Advertisement */ 96 #define PHY_NEXT_PAGE_TX_DEFAULT 0x2001 /* Next Page TX */ 97 #define PHY_1000T_CTRL_DEFAULT 0x0300 /* 1000Base-T Control Register */ 98 #define PHY_PHYSP_CONTROL_DEFAULT 0x01EE /* PHY Specific Control Register */ 99 100 /** 101 * pch_gbe_phy_get_id - Retrieve the PHY ID and revision 102 * @hw: Pointer to the HW structure 103 * Returns 104 * 0: Successful. 105 * Negative value: Failed. 106 */ 107 s32 pch_gbe_phy_get_id(struct pch_gbe_hw *hw) 108 { 109 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 110 struct pch_gbe_phy_info *phy = &hw->phy; 111 s32 ret; 112 u16 phy_id1; 113 u16 phy_id2; 114 115 ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID1, &phy_id1); 116 if (ret) 117 return ret; 118 ret = pch_gbe_phy_read_reg_miic(hw, PHY_ID2, &phy_id2); 119 if (ret) 120 return ret; 121 /* 122 * PHY_ID1: [bit15-0:ID(21-6)] 123 * PHY_ID2: [bit15-10:ID(5-0)][bit9-4:Model][bit3-0:revision] 124 */ 125 phy->id = (u32)phy_id1; 126 phy->id = ((phy->id << 6) | ((phy_id2 & 0xFC00) >> 10)); 127 phy->revision = (u32) (phy_id2 & 0x000F); 128 netdev_dbg(adapter->netdev, 129 "phy->id : 0x%08x phy->revision : 0x%08x\n", 130 phy->id, phy->revision); 131 return 0; 132 } 133 134 /** 135 * pch_gbe_phy_read_reg_miic - Read MII control register 136 * @hw: Pointer to the HW structure 137 * @offset: Register offset to be read 138 * @data: Pointer to the read data 139 * Returns 140 * 0: Successful. 141 * -EINVAL: Invalid argument. 142 */ 143 s32 pch_gbe_phy_read_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 *data) 144 { 145 struct pch_gbe_phy_info *phy = &hw->phy; 146 147 if (offset > PHY_MAX_REG_ADDRESS) { 148 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 149 150 netdev_err(adapter->netdev, "PHY Address %d is out of range\n", 151 offset); 152 return -EINVAL; 153 } 154 *data = pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_READ, 155 offset, (u16)0); 156 return 0; 157 } 158 159 /** 160 * pch_gbe_phy_write_reg_miic - Write MII control register 161 * @hw: Pointer to the HW structure 162 * @offset: Register offset to be read 163 * @data: data to write to register at offset 164 * Returns 165 * 0: Successful. 166 * -EINVAL: Invalid argument. 167 */ 168 s32 pch_gbe_phy_write_reg_miic(struct pch_gbe_hw *hw, u32 offset, u16 data) 169 { 170 struct pch_gbe_phy_info *phy = &hw->phy; 171 172 if (offset > PHY_MAX_REG_ADDRESS) { 173 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 174 175 netdev_err(adapter->netdev, "PHY Address %d is out of range\n", 176 offset); 177 return -EINVAL; 178 } 179 pch_gbe_mac_ctrl_miim(hw, phy->addr, PCH_GBE_HAL_MIIM_WRITE, 180 offset, data); 181 return 0; 182 } 183 184 /** 185 * pch_gbe_phy_sw_reset - PHY software reset 186 * @hw: Pointer to the HW structure 187 */ 188 void pch_gbe_phy_sw_reset(struct pch_gbe_hw *hw) 189 { 190 u16 phy_ctrl; 191 192 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &phy_ctrl); 193 phy_ctrl |= MII_CR_RESET; 194 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, phy_ctrl); 195 udelay(1); 196 } 197 198 /** 199 * pch_gbe_phy_hw_reset - PHY hardware reset 200 * @hw: Pointer to the HW structure 201 */ 202 void pch_gbe_phy_hw_reset(struct pch_gbe_hw *hw) 203 { 204 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, PHY_CONTROL_DEFAULT); 205 pch_gbe_phy_write_reg_miic(hw, PHY_AUTONEG_ADV, 206 PHY_AUTONEG_ADV_DEFAULT); 207 pch_gbe_phy_write_reg_miic(hw, PHY_NEXT_PAGE_TX, 208 PHY_NEXT_PAGE_TX_DEFAULT); 209 pch_gbe_phy_write_reg_miic(hw, PHY_1000T_CTRL, PHY_1000T_CTRL_DEFAULT); 210 pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, 211 PHY_PHYSP_CONTROL_DEFAULT); 212 } 213 214 /** 215 * pch_gbe_phy_power_up - restore link in case the phy was powered down 216 * @hw: Pointer to the HW structure 217 */ 218 void pch_gbe_phy_power_up(struct pch_gbe_hw *hw) 219 { 220 u16 mii_reg; 221 222 mii_reg = 0; 223 /* Just clear the power down bit to wake the phy back up */ 224 /* according to the manual, the phy will retain its 225 * settings across a power-down/up cycle */ 226 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); 227 mii_reg &= ~MII_CR_POWER_DOWN; 228 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); 229 } 230 231 /** 232 * pch_gbe_phy_power_down - Power down PHY 233 * @hw: Pointer to the HW structure 234 */ 235 void pch_gbe_phy_power_down(struct pch_gbe_hw *hw) 236 { 237 u16 mii_reg; 238 239 mii_reg = 0; 240 /* Power down the PHY so no link is implied when interface is down * 241 * The PHY cannot be powered down if any of the following is TRUE * 242 * (a) WoL is enabled 243 * (b) AMT is active 244 */ 245 pch_gbe_phy_read_reg_miic(hw, PHY_CONTROL, &mii_reg); 246 mii_reg |= MII_CR_POWER_DOWN; 247 pch_gbe_phy_write_reg_miic(hw, PHY_CONTROL, mii_reg); 248 mdelay(1); 249 } 250 251 /** 252 * pch_gbe_phy_set_rgmii - RGMII interface setting 253 * @hw: Pointer to the HW structure 254 */ 255 void pch_gbe_phy_set_rgmii(struct pch_gbe_hw *hw) 256 { 257 pch_gbe_phy_sw_reset(hw); 258 } 259 260 /** 261 * pch_gbe_phy_tx_clk_delay - Setup TX clock delay via the PHY 262 * @hw: Pointer to the HW structure 263 * Returns 264 * 0: Successful. 265 * -EINVAL: Invalid argument. 266 */ 267 static int pch_gbe_phy_tx_clk_delay(struct pch_gbe_hw *hw) 268 { 269 /* The RGMII interface requires a ~2ns TX clock delay. This is typically 270 * done in layout with a longer trace or via PHY strapping, but can also 271 * be done via PHY configuration registers. 272 */ 273 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 274 u16 mii_reg; 275 int ret = 0; 276 277 switch (hw->phy.id) { 278 case PHY_AR803X_ID: 279 netdev_dbg(adapter->netdev, 280 "Configuring AR803X PHY for 2ns TX clock delay\n"); 281 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_OFF, &mii_reg); 282 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF, 283 PHY_AR8031_SERDES); 284 if (ret) 285 break; 286 287 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg); 288 mii_reg |= PHY_AR8031_SERDES_TX_CLK_DLY; 289 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT, 290 mii_reg); 291 break; 292 default: 293 netdev_err(adapter->netdev, 294 "Unknown PHY (%x), could not set TX clock delay\n", 295 hw->phy.id); 296 return -EINVAL; 297 } 298 299 if (ret) 300 netdev_err(adapter->netdev, 301 "Could not configure tx clock delay for PHY\n"); 302 return ret; 303 } 304 305 /** 306 * pch_gbe_phy_init_setting - PHY initial setting 307 * @hw: Pointer to the HW structure 308 */ 309 void pch_gbe_phy_init_setting(struct pch_gbe_hw *hw) 310 { 311 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 312 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 313 int ret; 314 u16 mii_reg; 315 316 ret = mii_ethtool_gset(&adapter->mii, &cmd); 317 if (ret) 318 netdev_err(adapter->netdev, "Error: mii_ethtool_gset\n"); 319 320 ethtool_cmd_speed_set(&cmd, hw->mac.link_speed); 321 cmd.duplex = hw->mac.link_duplex; 322 cmd.advertising = hw->phy.autoneg_advertised; 323 cmd.autoneg = hw->mac.autoneg; 324 pch_gbe_phy_write_reg_miic(hw, MII_BMCR, BMCR_RESET); 325 ret = mii_ethtool_sset(&adapter->mii, &cmd); 326 if (ret) 327 netdev_err(adapter->netdev, "Error: mii_ethtool_sset\n"); 328 329 pch_gbe_phy_sw_reset(hw); 330 331 pch_gbe_phy_read_reg_miic(hw, PHY_PHYSP_CONTROL, &mii_reg); 332 mii_reg |= PHYSP_CTRL_ASSERT_CRS_TX; 333 pch_gbe_phy_write_reg_miic(hw, PHY_PHYSP_CONTROL, mii_reg); 334 335 /* Setup a TX clock delay on certain platforms */ 336 if (adapter->pdata && adapter->pdata->phy_tx_clk_delay) 337 pch_gbe_phy_tx_clk_delay(hw); 338 } 339 340 /** 341 * pch_gbe_phy_disable_hibernate - Disable the PHY low power state 342 * @hw: Pointer to the HW structure 343 * Returns 344 * 0: Successful. 345 * -EINVAL: Invalid argument. 346 */ 347 int pch_gbe_phy_disable_hibernate(struct pch_gbe_hw *hw) 348 { 349 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 350 u16 mii_reg; 351 int ret = 0; 352 353 switch (hw->phy.id) { 354 case PHY_AR803X_ID: 355 netdev_dbg(adapter->netdev, 356 "Disabling hibernation for AR803X PHY\n"); 357 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_OFF, 358 PHY_AR8031_HIBERNATE); 359 if (ret) 360 break; 361 362 pch_gbe_phy_read_reg_miic(hw, PHY_AR8031_DBG_DAT, &mii_reg); 363 mii_reg &= ~PHY_AR8031_PS_HIB_EN; 364 ret = pch_gbe_phy_write_reg_miic(hw, PHY_AR8031_DBG_DAT, 365 mii_reg); 366 break; 367 default: 368 netdev_err(adapter->netdev, 369 "Unknown PHY (%x), could not disable hibernation\n", 370 hw->phy.id); 371 return -EINVAL; 372 } 373 374 if (ret) 375 netdev_err(adapter->netdev, 376 "Could not disable PHY hibernation\n"); 377 return ret; 378 } 379