1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 1999 - 2010 Intel Corporation. 4 * Copyright (C) 2010 - 2012 LAPIS SEMICONDUCTOR CO., LTD. 5 * 6 * This code was derived from the Intel e1000e Linux driver. 7 */ 8 9 #include "pch_gbe.h" 10 #include "pch_gbe_phy.h" 11 12 #include <linux/gpio/consumer.h> 13 #include <linux/gpio/machine.h> 14 #include <linux/iopoll.h> 15 #include <linux/module.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/ptp_classify.h> 18 #include <linux/ptp_pch.h> 19 #include <linux/gpio.h> 20 21 #define PCH_GBE_MAR_ENTRIES 16 22 #define PCH_GBE_SHORT_PKT 64 23 #define DSC_INIT16 0xC000 24 #define PCH_GBE_DMA_ALIGN 0 25 #define PCH_GBE_DMA_PADDING 2 26 #define PCH_GBE_WATCHDOG_PERIOD (5 * HZ) /* watchdog time */ 27 #define PCH_GBE_PCI_BAR 1 28 #define PCH_GBE_RESERVE_MEMORY 0x200000 /* 2MB */ 29 30 #define PCI_DEVICE_ID_INTEL_IOH1_GBE 0x8802 31 32 #define PCI_DEVICE_ID_ROHM_ML7223_GBE 0x8013 33 #define PCI_DEVICE_ID_ROHM_ML7831_GBE 0x8802 34 35 #define PCH_GBE_TX_WEIGHT 64 36 #define PCH_GBE_RX_WEIGHT 64 37 #define PCH_GBE_RX_BUFFER_WRITE 16 38 39 /* Initialize the wake-on-LAN settings */ 40 #define PCH_GBE_WL_INIT_SETTING (PCH_GBE_WLC_MP) 41 42 #define PCH_GBE_MAC_RGMII_CTRL_SETTING ( \ 43 PCH_GBE_CHIP_TYPE_INTERNAL | \ 44 PCH_GBE_RGMII_MODE_RGMII \ 45 ) 46 47 /* Ethertype field values */ 48 #define PCH_GBE_MAX_RX_BUFFER_SIZE 0x2880 49 #define PCH_GBE_MAX_JUMBO_FRAME_SIZE 10318 50 #define PCH_GBE_FRAME_SIZE_2048 2048 51 #define PCH_GBE_FRAME_SIZE_4096 4096 52 #define PCH_GBE_FRAME_SIZE_8192 8192 53 54 #define PCH_GBE_GET_DESC(R, i, type) (&(((struct type *)((R).desc))[i])) 55 #define PCH_GBE_RX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_rx_desc) 56 #define PCH_GBE_TX_DESC(R, i) PCH_GBE_GET_DESC(R, i, pch_gbe_tx_desc) 57 #define PCH_GBE_DESC_UNUSED(R) \ 58 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \ 59 (R)->next_to_clean - (R)->next_to_use - 1) 60 61 /* Pause packet value */ 62 #define PCH_GBE_PAUSE_PKT1_VALUE 0x00C28001 63 #define PCH_GBE_PAUSE_PKT2_VALUE 0x00000100 64 #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 65 #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF 66 67 68 /* This defines the bits that are set in the Interrupt Mask 69 * Set/Read Register. Each bit is documented below: 70 * o RXT0 = Receiver Timer Interrupt (ring 0) 71 * o TXDW = Transmit Descriptor Written Back 72 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 73 * o RXSEQ = Receive Sequence Error 74 * o LSC = Link Status Change 75 */ 76 #define PCH_GBE_INT_ENABLE_MASK ( \ 77 PCH_GBE_INT_RX_DMA_CMPLT | \ 78 PCH_GBE_INT_RX_DSC_EMP | \ 79 PCH_GBE_INT_RX_FIFO_ERR | \ 80 PCH_GBE_INT_WOL_DET | \ 81 PCH_GBE_INT_TX_CMPLT \ 82 ) 83 84 #define PCH_GBE_INT_DISABLE_ALL 0 85 86 /* Macros for ieee1588 */ 87 /* 0x40 Time Synchronization Channel Control Register Bits */ 88 #define MASTER_MODE (1<<0) 89 #define SLAVE_MODE (0) 90 #define V2_MODE (1<<31) 91 #define CAP_MODE0 (0) 92 #define CAP_MODE2 (1<<17) 93 94 /* 0x44 Time Synchronization Channel Event Register Bits */ 95 #define TX_SNAPSHOT_LOCKED (1<<0) 96 #define RX_SNAPSHOT_LOCKED (1<<1) 97 98 #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81" 99 #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00" 100 101 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); 102 static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, 103 int data); 104 static void pch_gbe_set_multi(struct net_device *netdev); 105 106 static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) 107 { 108 u8 *data = skb->data; 109 unsigned int offset; 110 u16 hi, id; 111 u32 lo; 112 113 if (ptp_classify_raw(skb) == PTP_CLASS_NONE) 114 return 0; 115 116 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; 117 118 if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid)) 119 return 0; 120 121 hi = get_unaligned_be16(data + offset + OFF_PTP_SOURCE_UUID + 0); 122 lo = get_unaligned_be32(data + offset + OFF_PTP_SOURCE_UUID + 2); 123 id = get_unaligned_be16(data + offset + OFF_PTP_SEQUENCE_ID); 124 125 return (uid_hi == hi && uid_lo == lo && seqid == id); 126 } 127 128 static void 129 pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 130 { 131 struct skb_shared_hwtstamps *shhwtstamps; 132 struct pci_dev *pdev; 133 u64 ns; 134 u32 hi, lo, val; 135 136 if (!adapter->hwts_rx_en) 137 return; 138 139 /* Get ieee1588's dev information */ 140 pdev = adapter->ptp_pdev; 141 142 val = pch_ch_event_read(pdev); 143 144 if (!(val & RX_SNAPSHOT_LOCKED)) 145 return; 146 147 lo = pch_src_uuid_lo_read(pdev); 148 hi = pch_src_uuid_hi_read(pdev); 149 150 if (!pch_ptp_match(skb, hi, lo, hi >> 16)) 151 goto out; 152 153 ns = pch_rx_snap_read(pdev); 154 155 shhwtstamps = skb_hwtstamps(skb); 156 memset(shhwtstamps, 0, sizeof(*shhwtstamps)); 157 shhwtstamps->hwtstamp = ns_to_ktime(ns); 158 out: 159 pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); 160 } 161 162 static void 163 pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) 164 { 165 struct skb_shared_hwtstamps shhwtstamps; 166 struct pci_dev *pdev; 167 struct skb_shared_info *shtx; 168 u64 ns; 169 u32 cnt, val; 170 171 shtx = skb_shinfo(skb); 172 if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))) 173 return; 174 175 shtx->tx_flags |= SKBTX_IN_PROGRESS; 176 177 /* Get ieee1588's dev information */ 178 pdev = adapter->ptp_pdev; 179 180 /* 181 * This really stinks, but we have to poll for the Tx time stamp. 182 */ 183 for (cnt = 0; cnt < 100; cnt++) { 184 val = pch_ch_event_read(pdev); 185 if (val & TX_SNAPSHOT_LOCKED) 186 break; 187 udelay(1); 188 } 189 if (!(val & TX_SNAPSHOT_LOCKED)) { 190 shtx->tx_flags &= ~SKBTX_IN_PROGRESS; 191 return; 192 } 193 194 ns = pch_tx_snap_read(pdev); 195 196 memset(&shhwtstamps, 0, sizeof(shhwtstamps)); 197 shhwtstamps.hwtstamp = ns_to_ktime(ns); 198 skb_tstamp_tx(skb, &shhwtstamps); 199 200 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED); 201 } 202 203 static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 204 { 205 struct hwtstamp_config cfg; 206 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 207 struct pci_dev *pdev; 208 u8 station[20]; 209 210 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 211 return -EFAULT; 212 213 if (cfg.flags) /* reserved for future extensions */ 214 return -EINVAL; 215 216 /* Get ieee1588's dev information */ 217 pdev = adapter->ptp_pdev; 218 219 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 220 return -ERANGE; 221 222 switch (cfg.rx_filter) { 223 case HWTSTAMP_FILTER_NONE: 224 adapter->hwts_rx_en = 0; 225 break; 226 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 227 adapter->hwts_rx_en = 0; 228 pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0); 229 break; 230 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 231 adapter->hwts_rx_en = 1; 232 pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0); 233 break; 234 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 235 adapter->hwts_rx_en = 1; 236 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 237 strcpy(station, PTP_L4_MULTICAST_SA); 238 pch_set_station_address(station, pdev); 239 break; 240 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 241 adapter->hwts_rx_en = 1; 242 pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); 243 strcpy(station, PTP_L2_MULTICAST_SA); 244 pch_set_station_address(station, pdev); 245 break; 246 default: 247 return -ERANGE; 248 } 249 250 adapter->hwts_tx_en = cfg.tx_type == HWTSTAMP_TX_ON; 251 252 /* Clear out any old time stamps. */ 253 pch_ch_event_write(pdev, TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED); 254 255 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 256 } 257 258 static inline void pch_gbe_mac_load_mac_addr(struct pch_gbe_hw *hw) 259 { 260 iowrite32(0x01, &hw->reg->MAC_ADDR_LOAD); 261 } 262 263 /** 264 * pch_gbe_mac_read_mac_addr - Read MAC address 265 * @hw: Pointer to the HW structure 266 * Returns: 267 * 0: Successful. 268 */ 269 static s32 pch_gbe_mac_read_mac_addr(struct pch_gbe_hw *hw) 270 { 271 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 272 u32 adr1a, adr1b; 273 274 adr1a = ioread32(&hw->reg->mac_adr[0].high); 275 adr1b = ioread32(&hw->reg->mac_adr[0].low); 276 277 hw->mac.addr[0] = (u8)(adr1a & 0xFF); 278 hw->mac.addr[1] = (u8)((adr1a >> 8) & 0xFF); 279 hw->mac.addr[2] = (u8)((adr1a >> 16) & 0xFF); 280 hw->mac.addr[3] = (u8)((adr1a >> 24) & 0xFF); 281 hw->mac.addr[4] = (u8)(adr1b & 0xFF); 282 hw->mac.addr[5] = (u8)((adr1b >> 8) & 0xFF); 283 284 netdev_dbg(adapter->netdev, "hw->mac.addr : %pM\n", hw->mac.addr); 285 return 0; 286 } 287 288 /** 289 * pch_gbe_wait_clr_bit - Wait to clear a bit 290 * @reg: Pointer of register 291 * @bit: Busy bit 292 */ 293 static void pch_gbe_wait_clr_bit(void __iomem *reg, u32 bit) 294 { 295 u32 tmp; 296 297 /* wait busy */ 298 if (readx_poll_timeout_atomic(ioread32, reg, tmp, !(tmp & bit), 0, 10)) 299 pr_err("Error: busy bit is not cleared\n"); 300 } 301 302 /** 303 * pch_gbe_mac_mar_set - Set MAC address register 304 * @hw: Pointer to the HW structure 305 * @addr: Pointer to the MAC address 306 * @index: MAC address array register 307 */ 308 static void pch_gbe_mac_mar_set(struct pch_gbe_hw *hw, u8 * addr, u32 index) 309 { 310 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 311 u32 mar_low, mar_high, adrmask; 312 313 netdev_dbg(adapter->netdev, "index : 0x%x\n", index); 314 315 /* 316 * HW expects these in little endian so we reverse the byte order 317 * from network order (big endian) to little endian 318 */ 319 mar_high = ((u32) addr[0] | ((u32) addr[1] << 8) | 320 ((u32) addr[2] << 16) | ((u32) addr[3] << 24)); 321 mar_low = ((u32) addr[4] | ((u32) addr[5] << 8)); 322 /* Stop the MAC Address of index. */ 323 adrmask = ioread32(&hw->reg->ADDR_MASK); 324 iowrite32((adrmask | (0x0001 << index)), &hw->reg->ADDR_MASK); 325 /* wait busy */ 326 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 327 /* Set the MAC address to the MAC address 1A/1B register */ 328 iowrite32(mar_high, &hw->reg->mac_adr[index].high); 329 iowrite32(mar_low, &hw->reg->mac_adr[index].low); 330 /* Start the MAC address of index */ 331 iowrite32((adrmask & ~(0x0001 << index)), &hw->reg->ADDR_MASK); 332 /* wait busy */ 333 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 334 } 335 336 /** 337 * pch_gbe_mac_reset_hw - Reset hardware 338 * @hw: Pointer to the HW structure 339 */ 340 static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) 341 { 342 /* Read the MAC address. and store to the private data */ 343 pch_gbe_mac_read_mac_addr(hw); 344 iowrite32(PCH_GBE_ALL_RST, &hw->reg->RESET); 345 iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); 346 pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); 347 /* Setup the receive addresses */ 348 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 349 return; 350 } 351 352 static void pch_gbe_disable_mac_rx(struct pch_gbe_hw *hw) 353 { 354 u32 rctl; 355 /* Disables Receive MAC */ 356 rctl = ioread32(&hw->reg->MAC_RX_EN); 357 iowrite32((rctl & ~PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 358 } 359 360 static void pch_gbe_enable_mac_rx(struct pch_gbe_hw *hw) 361 { 362 u32 rctl; 363 /* Enables Receive MAC */ 364 rctl = ioread32(&hw->reg->MAC_RX_EN); 365 iowrite32((rctl | PCH_GBE_MRE_MAC_RX_EN), &hw->reg->MAC_RX_EN); 366 } 367 368 /** 369 * pch_gbe_mac_init_rx_addrs - Initialize receive address's 370 * @hw: Pointer to the HW structure 371 * @mar_count: Receive address registers 372 */ 373 static void pch_gbe_mac_init_rx_addrs(struct pch_gbe_hw *hw, u16 mar_count) 374 { 375 u32 i; 376 377 /* Setup the receive address */ 378 pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); 379 380 /* Zero out the other receive addresses */ 381 for (i = 1; i < mar_count; i++) { 382 iowrite32(0, &hw->reg->mac_adr[i].high); 383 iowrite32(0, &hw->reg->mac_adr[i].low); 384 } 385 iowrite32(0xFFFE, &hw->reg->ADDR_MASK); 386 /* wait busy */ 387 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 388 } 389 390 /** 391 * pch_gbe_mac_force_mac_fc - Force the MAC's flow control settings 392 * @hw: Pointer to the HW structure 393 * Returns: 394 * 0: Successful. 395 * Negative value: Failed. 396 */ 397 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw) 398 { 399 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 400 struct pch_gbe_mac_info *mac = &hw->mac; 401 u32 rx_fctrl; 402 403 netdev_dbg(adapter->netdev, "mac->fc = %u\n", mac->fc); 404 405 rx_fctrl = ioread32(&hw->reg->RX_FCTRL); 406 407 switch (mac->fc) { 408 case PCH_GBE_FC_NONE: 409 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 410 mac->tx_fc_enable = false; 411 break; 412 case PCH_GBE_FC_RX_PAUSE: 413 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 414 mac->tx_fc_enable = false; 415 break; 416 case PCH_GBE_FC_TX_PAUSE: 417 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 418 mac->tx_fc_enable = true; 419 break; 420 case PCH_GBE_FC_FULL: 421 rx_fctrl |= PCH_GBE_FL_CTRL_EN; 422 mac->tx_fc_enable = true; 423 break; 424 default: 425 netdev_err(adapter->netdev, 426 "Flow control param set incorrectly\n"); 427 return -EINVAL; 428 } 429 if (mac->link_duplex == DUPLEX_HALF) 430 rx_fctrl &= ~PCH_GBE_FL_CTRL_EN; 431 iowrite32(rx_fctrl, &hw->reg->RX_FCTRL); 432 netdev_dbg(adapter->netdev, 433 "RX_FCTRL reg : 0x%08x mac->tx_fc_enable : %d\n", 434 ioread32(&hw->reg->RX_FCTRL), mac->tx_fc_enable); 435 return 0; 436 } 437 438 /** 439 * pch_gbe_mac_set_wol_event - Set wake-on-lan event 440 * @hw: Pointer to the HW structure 441 * @wu_evt: Wake up event 442 */ 443 static void pch_gbe_mac_set_wol_event(struct pch_gbe_hw *hw, u32 wu_evt) 444 { 445 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 446 u32 addr_mask; 447 448 netdev_dbg(adapter->netdev, "wu_evt : 0x%08x ADDR_MASK reg : 0x%08x\n", 449 wu_evt, ioread32(&hw->reg->ADDR_MASK)); 450 451 if (wu_evt) { 452 /* Set Wake-On-Lan address mask */ 453 addr_mask = ioread32(&hw->reg->ADDR_MASK); 454 iowrite32(addr_mask, &hw->reg->WOL_ADDR_MASK); 455 /* wait busy */ 456 pch_gbe_wait_clr_bit(&hw->reg->WOL_ADDR_MASK, PCH_GBE_WLA_BUSY); 457 iowrite32(0, &hw->reg->WOL_ST); 458 iowrite32((wu_evt | PCH_GBE_WLC_WOL_MODE), &hw->reg->WOL_CTRL); 459 iowrite32(0x02, &hw->reg->TCPIP_ACC); 460 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 461 } else { 462 iowrite32(0, &hw->reg->WOL_CTRL); 463 iowrite32(0, &hw->reg->WOL_ST); 464 } 465 return; 466 } 467 468 /** 469 * pch_gbe_mac_ctrl_miim - Control MIIM interface 470 * @hw: Pointer to the HW structure 471 * @addr: Address of PHY 472 * @dir: Operetion. (Write or Read) 473 * @reg: Access register of PHY 474 * @data: Write data. 475 * 476 * Returns: Read date. 477 */ 478 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg, 479 u16 data) 480 { 481 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 482 unsigned long flags; 483 u32 data_out; 484 485 spin_lock_irqsave(&hw->miim_lock, flags); 486 487 if (readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 488 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000)) { 489 netdev_err(adapter->netdev, "pch-gbe.miim won't go Ready\n"); 490 spin_unlock_irqrestore(&hw->miim_lock, flags); 491 return 0; /* No way to indicate timeout error */ 492 } 493 iowrite32(((reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) | 494 (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) | 495 dir | data), &hw->reg->MIIM); 496 readx_poll_timeout_atomic(ioread32, &hw->reg->MIIM, data_out, 497 data_out & PCH_GBE_MIIM_OPER_READY, 20, 2000); 498 spin_unlock_irqrestore(&hw->miim_lock, flags); 499 500 netdev_dbg(adapter->netdev, "PHY %s: reg=%d, data=0x%04X\n", 501 dir == PCH_GBE_MIIM_OPER_READ ? "READ" : "WRITE", reg, 502 dir == PCH_GBE_MIIM_OPER_READ ? data_out : data); 503 return (u16) data_out; 504 } 505 506 /** 507 * pch_gbe_mac_set_pause_packet - Set pause packet 508 * @hw: Pointer to the HW structure 509 */ 510 static void pch_gbe_mac_set_pause_packet(struct pch_gbe_hw *hw) 511 { 512 struct pch_gbe_adapter *adapter = pch_gbe_hw_to_adapter(hw); 513 unsigned long tmp2, tmp3; 514 515 /* Set Pause packet */ 516 tmp2 = hw->mac.addr[1]; 517 tmp2 = (tmp2 << 8) | hw->mac.addr[0]; 518 tmp2 = PCH_GBE_PAUSE_PKT2_VALUE | (tmp2 << 16); 519 520 tmp3 = hw->mac.addr[5]; 521 tmp3 = (tmp3 << 8) | hw->mac.addr[4]; 522 tmp3 = (tmp3 << 8) | hw->mac.addr[3]; 523 tmp3 = (tmp3 << 8) | hw->mac.addr[2]; 524 525 iowrite32(PCH_GBE_PAUSE_PKT1_VALUE, &hw->reg->PAUSE_PKT1); 526 iowrite32(tmp2, &hw->reg->PAUSE_PKT2); 527 iowrite32(tmp3, &hw->reg->PAUSE_PKT3); 528 iowrite32(PCH_GBE_PAUSE_PKT4_VALUE, &hw->reg->PAUSE_PKT4); 529 iowrite32(PCH_GBE_PAUSE_PKT5_VALUE, &hw->reg->PAUSE_PKT5); 530 531 /* Transmit Pause Packet */ 532 iowrite32(PCH_GBE_PS_PKT_RQ, &hw->reg->PAUSE_REQ); 533 534 netdev_dbg(adapter->netdev, 535 "PAUSE_PKT1-5 reg : 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 536 ioread32(&hw->reg->PAUSE_PKT1), 537 ioread32(&hw->reg->PAUSE_PKT2), 538 ioread32(&hw->reg->PAUSE_PKT3), 539 ioread32(&hw->reg->PAUSE_PKT4), 540 ioread32(&hw->reg->PAUSE_PKT5)); 541 542 return; 543 } 544 545 546 /** 547 * pch_gbe_alloc_queues - Allocate memory for all rings 548 * @adapter: Board private structure to initialize 549 * Returns: 550 * 0: Successfully 551 * Negative value: Failed 552 */ 553 static int pch_gbe_alloc_queues(struct pch_gbe_adapter *adapter) 554 { 555 adapter->tx_ring = devm_kzalloc(&adapter->pdev->dev, 556 sizeof(*adapter->tx_ring), GFP_KERNEL); 557 if (!adapter->tx_ring) 558 return -ENOMEM; 559 560 adapter->rx_ring = devm_kzalloc(&adapter->pdev->dev, 561 sizeof(*adapter->rx_ring), GFP_KERNEL); 562 if (!adapter->rx_ring) 563 return -ENOMEM; 564 return 0; 565 } 566 567 /** 568 * pch_gbe_init_stats - Initialize status 569 * @adapter: Board private structure to initialize 570 */ 571 static void pch_gbe_init_stats(struct pch_gbe_adapter *adapter) 572 { 573 memset(&adapter->stats, 0, sizeof(adapter->stats)); 574 return; 575 } 576 577 /** 578 * pch_gbe_init_phy - Initialize PHY 579 * @adapter: Board private structure to initialize 580 * Returns: 581 * 0: Successfully 582 * Negative value: Failed 583 */ 584 static int pch_gbe_init_phy(struct pch_gbe_adapter *adapter) 585 { 586 struct net_device *netdev = adapter->netdev; 587 u32 addr; 588 u16 bmcr, stat; 589 590 /* Discover phy addr by searching addrs in order {1,0,2,..., 31} */ 591 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 592 adapter->mii.phy_id = (addr == 0) ? 1 : (addr == 1) ? 0 : addr; 593 bmcr = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMCR); 594 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 595 stat = pch_gbe_mdio_read(netdev, adapter->mii.phy_id, MII_BMSR); 596 if (!((bmcr == 0xFFFF) || ((stat == 0) && (bmcr == 0)))) 597 break; 598 } 599 adapter->hw.phy.addr = adapter->mii.phy_id; 600 netdev_dbg(netdev, "phy_addr = %d\n", adapter->mii.phy_id); 601 if (addr == PCH_GBE_PHY_REGS_LEN) 602 return -EAGAIN; 603 /* Selected the phy and isolate the rest */ 604 for (addr = 0; addr < PCH_GBE_PHY_REGS_LEN; addr++) { 605 if (addr != adapter->mii.phy_id) { 606 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 607 BMCR_ISOLATE); 608 } else { 609 bmcr = pch_gbe_mdio_read(netdev, addr, MII_BMCR); 610 pch_gbe_mdio_write(netdev, addr, MII_BMCR, 611 bmcr & ~BMCR_ISOLATE); 612 } 613 } 614 615 /* MII setup */ 616 adapter->mii.phy_id_mask = 0x1F; 617 adapter->mii.reg_num_mask = 0x1F; 618 adapter->mii.dev = adapter->netdev; 619 adapter->mii.mdio_read = pch_gbe_mdio_read; 620 adapter->mii.mdio_write = pch_gbe_mdio_write; 621 adapter->mii.supports_gmii = mii_check_gmii_support(&adapter->mii); 622 return 0; 623 } 624 625 /** 626 * pch_gbe_mdio_read - The read function for mii 627 * @netdev: Network interface device structure 628 * @addr: Phy ID 629 * @reg: Access location 630 * Returns: 631 * 0: Successfully 632 * Negative value: Failed 633 */ 634 static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg) 635 { 636 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 637 struct pch_gbe_hw *hw = &adapter->hw; 638 639 return pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_READ, reg, 640 (u16) 0); 641 } 642 643 /** 644 * pch_gbe_mdio_write - The write function for mii 645 * @netdev: Network interface device structure 646 * @addr: Phy ID (not used) 647 * @reg: Access location 648 * @data: Write data 649 */ 650 static void pch_gbe_mdio_write(struct net_device *netdev, 651 int addr, int reg, int data) 652 { 653 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 654 struct pch_gbe_hw *hw = &adapter->hw; 655 656 pch_gbe_mac_ctrl_miim(hw, addr, PCH_GBE_HAL_MIIM_WRITE, reg, data); 657 } 658 659 /** 660 * pch_gbe_reset_task - Reset processing at the time of transmission timeout 661 * @work: Pointer of board private structure 662 */ 663 static void pch_gbe_reset_task(struct work_struct *work) 664 { 665 struct pch_gbe_adapter *adapter; 666 adapter = container_of(work, struct pch_gbe_adapter, reset_task); 667 668 rtnl_lock(); 669 pch_gbe_reinit_locked(adapter); 670 rtnl_unlock(); 671 } 672 673 /** 674 * pch_gbe_reinit_locked- Re-initialization 675 * @adapter: Board private structure 676 */ 677 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter) 678 { 679 pch_gbe_down(adapter); 680 pch_gbe_up(adapter); 681 } 682 683 /** 684 * pch_gbe_reset - Reset GbE 685 * @adapter: Board private structure 686 */ 687 void pch_gbe_reset(struct pch_gbe_adapter *adapter) 688 { 689 struct net_device *netdev = adapter->netdev; 690 struct pch_gbe_hw *hw = &adapter->hw; 691 s32 ret_val; 692 693 pch_gbe_mac_reset_hw(hw); 694 /* reprogram multicast address register after reset */ 695 pch_gbe_set_multi(netdev); 696 /* Setup the receive address. */ 697 pch_gbe_mac_init_rx_addrs(hw, PCH_GBE_MAR_ENTRIES); 698 699 ret_val = pch_gbe_phy_get_id(hw); 700 if (ret_val) { 701 netdev_err(adapter->netdev, "pch_gbe_phy_get_id error\n"); 702 return; 703 } 704 pch_gbe_phy_init_setting(hw); 705 /* Setup Mac interface option RGMII */ 706 pch_gbe_phy_set_rgmii(hw); 707 } 708 709 /** 710 * pch_gbe_free_irq - Free an interrupt 711 * @adapter: Board private structure 712 */ 713 static void pch_gbe_free_irq(struct pch_gbe_adapter *adapter) 714 { 715 struct net_device *netdev = adapter->netdev; 716 717 free_irq(adapter->irq, netdev); 718 pci_free_irq_vectors(adapter->pdev); 719 } 720 721 /** 722 * pch_gbe_irq_disable - Mask off interrupt generation on the NIC 723 * @adapter: Board private structure 724 */ 725 static void pch_gbe_irq_disable(struct pch_gbe_adapter *adapter) 726 { 727 struct pch_gbe_hw *hw = &adapter->hw; 728 729 atomic_inc(&adapter->irq_sem); 730 iowrite32(0, &hw->reg->INT_EN); 731 ioread32(&hw->reg->INT_ST); 732 synchronize_irq(adapter->irq); 733 734 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 735 ioread32(&hw->reg->INT_EN)); 736 } 737 738 /** 739 * pch_gbe_irq_enable - Enable default interrupt generation settings 740 * @adapter: Board private structure 741 */ 742 static void pch_gbe_irq_enable(struct pch_gbe_adapter *adapter) 743 { 744 struct pch_gbe_hw *hw = &adapter->hw; 745 746 if (likely(atomic_dec_and_test(&adapter->irq_sem))) 747 iowrite32(PCH_GBE_INT_ENABLE_MASK, &hw->reg->INT_EN); 748 ioread32(&hw->reg->INT_ST); 749 netdev_dbg(adapter->netdev, "INT_EN reg : 0x%08x\n", 750 ioread32(&hw->reg->INT_EN)); 751 } 752 753 754 755 /** 756 * pch_gbe_setup_tctl - configure the Transmit control registers 757 * @adapter: Board private structure 758 */ 759 static void pch_gbe_setup_tctl(struct pch_gbe_adapter *adapter) 760 { 761 struct pch_gbe_hw *hw = &adapter->hw; 762 u32 tx_mode, tcpip; 763 764 tx_mode = PCH_GBE_TM_LONG_PKT | 765 PCH_GBE_TM_ST_AND_FD | 766 PCH_GBE_TM_SHORT_PKT | 767 PCH_GBE_TM_TH_TX_STRT_8 | 768 PCH_GBE_TM_TH_ALM_EMP_4 | PCH_GBE_TM_TH_ALM_FULL_8; 769 770 iowrite32(tx_mode, &hw->reg->TX_MODE); 771 772 tcpip = ioread32(&hw->reg->TCPIP_ACC); 773 tcpip |= PCH_GBE_TX_TCPIPACC_EN; 774 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 775 return; 776 } 777 778 /** 779 * pch_gbe_configure_tx - Configure Transmit Unit after Reset 780 * @adapter: Board private structure 781 */ 782 static void pch_gbe_configure_tx(struct pch_gbe_adapter *adapter) 783 { 784 struct pch_gbe_hw *hw = &adapter->hw; 785 u32 tdba, tdlen, dctrl; 786 787 netdev_dbg(adapter->netdev, "dma addr = 0x%08llx size = 0x%08x\n", 788 (unsigned long long)adapter->tx_ring->dma, 789 adapter->tx_ring->size); 790 791 /* Setup the HW Tx Head and Tail descriptor pointers */ 792 tdba = adapter->tx_ring->dma; 793 tdlen = adapter->tx_ring->size - 0x10; 794 iowrite32(tdba, &hw->reg->TX_DSC_BASE); 795 iowrite32(tdlen, &hw->reg->TX_DSC_SIZE); 796 iowrite32(tdba, &hw->reg->TX_DSC_SW_P); 797 798 /* Enables Transmission DMA */ 799 dctrl = ioread32(&hw->reg->DMA_CTRL); 800 dctrl |= PCH_GBE_TX_DMA_EN; 801 iowrite32(dctrl, &hw->reg->DMA_CTRL); 802 } 803 804 /** 805 * pch_gbe_setup_rctl - Configure the receive control registers 806 * @adapter: Board private structure 807 */ 808 static void pch_gbe_setup_rctl(struct pch_gbe_adapter *adapter) 809 { 810 struct pch_gbe_hw *hw = &adapter->hw; 811 u32 rx_mode, tcpip; 812 813 rx_mode = PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN | 814 PCH_GBE_RH_ALM_EMP_4 | PCH_GBE_RH_ALM_FULL_4 | PCH_GBE_RH_RD_TRG_8; 815 816 iowrite32(rx_mode, &hw->reg->RX_MODE); 817 818 tcpip = ioread32(&hw->reg->TCPIP_ACC); 819 820 tcpip |= PCH_GBE_RX_TCPIPACC_OFF; 821 tcpip &= ~PCH_GBE_RX_TCPIPACC_EN; 822 iowrite32(tcpip, &hw->reg->TCPIP_ACC); 823 return; 824 } 825 826 /** 827 * pch_gbe_configure_rx - Configure Receive Unit after Reset 828 * @adapter: Board private structure 829 */ 830 static void pch_gbe_configure_rx(struct pch_gbe_adapter *adapter) 831 { 832 struct pch_gbe_hw *hw = &adapter->hw; 833 u32 rdba, rdlen, rxdma; 834 835 netdev_dbg(adapter->netdev, "dma adr = 0x%08llx size = 0x%08x\n", 836 (unsigned long long)adapter->rx_ring->dma, 837 adapter->rx_ring->size); 838 839 pch_gbe_mac_force_mac_fc(hw); 840 841 pch_gbe_disable_mac_rx(hw); 842 843 /* Disables Receive DMA */ 844 rxdma = ioread32(&hw->reg->DMA_CTRL); 845 rxdma &= ~PCH_GBE_RX_DMA_EN; 846 iowrite32(rxdma, &hw->reg->DMA_CTRL); 847 848 netdev_dbg(adapter->netdev, 849 "MAC_RX_EN reg = 0x%08x DMA_CTRL reg = 0x%08x\n", 850 ioread32(&hw->reg->MAC_RX_EN), 851 ioread32(&hw->reg->DMA_CTRL)); 852 853 /* Setup the HW Rx Head and Tail Descriptor Pointers and 854 * the Base and Length of the Rx Descriptor Ring */ 855 rdba = adapter->rx_ring->dma; 856 rdlen = adapter->rx_ring->size - 0x10; 857 iowrite32(rdba, &hw->reg->RX_DSC_BASE); 858 iowrite32(rdlen, &hw->reg->RX_DSC_SIZE); 859 iowrite32((rdba + rdlen), &hw->reg->RX_DSC_SW_P); 860 } 861 862 /** 863 * pch_gbe_unmap_and_free_tx_resource - Unmap and free tx socket buffer 864 * @adapter: Board private structure 865 * @buffer_info: Buffer information structure 866 */ 867 static void pch_gbe_unmap_and_free_tx_resource( 868 struct pch_gbe_adapter *adapter, struct pch_gbe_buffer *buffer_info) 869 { 870 if (buffer_info->mapped) { 871 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 872 buffer_info->length, DMA_TO_DEVICE); 873 buffer_info->mapped = false; 874 } 875 if (buffer_info->skb) { 876 dev_kfree_skb_any(buffer_info->skb); 877 buffer_info->skb = NULL; 878 } 879 } 880 881 /** 882 * pch_gbe_unmap_and_free_rx_resource - Unmap and free rx socket buffer 883 * @adapter: Board private structure 884 * @buffer_info: Buffer information structure 885 */ 886 static void pch_gbe_unmap_and_free_rx_resource( 887 struct pch_gbe_adapter *adapter, 888 struct pch_gbe_buffer *buffer_info) 889 { 890 if (buffer_info->mapped) { 891 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 892 buffer_info->length, DMA_FROM_DEVICE); 893 buffer_info->mapped = false; 894 } 895 if (buffer_info->skb) { 896 dev_kfree_skb_any(buffer_info->skb); 897 buffer_info->skb = NULL; 898 } 899 } 900 901 /** 902 * pch_gbe_clean_tx_ring - Free Tx Buffers 903 * @adapter: Board private structure 904 * @tx_ring: Ring to be cleaned 905 */ 906 static void pch_gbe_clean_tx_ring(struct pch_gbe_adapter *adapter, 907 struct pch_gbe_tx_ring *tx_ring) 908 { 909 struct pch_gbe_hw *hw = &adapter->hw; 910 struct pch_gbe_buffer *buffer_info; 911 unsigned long size; 912 unsigned int i; 913 914 /* Free all the Tx ring sk_buffs */ 915 for (i = 0; i < tx_ring->count; i++) { 916 buffer_info = &tx_ring->buffer_info[i]; 917 pch_gbe_unmap_and_free_tx_resource(adapter, buffer_info); 918 } 919 netdev_dbg(adapter->netdev, 920 "call pch_gbe_unmap_and_free_tx_resource() %d count\n", i); 921 922 size = (unsigned long)sizeof(struct pch_gbe_buffer) * tx_ring->count; 923 memset(tx_ring->buffer_info, 0, size); 924 925 /* Zero out the descriptor ring */ 926 memset(tx_ring->desc, 0, tx_ring->size); 927 tx_ring->next_to_use = 0; 928 tx_ring->next_to_clean = 0; 929 iowrite32(tx_ring->dma, &hw->reg->TX_DSC_HW_P); 930 iowrite32((tx_ring->size - 0x10), &hw->reg->TX_DSC_SIZE); 931 } 932 933 /** 934 * pch_gbe_clean_rx_ring - Free Rx Buffers 935 * @adapter: Board private structure 936 * @rx_ring: Ring to free buffers from 937 */ 938 static void 939 pch_gbe_clean_rx_ring(struct pch_gbe_adapter *adapter, 940 struct pch_gbe_rx_ring *rx_ring) 941 { 942 struct pch_gbe_hw *hw = &adapter->hw; 943 struct pch_gbe_buffer *buffer_info; 944 unsigned long size; 945 unsigned int i; 946 947 /* Free all the Rx ring sk_buffs */ 948 for (i = 0; i < rx_ring->count; i++) { 949 buffer_info = &rx_ring->buffer_info[i]; 950 pch_gbe_unmap_and_free_rx_resource(adapter, buffer_info); 951 } 952 netdev_dbg(adapter->netdev, 953 "call pch_gbe_unmap_and_free_rx_resource() %d count\n", i); 954 size = (unsigned long)sizeof(struct pch_gbe_buffer) * rx_ring->count; 955 memset(rx_ring->buffer_info, 0, size); 956 957 /* Zero out the descriptor ring */ 958 memset(rx_ring->desc, 0, rx_ring->size); 959 rx_ring->next_to_clean = 0; 960 rx_ring->next_to_use = 0; 961 iowrite32(rx_ring->dma, &hw->reg->RX_DSC_HW_P); 962 iowrite32((rx_ring->size - 0x10), &hw->reg->RX_DSC_SIZE); 963 } 964 965 static void pch_gbe_set_rgmii_ctrl(struct pch_gbe_adapter *adapter, u16 speed, 966 u16 duplex) 967 { 968 struct pch_gbe_hw *hw = &adapter->hw; 969 unsigned long rgmii = 0; 970 971 /* Set the RGMII control. */ 972 switch (speed) { 973 case SPEED_10: 974 rgmii = (PCH_GBE_RGMII_RATE_2_5M | 975 PCH_GBE_MAC_RGMII_CTRL_SETTING); 976 break; 977 case SPEED_100: 978 rgmii = (PCH_GBE_RGMII_RATE_25M | 979 PCH_GBE_MAC_RGMII_CTRL_SETTING); 980 break; 981 case SPEED_1000: 982 rgmii = (PCH_GBE_RGMII_RATE_125M | 983 PCH_GBE_MAC_RGMII_CTRL_SETTING); 984 break; 985 } 986 iowrite32(rgmii, &hw->reg->RGMII_CTRL); 987 } 988 static void pch_gbe_set_mode(struct pch_gbe_adapter *adapter, u16 speed, 989 u16 duplex) 990 { 991 struct net_device *netdev = adapter->netdev; 992 struct pch_gbe_hw *hw = &adapter->hw; 993 unsigned long mode = 0; 994 995 /* Set the communication mode */ 996 switch (speed) { 997 case SPEED_10: 998 mode = PCH_GBE_MODE_MII_ETHER; 999 netdev->tx_queue_len = 10; 1000 break; 1001 case SPEED_100: 1002 mode = PCH_GBE_MODE_MII_ETHER; 1003 netdev->tx_queue_len = 100; 1004 break; 1005 case SPEED_1000: 1006 mode = PCH_GBE_MODE_GMII_ETHER; 1007 break; 1008 } 1009 if (duplex == DUPLEX_FULL) 1010 mode |= PCH_GBE_MODE_FULL_DUPLEX; 1011 else 1012 mode |= PCH_GBE_MODE_HALF_DUPLEX; 1013 iowrite32(mode, &hw->reg->MODE); 1014 } 1015 1016 /** 1017 * pch_gbe_watchdog - Watchdog process 1018 * @t: timer list containing a Board private structure 1019 */ 1020 static void pch_gbe_watchdog(struct timer_list *t) 1021 { 1022 struct pch_gbe_adapter *adapter = from_timer(adapter, t, 1023 watchdog_timer); 1024 struct net_device *netdev = adapter->netdev; 1025 struct pch_gbe_hw *hw = &adapter->hw; 1026 1027 netdev_dbg(netdev, "right now = %ld\n", jiffies); 1028 1029 pch_gbe_update_stats(adapter); 1030 if ((mii_link_ok(&adapter->mii)) && (!netif_carrier_ok(netdev))) { 1031 struct ethtool_cmd cmd = { .cmd = ETHTOOL_GSET }; 1032 netdev->tx_queue_len = adapter->tx_queue_len; 1033 /* mii library handles link maintenance tasks */ 1034 if (mii_ethtool_gset(&adapter->mii, &cmd)) { 1035 netdev_err(netdev, "ethtool get setting Error\n"); 1036 mod_timer(&adapter->watchdog_timer, 1037 round_jiffies(jiffies + 1038 PCH_GBE_WATCHDOG_PERIOD)); 1039 return; 1040 } 1041 hw->mac.link_speed = ethtool_cmd_speed(&cmd); 1042 hw->mac.link_duplex = cmd.duplex; 1043 /* Set the RGMII control. */ 1044 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 1045 hw->mac.link_duplex); 1046 /* Set the communication mode */ 1047 pch_gbe_set_mode(adapter, hw->mac.link_speed, 1048 hw->mac.link_duplex); 1049 netdev_dbg(netdev, 1050 "Link is Up %d Mbps %s-Duplex\n", 1051 hw->mac.link_speed, 1052 cmd.duplex == DUPLEX_FULL ? "Full" : "Half"); 1053 netif_carrier_on(netdev); 1054 netif_wake_queue(netdev); 1055 } else if ((!mii_link_ok(&adapter->mii)) && 1056 (netif_carrier_ok(netdev))) { 1057 netdev_dbg(netdev, "NIC Link is Down\n"); 1058 hw->mac.link_speed = SPEED_10; 1059 hw->mac.link_duplex = DUPLEX_HALF; 1060 netif_carrier_off(netdev); 1061 netif_stop_queue(netdev); 1062 } 1063 mod_timer(&adapter->watchdog_timer, 1064 round_jiffies(jiffies + PCH_GBE_WATCHDOG_PERIOD)); 1065 } 1066 1067 /** 1068 * pch_gbe_tx_queue - Carry out queuing of the transmission data 1069 * @adapter: Board private structure 1070 * @tx_ring: Tx descriptor ring structure 1071 * @skb: Sockt buffer structure 1072 */ 1073 static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter, 1074 struct pch_gbe_tx_ring *tx_ring, 1075 struct sk_buff *skb) 1076 { 1077 struct pch_gbe_hw *hw = &adapter->hw; 1078 struct pch_gbe_tx_desc *tx_desc; 1079 struct pch_gbe_buffer *buffer_info; 1080 struct sk_buff *tmp_skb; 1081 unsigned int frame_ctrl; 1082 unsigned int ring_num; 1083 1084 /*-- Set frame control --*/ 1085 frame_ctrl = 0; 1086 if (unlikely(skb->len < PCH_GBE_SHORT_PKT)) 1087 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD; 1088 if (skb->ip_summed == CHECKSUM_NONE) 1089 frame_ctrl |= PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1090 1091 /* Performs checksum processing */ 1092 /* 1093 * It is because the hardware accelerator does not support a checksum, 1094 * when the received data size is less than 64 bytes. 1095 */ 1096 if (skb->len < PCH_GBE_SHORT_PKT && skb->ip_summed != CHECKSUM_NONE) { 1097 frame_ctrl |= PCH_GBE_TXD_CTRL_APAD | 1098 PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF; 1099 if (skb->protocol == htons(ETH_P_IP)) { 1100 struct iphdr *iph = ip_hdr(skb); 1101 unsigned int offset; 1102 offset = skb_transport_offset(skb); 1103 if (iph->protocol == IPPROTO_TCP) { 1104 skb->csum = 0; 1105 tcp_hdr(skb)->check = 0; 1106 skb->csum = skb_checksum(skb, offset, 1107 skb->len - offset, 0); 1108 tcp_hdr(skb)->check = 1109 csum_tcpudp_magic(iph->saddr, 1110 iph->daddr, 1111 skb->len - offset, 1112 IPPROTO_TCP, 1113 skb->csum); 1114 } else if (iph->protocol == IPPROTO_UDP) { 1115 skb->csum = 0; 1116 udp_hdr(skb)->check = 0; 1117 skb->csum = 1118 skb_checksum(skb, offset, 1119 skb->len - offset, 0); 1120 udp_hdr(skb)->check = 1121 csum_tcpudp_magic(iph->saddr, 1122 iph->daddr, 1123 skb->len - offset, 1124 IPPROTO_UDP, 1125 skb->csum); 1126 } 1127 } 1128 } 1129 1130 ring_num = tx_ring->next_to_use; 1131 if (unlikely((ring_num + 1) == tx_ring->count)) 1132 tx_ring->next_to_use = 0; 1133 else 1134 tx_ring->next_to_use = ring_num + 1; 1135 1136 1137 buffer_info = &tx_ring->buffer_info[ring_num]; 1138 tmp_skb = buffer_info->skb; 1139 1140 /* [Header:14][payload] ---> [Header:14][paddong:2][payload] */ 1141 memcpy(tmp_skb->data, skb->data, ETH_HLEN); 1142 tmp_skb->data[ETH_HLEN] = 0x00; 1143 tmp_skb->data[ETH_HLEN + 1] = 0x00; 1144 tmp_skb->len = skb->len; 1145 memcpy(&tmp_skb->data[ETH_HLEN + 2], &skb->data[ETH_HLEN], 1146 (skb->len - ETH_HLEN)); 1147 /*-- Set Buffer information --*/ 1148 buffer_info->length = tmp_skb->len; 1149 buffer_info->dma = dma_map_single(&adapter->pdev->dev, tmp_skb->data, 1150 buffer_info->length, 1151 DMA_TO_DEVICE); 1152 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1153 netdev_err(adapter->netdev, "TX DMA map failed\n"); 1154 buffer_info->dma = 0; 1155 buffer_info->time_stamp = 0; 1156 tx_ring->next_to_use = ring_num; 1157 return; 1158 } 1159 buffer_info->mapped = true; 1160 buffer_info->time_stamp = jiffies; 1161 1162 /*-- Set Tx descriptor --*/ 1163 tx_desc = PCH_GBE_TX_DESC(*tx_ring, ring_num); 1164 tx_desc->buffer_addr = (buffer_info->dma); 1165 tx_desc->length = (tmp_skb->len); 1166 tx_desc->tx_words_eob = ((tmp_skb->len + 3)); 1167 tx_desc->tx_frame_ctrl = (frame_ctrl); 1168 tx_desc->gbec_status = (DSC_INIT16); 1169 1170 if (unlikely(++ring_num == tx_ring->count)) 1171 ring_num = 0; 1172 1173 /* Update software pointer of TX descriptor */ 1174 iowrite32(tx_ring->dma + 1175 (int)sizeof(struct pch_gbe_tx_desc) * ring_num, 1176 &hw->reg->TX_DSC_SW_P); 1177 1178 pch_tx_timestamp(adapter, skb); 1179 1180 dev_kfree_skb_any(skb); 1181 } 1182 1183 /** 1184 * pch_gbe_update_stats - Update the board statistics counters 1185 * @adapter: Board private structure 1186 */ 1187 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter) 1188 { 1189 struct net_device *netdev = adapter->netdev; 1190 struct pci_dev *pdev = adapter->pdev; 1191 struct pch_gbe_hw_stats *stats = &adapter->stats; 1192 unsigned long flags; 1193 1194 /* 1195 * Prevent stats update while adapter is being reset, or if the pci 1196 * connection is down. 1197 */ 1198 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1199 return; 1200 1201 spin_lock_irqsave(&adapter->stats_lock, flags); 1202 1203 /* Update device status "adapter->stats" */ 1204 stats->rx_errors = stats->rx_crc_errors + stats->rx_frame_errors; 1205 stats->tx_errors = stats->tx_length_errors + 1206 stats->tx_aborted_errors + 1207 stats->tx_carrier_errors + stats->tx_timeout_count; 1208 1209 /* Update network device status "adapter->net_stats" */ 1210 netdev->stats.rx_packets = stats->rx_packets; 1211 netdev->stats.rx_bytes = stats->rx_bytes; 1212 netdev->stats.rx_dropped = stats->rx_dropped; 1213 netdev->stats.tx_packets = stats->tx_packets; 1214 netdev->stats.tx_bytes = stats->tx_bytes; 1215 netdev->stats.tx_dropped = stats->tx_dropped; 1216 /* Fill out the OS statistics structure */ 1217 netdev->stats.multicast = stats->multicast; 1218 netdev->stats.collisions = stats->collisions; 1219 /* Rx Errors */ 1220 netdev->stats.rx_errors = stats->rx_errors; 1221 netdev->stats.rx_crc_errors = stats->rx_crc_errors; 1222 netdev->stats.rx_frame_errors = stats->rx_frame_errors; 1223 /* Tx Errors */ 1224 netdev->stats.tx_errors = stats->tx_errors; 1225 netdev->stats.tx_aborted_errors = stats->tx_aborted_errors; 1226 netdev->stats.tx_carrier_errors = stats->tx_carrier_errors; 1227 1228 spin_unlock_irqrestore(&adapter->stats_lock, flags); 1229 } 1230 1231 static void pch_gbe_disable_dma_rx(struct pch_gbe_hw *hw) 1232 { 1233 u32 rxdma; 1234 1235 /* Disable Receive DMA */ 1236 rxdma = ioread32(&hw->reg->DMA_CTRL); 1237 rxdma &= ~PCH_GBE_RX_DMA_EN; 1238 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1239 } 1240 1241 static void pch_gbe_enable_dma_rx(struct pch_gbe_hw *hw) 1242 { 1243 u32 rxdma; 1244 1245 /* Enables Receive DMA */ 1246 rxdma = ioread32(&hw->reg->DMA_CTRL); 1247 rxdma |= PCH_GBE_RX_DMA_EN; 1248 iowrite32(rxdma, &hw->reg->DMA_CTRL); 1249 } 1250 1251 /** 1252 * pch_gbe_intr - Interrupt Handler 1253 * @irq: Interrupt number 1254 * @data: Pointer to a network interface device structure 1255 * Returns: 1256 * - IRQ_HANDLED: Our interrupt 1257 * - IRQ_NONE: Not our interrupt 1258 */ 1259 static irqreturn_t pch_gbe_intr(int irq, void *data) 1260 { 1261 struct net_device *netdev = data; 1262 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1263 struct pch_gbe_hw *hw = &adapter->hw; 1264 u32 int_st; 1265 u32 int_en; 1266 1267 /* Check request status */ 1268 int_st = ioread32(&hw->reg->INT_ST); 1269 int_st = int_st & ioread32(&hw->reg->INT_EN); 1270 /* When request status is no interruption factor */ 1271 if (unlikely(!int_st)) 1272 return IRQ_NONE; /* Not our interrupt. End processing. */ 1273 netdev_dbg(netdev, "%s occur int_st = 0x%08x\n", __func__, int_st); 1274 if (int_st & PCH_GBE_INT_RX_FRAME_ERR) 1275 adapter->stats.intr_rx_frame_err_count++; 1276 if (int_st & PCH_GBE_INT_RX_FIFO_ERR) 1277 if (!adapter->rx_stop_flag) { 1278 adapter->stats.intr_rx_fifo_err_count++; 1279 netdev_dbg(netdev, "Rx fifo over run\n"); 1280 adapter->rx_stop_flag = true; 1281 int_en = ioread32(&hw->reg->INT_EN); 1282 iowrite32((int_en & ~PCH_GBE_INT_RX_FIFO_ERR), 1283 &hw->reg->INT_EN); 1284 pch_gbe_disable_dma_rx(&adapter->hw); 1285 int_st |= ioread32(&hw->reg->INT_ST); 1286 int_st = int_st & ioread32(&hw->reg->INT_EN); 1287 } 1288 if (int_st & PCH_GBE_INT_RX_DMA_ERR) 1289 adapter->stats.intr_rx_dma_err_count++; 1290 if (int_st & PCH_GBE_INT_TX_FIFO_ERR) 1291 adapter->stats.intr_tx_fifo_err_count++; 1292 if (int_st & PCH_GBE_INT_TX_DMA_ERR) 1293 adapter->stats.intr_tx_dma_err_count++; 1294 if (int_st & PCH_GBE_INT_TCPIP_ERR) 1295 adapter->stats.intr_tcpip_err_count++; 1296 /* When Rx descriptor is empty */ 1297 if ((int_st & PCH_GBE_INT_RX_DSC_EMP)) { 1298 adapter->stats.intr_rx_dsc_empty_count++; 1299 netdev_dbg(netdev, "Rx descriptor is empty\n"); 1300 int_en = ioread32(&hw->reg->INT_EN); 1301 iowrite32((int_en & ~PCH_GBE_INT_RX_DSC_EMP), &hw->reg->INT_EN); 1302 if (hw->mac.tx_fc_enable) { 1303 /* Set Pause packet */ 1304 pch_gbe_mac_set_pause_packet(hw); 1305 } 1306 } 1307 1308 /* When request status is Receive interruption */ 1309 if ((int_st & (PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT)) || 1310 (adapter->rx_stop_flag)) { 1311 if (likely(napi_schedule_prep(&adapter->napi))) { 1312 /* Enable only Rx Descriptor empty */ 1313 atomic_inc(&adapter->irq_sem); 1314 int_en = ioread32(&hw->reg->INT_EN); 1315 int_en &= 1316 ~(PCH_GBE_INT_RX_DMA_CMPLT | PCH_GBE_INT_TX_CMPLT); 1317 iowrite32(int_en, &hw->reg->INT_EN); 1318 /* Start polling for NAPI */ 1319 __napi_schedule(&adapter->napi); 1320 } 1321 } 1322 netdev_dbg(netdev, "return = 0x%08x INT_EN reg = 0x%08x\n", 1323 IRQ_HANDLED, ioread32(&hw->reg->INT_EN)); 1324 return IRQ_HANDLED; 1325 } 1326 1327 /** 1328 * pch_gbe_alloc_rx_buffers - Replace used receive buffers; legacy & extended 1329 * @adapter: Board private structure 1330 * @rx_ring: Rx descriptor ring 1331 * @cleaned_count: Cleaned count 1332 */ 1333 static void 1334 pch_gbe_alloc_rx_buffers(struct pch_gbe_adapter *adapter, 1335 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1336 { 1337 struct net_device *netdev = adapter->netdev; 1338 struct pci_dev *pdev = adapter->pdev; 1339 struct pch_gbe_hw *hw = &adapter->hw; 1340 struct pch_gbe_rx_desc *rx_desc; 1341 struct pch_gbe_buffer *buffer_info; 1342 struct sk_buff *skb; 1343 unsigned int i; 1344 unsigned int bufsz; 1345 1346 bufsz = adapter->rx_buffer_len + NET_IP_ALIGN; 1347 i = rx_ring->next_to_use; 1348 1349 while ((cleaned_count--)) { 1350 buffer_info = &rx_ring->buffer_info[i]; 1351 skb = netdev_alloc_skb(netdev, bufsz); 1352 if (unlikely(!skb)) { 1353 /* Better luck next round */ 1354 adapter->stats.rx_alloc_buff_failed++; 1355 break; 1356 } 1357 /* align */ 1358 skb_reserve(skb, NET_IP_ALIGN); 1359 buffer_info->skb = skb; 1360 1361 buffer_info->dma = dma_map_single(&pdev->dev, 1362 buffer_info->rx_buffer, 1363 buffer_info->length, 1364 DMA_FROM_DEVICE); 1365 if (dma_mapping_error(&adapter->pdev->dev, buffer_info->dma)) { 1366 dev_kfree_skb(skb); 1367 buffer_info->skb = NULL; 1368 buffer_info->dma = 0; 1369 adapter->stats.rx_alloc_buff_failed++; 1370 break; /* while !buffer_info->skb */ 1371 } 1372 buffer_info->mapped = true; 1373 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1374 rx_desc->buffer_addr = (buffer_info->dma); 1375 rx_desc->gbec_status = DSC_INIT16; 1376 1377 netdev_dbg(netdev, 1378 "i = %d buffer_info->dma = 0x08%llx buffer_info->length = 0x%x\n", 1379 i, (unsigned long long)buffer_info->dma, 1380 buffer_info->length); 1381 1382 if (unlikely(++i == rx_ring->count)) 1383 i = 0; 1384 } 1385 if (likely(rx_ring->next_to_use != i)) { 1386 rx_ring->next_to_use = i; 1387 if (unlikely(i-- == 0)) 1388 i = (rx_ring->count - 1); 1389 iowrite32(rx_ring->dma + 1390 (int)sizeof(struct pch_gbe_rx_desc) * i, 1391 &hw->reg->RX_DSC_SW_P); 1392 } 1393 return; 1394 } 1395 1396 static int 1397 pch_gbe_alloc_rx_buffers_pool(struct pch_gbe_adapter *adapter, 1398 struct pch_gbe_rx_ring *rx_ring, int cleaned_count) 1399 { 1400 struct pci_dev *pdev = adapter->pdev; 1401 struct pch_gbe_buffer *buffer_info; 1402 unsigned int i; 1403 unsigned int bufsz; 1404 unsigned int size; 1405 1406 bufsz = adapter->rx_buffer_len; 1407 1408 size = rx_ring->count * bufsz + PCH_GBE_RESERVE_MEMORY; 1409 rx_ring->rx_buff_pool = 1410 dma_alloc_coherent(&pdev->dev, size, 1411 &rx_ring->rx_buff_pool_logic, GFP_KERNEL); 1412 if (!rx_ring->rx_buff_pool) 1413 return -ENOMEM; 1414 1415 rx_ring->rx_buff_pool_size = size; 1416 for (i = 0; i < rx_ring->count; i++) { 1417 buffer_info = &rx_ring->buffer_info[i]; 1418 buffer_info->rx_buffer = rx_ring->rx_buff_pool + bufsz * i; 1419 buffer_info->length = bufsz; 1420 } 1421 return 0; 1422 } 1423 1424 /** 1425 * pch_gbe_alloc_tx_buffers - Allocate transmit buffers 1426 * @adapter: Board private structure 1427 * @tx_ring: Tx descriptor ring 1428 */ 1429 static void pch_gbe_alloc_tx_buffers(struct pch_gbe_adapter *adapter, 1430 struct pch_gbe_tx_ring *tx_ring) 1431 { 1432 struct pch_gbe_buffer *buffer_info; 1433 struct sk_buff *skb; 1434 unsigned int i; 1435 unsigned int bufsz; 1436 struct pch_gbe_tx_desc *tx_desc; 1437 1438 bufsz = 1439 adapter->hw.mac.max_frame_size + PCH_GBE_DMA_ALIGN + NET_IP_ALIGN; 1440 1441 for (i = 0; i < tx_ring->count; i++) { 1442 buffer_info = &tx_ring->buffer_info[i]; 1443 skb = netdev_alloc_skb(adapter->netdev, bufsz); 1444 skb_reserve(skb, PCH_GBE_DMA_ALIGN); 1445 buffer_info->skb = skb; 1446 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1447 tx_desc->gbec_status = (DSC_INIT16); 1448 } 1449 return; 1450 } 1451 1452 /** 1453 * pch_gbe_clean_tx - Reclaim resources after transmit completes 1454 * @adapter: Board private structure 1455 * @tx_ring: Tx descriptor ring 1456 * Returns: 1457 * true: Cleaned the descriptor 1458 * false: Not cleaned the descriptor 1459 */ 1460 static bool 1461 pch_gbe_clean_tx(struct pch_gbe_adapter *adapter, 1462 struct pch_gbe_tx_ring *tx_ring) 1463 { 1464 struct pch_gbe_tx_desc *tx_desc; 1465 struct pch_gbe_buffer *buffer_info; 1466 struct sk_buff *skb; 1467 unsigned int i; 1468 unsigned int cleaned_count = 0; 1469 bool cleaned = false; 1470 int unused, thresh; 1471 1472 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1473 tx_ring->next_to_clean); 1474 1475 i = tx_ring->next_to_clean; 1476 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1477 netdev_dbg(adapter->netdev, "gbec_status:0x%04x dma_status:0x%04x\n", 1478 tx_desc->gbec_status, tx_desc->dma_status); 1479 1480 unused = PCH_GBE_DESC_UNUSED(tx_ring); 1481 thresh = tx_ring->count - PCH_GBE_TX_WEIGHT; 1482 if ((tx_desc->gbec_status == DSC_INIT16) && (unused < thresh)) 1483 { /* current marked clean, tx queue filling up, do extra clean */ 1484 int j, k; 1485 if (unused < 8) { /* tx queue nearly full */ 1486 netdev_dbg(adapter->netdev, 1487 "clean_tx: transmit queue warning (%x,%x) unused=%d\n", 1488 tx_ring->next_to_clean, tx_ring->next_to_use, 1489 unused); 1490 } 1491 1492 /* current marked clean, scan for more that need cleaning. */ 1493 k = i; 1494 for (j = 0; j < PCH_GBE_TX_WEIGHT; j++) 1495 { 1496 tx_desc = PCH_GBE_TX_DESC(*tx_ring, k); 1497 if (tx_desc->gbec_status != DSC_INIT16) break; /*found*/ 1498 if (++k >= tx_ring->count) k = 0; /*increment, wrap*/ 1499 } 1500 if (j < PCH_GBE_TX_WEIGHT) { 1501 netdev_dbg(adapter->netdev, 1502 "clean_tx: unused=%d loops=%d found tx_desc[%x,%x:%x].gbec_status=%04x\n", 1503 unused, j, i, k, tx_ring->next_to_use, 1504 tx_desc->gbec_status); 1505 i = k; /*found one to clean, usu gbec_status==2000.*/ 1506 } 1507 } 1508 1509 while ((tx_desc->gbec_status & DSC_INIT16) == 0x0000) { 1510 netdev_dbg(adapter->netdev, "gbec_status:0x%04x\n", 1511 tx_desc->gbec_status); 1512 buffer_info = &tx_ring->buffer_info[i]; 1513 skb = buffer_info->skb; 1514 cleaned = true; 1515 1516 if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_ABT)) { 1517 adapter->stats.tx_aborted_errors++; 1518 netdev_err(adapter->netdev, "Transfer Abort Error\n"); 1519 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CRSER) 1520 ) { 1521 adapter->stats.tx_carrier_errors++; 1522 netdev_err(adapter->netdev, 1523 "Transfer Carrier Sense Error\n"); 1524 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_EXCOL) 1525 ) { 1526 adapter->stats.tx_aborted_errors++; 1527 netdev_err(adapter->netdev, 1528 "Transfer Collision Abort Error\n"); 1529 } else if ((tx_desc->gbec_status & 1530 (PCH_GBE_TXD_GMAC_STAT_SNGCOL | 1531 PCH_GBE_TXD_GMAC_STAT_MLTCOL))) { 1532 adapter->stats.collisions++; 1533 adapter->stats.tx_packets++; 1534 adapter->stats.tx_bytes += skb->len; 1535 netdev_dbg(adapter->netdev, "Transfer Collision\n"); 1536 } else if ((tx_desc->gbec_status & PCH_GBE_TXD_GMAC_STAT_CMPLT) 1537 ) { 1538 adapter->stats.tx_packets++; 1539 adapter->stats.tx_bytes += skb->len; 1540 } 1541 if (buffer_info->mapped) { 1542 netdev_dbg(adapter->netdev, 1543 "unmap buffer_info->dma : %d\n", i); 1544 dma_unmap_single(&adapter->pdev->dev, buffer_info->dma, 1545 buffer_info->length, DMA_TO_DEVICE); 1546 buffer_info->mapped = false; 1547 } 1548 if (buffer_info->skb) { 1549 netdev_dbg(adapter->netdev, 1550 "trim buffer_info->skb : %d\n", i); 1551 skb_trim(buffer_info->skb, 0); 1552 } 1553 tx_desc->gbec_status = DSC_INIT16; 1554 if (unlikely(++i == tx_ring->count)) 1555 i = 0; 1556 tx_desc = PCH_GBE_TX_DESC(*tx_ring, i); 1557 1558 /* weight of a sort for tx, to avoid endless transmit cleanup */ 1559 if (cleaned_count++ == PCH_GBE_TX_WEIGHT) { 1560 cleaned = false; 1561 break; 1562 } 1563 } 1564 netdev_dbg(adapter->netdev, 1565 "called pch_gbe_unmap_and_free_tx_resource() %d count\n", 1566 cleaned_count); 1567 if (cleaned_count > 0) { /*skip this if nothing cleaned*/ 1568 /* Recover from running out of Tx resources in xmit_frame */ 1569 netif_tx_lock(adapter->netdev); 1570 if (unlikely(cleaned && (netif_queue_stopped(adapter->netdev)))) 1571 { 1572 netif_wake_queue(adapter->netdev); 1573 adapter->stats.tx_restart_count++; 1574 netdev_dbg(adapter->netdev, "Tx wake queue\n"); 1575 } 1576 1577 tx_ring->next_to_clean = i; 1578 1579 netdev_dbg(adapter->netdev, "next_to_clean : %d\n", 1580 tx_ring->next_to_clean); 1581 netif_tx_unlock(adapter->netdev); 1582 } 1583 return cleaned; 1584 } 1585 1586 /** 1587 * pch_gbe_clean_rx - Send received data up the network stack; legacy 1588 * @adapter: Board private structure 1589 * @rx_ring: Rx descriptor ring 1590 * @work_done: Completed count 1591 * @work_to_do: Request count 1592 * Returns: 1593 * true: Cleaned the descriptor 1594 * false: Not cleaned the descriptor 1595 */ 1596 static bool 1597 pch_gbe_clean_rx(struct pch_gbe_adapter *adapter, 1598 struct pch_gbe_rx_ring *rx_ring, 1599 int *work_done, int work_to_do) 1600 { 1601 struct net_device *netdev = adapter->netdev; 1602 struct pci_dev *pdev = adapter->pdev; 1603 struct pch_gbe_buffer *buffer_info; 1604 struct pch_gbe_rx_desc *rx_desc; 1605 u32 length; 1606 unsigned int i; 1607 unsigned int cleaned_count = 0; 1608 bool cleaned = false; 1609 struct sk_buff *skb; 1610 u8 dma_status; 1611 u16 gbec_status; 1612 u32 tcp_ip_status; 1613 1614 i = rx_ring->next_to_clean; 1615 1616 while (*work_done < work_to_do) { 1617 /* Check Rx descriptor status */ 1618 rx_desc = PCH_GBE_RX_DESC(*rx_ring, i); 1619 if (rx_desc->gbec_status == DSC_INIT16) 1620 break; 1621 cleaned = true; 1622 cleaned_count++; 1623 1624 dma_status = rx_desc->dma_status; 1625 gbec_status = rx_desc->gbec_status; 1626 tcp_ip_status = rx_desc->tcp_ip_status; 1627 rx_desc->gbec_status = DSC_INIT16; 1628 buffer_info = &rx_ring->buffer_info[i]; 1629 skb = buffer_info->skb; 1630 buffer_info->skb = NULL; 1631 1632 /* unmap dma */ 1633 dma_unmap_single(&pdev->dev, buffer_info->dma, 1634 buffer_info->length, DMA_FROM_DEVICE); 1635 buffer_info->mapped = false; 1636 1637 netdev_dbg(netdev, 1638 "RxDecNo = 0x%04x Status[DMA:0x%02x GBE:0x%04x TCP:0x%08x] BufInf = 0x%p\n", 1639 i, dma_status, gbec_status, tcp_ip_status, 1640 buffer_info); 1641 /* Error check */ 1642 if (unlikely(gbec_status & PCH_GBE_RXD_GMAC_STAT_NOTOCTAL)) { 1643 adapter->stats.rx_frame_errors++; 1644 netdev_err(netdev, "Receive Not Octal Error\n"); 1645 } else if (unlikely(gbec_status & 1646 PCH_GBE_RXD_GMAC_STAT_NBLERR)) { 1647 adapter->stats.rx_frame_errors++; 1648 netdev_err(netdev, "Receive Nibble Error\n"); 1649 } else if (unlikely(gbec_status & 1650 PCH_GBE_RXD_GMAC_STAT_CRCERR)) { 1651 adapter->stats.rx_crc_errors++; 1652 netdev_err(netdev, "Receive CRC Error\n"); 1653 } else { 1654 /* get receive length */ 1655 /* length convert[-3], length includes FCS length */ 1656 length = (rx_desc->rx_words_eob) - 3 - ETH_FCS_LEN; 1657 if (rx_desc->rx_words_eob & 0x02) 1658 length = length - 4; 1659 /* 1660 * buffer_info->rx_buffer: [Header:14][payload] 1661 * skb->data: [Reserve:2][Header:14][payload] 1662 */ 1663 memcpy(skb->data, buffer_info->rx_buffer, length); 1664 1665 /* update status of driver */ 1666 adapter->stats.rx_bytes += length; 1667 adapter->stats.rx_packets++; 1668 if ((gbec_status & PCH_GBE_RXD_GMAC_STAT_MARMLT)) 1669 adapter->stats.multicast++; 1670 /* Write meta date of skb */ 1671 skb_put(skb, length); 1672 1673 pch_rx_timestamp(adapter, skb); 1674 1675 skb->protocol = eth_type_trans(skb, netdev); 1676 if (tcp_ip_status & PCH_GBE_RXD_ACC_STAT_TCPIPOK) 1677 skb->ip_summed = CHECKSUM_UNNECESSARY; 1678 else 1679 skb->ip_summed = CHECKSUM_NONE; 1680 1681 napi_gro_receive(&adapter->napi, skb); 1682 (*work_done)++; 1683 netdev_dbg(netdev, 1684 "Receive skb->ip_summed: %d length: %d\n", 1685 skb->ip_summed, length); 1686 } 1687 /* return some buffers to hardware, one at a time is too slow */ 1688 if (unlikely(cleaned_count >= PCH_GBE_RX_BUFFER_WRITE)) { 1689 pch_gbe_alloc_rx_buffers(adapter, rx_ring, 1690 cleaned_count); 1691 cleaned_count = 0; 1692 } 1693 if (++i == rx_ring->count) 1694 i = 0; 1695 } 1696 rx_ring->next_to_clean = i; 1697 if (cleaned_count) 1698 pch_gbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count); 1699 return cleaned; 1700 } 1701 1702 /** 1703 * pch_gbe_setup_tx_resources - Allocate Tx resources (Descriptors) 1704 * @adapter: Board private structure 1705 * @tx_ring: Tx descriptor ring (for a specific queue) to setup 1706 * Returns: 1707 * 0: Successfully 1708 * Negative value: Failed 1709 */ 1710 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter, 1711 struct pch_gbe_tx_ring *tx_ring) 1712 { 1713 struct pci_dev *pdev = adapter->pdev; 1714 struct pch_gbe_tx_desc *tx_desc; 1715 int size; 1716 int desNo; 1717 1718 size = (int)sizeof(struct pch_gbe_buffer) * tx_ring->count; 1719 tx_ring->buffer_info = vzalloc(size); 1720 if (!tx_ring->buffer_info) 1721 return -ENOMEM; 1722 1723 tx_ring->size = tx_ring->count * (int)sizeof(struct pch_gbe_tx_desc); 1724 1725 tx_ring->desc = dma_alloc_coherent(&pdev->dev, tx_ring->size, 1726 &tx_ring->dma, GFP_KERNEL); 1727 if (!tx_ring->desc) { 1728 vfree(tx_ring->buffer_info); 1729 return -ENOMEM; 1730 } 1731 1732 tx_ring->next_to_use = 0; 1733 tx_ring->next_to_clean = 0; 1734 1735 for (desNo = 0; desNo < tx_ring->count; desNo++) { 1736 tx_desc = PCH_GBE_TX_DESC(*tx_ring, desNo); 1737 tx_desc->gbec_status = DSC_INIT16; 1738 } 1739 netdev_dbg(adapter->netdev, 1740 "tx_ring->desc = 0x%p tx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1741 tx_ring->desc, (unsigned long long)tx_ring->dma, 1742 tx_ring->next_to_clean, tx_ring->next_to_use); 1743 return 0; 1744 } 1745 1746 /** 1747 * pch_gbe_setup_rx_resources - Allocate Rx resources (Descriptors) 1748 * @adapter: Board private structure 1749 * @rx_ring: Rx descriptor ring (for a specific queue) to setup 1750 * Returns: 1751 * 0: Successfully 1752 * Negative value: Failed 1753 */ 1754 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter, 1755 struct pch_gbe_rx_ring *rx_ring) 1756 { 1757 struct pci_dev *pdev = adapter->pdev; 1758 struct pch_gbe_rx_desc *rx_desc; 1759 int size; 1760 int desNo; 1761 1762 size = (int)sizeof(struct pch_gbe_buffer) * rx_ring->count; 1763 rx_ring->buffer_info = vzalloc(size); 1764 if (!rx_ring->buffer_info) 1765 return -ENOMEM; 1766 1767 rx_ring->size = rx_ring->count * (int)sizeof(struct pch_gbe_rx_desc); 1768 rx_ring->desc = dma_alloc_coherent(&pdev->dev, rx_ring->size, 1769 &rx_ring->dma, GFP_KERNEL); 1770 if (!rx_ring->desc) { 1771 vfree(rx_ring->buffer_info); 1772 return -ENOMEM; 1773 } 1774 rx_ring->next_to_clean = 0; 1775 rx_ring->next_to_use = 0; 1776 for (desNo = 0; desNo < rx_ring->count; desNo++) { 1777 rx_desc = PCH_GBE_RX_DESC(*rx_ring, desNo); 1778 rx_desc->gbec_status = DSC_INIT16; 1779 } 1780 netdev_dbg(adapter->netdev, 1781 "rx_ring->desc = 0x%p rx_ring->dma = 0x%08llx next_to_clean = 0x%08x next_to_use = 0x%08x\n", 1782 rx_ring->desc, (unsigned long long)rx_ring->dma, 1783 rx_ring->next_to_clean, rx_ring->next_to_use); 1784 return 0; 1785 } 1786 1787 /** 1788 * pch_gbe_free_tx_resources - Free Tx Resources 1789 * @adapter: Board private structure 1790 * @tx_ring: Tx descriptor ring for a specific queue 1791 */ 1792 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter, 1793 struct pch_gbe_tx_ring *tx_ring) 1794 { 1795 struct pci_dev *pdev = adapter->pdev; 1796 1797 pch_gbe_clean_tx_ring(adapter, tx_ring); 1798 vfree(tx_ring->buffer_info); 1799 tx_ring->buffer_info = NULL; 1800 dma_free_coherent(&pdev->dev, tx_ring->size, tx_ring->desc, 1801 tx_ring->dma); 1802 tx_ring->desc = NULL; 1803 } 1804 1805 /** 1806 * pch_gbe_free_rx_resources - Free Rx Resources 1807 * @adapter: Board private structure 1808 * @rx_ring: Ring to clean the resources from 1809 */ 1810 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter, 1811 struct pch_gbe_rx_ring *rx_ring) 1812 { 1813 struct pci_dev *pdev = adapter->pdev; 1814 1815 pch_gbe_clean_rx_ring(adapter, rx_ring); 1816 vfree(rx_ring->buffer_info); 1817 rx_ring->buffer_info = NULL; 1818 dma_free_coherent(&pdev->dev, rx_ring->size, rx_ring->desc, 1819 rx_ring->dma); 1820 rx_ring->desc = NULL; 1821 } 1822 1823 /** 1824 * pch_gbe_request_irq - Allocate an interrupt line 1825 * @adapter: Board private structure 1826 * Returns: 1827 * 0: Successfully 1828 * Negative value: Failed 1829 */ 1830 static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter) 1831 { 1832 struct net_device *netdev = adapter->netdev; 1833 int err; 1834 1835 err = pci_alloc_irq_vectors(adapter->pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1836 if (err < 0) 1837 return err; 1838 1839 adapter->irq = pci_irq_vector(adapter->pdev, 0); 1840 1841 err = request_irq(adapter->irq, &pch_gbe_intr, IRQF_SHARED, 1842 netdev->name, netdev); 1843 if (err) 1844 netdev_err(netdev, "Unable to allocate interrupt Error: %d\n", 1845 err); 1846 netdev_dbg(netdev, "have_msi : %d return : 0x%04x\n", 1847 pci_dev_msi_enabled(adapter->pdev), err); 1848 return err; 1849 } 1850 1851 /** 1852 * pch_gbe_up - Up GbE network device 1853 * @adapter: Board private structure 1854 * Returns: 1855 * 0: Successfully 1856 * Negative value: Failed 1857 */ 1858 int pch_gbe_up(struct pch_gbe_adapter *adapter) 1859 { 1860 struct net_device *netdev = adapter->netdev; 1861 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 1862 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1863 int err = -EINVAL; 1864 1865 /* Ensure we have a valid MAC */ 1866 if (!is_valid_ether_addr(adapter->hw.mac.addr)) { 1867 netdev_err(netdev, "Error: Invalid MAC address\n"); 1868 goto out; 1869 } 1870 1871 /* hardware has been reset, we need to reload some things */ 1872 pch_gbe_set_multi(netdev); 1873 1874 pch_gbe_setup_tctl(adapter); 1875 pch_gbe_configure_tx(adapter); 1876 pch_gbe_setup_rctl(adapter); 1877 pch_gbe_configure_rx(adapter); 1878 1879 err = pch_gbe_request_irq(adapter); 1880 if (err) { 1881 netdev_err(netdev, 1882 "Error: can't bring device up - irq request failed\n"); 1883 goto out; 1884 } 1885 err = pch_gbe_alloc_rx_buffers_pool(adapter, rx_ring, rx_ring->count); 1886 if (err) { 1887 netdev_err(netdev, 1888 "Error: can't bring device up - alloc rx buffers pool failed\n"); 1889 goto freeirq; 1890 } 1891 pch_gbe_alloc_tx_buffers(adapter, tx_ring); 1892 pch_gbe_alloc_rx_buffers(adapter, rx_ring, rx_ring->count); 1893 adapter->tx_queue_len = netdev->tx_queue_len; 1894 pch_gbe_enable_dma_rx(&adapter->hw); 1895 pch_gbe_enable_mac_rx(&adapter->hw); 1896 1897 mod_timer(&adapter->watchdog_timer, jiffies); 1898 1899 napi_enable(&adapter->napi); 1900 pch_gbe_irq_enable(adapter); 1901 netif_start_queue(adapter->netdev); 1902 1903 return 0; 1904 1905 freeirq: 1906 pch_gbe_free_irq(adapter); 1907 out: 1908 return err; 1909 } 1910 1911 /** 1912 * pch_gbe_down - Down GbE network device 1913 * @adapter: Board private structure 1914 */ 1915 void pch_gbe_down(struct pch_gbe_adapter *adapter) 1916 { 1917 struct net_device *netdev = adapter->netdev; 1918 struct pci_dev *pdev = adapter->pdev; 1919 struct pch_gbe_rx_ring *rx_ring = adapter->rx_ring; 1920 1921 /* signal that we're down so the interrupt handler does not 1922 * reschedule our watchdog timer */ 1923 napi_disable(&adapter->napi); 1924 atomic_set(&adapter->irq_sem, 0); 1925 1926 pch_gbe_irq_disable(adapter); 1927 pch_gbe_free_irq(adapter); 1928 1929 del_timer_sync(&adapter->watchdog_timer); 1930 1931 netdev->tx_queue_len = adapter->tx_queue_len; 1932 netif_carrier_off(netdev); 1933 netif_stop_queue(netdev); 1934 1935 if ((pdev->error_state) && (pdev->error_state != pci_channel_io_normal)) 1936 pch_gbe_reset(adapter); 1937 pch_gbe_clean_tx_ring(adapter, adapter->tx_ring); 1938 pch_gbe_clean_rx_ring(adapter, adapter->rx_ring); 1939 1940 dma_free_coherent(&adapter->pdev->dev, rx_ring->rx_buff_pool_size, 1941 rx_ring->rx_buff_pool, rx_ring->rx_buff_pool_logic); 1942 rx_ring->rx_buff_pool_logic = 0; 1943 rx_ring->rx_buff_pool_size = 0; 1944 rx_ring->rx_buff_pool = NULL; 1945 } 1946 1947 /** 1948 * pch_gbe_sw_init - Initialize general software structures (struct pch_gbe_adapter) 1949 * @adapter: Board private structure to initialize 1950 * Returns: 1951 * 0: Successfully 1952 * Negative value: Failed 1953 */ 1954 static int pch_gbe_sw_init(struct pch_gbe_adapter *adapter) 1955 { 1956 struct pch_gbe_hw *hw = &adapter->hw; 1957 struct net_device *netdev = adapter->netdev; 1958 1959 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 1960 hw->mac.max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN; 1961 hw->mac.min_frame_size = ETH_ZLEN + ETH_FCS_LEN; 1962 hw->phy.reset_delay_us = PCH_GBE_PHY_RESET_DELAY_US; 1963 1964 if (pch_gbe_alloc_queues(adapter)) { 1965 netdev_err(netdev, "Unable to allocate memory for queues\n"); 1966 return -ENOMEM; 1967 } 1968 spin_lock_init(&adapter->hw.miim_lock); 1969 spin_lock_init(&adapter->stats_lock); 1970 spin_lock_init(&adapter->ethtool_lock); 1971 atomic_set(&adapter->irq_sem, 0); 1972 pch_gbe_irq_disable(adapter); 1973 1974 pch_gbe_init_stats(adapter); 1975 1976 netdev_dbg(netdev, 1977 "rx_buffer_len : %d mac.min_frame_size : %d mac.max_frame_size : %d\n", 1978 (u32) adapter->rx_buffer_len, 1979 hw->mac.min_frame_size, hw->mac.max_frame_size); 1980 return 0; 1981 } 1982 1983 /** 1984 * pch_gbe_open - Called when a network interface is made active 1985 * @netdev: Network interface device structure 1986 * Returns: 1987 * 0: Successfully 1988 * Negative value: Failed 1989 */ 1990 static int pch_gbe_open(struct net_device *netdev) 1991 { 1992 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 1993 struct pch_gbe_hw *hw = &adapter->hw; 1994 int err; 1995 1996 /* allocate transmit descriptors */ 1997 err = pch_gbe_setup_tx_resources(adapter, adapter->tx_ring); 1998 if (err) 1999 goto err_setup_tx; 2000 /* allocate receive descriptors */ 2001 err = pch_gbe_setup_rx_resources(adapter, adapter->rx_ring); 2002 if (err) 2003 goto err_setup_rx; 2004 pch_gbe_phy_power_up(hw); 2005 err = pch_gbe_up(adapter); 2006 if (err) 2007 goto err_up; 2008 netdev_dbg(netdev, "Success End\n"); 2009 return 0; 2010 2011 err_up: 2012 if (!adapter->wake_up_evt) 2013 pch_gbe_phy_power_down(hw); 2014 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2015 err_setup_rx: 2016 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2017 err_setup_tx: 2018 pch_gbe_reset(adapter); 2019 netdev_err(netdev, "Error End\n"); 2020 return err; 2021 } 2022 2023 /** 2024 * pch_gbe_stop - Disables a network interface 2025 * @netdev: Network interface device structure 2026 * Returns: 2027 * 0: Successfully 2028 */ 2029 static int pch_gbe_stop(struct net_device *netdev) 2030 { 2031 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2032 struct pch_gbe_hw *hw = &adapter->hw; 2033 2034 pch_gbe_down(adapter); 2035 if (!adapter->wake_up_evt) 2036 pch_gbe_phy_power_down(hw); 2037 pch_gbe_free_tx_resources(adapter, adapter->tx_ring); 2038 pch_gbe_free_rx_resources(adapter, adapter->rx_ring); 2039 return 0; 2040 } 2041 2042 /** 2043 * pch_gbe_xmit_frame - Packet transmitting start 2044 * @skb: Socket buffer structure 2045 * @netdev: Network interface device structure 2046 * Returns: 2047 * - NETDEV_TX_OK: Normal end 2048 * - NETDEV_TX_BUSY: Error end 2049 */ 2050 static netdev_tx_t pch_gbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev) 2051 { 2052 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2053 struct pch_gbe_tx_ring *tx_ring = adapter->tx_ring; 2054 2055 if (unlikely(!PCH_GBE_DESC_UNUSED(tx_ring))) { 2056 netif_stop_queue(netdev); 2057 netdev_dbg(netdev, 2058 "Return : BUSY next_to use : 0x%08x next_to clean : 0x%08x\n", 2059 tx_ring->next_to_use, tx_ring->next_to_clean); 2060 return NETDEV_TX_BUSY; 2061 } 2062 2063 /* CRC,ITAG no support */ 2064 pch_gbe_tx_queue(adapter, tx_ring, skb); 2065 return NETDEV_TX_OK; 2066 } 2067 2068 /** 2069 * pch_gbe_set_multi - Multicast and Promiscuous mode set 2070 * @netdev: Network interface device structure 2071 */ 2072 static void pch_gbe_set_multi(struct net_device *netdev) 2073 { 2074 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2075 struct pch_gbe_hw *hw = &adapter->hw; 2076 struct netdev_hw_addr *ha; 2077 u32 rctl, adrmask; 2078 int mc_count, i; 2079 2080 netdev_dbg(netdev, "netdev->flags : 0x%08x\n", netdev->flags); 2081 2082 /* By default enable address & multicast filtering */ 2083 rctl = ioread32(&hw->reg->RX_MODE); 2084 rctl |= PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN; 2085 2086 /* Promiscuous mode disables all hardware address filtering */ 2087 if (netdev->flags & IFF_PROMISC) 2088 rctl &= ~(PCH_GBE_ADD_FIL_EN | PCH_GBE_MLT_FIL_EN); 2089 2090 /* If we want to monitor more multicast addresses than the hardware can 2091 * support then disable hardware multicast filtering. 2092 */ 2093 mc_count = netdev_mc_count(netdev); 2094 if ((netdev->flags & IFF_ALLMULTI) || mc_count >= PCH_GBE_MAR_ENTRIES) 2095 rctl &= ~PCH_GBE_MLT_FIL_EN; 2096 2097 iowrite32(rctl, &hw->reg->RX_MODE); 2098 2099 /* If we're not using multicast filtering then there's no point 2100 * configuring the unused MAC address registers. 2101 */ 2102 if (!(rctl & PCH_GBE_MLT_FIL_EN)) 2103 return; 2104 2105 /* Load the first set of multicast addresses into MAC address registers 2106 * for use by hardware filtering. 2107 */ 2108 i = 1; 2109 netdev_for_each_mc_addr(ha, netdev) 2110 pch_gbe_mac_mar_set(hw, ha->addr, i++); 2111 2112 /* If there are spare MAC registers, mask & clear them */ 2113 for (; i < PCH_GBE_MAR_ENTRIES; i++) { 2114 /* Clear MAC address mask */ 2115 adrmask = ioread32(&hw->reg->ADDR_MASK); 2116 iowrite32(adrmask | BIT(i), &hw->reg->ADDR_MASK); 2117 /* wait busy */ 2118 pch_gbe_wait_clr_bit(&hw->reg->ADDR_MASK, PCH_GBE_BUSY); 2119 /* Clear MAC address */ 2120 iowrite32(0, &hw->reg->mac_adr[i].high); 2121 iowrite32(0, &hw->reg->mac_adr[i].low); 2122 } 2123 2124 netdev_dbg(netdev, 2125 "RX_MODE reg(check bit31,30 ADD,MLT) : 0x%08x netdev->mc_count : 0x%08x\n", 2126 ioread32(&hw->reg->RX_MODE), mc_count); 2127 } 2128 2129 /** 2130 * pch_gbe_set_mac - Change the Ethernet Address of the NIC 2131 * @netdev: Network interface device structure 2132 * @addr: Pointer to an address structure 2133 * Returns: 2134 * 0: Successfully 2135 * -EADDRNOTAVAIL: Failed 2136 */ 2137 static int pch_gbe_set_mac(struct net_device *netdev, void *addr) 2138 { 2139 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2140 struct sockaddr *skaddr = addr; 2141 int ret_val; 2142 2143 if (!is_valid_ether_addr(skaddr->sa_data)) { 2144 ret_val = -EADDRNOTAVAIL; 2145 } else { 2146 memcpy(netdev->dev_addr, skaddr->sa_data, netdev->addr_len); 2147 memcpy(adapter->hw.mac.addr, skaddr->sa_data, netdev->addr_len); 2148 pch_gbe_mac_mar_set(&adapter->hw, adapter->hw.mac.addr, 0); 2149 ret_val = 0; 2150 } 2151 netdev_dbg(netdev, "ret_val : 0x%08x\n", ret_val); 2152 netdev_dbg(netdev, "dev_addr : %pM\n", netdev->dev_addr); 2153 netdev_dbg(netdev, "mac_addr : %pM\n", adapter->hw.mac.addr); 2154 netdev_dbg(netdev, "MAC_ADR1AB reg : 0x%08x 0x%08x\n", 2155 ioread32(&adapter->hw.reg->mac_adr[0].high), 2156 ioread32(&adapter->hw.reg->mac_adr[0].low)); 2157 return ret_val; 2158 } 2159 2160 /** 2161 * pch_gbe_change_mtu - Change the Maximum Transfer Unit 2162 * @netdev: Network interface device structure 2163 * @new_mtu: New value for maximum frame size 2164 * Returns: 2165 * 0: Successfully 2166 * -EINVAL: Failed 2167 */ 2168 static int pch_gbe_change_mtu(struct net_device *netdev, int new_mtu) 2169 { 2170 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2171 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN; 2172 unsigned long old_rx_buffer_len = adapter->rx_buffer_len; 2173 int err; 2174 2175 if (max_frame <= PCH_GBE_FRAME_SIZE_2048) 2176 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_2048; 2177 else if (max_frame <= PCH_GBE_FRAME_SIZE_4096) 2178 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_4096; 2179 else if (max_frame <= PCH_GBE_FRAME_SIZE_8192) 2180 adapter->rx_buffer_len = PCH_GBE_FRAME_SIZE_8192; 2181 else 2182 adapter->rx_buffer_len = PCH_GBE_MAX_RX_BUFFER_SIZE; 2183 2184 if (netif_running(netdev)) { 2185 pch_gbe_down(adapter); 2186 err = pch_gbe_up(adapter); 2187 if (err) { 2188 adapter->rx_buffer_len = old_rx_buffer_len; 2189 pch_gbe_up(adapter); 2190 return err; 2191 } else { 2192 netdev->mtu = new_mtu; 2193 adapter->hw.mac.max_frame_size = max_frame; 2194 } 2195 } else { 2196 pch_gbe_reset(adapter); 2197 netdev->mtu = new_mtu; 2198 adapter->hw.mac.max_frame_size = max_frame; 2199 } 2200 2201 netdev_dbg(netdev, 2202 "max_frame : %d rx_buffer_len : %d mtu : %d max_frame_size : %d\n", 2203 max_frame, (u32) adapter->rx_buffer_len, netdev->mtu, 2204 adapter->hw.mac.max_frame_size); 2205 return 0; 2206 } 2207 2208 /** 2209 * pch_gbe_set_features - Reset device after features changed 2210 * @netdev: Network interface device structure 2211 * @features: New features 2212 * Returns: 2213 * 0: HW state updated successfully 2214 */ 2215 static int pch_gbe_set_features(struct net_device *netdev, 2216 netdev_features_t features) 2217 { 2218 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2219 netdev_features_t changed = features ^ netdev->features; 2220 2221 if (!(changed & NETIF_F_RXCSUM)) 2222 return 0; 2223 2224 if (netif_running(netdev)) 2225 pch_gbe_reinit_locked(adapter); 2226 else 2227 pch_gbe_reset(adapter); 2228 2229 return 0; 2230 } 2231 2232 /** 2233 * pch_gbe_ioctl - Controls register through a MII interface 2234 * @netdev: Network interface device structure 2235 * @ifr: Pointer to ifr structure 2236 * @cmd: Control command 2237 * Returns: 2238 * 0: Successfully 2239 * Negative value: Failed 2240 */ 2241 static int pch_gbe_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) 2242 { 2243 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2244 2245 netdev_dbg(netdev, "cmd : 0x%04x\n", cmd); 2246 2247 if (cmd == SIOCSHWTSTAMP) 2248 return hwtstamp_ioctl(netdev, ifr, cmd); 2249 2250 return generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL); 2251 } 2252 2253 /** 2254 * pch_gbe_tx_timeout - Respond to a Tx Hang 2255 * @netdev: Network interface device structure 2256 * @txqueue: index of hanging queue 2257 */ 2258 static void pch_gbe_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2259 { 2260 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2261 2262 /* Do the reset outside of interrupt context */ 2263 adapter->stats.tx_timeout_count++; 2264 schedule_work(&adapter->reset_task); 2265 } 2266 2267 /** 2268 * pch_gbe_napi_poll - NAPI receive and transfer polling callback 2269 * @napi: Pointer of polling device struct 2270 * @budget: The maximum number of a packet 2271 * Returns: 2272 * false: Exit the polling mode 2273 * true: Continue the polling mode 2274 */ 2275 static int pch_gbe_napi_poll(struct napi_struct *napi, int budget) 2276 { 2277 struct pch_gbe_adapter *adapter = 2278 container_of(napi, struct pch_gbe_adapter, napi); 2279 int work_done = 0; 2280 bool poll_end_flag = false; 2281 bool cleaned = false; 2282 2283 netdev_dbg(adapter->netdev, "budget : %d\n", budget); 2284 2285 pch_gbe_clean_rx(adapter, adapter->rx_ring, &work_done, budget); 2286 cleaned = pch_gbe_clean_tx(adapter, adapter->tx_ring); 2287 2288 if (cleaned) 2289 work_done = budget; 2290 /* If no Tx and not enough Rx work done, 2291 * exit the polling mode 2292 */ 2293 if (work_done < budget) 2294 poll_end_flag = true; 2295 2296 if (poll_end_flag) { 2297 napi_complete_done(napi, work_done); 2298 pch_gbe_irq_enable(adapter); 2299 } 2300 2301 if (adapter->rx_stop_flag) { 2302 adapter->rx_stop_flag = false; 2303 pch_gbe_enable_dma_rx(&adapter->hw); 2304 } 2305 2306 netdev_dbg(adapter->netdev, 2307 "poll_end_flag : %d work_done : %d budget : %d\n", 2308 poll_end_flag, work_done, budget); 2309 2310 return work_done; 2311 } 2312 2313 #ifdef CONFIG_NET_POLL_CONTROLLER 2314 /** 2315 * pch_gbe_netpoll - Used by things like netconsole to send skbs 2316 * @netdev: Network interface device structure 2317 */ 2318 static void pch_gbe_netpoll(struct net_device *netdev) 2319 { 2320 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2321 2322 disable_irq(adapter->irq); 2323 pch_gbe_intr(adapter->irq, netdev); 2324 enable_irq(adapter->irq); 2325 } 2326 #endif 2327 2328 static const struct net_device_ops pch_gbe_netdev_ops = { 2329 .ndo_open = pch_gbe_open, 2330 .ndo_stop = pch_gbe_stop, 2331 .ndo_start_xmit = pch_gbe_xmit_frame, 2332 .ndo_set_mac_address = pch_gbe_set_mac, 2333 .ndo_tx_timeout = pch_gbe_tx_timeout, 2334 .ndo_change_mtu = pch_gbe_change_mtu, 2335 .ndo_set_features = pch_gbe_set_features, 2336 .ndo_do_ioctl = pch_gbe_ioctl, 2337 .ndo_set_rx_mode = pch_gbe_set_multi, 2338 #ifdef CONFIG_NET_POLL_CONTROLLER 2339 .ndo_poll_controller = pch_gbe_netpoll, 2340 #endif 2341 }; 2342 2343 static pci_ers_result_t pch_gbe_io_error_detected(struct pci_dev *pdev, 2344 pci_channel_state_t state) 2345 { 2346 struct net_device *netdev = pci_get_drvdata(pdev); 2347 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2348 2349 netif_device_detach(netdev); 2350 if (netif_running(netdev)) 2351 pch_gbe_down(adapter); 2352 pci_disable_device(pdev); 2353 /* Request a slot slot reset. */ 2354 return PCI_ERS_RESULT_NEED_RESET; 2355 } 2356 2357 static pci_ers_result_t pch_gbe_io_slot_reset(struct pci_dev *pdev) 2358 { 2359 struct net_device *netdev = pci_get_drvdata(pdev); 2360 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2361 struct pch_gbe_hw *hw = &adapter->hw; 2362 2363 if (pci_enable_device(pdev)) { 2364 netdev_err(netdev, "Cannot re-enable PCI device after reset\n"); 2365 return PCI_ERS_RESULT_DISCONNECT; 2366 } 2367 pci_set_master(pdev); 2368 pci_enable_wake(pdev, PCI_D0, 0); 2369 pch_gbe_phy_power_up(hw); 2370 pch_gbe_reset(adapter); 2371 /* Clear wake up status */ 2372 pch_gbe_mac_set_wol_event(hw, 0); 2373 2374 return PCI_ERS_RESULT_RECOVERED; 2375 } 2376 2377 static void pch_gbe_io_resume(struct pci_dev *pdev) 2378 { 2379 struct net_device *netdev = pci_get_drvdata(pdev); 2380 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2381 2382 if (netif_running(netdev)) { 2383 if (pch_gbe_up(adapter)) { 2384 netdev_dbg(netdev, 2385 "can't bring device back up after reset\n"); 2386 return; 2387 } 2388 } 2389 netif_device_attach(netdev); 2390 } 2391 2392 static int __pch_gbe_suspend(struct pci_dev *pdev) 2393 { 2394 struct net_device *netdev = pci_get_drvdata(pdev); 2395 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2396 struct pch_gbe_hw *hw = &adapter->hw; 2397 u32 wufc = adapter->wake_up_evt; 2398 2399 netif_device_detach(netdev); 2400 if (netif_running(netdev)) 2401 pch_gbe_down(adapter); 2402 if (wufc) { 2403 pch_gbe_set_multi(netdev); 2404 pch_gbe_setup_rctl(adapter); 2405 pch_gbe_configure_rx(adapter); 2406 pch_gbe_set_rgmii_ctrl(adapter, hw->mac.link_speed, 2407 hw->mac.link_duplex); 2408 pch_gbe_set_mode(adapter, hw->mac.link_speed, 2409 hw->mac.link_duplex); 2410 pch_gbe_mac_set_wol_event(hw, wufc); 2411 pci_disable_device(pdev); 2412 } else { 2413 pch_gbe_phy_power_down(hw); 2414 pch_gbe_mac_set_wol_event(hw, wufc); 2415 pci_disable_device(pdev); 2416 } 2417 return 0; 2418 } 2419 2420 #ifdef CONFIG_PM 2421 static int pch_gbe_suspend(struct device *device) 2422 { 2423 struct pci_dev *pdev = to_pci_dev(device); 2424 2425 return __pch_gbe_suspend(pdev); 2426 } 2427 2428 static int pch_gbe_resume(struct device *device) 2429 { 2430 struct pci_dev *pdev = to_pci_dev(device); 2431 struct net_device *netdev = pci_get_drvdata(pdev); 2432 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2433 struct pch_gbe_hw *hw = &adapter->hw; 2434 u32 err; 2435 2436 err = pci_enable_device(pdev); 2437 if (err) { 2438 netdev_err(netdev, "Cannot enable PCI device from suspend\n"); 2439 return err; 2440 } 2441 pci_set_master(pdev); 2442 pch_gbe_phy_power_up(hw); 2443 pch_gbe_reset(adapter); 2444 /* Clear wake on lan control and status */ 2445 pch_gbe_mac_set_wol_event(hw, 0); 2446 2447 if (netif_running(netdev)) 2448 pch_gbe_up(adapter); 2449 netif_device_attach(netdev); 2450 2451 return 0; 2452 } 2453 #endif /* CONFIG_PM */ 2454 2455 static void pch_gbe_shutdown(struct pci_dev *pdev) 2456 { 2457 __pch_gbe_suspend(pdev); 2458 if (system_state == SYSTEM_POWER_OFF) { 2459 pci_wake_from_d3(pdev, true); 2460 pci_set_power_state(pdev, PCI_D3hot); 2461 } 2462 } 2463 2464 static void pch_gbe_remove(struct pci_dev *pdev) 2465 { 2466 struct net_device *netdev = pci_get_drvdata(pdev); 2467 struct pch_gbe_adapter *adapter = netdev_priv(netdev); 2468 2469 cancel_work_sync(&adapter->reset_task); 2470 unregister_netdev(netdev); 2471 2472 pch_gbe_phy_hw_reset(&adapter->hw); 2473 2474 free_netdev(netdev); 2475 } 2476 2477 static int pch_gbe_probe(struct pci_dev *pdev, 2478 const struct pci_device_id *pci_id) 2479 { 2480 struct net_device *netdev; 2481 struct pch_gbe_adapter *adapter; 2482 int ret; 2483 2484 ret = pcim_enable_device(pdev); 2485 if (ret) 2486 return ret; 2487 2488 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) { 2489 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 2490 if (ret) { 2491 dev_err(&pdev->dev, "ERR: No usable DMA configuration, aborting\n"); 2492 return ret; 2493 } 2494 } 2495 2496 ret = pcim_iomap_regions(pdev, 1 << PCH_GBE_PCI_BAR, pci_name(pdev)); 2497 if (ret) { 2498 dev_err(&pdev->dev, 2499 "ERR: Can't reserve PCI I/O and memory resources\n"); 2500 return ret; 2501 } 2502 pci_set_master(pdev); 2503 2504 netdev = alloc_etherdev((int)sizeof(struct pch_gbe_adapter)); 2505 if (!netdev) 2506 return -ENOMEM; 2507 SET_NETDEV_DEV(netdev, &pdev->dev); 2508 2509 pci_set_drvdata(pdev, netdev); 2510 adapter = netdev_priv(netdev); 2511 adapter->netdev = netdev; 2512 adapter->pdev = pdev; 2513 adapter->hw.back = adapter; 2514 adapter->hw.reg = pcim_iomap_table(pdev)[PCH_GBE_PCI_BAR]; 2515 2516 adapter->pdata = (struct pch_gbe_privdata *)pci_id->driver_data; 2517 if (adapter->pdata && adapter->pdata->platform_init) { 2518 ret = adapter->pdata->platform_init(pdev); 2519 if (ret) 2520 goto err_free_netdev; 2521 } 2522 2523 adapter->ptp_pdev = 2524 pci_get_domain_bus_and_slot(pci_domain_nr(adapter->pdev->bus), 2525 adapter->pdev->bus->number, 2526 PCI_DEVFN(12, 4)); 2527 2528 netdev->netdev_ops = &pch_gbe_netdev_ops; 2529 netdev->watchdog_timeo = PCH_GBE_WATCHDOG_PERIOD; 2530 netif_napi_add(netdev, &adapter->napi, 2531 pch_gbe_napi_poll, PCH_GBE_RX_WEIGHT); 2532 netdev->hw_features = NETIF_F_RXCSUM | 2533 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM; 2534 netdev->features = netdev->hw_features; 2535 pch_gbe_set_ethtool_ops(netdev); 2536 2537 /* MTU range: 46 - 10300 */ 2538 netdev->min_mtu = ETH_ZLEN - ETH_HLEN; 2539 netdev->max_mtu = PCH_GBE_MAX_JUMBO_FRAME_SIZE - 2540 (ETH_HLEN + ETH_FCS_LEN); 2541 2542 pch_gbe_mac_load_mac_addr(&adapter->hw); 2543 pch_gbe_mac_reset_hw(&adapter->hw); 2544 2545 /* setup the private structure */ 2546 ret = pch_gbe_sw_init(adapter); 2547 if (ret) 2548 goto err_free_netdev; 2549 2550 /* Initialize PHY */ 2551 ret = pch_gbe_init_phy(adapter); 2552 if (ret) { 2553 dev_err(&pdev->dev, "PHY initialize error\n"); 2554 goto err_free_adapter; 2555 } 2556 2557 /* Read the MAC address. and store to the private data */ 2558 ret = pch_gbe_mac_read_mac_addr(&adapter->hw); 2559 if (ret) { 2560 dev_err(&pdev->dev, "MAC address Read Error\n"); 2561 goto err_free_adapter; 2562 } 2563 2564 memcpy(netdev->dev_addr, adapter->hw.mac.addr, netdev->addr_len); 2565 if (!is_valid_ether_addr(netdev->dev_addr)) { 2566 /* 2567 * If the MAC is invalid (or just missing), display a warning 2568 * but do not abort setting up the device. pch_gbe_up will 2569 * prevent the interface from being brought up until a valid MAC 2570 * is set. 2571 */ 2572 dev_err(&pdev->dev, "Invalid MAC address, " 2573 "interface disabled.\n"); 2574 } 2575 timer_setup(&adapter->watchdog_timer, pch_gbe_watchdog, 0); 2576 2577 INIT_WORK(&adapter->reset_task, pch_gbe_reset_task); 2578 2579 pch_gbe_check_options(adapter); 2580 2581 /* initialize the wol settings based on the eeprom settings */ 2582 adapter->wake_up_evt = PCH_GBE_WL_INIT_SETTING; 2583 dev_info(&pdev->dev, "MAC address : %pM\n", netdev->dev_addr); 2584 2585 /* reset the hardware with the new settings */ 2586 pch_gbe_reset(adapter); 2587 2588 ret = register_netdev(netdev); 2589 if (ret) 2590 goto err_free_adapter; 2591 /* tell the stack to leave us alone until pch_gbe_open() is called */ 2592 netif_carrier_off(netdev); 2593 netif_stop_queue(netdev); 2594 2595 dev_dbg(&pdev->dev, "PCH Network Connection\n"); 2596 2597 /* Disable hibernation on certain platforms */ 2598 if (adapter->pdata && adapter->pdata->phy_disable_hibernate) 2599 pch_gbe_phy_disable_hibernate(&adapter->hw); 2600 2601 device_set_wakeup_enable(&pdev->dev, 1); 2602 return 0; 2603 2604 err_free_adapter: 2605 pch_gbe_phy_hw_reset(&adapter->hw); 2606 err_free_netdev: 2607 free_netdev(netdev); 2608 return ret; 2609 } 2610 2611 static void pch_gbe_gpio_remove_table(void *table) 2612 { 2613 gpiod_remove_lookup_table(table); 2614 } 2615 2616 static int pch_gbe_gpio_add_table(struct device *dev, void *table) 2617 { 2618 gpiod_add_lookup_table(table); 2619 return devm_add_action_or_reset(dev, pch_gbe_gpio_remove_table, table); 2620 } 2621 2622 static struct gpiod_lookup_table pch_gbe_minnow_gpio_table = { 2623 .dev_id = "0000:02:00.1", 2624 .table = { 2625 GPIO_LOOKUP("sch_gpio.33158", 13, NULL, GPIO_ACTIVE_LOW), 2626 {} 2627 }, 2628 }; 2629 2630 /* The AR803X PHY on the MinnowBoard requires a physical pin to be toggled to 2631 * ensure it is awake for probe and init. Request the line and reset the PHY. 2632 */ 2633 static int pch_gbe_minnow_platform_init(struct pci_dev *pdev) 2634 { 2635 struct gpio_desc *gpiod; 2636 int ret; 2637 2638 ret = pch_gbe_gpio_add_table(&pdev->dev, &pch_gbe_minnow_gpio_table); 2639 if (ret) 2640 return ret; 2641 2642 gpiod = devm_gpiod_get(&pdev->dev, NULL, GPIOD_OUT_HIGH); 2643 if (IS_ERR(gpiod)) 2644 return dev_err_probe(&pdev->dev, PTR_ERR(gpiod), 2645 "Can't request PHY reset GPIO line\n"); 2646 2647 gpiod_set_value(gpiod, 1); 2648 usleep_range(1250, 1500); 2649 gpiod_set_value(gpiod, 0); 2650 usleep_range(1250, 1500); 2651 2652 return ret; 2653 } 2654 2655 static struct pch_gbe_privdata pch_gbe_minnow_privdata = { 2656 .phy_tx_clk_delay = true, 2657 .phy_disable_hibernate = true, 2658 .platform_init = pch_gbe_minnow_platform_init, 2659 }; 2660 2661 static const struct pci_device_id pch_gbe_pcidev_id[] = { 2662 {.vendor = PCI_VENDOR_ID_INTEL, 2663 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2664 .subvendor = PCI_VENDOR_ID_CIRCUITCO, 2665 .subdevice = PCI_SUBSYSTEM_ID_CIRCUITCO_MINNOWBOARD, 2666 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2667 .class_mask = (0xFFFF00), 2668 .driver_data = (kernel_ulong_t)&pch_gbe_minnow_privdata 2669 }, 2670 {.vendor = PCI_VENDOR_ID_INTEL, 2671 .device = PCI_DEVICE_ID_INTEL_IOH1_GBE, 2672 .subvendor = PCI_ANY_ID, 2673 .subdevice = PCI_ANY_ID, 2674 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2675 .class_mask = (0xFFFF00) 2676 }, 2677 {.vendor = PCI_VENDOR_ID_ROHM, 2678 .device = PCI_DEVICE_ID_ROHM_ML7223_GBE, 2679 .subvendor = PCI_ANY_ID, 2680 .subdevice = PCI_ANY_ID, 2681 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2682 .class_mask = (0xFFFF00) 2683 }, 2684 {.vendor = PCI_VENDOR_ID_ROHM, 2685 .device = PCI_DEVICE_ID_ROHM_ML7831_GBE, 2686 .subvendor = PCI_ANY_ID, 2687 .subdevice = PCI_ANY_ID, 2688 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), 2689 .class_mask = (0xFFFF00) 2690 }, 2691 /* required last entry */ 2692 {0} 2693 }; 2694 2695 #ifdef CONFIG_PM 2696 static const struct dev_pm_ops pch_gbe_pm_ops = { 2697 .suspend = pch_gbe_suspend, 2698 .resume = pch_gbe_resume, 2699 .freeze = pch_gbe_suspend, 2700 .thaw = pch_gbe_resume, 2701 .poweroff = pch_gbe_suspend, 2702 .restore = pch_gbe_resume, 2703 }; 2704 #endif 2705 2706 static const struct pci_error_handlers pch_gbe_err_handler = { 2707 .error_detected = pch_gbe_io_error_detected, 2708 .slot_reset = pch_gbe_io_slot_reset, 2709 .resume = pch_gbe_io_resume 2710 }; 2711 2712 static struct pci_driver pch_gbe_driver = { 2713 .name = KBUILD_MODNAME, 2714 .id_table = pch_gbe_pcidev_id, 2715 .probe = pch_gbe_probe, 2716 .remove = pch_gbe_remove, 2717 #ifdef CONFIG_PM 2718 .driver.pm = &pch_gbe_pm_ops, 2719 #endif 2720 .shutdown = pch_gbe_shutdown, 2721 .err_handler = &pch_gbe_err_handler 2722 }; 2723 module_pci_driver(pch_gbe_driver); 2724 2725 MODULE_DESCRIPTION("EG20T PCH Gigabit ethernet Driver"); 2726 MODULE_AUTHOR("LAPIS SEMICONDUCTOR, <tshimizu818@gmail.com>"); 2727 MODULE_LICENSE("GPL"); 2728 MODULE_DEVICE_TABLE(pci, pch_gbe_pcidev_id); 2729 2730 /* pch_gbe_main.c */ 2731