1 /*
2  * Copyright (C) 1999 - 2010 Intel Corporation.
3  * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
4  *
5  * This code was derived from the Intel e1000e Linux driver.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef _PCH_GBE_H_
21 #define _PCH_GBE_H_
22 
23 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
24 
25 #include <linux/mii.h>
26 #include <linux/delay.h>
27 #include <linux/pci.h>
28 #include <linux/netdevice.h>
29 #include <linux/etherdevice.h>
30 #include <linux/ethtool.h>
31 #include <linux/vmalloc.h>
32 #include <net/ip.h>
33 #include <net/tcp.h>
34 #include <net/udp.h>
35 
36 /**
37  * pch_gbe_regs_mac_adr - Structure holding values of mac address registers
38  * @high	Denotes the 1st to 4th byte from the initial of MAC address
39  * @low		Denotes the 5th to 6th byte from the initial of MAC address
40  */
41 struct pch_gbe_regs_mac_adr {
42 	u32 high;
43 	u32 low;
44 };
45 /**
46  * pch_udc_regs - Structure holding values of MAC registers
47  */
48 struct pch_gbe_regs {
49 	u32 INT_ST;
50 	u32 INT_EN;
51 	u32 MODE;
52 	u32 RESET;
53 	u32 TCPIP_ACC;
54 	u32 EX_LIST;
55 	u32 INT_ST_HOLD;
56 	u32 PHY_INT_CTRL;
57 	u32 MAC_RX_EN;
58 	u32 RX_FCTRL;
59 	u32 PAUSE_REQ;
60 	u32 RX_MODE;
61 	u32 TX_MODE;
62 	u32 RX_FIFO_ST;
63 	u32 TX_FIFO_ST;
64 	u32 TX_FID;
65 	u32 TX_RESULT;
66 	u32 PAUSE_PKT1;
67 	u32 PAUSE_PKT2;
68 	u32 PAUSE_PKT3;
69 	u32 PAUSE_PKT4;
70 	u32 PAUSE_PKT5;
71 	u32 reserve[2];
72 	struct pch_gbe_regs_mac_adr mac_adr[16];
73 	u32 ADDR_MASK;
74 	u32 MIIM;
75 	u32 MAC_ADDR_LOAD;
76 	u32 RGMII_ST;
77 	u32 RGMII_CTRL;
78 	u32 reserve3[3];
79 	u32 DMA_CTRL;
80 	u32 reserve4[3];
81 	u32 RX_DSC_BASE;
82 	u32 RX_DSC_SIZE;
83 	u32 RX_DSC_HW_P;
84 	u32 RX_DSC_HW_P_HLD;
85 	u32 RX_DSC_SW_P;
86 	u32 reserve5[3];
87 	u32 TX_DSC_BASE;
88 	u32 TX_DSC_SIZE;
89 	u32 TX_DSC_HW_P;
90 	u32 TX_DSC_HW_P_HLD;
91 	u32 TX_DSC_SW_P;
92 	u32 reserve6[3];
93 	u32 RX_DMA_ST;
94 	u32 TX_DMA_ST;
95 	u32 reserve7[2];
96 	u32 WOL_ST;
97 	u32 WOL_CTRL;
98 	u32 WOL_ADDR_MASK;
99 };
100 
101 /* Interrupt Status */
102 /* Interrupt Status Hold */
103 /* Interrupt Enable */
104 #define PCH_GBE_INT_RX_DMA_CMPLT  0x00000001 /* Receive DMA Transfer Complete */
105 #define PCH_GBE_INT_RX_VALID      0x00000002 /* MAC Normal Receive Complete */
106 #define PCH_GBE_INT_RX_FRAME_ERR  0x00000004 /* Receive frame error */
107 #define PCH_GBE_INT_RX_FIFO_ERR   0x00000008 /* Receive FIFO Overflow */
108 #define PCH_GBE_INT_RX_DMA_ERR    0x00000010 /* Receive DMA Transfer Error */
109 #define PCH_GBE_INT_RX_DSC_EMP    0x00000020 /* Receive Descriptor Empty */
110 #define PCH_GBE_INT_TX_CMPLT      0x00000100 /* MAC Transmission Complete */
111 #define PCH_GBE_INT_TX_DMA_CMPLT  0x00000200 /* DMA Transfer Complete */
112 #define PCH_GBE_INT_TX_FIFO_ERR   0x00000400 /* Transmission FIFO underflow. */
113 #define PCH_GBE_INT_TX_DMA_ERR    0x00000800 /* Transmission DMA Error */
114 #define PCH_GBE_INT_PAUSE_CMPLT   0x00001000 /* Pause Transmission complete */
115 #define PCH_GBE_INT_MIIM_CMPLT    0x00010000 /* MIIM I/F Read completion */
116 #define PCH_GBE_INT_PHY_INT       0x00100000 /* Interruption from PHY */
117 #define PCH_GBE_INT_WOL_DET       0x01000000 /* Wake On LAN Event detection. */
118 #define PCH_GBE_INT_TCPIP_ERR     0x10000000 /* TCP/IP Accelerator Error */
119 
120 /* Mode */
121 #define PCH_GBE_MODE_MII_ETHER      0x00000000  /* GIGA Ethernet Mode [MII] */
122 #define PCH_GBE_MODE_GMII_ETHER     0x80000000  /* GIGA Ethernet Mode [GMII] */
123 #define PCH_GBE_MODE_HALF_DUPLEX    0x00000000  /* Duplex Mode [half duplex] */
124 #define PCH_GBE_MODE_FULL_DUPLEX    0x40000000  /* Duplex Mode [full duplex] */
125 #define PCH_GBE_MODE_FR_BST         0x04000000  /* Frame bursting is done */
126 
127 /* Reset */
128 #define PCH_GBE_ALL_RST         0x80000000  /* All reset */
129 #define PCH_GBE_TX_RST          0x00008000  /* TX MAC, TX FIFO, TX DMA reset */
130 #define PCH_GBE_RX_RST          0x00004000  /* RX MAC, RX FIFO, RX DMA reset */
131 
132 /* TCP/IP Accelerator Control */
133 #define PCH_GBE_EX_LIST_EN      0x00000008  /* External List Enable */
134 #define PCH_GBE_RX_TCPIPACC_OFF 0x00000004  /* RX TCP/IP ACC Disabled */
135 #define PCH_GBE_TX_TCPIPACC_EN  0x00000002  /* TX TCP/IP ACC Enable */
136 #define PCH_GBE_RX_TCPIPACC_EN  0x00000001  /* RX TCP/IP ACC Enable */
137 
138 /* MAC RX Enable */
139 #define PCH_GBE_MRE_MAC_RX_EN   0x00000001      /* MAC Receive Enable */
140 
141 /* RX Flow Control */
142 #define PCH_GBE_FL_CTRL_EN      0x80000000  /* Pause packet is enabled */
143 
144 /* Pause Packet Request */
145 #define PCH_GBE_PS_PKT_RQ       0x80000000  /* Pause packet Request */
146 
147 /* RX Mode */
148 #define PCH_GBE_ADD_FIL_EN      0x80000000  /* Address Filtering Enable */
149 /* Multicast Filtering Enable */
150 #define PCH_GBE_MLT_FIL_EN      0x40000000
151 /* Receive Almost Empty Threshold */
152 #define PCH_GBE_RH_ALM_EMP_4    0x00000000      /* 4 words */
153 #define PCH_GBE_RH_ALM_EMP_8    0x00004000      /* 8 words */
154 #define PCH_GBE_RH_ALM_EMP_16   0x00008000      /* 16 words */
155 #define PCH_GBE_RH_ALM_EMP_32   0x0000C000      /* 32 words */
156 /* Receive Almost Full Threshold */
157 #define PCH_GBE_RH_ALM_FULL_4   0x00000000      /* 4 words */
158 #define PCH_GBE_RH_ALM_FULL_8   0x00001000      /* 8 words */
159 #define PCH_GBE_RH_ALM_FULL_16  0x00002000      /* 16 words */
160 #define PCH_GBE_RH_ALM_FULL_32  0x00003000      /* 32 words */
161 /* RX FIFO Read Triger Threshold */
162 #define PCH_GBE_RH_RD_TRG_4     0x00000000      /* 4 words */
163 #define PCH_GBE_RH_RD_TRG_8     0x00000200      /* 8 words */
164 #define PCH_GBE_RH_RD_TRG_16    0x00000400      /* 16 words */
165 #define PCH_GBE_RH_RD_TRG_32    0x00000600      /* 32 words */
166 #define PCH_GBE_RH_RD_TRG_64    0x00000800      /* 64 words */
167 #define PCH_GBE_RH_RD_TRG_128   0x00000A00      /* 128 words */
168 #define PCH_GBE_RH_RD_TRG_256   0x00000C00      /* 256 words */
169 #define PCH_GBE_RH_RD_TRG_512   0x00000E00      /* 512 words */
170 
171 /* Receive Descriptor bit definitions */
172 #define PCH_GBE_RXD_ACC_STAT_BCAST          0x00000400
173 #define PCH_GBE_RXD_ACC_STAT_MCAST          0x00000200
174 #define PCH_GBE_RXD_ACC_STAT_UCAST          0x00000100
175 #define PCH_GBE_RXD_ACC_STAT_TCPIPOK        0x000000C0
176 #define PCH_GBE_RXD_ACC_STAT_IPOK           0x00000080
177 #define PCH_GBE_RXD_ACC_STAT_TCPOK          0x00000040
178 #define PCH_GBE_RXD_ACC_STAT_IP6ERR         0x00000020
179 #define PCH_GBE_RXD_ACC_STAT_OFLIST         0x00000010
180 #define PCH_GBE_RXD_ACC_STAT_TYPEIP         0x00000008
181 #define PCH_GBE_RXD_ACC_STAT_MACL           0x00000004
182 #define PCH_GBE_RXD_ACC_STAT_PPPOE          0x00000002
183 #define PCH_GBE_RXD_ACC_STAT_VTAGT          0x00000001
184 #define PCH_GBE_RXD_GMAC_STAT_PAUSE         0x0200
185 #define PCH_GBE_RXD_GMAC_STAT_MARBR         0x0100
186 #define PCH_GBE_RXD_GMAC_STAT_MARMLT        0x0080
187 #define PCH_GBE_RXD_GMAC_STAT_MARIND        0x0040
188 #define PCH_GBE_RXD_GMAC_STAT_MARNOTMT      0x0020
189 #define PCH_GBE_RXD_GMAC_STAT_TLONG         0x0010
190 #define PCH_GBE_RXD_GMAC_STAT_TSHRT         0x0008
191 #define PCH_GBE_RXD_GMAC_STAT_NOTOCTAL      0x0004
192 #define PCH_GBE_RXD_GMAC_STAT_NBLERR        0x0002
193 #define PCH_GBE_RXD_GMAC_STAT_CRCERR        0x0001
194 
195 /* Transmit Descriptor bit definitions */
196 #define PCH_GBE_TXD_CTRL_TCPIP_ACC_OFF      0x0008
197 #define PCH_GBE_TXD_CTRL_ITAG               0x0004
198 #define PCH_GBE_TXD_CTRL_ICRC               0x0002
199 #define PCH_GBE_TXD_CTRL_APAD               0x0001
200 #define PCH_GBE_TXD_WORDS_SHIFT             2
201 #define PCH_GBE_TXD_GMAC_STAT_CMPLT         0x2000
202 #define PCH_GBE_TXD_GMAC_STAT_ABT           0x1000
203 #define PCH_GBE_TXD_GMAC_STAT_EXCOL         0x0800
204 #define PCH_GBE_TXD_GMAC_STAT_SNGCOL        0x0400
205 #define PCH_GBE_TXD_GMAC_STAT_MLTCOL        0x0200
206 #define PCH_GBE_TXD_GMAC_STAT_CRSER         0x0100
207 #define PCH_GBE_TXD_GMAC_STAT_TLNG          0x0080
208 #define PCH_GBE_TXD_GMAC_STAT_TSHRT         0x0040
209 #define PCH_GBE_TXD_GMAC_STAT_LTCOL         0x0020
210 #define PCH_GBE_TXD_GMAC_STAT_TFUNDFLW      0x0010
211 #define PCH_GBE_TXD_GMAC_STAT_RTYCNT_MASK   0x000F
212 
213 /* TX Mode */
214 #define PCH_GBE_TM_NO_RTRY     0x80000000 /* No Retransmission */
215 #define PCH_GBE_TM_LONG_PKT    0x40000000 /* Long Packt TX Enable */
216 #define PCH_GBE_TM_ST_AND_FD   0x20000000 /* Stare and Forward */
217 #define PCH_GBE_TM_SHORT_PKT   0x10000000 /* Short Packet TX Enable */
218 #define PCH_GBE_TM_LTCOL_RETX  0x08000000 /* Retransmission at Late Collision */
219 /* Frame Start Threshold */
220 #define PCH_GBE_TM_TH_TX_STRT_4    0x00000000    /* 4 words */
221 #define PCH_GBE_TM_TH_TX_STRT_8    0x00004000    /* 8 words */
222 #define PCH_GBE_TM_TH_TX_STRT_16   0x00008000    /* 16 words */
223 #define PCH_GBE_TM_TH_TX_STRT_32   0x0000C000    /* 32 words */
224 /* Transmit Almost Empty Threshold */
225 #define PCH_GBE_TM_TH_ALM_EMP_4    0x00000000    /* 4 words */
226 #define PCH_GBE_TM_TH_ALM_EMP_8    0x00000800    /* 8 words */
227 #define PCH_GBE_TM_TH_ALM_EMP_16   0x00001000    /* 16 words */
228 #define PCH_GBE_TM_TH_ALM_EMP_32   0x00001800    /* 32 words */
229 #define PCH_GBE_TM_TH_ALM_EMP_64   0x00002000    /* 64 words */
230 #define PCH_GBE_TM_TH_ALM_EMP_128  0x00002800    /* 128 words */
231 #define PCH_GBE_TM_TH_ALM_EMP_256  0x00003000    /* 256 words */
232 #define PCH_GBE_TM_TH_ALM_EMP_512  0x00003800    /* 512 words */
233 /* Transmit Almost Full Threshold */
234 #define PCH_GBE_TM_TH_ALM_FULL_4   0x00000000    /* 4 words */
235 #define PCH_GBE_TM_TH_ALM_FULL_8   0x00000200    /* 8 words */
236 #define PCH_GBE_TM_TH_ALM_FULL_16  0x00000400    /* 16 words */
237 #define PCH_GBE_TM_TH_ALM_FULL_32  0x00000600    /* 32 words */
238 
239 /* RX FIFO Status */
240 #define PCH_GBE_RF_ALM_FULL     0x80000000  /* RX FIFO is almost full. */
241 #define PCH_GBE_RF_ALM_EMP      0x40000000  /* RX FIFO is almost empty. */
242 #define PCH_GBE_RF_RD_TRG       0x20000000  /* Become more than RH_RD_TRG. */
243 #define PCH_GBE_RF_STRWD        0x1FFE0000  /* The word count of RX FIFO. */
244 #define PCH_GBE_RF_RCVING       0x00010000  /* Stored in RX FIFO. */
245 
246 /* MAC Address Mask */
247 #define PCH_GBE_BUSY                0x80000000
248 
249 /* MIIM  */
250 #define PCH_GBE_MIIM_OPER_WRITE     0x04000000
251 #define PCH_GBE_MIIM_OPER_READ      0x00000000
252 #define PCH_GBE_MIIM_OPER_READY     0x04000000
253 #define PCH_GBE_MIIM_PHY_ADDR_SHIFT 21
254 #define PCH_GBE_MIIM_REG_ADDR_SHIFT 16
255 
256 /* RGMII Status */
257 #define PCH_GBE_LINK_UP             0x80000008
258 #define PCH_GBE_RXC_SPEED_MSK       0x00000006
259 #define PCH_GBE_RXC_SPEED_2_5M      0x00000000    /* 2.5MHz */
260 #define PCH_GBE_RXC_SPEED_25M       0x00000002    /* 25MHz  */
261 #define PCH_GBE_RXC_SPEED_125M      0x00000004    /* 100MHz */
262 #define PCH_GBE_DUPLEX_FULL         0x00000001
263 
264 /* RGMII Control */
265 #define PCH_GBE_CRS_SEL             0x00000010
266 #define PCH_GBE_RGMII_RATE_125M     0x00000000
267 #define PCH_GBE_RGMII_RATE_25M      0x00000008
268 #define PCH_GBE_RGMII_RATE_2_5M     0x0000000C
269 #define PCH_GBE_RGMII_MODE_GMII     0x00000000
270 #define PCH_GBE_RGMII_MODE_RGMII    0x00000002
271 #define PCH_GBE_CHIP_TYPE_EXTERNAL  0x00000000
272 #define PCH_GBE_CHIP_TYPE_INTERNAL  0x00000001
273 
274 /* DMA Control */
275 #define PCH_GBE_RX_DMA_EN       0x00000002   /* Enables Receive DMA */
276 #define PCH_GBE_TX_DMA_EN       0x00000001   /* Enables Transmission DMA */
277 
278 /* RX DMA STATUS */
279 #define PCH_GBE_IDLE_CHECK       0xFFFFFFFE
280 
281 /* Wake On LAN Status */
282 #define PCH_GBE_WLS_BR          0x00000008 /* Broadcas Address */
283 #define PCH_GBE_WLS_MLT         0x00000004 /* Multicast Address */
284 
285 /* The Frame registered in Address Recognizer */
286 #define PCH_GBE_WLS_IND         0x00000002
287 #define PCH_GBE_WLS_MP          0x00000001 /* Magic packet Address */
288 
289 /* Wake On LAN Control */
290 #define PCH_GBE_WLC_WOL_MODE    0x00010000
291 #define PCH_GBE_WLC_IGN_TLONG   0x00000100
292 #define PCH_GBE_WLC_IGN_TSHRT   0x00000080
293 #define PCH_GBE_WLC_IGN_OCTER   0x00000040
294 #define PCH_GBE_WLC_IGN_NBLER   0x00000020
295 #define PCH_GBE_WLC_IGN_CRCER   0x00000010
296 #define PCH_GBE_WLC_BR          0x00000008
297 #define PCH_GBE_WLC_MLT         0x00000004
298 #define PCH_GBE_WLC_IND         0x00000002
299 #define PCH_GBE_WLC_MP          0x00000001
300 
301 /* Wake On LAN Address Mask */
302 #define PCH_GBE_WLA_BUSY        0x80000000
303 
304 
305 
306 /* TX/RX descriptor defines */
307 #define PCH_GBE_MAX_TXD                     4096
308 #define PCH_GBE_DEFAULT_TXD                  256
309 #define PCH_GBE_MIN_TXD                        8
310 #define PCH_GBE_MAX_RXD                     4096
311 #define PCH_GBE_DEFAULT_RXD                  256
312 #define PCH_GBE_MIN_RXD                        8
313 
314 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
315 #define PCH_GBE_TX_DESC_MULTIPLE               8
316 #define PCH_GBE_RX_DESC_MULTIPLE               8
317 
318 /* Read/Write operation is done through MII Management IF */
319 #define PCH_GBE_HAL_MIIM_READ          ((u32)0x00000000)
320 #define PCH_GBE_HAL_MIIM_WRITE         ((u32)0x04000000)
321 
322 /* flow control values */
323 #define PCH_GBE_FC_NONE			0
324 #define PCH_GBE_FC_RX_PAUSE		1
325 #define PCH_GBE_FC_TX_PAUSE		2
326 #define PCH_GBE_FC_FULL			3
327 #define PCH_GBE_FC_DEFAULT		PCH_GBE_FC_FULL
328 
329 /**
330  * struct pch_gbe_mac_info - MAC information
331  * @addr[6]:		Store the MAC address
332  * @fc:			Mode of flow control
333  * @fc_autoneg:		Auto negotiation enable for flow control setting
334  * @tx_fc_enable:	Enable flag of Transmit flow control
335  * @max_frame_size:	Max transmit frame size
336  * @min_frame_size:	Min transmit frame size
337  * @autoneg:		Auto negotiation enable
338  * @link_speed:		Link speed
339  * @link_duplex:	Link duplex
340  */
341 struct pch_gbe_mac_info {
342 	u8 addr[6];
343 	u8 fc;
344 	u8 fc_autoneg;
345 	u8 tx_fc_enable;
346 	u32 max_frame_size;
347 	u32 min_frame_size;
348 	u8 autoneg;
349 	u16 link_speed;
350 	u16 link_duplex;
351 };
352 
353 /**
354  * struct pch_gbe_phy_info - PHY information
355  * @addr:		PHY address
356  * @id:			PHY's identifier
357  * @revision:		PHY's revision
358  * @reset_delay_us:	HW reset delay time[us]
359  * @autoneg_advertised:	Autoneg advertised
360  */
361 struct pch_gbe_phy_info {
362 	u32 addr;
363 	u32 id;
364 	u32 revision;
365 	u32 reset_delay_us;
366 	u16 autoneg_advertised;
367 };
368 
369 /*!
370  * @ingroup Gigabit Ether driver Layer
371  * @struct  pch_gbe_hw
372  * @brief   Hardware information
373  */
374 struct pch_gbe_hw {
375 	void *back;
376 
377 	struct pch_gbe_regs  __iomem *reg;
378 	spinlock_t miim_lock;
379 
380 	struct pch_gbe_mac_info mac;
381 	struct pch_gbe_phy_info phy;
382 };
383 
384 /**
385  * struct pch_gbe_rx_desc - Receive Descriptor
386  * @buffer_addr:	RX Frame Buffer Address
387  * @tcp_ip_status:	TCP/IP Accelerator Status
388  * @rx_words_eob:	RX word count and Byte position
389  * @gbec_status:	GMAC Status
390  * @dma_status:		DMA Status
391  * @reserved1:		Reserved
392  * @reserved2:		Reserved
393  */
394 struct pch_gbe_rx_desc {
395 	u32 buffer_addr;
396 	u32 tcp_ip_status;
397 	u16 rx_words_eob;
398 	u16 gbec_status;
399 	u8 dma_status;
400 	u8 reserved1;
401 	u16 reserved2;
402 };
403 
404 /**
405  * struct pch_gbe_tx_desc - Transmit Descriptor
406  * @buffer_addr:	TX Frame Buffer Address
407  * @length:		Data buffer length
408  * @reserved1:		Reserved
409  * @tx_words_eob:	TX word count and Byte position
410  * @tx_frame_ctrl:	TX Frame Control
411  * @dma_status:		DMA Status
412  * @reserved2:		Reserved
413  * @gbec_status:	GMAC Status
414  */
415 struct pch_gbe_tx_desc {
416 	u32 buffer_addr;
417 	u16 length;
418 	u16 reserved1;
419 	u16 tx_words_eob;
420 	u16 tx_frame_ctrl;
421 	u8 dma_status;
422 	u8 reserved2;
423 	u16 gbec_status;
424 };
425 
426 
427 /**
428  * struct pch_gbe_buffer - Buffer information
429  * @skb:	pointer to a socket buffer
430  * @dma:	DMA address
431  * @time_stamp:	time stamp
432  * @length:	data size
433  */
434 struct pch_gbe_buffer {
435 	struct sk_buff *skb;
436 	dma_addr_t dma;
437 	unsigned char *rx_buffer;
438 	unsigned long time_stamp;
439 	u16 length;
440 	bool mapped;
441 };
442 
443 /**
444  * struct pch_gbe_tx_ring - tx ring information
445  * @desc:	pointer to the descriptor ring memory
446  * @dma:	physical address of the descriptor ring
447  * @size:	length of descriptor ring in bytes
448  * @count:	number of descriptors in the ring
449  * @next_to_use:	next descriptor to associate a buffer with
450  * @next_to_clean:	next descriptor to check for DD status bit
451  * @buffer_info:	array of buffer information structs
452  */
453 struct pch_gbe_tx_ring {
454 	struct pch_gbe_tx_desc *desc;
455 	dma_addr_t dma;
456 	unsigned int size;
457 	unsigned int count;
458 	unsigned int next_to_use;
459 	unsigned int next_to_clean;
460 	struct pch_gbe_buffer *buffer_info;
461 };
462 
463 /**
464  * struct pch_gbe_rx_ring - rx ring information
465  * @desc:	pointer to the descriptor ring memory
466  * @dma:	physical address of the descriptor ring
467  * @size:	length of descriptor ring in bytes
468  * @count:	number of descriptors in the ring
469  * @next_to_use:	next descriptor to associate a buffer with
470  * @next_to_clean:	next descriptor to check for DD status bit
471  * @buffer_info:	array of buffer information structs
472  */
473 struct pch_gbe_rx_ring {
474 	struct pch_gbe_rx_desc *desc;
475 	dma_addr_t dma;
476 	unsigned char *rx_buff_pool;
477 	dma_addr_t rx_buff_pool_logic;
478 	unsigned int rx_buff_pool_size;
479 	unsigned int size;
480 	unsigned int count;
481 	unsigned int next_to_use;
482 	unsigned int next_to_clean;
483 	struct pch_gbe_buffer *buffer_info;
484 };
485 
486 /**
487  * struct pch_gbe_hw_stats - Statistics counters collected by the MAC
488  * @rx_packets:		    total packets received
489  * @tx_packets:		    total packets transmitted
490  * @rx_bytes:		    total bytes received
491  * @tx_bytes:		    total bytes transmitted
492  * @rx_errors:		    bad packets received
493  * @tx_errors:		    packet transmit problems
494  * @rx_dropped:		    no space in Linux buffers
495  * @tx_dropped:		    no space available in Linux
496  * @multicast:		    multicast packets received
497  * @collisions:		    collisions
498  * @rx_crc_errors:	    received packet with crc error
499  * @rx_frame_errors:	    received frame alignment error
500  * @rx_alloc_buff_failed:   allocate failure of a receive buffer
501  * @tx_length_errors:	    transmit length error
502  * @tx_aborted_errors:	    transmit aborted error
503  * @tx_carrier_errors:	    transmit carrier error
504  * @tx_timeout_count:	    Number of transmit timeout
505  * @tx_restart_count:	    Number of transmit restert
506  * @intr_rx_dsc_empty_count:	Interrupt count of receive descriptor empty
507  * @intr_rx_frame_err_count:	Interrupt count of receive frame error
508  * @intr_rx_fifo_err_count:	Interrupt count of receive FIFO error
509  * @intr_rx_dma_err_count:	Interrupt count of receive DMA error
510  * @intr_tx_fifo_err_count:	Interrupt count of transmit FIFO error
511  * @intr_tx_dma_err_count:	Interrupt count of transmit DMA error
512  * @intr_tcpip_err_count:	Interrupt count of TCP/IP Accelerator
513  */
514 struct pch_gbe_hw_stats {
515 	u32 rx_packets;
516 	u32 tx_packets;
517 	u32 rx_bytes;
518 	u32 tx_bytes;
519 	u32 rx_errors;
520 	u32 tx_errors;
521 	u32 rx_dropped;
522 	u32 tx_dropped;
523 	u32 multicast;
524 	u32 collisions;
525 	u32 rx_crc_errors;
526 	u32 rx_frame_errors;
527 	u32 rx_alloc_buff_failed;
528 	u32 tx_length_errors;
529 	u32 tx_aborted_errors;
530 	u32 tx_carrier_errors;
531 	u32 tx_timeout_count;
532 	u32 tx_restart_count;
533 	u32 intr_rx_dsc_empty_count;
534 	u32 intr_rx_frame_err_count;
535 	u32 intr_rx_fifo_err_count;
536 	u32 intr_rx_dma_err_count;
537 	u32 intr_tx_fifo_err_count;
538 	u32 intr_tx_dma_err_count;
539 	u32 intr_tcpip_err_count;
540 };
541 
542 /**
543  * struct pch_gbe_privdata - PCI Device ID driver data
544  * @phy_tx_clk_delay:		Bool, configure the PHY TX delay in software
545  * @phy_disable_hibernate:	Bool, disable PHY hibernation
546  * @platform_init:		Platform initialization callback, called from
547  *				probe, prior to PHY initialization.
548  */
549 struct pch_gbe_privdata {
550 	bool phy_tx_clk_delay;
551 	bool phy_disable_hibernate;
552 	int (*platform_init)(struct pci_dev *pdev);
553 };
554 
555 /**
556  * struct pch_gbe_adapter - board specific private data structure
557  * @stats_lock:	Spinlock structure for status
558  * @ethtool_lock:	Spinlock structure for ethtool
559  * @irq_sem:		Semaphore for interrupt
560  * @netdev:		Pointer of network device structure
561  * @pdev:		Pointer of pci device structure
562  * @polling_netdev:	Pointer of polling network device structure
563  * @napi:		NAPI structure
564  * @hw:			Pointer of hardware structure
565  * @stats:		Hardware status
566  * @reset_task:		Reset task
567  * @mii:		MII information structure
568  * @watchdog_timer:	Watchdog timer list
569  * @wake_up_evt:	Wake up event
570  * @config_space:	Configuration space
571  * @msg_enable:		Driver message level
572  * @led_status:		LED status
573  * @tx_ring:		Pointer of Tx descriptor ring structure
574  * @rx_ring:		Pointer of Rx descriptor ring structure
575  * @rx_buffer_len:	Receive buffer length
576  * @tx_queue_len:	Transmit queue length
577  * @pch_gbe_privdata:	PCI Device ID driver_data
578  */
579 
580 struct pch_gbe_adapter {
581 	spinlock_t stats_lock;
582 	spinlock_t ethtool_lock;
583 	atomic_t irq_sem;
584 	struct net_device *netdev;
585 	struct pci_dev *pdev;
586 	int irq;
587 	struct net_device *polling_netdev;
588 	struct napi_struct napi;
589 	struct pch_gbe_hw hw;
590 	struct pch_gbe_hw_stats stats;
591 	struct work_struct reset_task;
592 	struct mii_if_info mii;
593 	struct timer_list watchdog_timer;
594 	u32 wake_up_evt;
595 	u32 *config_space;
596 	unsigned long led_status;
597 	struct pch_gbe_tx_ring *tx_ring;
598 	struct pch_gbe_rx_ring *rx_ring;
599 	unsigned long rx_buffer_len;
600 	unsigned long tx_queue_len;
601 	bool rx_stop_flag;
602 	int hwts_tx_en;
603 	int hwts_rx_en;
604 	struct pci_dev *ptp_pdev;
605 	struct pch_gbe_privdata *pdata;
606 };
607 
608 #define pch_gbe_hw_to_adapter(hw)	container_of(hw, struct pch_gbe_adapter, hw)
609 
610 extern const char pch_driver_version[];
611 
612 /* pch_gbe_main.c */
613 int pch_gbe_up(struct pch_gbe_adapter *adapter);
614 void pch_gbe_down(struct pch_gbe_adapter *adapter);
615 void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter);
616 void pch_gbe_reset(struct pch_gbe_adapter *adapter);
617 int pch_gbe_setup_tx_resources(struct pch_gbe_adapter *adapter,
618 			       struct pch_gbe_tx_ring *txdr);
619 int pch_gbe_setup_rx_resources(struct pch_gbe_adapter *adapter,
620 			       struct pch_gbe_rx_ring *rxdr);
621 void pch_gbe_free_tx_resources(struct pch_gbe_adapter *adapter,
622 			       struct pch_gbe_tx_ring *tx_ring);
623 void pch_gbe_free_rx_resources(struct pch_gbe_adapter *adapter,
624 			       struct pch_gbe_rx_ring *rx_ring);
625 void pch_gbe_update_stats(struct pch_gbe_adapter *adapter);
626 u32 pch_ch_control_read(struct pci_dev *pdev);
627 void pch_ch_control_write(struct pci_dev *pdev, u32 val);
628 u32 pch_ch_event_read(struct pci_dev *pdev);
629 void pch_ch_event_write(struct pci_dev *pdev, u32 val);
630 u32 pch_src_uuid_lo_read(struct pci_dev *pdev);
631 u32 pch_src_uuid_hi_read(struct pci_dev *pdev);
632 u64 pch_rx_snap_read(struct pci_dev *pdev);
633 u64 pch_tx_snap_read(struct pci_dev *pdev);
634 int pch_set_station_address(u8 *addr, struct pci_dev *pdev);
635 
636 /* pch_gbe_param.c */
637 void pch_gbe_check_options(struct pch_gbe_adapter *adapter);
638 
639 /* pch_gbe_ethtool.c */
640 void pch_gbe_set_ethtool_ops(struct net_device *netdev);
641 
642 /* pch_gbe_mac.c */
643 s32 pch_gbe_mac_force_mac_fc(struct pch_gbe_hw *hw);
644 u16 pch_gbe_mac_ctrl_miim(struct pch_gbe_hw *hw, u32 addr, u32 dir, u32 reg,
645 			  u16 data);
646 #endif /* _PCH_GBE_H_ */
647