xref: /openbmc/linux/drivers/net/ethernet/ni/nixge.c (revision 7b73a9c8)
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016-2017, National Instruments Corp.
3  *
4  * Author: Moritz Fischer <mdf@kernel.org>
5  */
6 
7 #include <linux/etherdevice.h>
8 #include <linux/module.h>
9 #include <linux/netdevice.h>
10 #include <linux/of_address.h>
11 #include <linux/of_mdio.h>
12 #include <linux/of_net.h>
13 #include <linux/of_platform.h>
14 #include <linux/of_irq.h>
15 #include <linux/skbuff.h>
16 #include <linux/phy.h>
17 #include <linux/mii.h>
18 #include <linux/nvmem-consumer.h>
19 #include <linux/ethtool.h>
20 #include <linux/iopoll.h>
21 
22 #define TX_BD_NUM		64
23 #define RX_BD_NUM		128
24 
25 /* Axi DMA Register definitions */
26 #define XAXIDMA_TX_CR_OFFSET	0x00 /* Channel control */
27 #define XAXIDMA_TX_SR_OFFSET	0x04 /* Status */
28 #define XAXIDMA_TX_CDESC_OFFSET	0x08 /* Current descriptor pointer */
29 #define XAXIDMA_TX_TDESC_OFFSET	0x10 /* Tail descriptor pointer */
30 
31 #define XAXIDMA_RX_CR_OFFSET	0x30 /* Channel control */
32 #define XAXIDMA_RX_SR_OFFSET	0x34 /* Status */
33 #define XAXIDMA_RX_CDESC_OFFSET	0x38 /* Current descriptor pointer */
34 #define XAXIDMA_RX_TDESC_OFFSET	0x40 /* Tail descriptor pointer */
35 
36 #define XAXIDMA_CR_RUNSTOP_MASK	0x1 /* Start/stop DMA channel */
37 #define XAXIDMA_CR_RESET_MASK	0x4 /* Reset DMA engine */
38 
39 #define XAXIDMA_BD_CTRL_LENGTH_MASK	0x007FFFFF /* Requested len */
40 #define XAXIDMA_BD_CTRL_TXSOF_MASK	0x08000000 /* First tx packet */
41 #define XAXIDMA_BD_CTRL_TXEOF_MASK	0x04000000 /* Last tx packet */
42 #define XAXIDMA_BD_CTRL_ALL_MASK	0x0C000000 /* All control bits */
43 
44 #define XAXIDMA_DELAY_MASK		0xFF000000 /* Delay timeout counter */
45 #define XAXIDMA_COALESCE_MASK		0x00FF0000 /* Coalesce counter */
46 
47 #define XAXIDMA_DELAY_SHIFT		24
48 #define XAXIDMA_COALESCE_SHIFT		16
49 
50 #define XAXIDMA_IRQ_IOC_MASK		0x00001000 /* Completion intr */
51 #define XAXIDMA_IRQ_DELAY_MASK		0x00002000 /* Delay interrupt */
52 #define XAXIDMA_IRQ_ERROR_MASK		0x00004000 /* Error interrupt */
53 #define XAXIDMA_IRQ_ALL_MASK		0x00007000 /* All interrupts */
54 
55 /* Default TX/RX Threshold and waitbound values for SGDMA mode */
56 #define XAXIDMA_DFT_TX_THRESHOLD	24
57 #define XAXIDMA_DFT_TX_WAITBOUND	254
58 #define XAXIDMA_DFT_RX_THRESHOLD	24
59 #define XAXIDMA_DFT_RX_WAITBOUND	254
60 
61 #define XAXIDMA_BD_STS_ACTUAL_LEN_MASK	0x007FFFFF /* Actual len */
62 #define XAXIDMA_BD_STS_COMPLETE_MASK	0x80000000 /* Completed */
63 #define XAXIDMA_BD_STS_DEC_ERR_MASK	0x40000000 /* Decode error */
64 #define XAXIDMA_BD_STS_SLV_ERR_MASK	0x20000000 /* Slave error */
65 #define XAXIDMA_BD_STS_INT_ERR_MASK	0x10000000 /* Internal err */
66 #define XAXIDMA_BD_STS_ALL_ERR_MASK	0x70000000 /* All errors */
67 #define XAXIDMA_BD_STS_RXSOF_MASK	0x08000000 /* First rx pkt */
68 #define XAXIDMA_BD_STS_RXEOF_MASK	0x04000000 /* Last rx pkt */
69 #define XAXIDMA_BD_STS_ALL_MASK		0xFC000000 /* All status bits */
70 
71 #define NIXGE_REG_CTRL_OFFSET	0x4000
72 #define NIXGE_REG_INFO		0x00
73 #define NIXGE_REG_MAC_CTL	0x04
74 #define NIXGE_REG_PHY_CTL	0x08
75 #define NIXGE_REG_LED_CTL	0x0c
76 #define NIXGE_REG_MDIO_DATA	0x10
77 #define NIXGE_REG_MDIO_ADDR	0x14
78 #define NIXGE_REG_MDIO_OP	0x18
79 #define NIXGE_REG_MDIO_CTRL	0x1c
80 
81 #define NIXGE_ID_LED_CTL_EN	BIT(0)
82 #define NIXGE_ID_LED_CTL_VAL	BIT(1)
83 
84 #define NIXGE_MDIO_CLAUSE45	BIT(12)
85 #define NIXGE_MDIO_CLAUSE22	0
86 #define NIXGE_MDIO_OP(n)     (((n) & 0x3) << 10)
87 #define NIXGE_MDIO_OP_ADDRESS	0
88 #define NIXGE_MDIO_C45_WRITE	BIT(0)
89 #define NIXGE_MDIO_C45_READ	(BIT(1) | BIT(0))
90 #define NIXGE_MDIO_C22_WRITE	BIT(0)
91 #define NIXGE_MDIO_C22_READ	BIT(1)
92 #define NIXGE_MDIO_ADDR(n)   (((n) & 0x1f) << 5)
93 #define NIXGE_MDIO_MMD(n)    (((n) & 0x1f) << 0)
94 
95 #define NIXGE_REG_MAC_LSB	0x1000
96 #define NIXGE_REG_MAC_MSB	0x1004
97 
98 /* Packet size info */
99 #define NIXGE_HDR_SIZE		14 /* Size of Ethernet header */
100 #define NIXGE_TRL_SIZE		4 /* Size of Ethernet trailer (FCS) */
101 #define NIXGE_MTU		1500 /* Max MTU of an Ethernet frame */
102 #define NIXGE_JUMBO_MTU		9000 /* Max MTU of a jumbo Eth. frame */
103 
104 #define NIXGE_MAX_FRAME_SIZE	 (NIXGE_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
105 #define NIXGE_MAX_JUMBO_FRAME_SIZE \
106 	(NIXGE_JUMBO_MTU + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE)
107 
108 enum nixge_version {
109 	NIXGE_V2,
110 	NIXGE_V3,
111 	NIXGE_VERSION_COUNT
112 };
113 
114 struct nixge_hw_dma_bd {
115 	u32 next_lo;
116 	u32 next_hi;
117 	u32 phys_lo;
118 	u32 phys_hi;
119 	u32 reserved3;
120 	u32 reserved4;
121 	u32 cntrl;
122 	u32 status;
123 	u32 app0;
124 	u32 app1;
125 	u32 app2;
126 	u32 app3;
127 	u32 app4;
128 	u32 sw_id_offset_lo;
129 	u32 sw_id_offset_hi;
130 	u32 reserved6;
131 };
132 
133 #ifdef CONFIG_PHYS_ADDR_T_64BIT
134 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
135 	do { \
136 		(bd)->field##_lo = lower_32_bits((addr)); \
137 		(bd)->field##_hi = upper_32_bits((addr)); \
138 	} while (0)
139 #else
140 #define nixge_hw_dma_bd_set_addr(bd, field, addr) \
141 	((bd)->field##_lo = lower_32_bits((addr)))
142 #endif
143 
144 #define nixge_hw_dma_bd_set_phys(bd, addr) \
145 	nixge_hw_dma_bd_set_addr((bd), phys, (addr))
146 
147 #define nixge_hw_dma_bd_set_next(bd, addr) \
148 	nixge_hw_dma_bd_set_addr((bd), next, (addr))
149 
150 #define nixge_hw_dma_bd_set_offset(bd, addr) \
151 	nixge_hw_dma_bd_set_addr((bd), sw_id_offset, (addr))
152 
153 #ifdef CONFIG_PHYS_ADDR_T_64BIT
154 #define nixge_hw_dma_bd_get_addr(bd, field) \
155 	(dma_addr_t)((((u64)(bd)->field##_hi) << 32) | ((bd)->field##_lo))
156 #else
157 #define nixge_hw_dma_bd_get_addr(bd, field) \
158 	(dma_addr_t)((bd)->field##_lo)
159 #endif
160 
161 struct nixge_tx_skb {
162 	struct sk_buff *skb;
163 	dma_addr_t mapping;
164 	size_t size;
165 	bool mapped_as_page;
166 };
167 
168 struct nixge_priv {
169 	struct net_device *ndev;
170 	struct napi_struct napi;
171 	struct device *dev;
172 
173 	/* Connection to PHY device */
174 	struct device_node *phy_node;
175 	phy_interface_t		phy_mode;
176 
177 	int link;
178 	unsigned int speed;
179 	unsigned int duplex;
180 
181 	/* MDIO bus data */
182 	struct mii_bus *mii_bus;	/* MII bus reference */
183 
184 	/* IO registers, dma functions and IRQs */
185 	void __iomem *ctrl_regs;
186 	void __iomem *dma_regs;
187 
188 	struct tasklet_struct dma_err_tasklet;
189 
190 	int tx_irq;
191 	int rx_irq;
192 
193 	/* Buffer descriptors */
194 	struct nixge_hw_dma_bd *tx_bd_v;
195 	struct nixge_tx_skb *tx_skb;
196 	dma_addr_t tx_bd_p;
197 
198 	struct nixge_hw_dma_bd *rx_bd_v;
199 	dma_addr_t rx_bd_p;
200 	u32 tx_bd_ci;
201 	u32 tx_bd_tail;
202 	u32 rx_bd_ci;
203 
204 	u32 coalesce_count_rx;
205 	u32 coalesce_count_tx;
206 };
207 
208 static void nixge_dma_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
209 {
210 	writel(val, priv->dma_regs + offset);
211 }
212 
213 static void nixge_dma_write_desc_reg(struct nixge_priv *priv, off_t offset,
214 				     dma_addr_t addr)
215 {
216 	writel(lower_32_bits(addr), priv->dma_regs + offset);
217 #ifdef CONFIG_PHYS_ADDR_T_64BIT
218 	writel(upper_32_bits(addr), priv->dma_regs + offset + 4);
219 #endif
220 }
221 
222 static u32 nixge_dma_read_reg(const struct nixge_priv *priv, off_t offset)
223 {
224 	return readl(priv->dma_regs + offset);
225 }
226 
227 static void nixge_ctrl_write_reg(struct nixge_priv *priv, off_t offset, u32 val)
228 {
229 	writel(val, priv->ctrl_regs + offset);
230 }
231 
232 static u32 nixge_ctrl_read_reg(struct nixge_priv *priv, off_t offset)
233 {
234 	return readl(priv->ctrl_regs + offset);
235 }
236 
237 #define nixge_ctrl_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
238 	readl_poll_timeout((priv)->ctrl_regs + (addr), (val), (cond), \
239 			   (sleep_us), (timeout_us))
240 
241 #define nixge_dma_poll_timeout(priv, addr, val, cond, sleep_us, timeout_us) \
242 	readl_poll_timeout((priv)->dma_regs + (addr), (val), (cond), \
243 			   (sleep_us), (timeout_us))
244 
245 static void nixge_hw_dma_bd_release(struct net_device *ndev)
246 {
247 	struct nixge_priv *priv = netdev_priv(ndev);
248 	dma_addr_t phys_addr;
249 	struct sk_buff *skb;
250 	int i;
251 
252 	for (i = 0; i < RX_BD_NUM; i++) {
253 		phys_addr = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
254 						     phys);
255 
256 		dma_unmap_single(ndev->dev.parent, phys_addr,
257 				 NIXGE_MAX_JUMBO_FRAME_SIZE,
258 				 DMA_FROM_DEVICE);
259 
260 		skb = (struct sk_buff *)(uintptr_t)
261 			nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[i],
262 						 sw_id_offset);
263 		dev_kfree_skb(skb);
264 	}
265 
266 	if (priv->rx_bd_v)
267 		dma_free_coherent(ndev->dev.parent,
268 				  sizeof(*priv->rx_bd_v) * RX_BD_NUM,
269 				  priv->rx_bd_v,
270 				  priv->rx_bd_p);
271 
272 	if (priv->tx_skb)
273 		devm_kfree(ndev->dev.parent, priv->tx_skb);
274 
275 	if (priv->tx_bd_v)
276 		dma_free_coherent(ndev->dev.parent,
277 				  sizeof(*priv->tx_bd_v) * TX_BD_NUM,
278 				  priv->tx_bd_v,
279 				  priv->tx_bd_p);
280 }
281 
282 static int nixge_hw_dma_bd_init(struct net_device *ndev)
283 {
284 	struct nixge_priv *priv = netdev_priv(ndev);
285 	struct sk_buff *skb;
286 	dma_addr_t phys;
287 	u32 cr;
288 	int i;
289 
290 	/* Reset the indexes which are used for accessing the BDs */
291 	priv->tx_bd_ci = 0;
292 	priv->tx_bd_tail = 0;
293 	priv->rx_bd_ci = 0;
294 
295 	/* Allocate the Tx and Rx buffer descriptors. */
296 	priv->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
297 					   sizeof(*priv->tx_bd_v) * TX_BD_NUM,
298 					   &priv->tx_bd_p, GFP_KERNEL);
299 	if (!priv->tx_bd_v)
300 		goto out;
301 
302 	priv->tx_skb = devm_kcalloc(ndev->dev.parent,
303 				    TX_BD_NUM, sizeof(*priv->tx_skb),
304 				    GFP_KERNEL);
305 	if (!priv->tx_skb)
306 		goto out;
307 
308 	priv->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
309 					   sizeof(*priv->rx_bd_v) * RX_BD_NUM,
310 					   &priv->rx_bd_p, GFP_KERNEL);
311 	if (!priv->rx_bd_v)
312 		goto out;
313 
314 	for (i = 0; i < TX_BD_NUM; i++) {
315 		nixge_hw_dma_bd_set_next(&priv->tx_bd_v[i],
316 					 priv->tx_bd_p +
317 					 sizeof(*priv->tx_bd_v) *
318 					 ((i + 1) % TX_BD_NUM));
319 	}
320 
321 	for (i = 0; i < RX_BD_NUM; i++) {
322 		nixge_hw_dma_bd_set_next(&priv->rx_bd_v[i],
323 					 priv->rx_bd_p
324 					 + sizeof(*priv->rx_bd_v) *
325 					 ((i + 1) % RX_BD_NUM));
326 
327 		skb = netdev_alloc_skb_ip_align(ndev,
328 						NIXGE_MAX_JUMBO_FRAME_SIZE);
329 		if (!skb)
330 			goto out;
331 
332 		nixge_hw_dma_bd_set_offset(&priv->rx_bd_v[i], (uintptr_t)skb);
333 		phys = dma_map_single(ndev->dev.parent, skb->data,
334 				      NIXGE_MAX_JUMBO_FRAME_SIZE,
335 				      DMA_FROM_DEVICE);
336 
337 		nixge_hw_dma_bd_set_phys(&priv->rx_bd_v[i], phys);
338 
339 		priv->rx_bd_v[i].cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
340 	}
341 
342 	/* Start updating the Rx channel control register */
343 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
344 	/* Update the interrupt coalesce count */
345 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
346 	      ((priv->coalesce_count_rx) << XAXIDMA_COALESCE_SHIFT));
347 	/* Update the delay timer count */
348 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |
349 	      (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
350 	/* Enable coalesce, delay timer and error interrupts */
351 	cr |= XAXIDMA_IRQ_ALL_MASK;
352 	/* Write to the Rx channel control register */
353 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
354 
355 	/* Start updating the Tx channel control register */
356 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
357 	/* Update the interrupt coalesce count */
358 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
359 	      ((priv->coalesce_count_tx) << XAXIDMA_COALESCE_SHIFT));
360 	/* Update the delay timer count */
361 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
362 	      (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
363 	/* Enable coalesce, delay timer and error interrupts */
364 	cr |= XAXIDMA_IRQ_ALL_MASK;
365 	/* Write to the Tx channel control register */
366 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
367 
368 	/* Populate the tail pointer and bring the Rx Axi DMA engine out of
369 	 * halted state. This will make the Rx side ready for reception.
370 	 */
371 	nixge_dma_write_desc_reg(priv, XAXIDMA_RX_CDESC_OFFSET, priv->rx_bd_p);
372 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
373 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
374 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
375 	nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, priv->rx_bd_p +
376 			    (sizeof(*priv->rx_bd_v) * (RX_BD_NUM - 1)));
377 
378 	/* Write to the RS (Run-stop) bit in the Tx channel control register.
379 	 * Tx channel is now ready to run. But only after we write to the
380 	 * tail pointer register that the Tx channel will start transmitting.
381 	 */
382 	nixge_dma_write_desc_reg(priv, XAXIDMA_TX_CDESC_OFFSET, priv->tx_bd_p);
383 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
384 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
385 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
386 
387 	return 0;
388 out:
389 	nixge_hw_dma_bd_release(ndev);
390 	return -ENOMEM;
391 }
392 
393 static void __nixge_device_reset(struct nixge_priv *priv, off_t offset)
394 {
395 	u32 status;
396 	int err;
397 
398 	/* Reset Axi DMA. This would reset NIXGE Ethernet core as well.
399 	 * The reset process of Axi DMA takes a while to complete as all
400 	 * pending commands/transfers will be flushed or completed during
401 	 * this reset process.
402 	 */
403 	nixge_dma_write_reg(priv, offset, XAXIDMA_CR_RESET_MASK);
404 	err = nixge_dma_poll_timeout(priv, offset, status,
405 				     !(status & XAXIDMA_CR_RESET_MASK), 10,
406 				     1000);
407 	if (err)
408 		netdev_err(priv->ndev, "%s: DMA reset timeout!\n", __func__);
409 }
410 
411 static void nixge_device_reset(struct net_device *ndev)
412 {
413 	struct nixge_priv *priv = netdev_priv(ndev);
414 
415 	__nixge_device_reset(priv, XAXIDMA_TX_CR_OFFSET);
416 	__nixge_device_reset(priv, XAXIDMA_RX_CR_OFFSET);
417 
418 	if (nixge_hw_dma_bd_init(ndev))
419 		netdev_err(ndev, "%s: descriptor allocation failed\n",
420 			   __func__);
421 
422 	netif_trans_update(ndev);
423 }
424 
425 static void nixge_handle_link_change(struct net_device *ndev)
426 {
427 	struct nixge_priv *priv = netdev_priv(ndev);
428 	struct phy_device *phydev = ndev->phydev;
429 
430 	if (phydev->link != priv->link || phydev->speed != priv->speed ||
431 	    phydev->duplex != priv->duplex) {
432 		priv->link = phydev->link;
433 		priv->speed = phydev->speed;
434 		priv->duplex = phydev->duplex;
435 		phy_print_status(phydev);
436 	}
437 }
438 
439 static void nixge_tx_skb_unmap(struct nixge_priv *priv,
440 			       struct nixge_tx_skb *tx_skb)
441 {
442 	if (tx_skb->mapping) {
443 		if (tx_skb->mapped_as_page)
444 			dma_unmap_page(priv->ndev->dev.parent, tx_skb->mapping,
445 				       tx_skb->size, DMA_TO_DEVICE);
446 		else
447 			dma_unmap_single(priv->ndev->dev.parent,
448 					 tx_skb->mapping,
449 					 tx_skb->size, DMA_TO_DEVICE);
450 		tx_skb->mapping = 0;
451 	}
452 
453 	if (tx_skb->skb) {
454 		dev_kfree_skb_any(tx_skb->skb);
455 		tx_skb->skb = NULL;
456 	}
457 }
458 
459 static void nixge_start_xmit_done(struct net_device *ndev)
460 {
461 	struct nixge_priv *priv = netdev_priv(ndev);
462 	struct nixge_hw_dma_bd *cur_p;
463 	struct nixge_tx_skb *tx_skb;
464 	unsigned int status = 0;
465 	u32 packets = 0;
466 	u32 size = 0;
467 
468 	cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
469 	tx_skb = &priv->tx_skb[priv->tx_bd_ci];
470 
471 	status = cur_p->status;
472 
473 	while (status & XAXIDMA_BD_STS_COMPLETE_MASK) {
474 		nixge_tx_skb_unmap(priv, tx_skb);
475 		cur_p->status = 0;
476 
477 		size += status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
478 		packets++;
479 
480 		++priv->tx_bd_ci;
481 		priv->tx_bd_ci %= TX_BD_NUM;
482 		cur_p = &priv->tx_bd_v[priv->tx_bd_ci];
483 		tx_skb = &priv->tx_skb[priv->tx_bd_ci];
484 		status = cur_p->status;
485 	}
486 
487 	ndev->stats.tx_packets += packets;
488 	ndev->stats.tx_bytes += size;
489 
490 	if (packets)
491 		netif_wake_queue(ndev);
492 }
493 
494 static int nixge_check_tx_bd_space(struct nixge_priv *priv,
495 				   int num_frag)
496 {
497 	struct nixge_hw_dma_bd *cur_p;
498 
499 	cur_p = &priv->tx_bd_v[(priv->tx_bd_tail + num_frag) % TX_BD_NUM];
500 	if (cur_p->status & XAXIDMA_BD_STS_ALL_MASK)
501 		return NETDEV_TX_BUSY;
502 	return 0;
503 }
504 
505 static int nixge_start_xmit(struct sk_buff *skb, struct net_device *ndev)
506 {
507 	struct nixge_priv *priv = netdev_priv(ndev);
508 	struct nixge_hw_dma_bd *cur_p;
509 	struct nixge_tx_skb *tx_skb;
510 	dma_addr_t tail_p, cur_phys;
511 	skb_frag_t *frag;
512 	u32 num_frag;
513 	u32 ii;
514 
515 	num_frag = skb_shinfo(skb)->nr_frags;
516 	cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
517 	tx_skb = &priv->tx_skb[priv->tx_bd_tail];
518 
519 	if (nixge_check_tx_bd_space(priv, num_frag)) {
520 		if (!netif_queue_stopped(ndev))
521 			netif_stop_queue(ndev);
522 		return NETDEV_TX_OK;
523 	}
524 
525 	cur_phys = dma_map_single(ndev->dev.parent, skb->data,
526 				  skb_headlen(skb), DMA_TO_DEVICE);
527 	if (dma_mapping_error(ndev->dev.parent, cur_phys))
528 		goto drop;
529 	nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
530 
531 	cur_p->cntrl = skb_headlen(skb) | XAXIDMA_BD_CTRL_TXSOF_MASK;
532 
533 	tx_skb->skb = NULL;
534 	tx_skb->mapping = cur_phys;
535 	tx_skb->size = skb_headlen(skb);
536 	tx_skb->mapped_as_page = false;
537 
538 	for (ii = 0; ii < num_frag; ii++) {
539 		++priv->tx_bd_tail;
540 		priv->tx_bd_tail %= TX_BD_NUM;
541 		cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
542 		tx_skb = &priv->tx_skb[priv->tx_bd_tail];
543 		frag = &skb_shinfo(skb)->frags[ii];
544 
545 		cur_phys = skb_frag_dma_map(ndev->dev.parent, frag, 0,
546 					    skb_frag_size(frag),
547 					    DMA_TO_DEVICE);
548 		if (dma_mapping_error(ndev->dev.parent, cur_phys))
549 			goto frag_err;
550 		nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
551 
552 		cur_p->cntrl = skb_frag_size(frag);
553 
554 		tx_skb->skb = NULL;
555 		tx_skb->mapping = cur_phys;
556 		tx_skb->size = skb_frag_size(frag);
557 		tx_skb->mapped_as_page = true;
558 	}
559 
560 	/* last buffer of the frame */
561 	tx_skb->skb = skb;
562 
563 	cur_p->cntrl |= XAXIDMA_BD_CTRL_TXEOF_MASK;
564 
565 	tail_p = priv->tx_bd_p + sizeof(*priv->tx_bd_v) * priv->tx_bd_tail;
566 	/* Start the transfer */
567 	nixge_dma_write_desc_reg(priv, XAXIDMA_TX_TDESC_OFFSET, tail_p);
568 	++priv->tx_bd_tail;
569 	priv->tx_bd_tail %= TX_BD_NUM;
570 
571 	return NETDEV_TX_OK;
572 frag_err:
573 	for (; ii > 0; ii--) {
574 		if (priv->tx_bd_tail)
575 			priv->tx_bd_tail--;
576 		else
577 			priv->tx_bd_tail = TX_BD_NUM - 1;
578 
579 		tx_skb = &priv->tx_skb[priv->tx_bd_tail];
580 		nixge_tx_skb_unmap(priv, tx_skb);
581 
582 		cur_p = &priv->tx_bd_v[priv->tx_bd_tail];
583 		cur_p->status = 0;
584 	}
585 	dma_unmap_single(priv->ndev->dev.parent,
586 			 tx_skb->mapping,
587 			 tx_skb->size, DMA_TO_DEVICE);
588 drop:
589 	ndev->stats.tx_dropped++;
590 	return NETDEV_TX_OK;
591 }
592 
593 static int nixge_recv(struct net_device *ndev, int budget)
594 {
595 	struct nixge_priv *priv = netdev_priv(ndev);
596 	struct sk_buff *skb, *new_skb;
597 	struct nixge_hw_dma_bd *cur_p;
598 	dma_addr_t tail_p = 0, cur_phys = 0;
599 	u32 packets = 0;
600 	u32 length = 0;
601 	u32 size = 0;
602 
603 	cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
604 
605 	while ((cur_p->status & XAXIDMA_BD_STS_COMPLETE_MASK &&
606 		budget > packets)) {
607 		tail_p = priv->rx_bd_p + sizeof(*priv->rx_bd_v) *
608 			 priv->rx_bd_ci;
609 
610 		skb = (struct sk_buff *)(uintptr_t)
611 			nixge_hw_dma_bd_get_addr(cur_p, sw_id_offset);
612 
613 		length = cur_p->status & XAXIDMA_BD_STS_ACTUAL_LEN_MASK;
614 		if (length > NIXGE_MAX_JUMBO_FRAME_SIZE)
615 			length = NIXGE_MAX_JUMBO_FRAME_SIZE;
616 
617 		dma_unmap_single(ndev->dev.parent,
618 				 nixge_hw_dma_bd_get_addr(cur_p, phys),
619 				 NIXGE_MAX_JUMBO_FRAME_SIZE,
620 				 DMA_FROM_DEVICE);
621 
622 		skb_put(skb, length);
623 
624 		skb->protocol = eth_type_trans(skb, ndev);
625 		skb_checksum_none_assert(skb);
626 
627 		/* For now mark them as CHECKSUM_NONE since
628 		 * we don't have offload capabilities
629 		 */
630 		skb->ip_summed = CHECKSUM_NONE;
631 
632 		napi_gro_receive(&priv->napi, skb);
633 
634 		size += length;
635 		packets++;
636 
637 		new_skb = netdev_alloc_skb_ip_align(ndev,
638 						    NIXGE_MAX_JUMBO_FRAME_SIZE);
639 		if (!new_skb)
640 			return packets;
641 
642 		cur_phys = dma_map_single(ndev->dev.parent, new_skb->data,
643 					  NIXGE_MAX_JUMBO_FRAME_SIZE,
644 					  DMA_FROM_DEVICE);
645 		if (dma_mapping_error(ndev->dev.parent, cur_phys)) {
646 			/* FIXME: bail out and clean up */
647 			netdev_err(ndev, "Failed to map ...\n");
648 		}
649 		nixge_hw_dma_bd_set_phys(cur_p, cur_phys);
650 		cur_p->cntrl = NIXGE_MAX_JUMBO_FRAME_SIZE;
651 		cur_p->status = 0;
652 		nixge_hw_dma_bd_set_offset(cur_p, (uintptr_t)new_skb);
653 
654 		++priv->rx_bd_ci;
655 		priv->rx_bd_ci %= RX_BD_NUM;
656 		cur_p = &priv->rx_bd_v[priv->rx_bd_ci];
657 	}
658 
659 	ndev->stats.rx_packets += packets;
660 	ndev->stats.rx_bytes += size;
661 
662 	if (tail_p)
663 		nixge_dma_write_desc_reg(priv, XAXIDMA_RX_TDESC_OFFSET, tail_p);
664 
665 	return packets;
666 }
667 
668 static int nixge_poll(struct napi_struct *napi, int budget)
669 {
670 	struct nixge_priv *priv = container_of(napi, struct nixge_priv, napi);
671 	int work_done;
672 	u32 status, cr;
673 
674 	work_done = 0;
675 
676 	work_done = nixge_recv(priv->ndev, budget);
677 	if (work_done < budget) {
678 		napi_complete_done(napi, work_done);
679 		status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
680 
681 		if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
682 			/* If there's more, reschedule, but clear */
683 			nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
684 			napi_reschedule(napi);
685 		} else {
686 			/* if not, turn on RX IRQs again ... */
687 			cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
688 			cr |= (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
689 			nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
690 		}
691 	}
692 
693 	return work_done;
694 }
695 
696 static irqreturn_t nixge_tx_irq(int irq, void *_ndev)
697 {
698 	struct nixge_priv *priv = netdev_priv(_ndev);
699 	struct net_device *ndev = _ndev;
700 	unsigned int status;
701 	dma_addr_t phys;
702 	u32 cr;
703 
704 	status = nixge_dma_read_reg(priv, XAXIDMA_TX_SR_OFFSET);
705 	if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
706 		nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
707 		nixge_start_xmit_done(priv->ndev);
708 		goto out;
709 	}
710 	if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
711 		netdev_err(ndev, "No interrupts asserted in Tx path\n");
712 		return IRQ_NONE;
713 	}
714 	if (status & XAXIDMA_IRQ_ERROR_MASK) {
715 		phys = nixge_hw_dma_bd_get_addr(&priv->tx_bd_v[priv->tx_bd_ci],
716 						phys);
717 
718 		netdev_err(ndev, "DMA Tx error 0x%x\n", status);
719 		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
720 
721 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
722 		/* Disable coalesce, delay timer and error interrupts */
723 		cr &= (~XAXIDMA_IRQ_ALL_MASK);
724 		/* Write to the Tx channel control register */
725 		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
726 
727 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
728 		/* Disable coalesce, delay timer and error interrupts */
729 		cr &= (~XAXIDMA_IRQ_ALL_MASK);
730 		/* Write to the Rx channel control register */
731 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
732 
733 		tasklet_schedule(&priv->dma_err_tasklet);
734 		nixge_dma_write_reg(priv, XAXIDMA_TX_SR_OFFSET, status);
735 	}
736 out:
737 	return IRQ_HANDLED;
738 }
739 
740 static irqreturn_t nixge_rx_irq(int irq, void *_ndev)
741 {
742 	struct nixge_priv *priv = netdev_priv(_ndev);
743 	struct net_device *ndev = _ndev;
744 	unsigned int status;
745 	dma_addr_t phys;
746 	u32 cr;
747 
748 	status = nixge_dma_read_reg(priv, XAXIDMA_RX_SR_OFFSET);
749 	if (status & (XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK)) {
750 		/* Turn of IRQs because NAPI */
751 		nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
752 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
753 		cr &= ~(XAXIDMA_IRQ_IOC_MASK | XAXIDMA_IRQ_DELAY_MASK);
754 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
755 
756 		if (napi_schedule_prep(&priv->napi))
757 			__napi_schedule(&priv->napi);
758 		goto out;
759 	}
760 	if (!(status & XAXIDMA_IRQ_ALL_MASK)) {
761 		netdev_err(ndev, "No interrupts asserted in Rx path\n");
762 		return IRQ_NONE;
763 	}
764 	if (status & XAXIDMA_IRQ_ERROR_MASK) {
765 		phys = nixge_hw_dma_bd_get_addr(&priv->rx_bd_v[priv->rx_bd_ci],
766 						phys);
767 		netdev_err(ndev, "DMA Rx error 0x%x\n", status);
768 		netdev_err(ndev, "Current BD is at: 0x%llx\n", (u64)phys);
769 
770 		cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
771 		/* Disable coalesce, delay timer and error interrupts */
772 		cr &= (~XAXIDMA_IRQ_ALL_MASK);
773 		/* Finally write to the Tx channel control register */
774 		nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET, cr);
775 
776 		cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
777 		/* Disable coalesce, delay timer and error interrupts */
778 		cr &= (~XAXIDMA_IRQ_ALL_MASK);
779 		/* write to the Rx channel control register */
780 		nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET, cr);
781 
782 		tasklet_schedule(&priv->dma_err_tasklet);
783 		nixge_dma_write_reg(priv, XAXIDMA_RX_SR_OFFSET, status);
784 	}
785 out:
786 	return IRQ_HANDLED;
787 }
788 
789 static void nixge_dma_err_handler(unsigned long data)
790 {
791 	struct nixge_priv *lp = (struct nixge_priv *)data;
792 	struct nixge_hw_dma_bd *cur_p;
793 	struct nixge_tx_skb *tx_skb;
794 	u32 cr, i;
795 
796 	__nixge_device_reset(lp, XAXIDMA_TX_CR_OFFSET);
797 	__nixge_device_reset(lp, XAXIDMA_RX_CR_OFFSET);
798 
799 	for (i = 0; i < TX_BD_NUM; i++) {
800 		cur_p = &lp->tx_bd_v[i];
801 		tx_skb = &lp->tx_skb[i];
802 		nixge_tx_skb_unmap(lp, tx_skb);
803 
804 		nixge_hw_dma_bd_set_phys(cur_p, 0);
805 		cur_p->cntrl = 0;
806 		cur_p->status = 0;
807 		nixge_hw_dma_bd_set_offset(cur_p, 0);
808 	}
809 
810 	for (i = 0; i < RX_BD_NUM; i++) {
811 		cur_p = &lp->rx_bd_v[i];
812 		cur_p->status = 0;
813 	}
814 
815 	lp->tx_bd_ci = 0;
816 	lp->tx_bd_tail = 0;
817 	lp->rx_bd_ci = 0;
818 
819 	/* Start updating the Rx channel control register */
820 	cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
821 	/* Update the interrupt coalesce count */
822 	cr = ((cr & ~XAXIDMA_COALESCE_MASK) |
823 	      (XAXIDMA_DFT_RX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
824 	/* Update the delay timer count */
825 	cr = ((cr & ~XAXIDMA_DELAY_MASK) |
826 	      (XAXIDMA_DFT_RX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
827 	/* Enable coalesce, delay timer and error interrupts */
828 	cr |= XAXIDMA_IRQ_ALL_MASK;
829 	/* Finally write to the Rx channel control register */
830 	nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET, cr);
831 
832 	/* Start updating the Tx channel control register */
833 	cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
834 	/* Update the interrupt coalesce count */
835 	cr = (((cr & ~XAXIDMA_COALESCE_MASK)) |
836 	      (XAXIDMA_DFT_TX_THRESHOLD << XAXIDMA_COALESCE_SHIFT));
837 	/* Update the delay timer count */
838 	cr = (((cr & ~XAXIDMA_DELAY_MASK)) |
839 	      (XAXIDMA_DFT_TX_WAITBOUND << XAXIDMA_DELAY_SHIFT));
840 	/* Enable coalesce, delay timer and error interrupts */
841 	cr |= XAXIDMA_IRQ_ALL_MASK;
842 	/* Finally write to the Tx channel control register */
843 	nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET, cr);
844 
845 	/* Populate the tail pointer and bring the Rx Axi DMA engine out of
846 	 * halted state. This will make the Rx side ready for reception.
847 	 */
848 	nixge_dma_write_desc_reg(lp, XAXIDMA_RX_CDESC_OFFSET, lp->rx_bd_p);
849 	cr = nixge_dma_read_reg(lp, XAXIDMA_RX_CR_OFFSET);
850 	nixge_dma_write_reg(lp, XAXIDMA_RX_CR_OFFSET,
851 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
852 	nixge_dma_write_desc_reg(lp, XAXIDMA_RX_TDESC_OFFSET, lp->rx_bd_p +
853 			    (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
854 
855 	/* Write to the RS (Run-stop) bit in the Tx channel control register.
856 	 * Tx channel is now ready to run. But only after we write to the
857 	 * tail pointer register that the Tx channel will start transmitting
858 	 */
859 	nixge_dma_write_desc_reg(lp, XAXIDMA_TX_CDESC_OFFSET, lp->tx_bd_p);
860 	cr = nixge_dma_read_reg(lp, XAXIDMA_TX_CR_OFFSET);
861 	nixge_dma_write_reg(lp, XAXIDMA_TX_CR_OFFSET,
862 			    cr | XAXIDMA_CR_RUNSTOP_MASK);
863 }
864 
865 static int nixge_open(struct net_device *ndev)
866 {
867 	struct nixge_priv *priv = netdev_priv(ndev);
868 	struct phy_device *phy;
869 	int ret;
870 
871 	nixge_device_reset(ndev);
872 
873 	phy = of_phy_connect(ndev, priv->phy_node,
874 			     &nixge_handle_link_change, 0, priv->phy_mode);
875 	if (!phy)
876 		return -ENODEV;
877 
878 	phy_start(phy);
879 
880 	/* Enable tasklets for Axi DMA error handling */
881 	tasklet_init(&priv->dma_err_tasklet, nixge_dma_err_handler,
882 		     (unsigned long)priv);
883 
884 	napi_enable(&priv->napi);
885 
886 	/* Enable interrupts for Axi DMA Tx */
887 	ret = request_irq(priv->tx_irq, nixge_tx_irq, 0, ndev->name, ndev);
888 	if (ret)
889 		goto err_tx_irq;
890 	/* Enable interrupts for Axi DMA Rx */
891 	ret = request_irq(priv->rx_irq, nixge_rx_irq, 0, ndev->name, ndev);
892 	if (ret)
893 		goto err_rx_irq;
894 
895 	netif_start_queue(ndev);
896 
897 	return 0;
898 
899 err_rx_irq:
900 	free_irq(priv->tx_irq, ndev);
901 err_tx_irq:
902 	phy_stop(phy);
903 	phy_disconnect(phy);
904 	tasklet_kill(&priv->dma_err_tasklet);
905 	netdev_err(ndev, "request_irq() failed\n");
906 	return ret;
907 }
908 
909 static int nixge_stop(struct net_device *ndev)
910 {
911 	struct nixge_priv *priv = netdev_priv(ndev);
912 	u32 cr;
913 
914 	netif_stop_queue(ndev);
915 	napi_disable(&priv->napi);
916 
917 	if (ndev->phydev) {
918 		phy_stop(ndev->phydev);
919 		phy_disconnect(ndev->phydev);
920 	}
921 
922 	cr = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
923 	nixge_dma_write_reg(priv, XAXIDMA_RX_CR_OFFSET,
924 			    cr & (~XAXIDMA_CR_RUNSTOP_MASK));
925 	cr = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
926 	nixge_dma_write_reg(priv, XAXIDMA_TX_CR_OFFSET,
927 			    cr & (~XAXIDMA_CR_RUNSTOP_MASK));
928 
929 	tasklet_kill(&priv->dma_err_tasklet);
930 
931 	free_irq(priv->tx_irq, ndev);
932 	free_irq(priv->rx_irq, ndev);
933 
934 	nixge_hw_dma_bd_release(ndev);
935 
936 	return 0;
937 }
938 
939 static int nixge_change_mtu(struct net_device *ndev, int new_mtu)
940 {
941 	if (netif_running(ndev))
942 		return -EBUSY;
943 
944 	if ((new_mtu + NIXGE_HDR_SIZE + NIXGE_TRL_SIZE) >
945 	     NIXGE_MAX_JUMBO_FRAME_SIZE)
946 		return -EINVAL;
947 
948 	ndev->mtu = new_mtu;
949 
950 	return 0;
951 }
952 
953 static s32 __nixge_hw_set_mac_address(struct net_device *ndev)
954 {
955 	struct nixge_priv *priv = netdev_priv(ndev);
956 
957 	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_LSB,
958 			     (ndev->dev_addr[2]) << 24 |
959 			     (ndev->dev_addr[3] << 16) |
960 			     (ndev->dev_addr[4] << 8) |
961 			     (ndev->dev_addr[5] << 0));
962 
963 	nixge_ctrl_write_reg(priv, NIXGE_REG_MAC_MSB,
964 			     (ndev->dev_addr[1] | (ndev->dev_addr[0] << 8)));
965 
966 	return 0;
967 }
968 
969 static int nixge_net_set_mac_address(struct net_device *ndev, void *p)
970 {
971 	int err;
972 
973 	err = eth_mac_addr(ndev, p);
974 	if (!err)
975 		__nixge_hw_set_mac_address(ndev);
976 
977 	return err;
978 }
979 
980 static const struct net_device_ops nixge_netdev_ops = {
981 	.ndo_open = nixge_open,
982 	.ndo_stop = nixge_stop,
983 	.ndo_start_xmit = nixge_start_xmit,
984 	.ndo_change_mtu	= nixge_change_mtu,
985 	.ndo_set_mac_address = nixge_net_set_mac_address,
986 	.ndo_validate_addr = eth_validate_addr,
987 };
988 
989 static void nixge_ethtools_get_drvinfo(struct net_device *ndev,
990 				       struct ethtool_drvinfo *ed)
991 {
992 	strlcpy(ed->driver, "nixge", sizeof(ed->driver));
993 	strlcpy(ed->bus_info, "platform", sizeof(ed->bus_info));
994 }
995 
996 static int nixge_ethtools_get_coalesce(struct net_device *ndev,
997 				       struct ethtool_coalesce *ecoalesce)
998 {
999 	struct nixge_priv *priv = netdev_priv(ndev);
1000 	u32 regval = 0;
1001 
1002 	regval = nixge_dma_read_reg(priv, XAXIDMA_RX_CR_OFFSET);
1003 	ecoalesce->rx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1004 					     >> XAXIDMA_COALESCE_SHIFT;
1005 	regval = nixge_dma_read_reg(priv, XAXIDMA_TX_CR_OFFSET);
1006 	ecoalesce->tx_max_coalesced_frames = (regval & XAXIDMA_COALESCE_MASK)
1007 					     >> XAXIDMA_COALESCE_SHIFT;
1008 	return 0;
1009 }
1010 
1011 static int nixge_ethtools_set_coalesce(struct net_device *ndev,
1012 				       struct ethtool_coalesce *ecoalesce)
1013 {
1014 	struct nixge_priv *priv = netdev_priv(ndev);
1015 
1016 	if (netif_running(ndev)) {
1017 		netdev_err(ndev,
1018 			   "Please stop netif before applying configuration\n");
1019 		return -EBUSY;
1020 	}
1021 
1022 	if (ecoalesce->rx_coalesce_usecs ||
1023 	    ecoalesce->rx_coalesce_usecs_irq ||
1024 	    ecoalesce->rx_max_coalesced_frames_irq ||
1025 	    ecoalesce->tx_coalesce_usecs ||
1026 	    ecoalesce->tx_coalesce_usecs_irq ||
1027 	    ecoalesce->tx_max_coalesced_frames_irq ||
1028 	    ecoalesce->stats_block_coalesce_usecs ||
1029 	    ecoalesce->use_adaptive_rx_coalesce ||
1030 	    ecoalesce->use_adaptive_tx_coalesce ||
1031 	    ecoalesce->pkt_rate_low ||
1032 	    ecoalesce->rx_coalesce_usecs_low ||
1033 	    ecoalesce->rx_max_coalesced_frames_low ||
1034 	    ecoalesce->tx_coalesce_usecs_low ||
1035 	    ecoalesce->tx_max_coalesced_frames_low ||
1036 	    ecoalesce->pkt_rate_high ||
1037 	    ecoalesce->rx_coalesce_usecs_high ||
1038 	    ecoalesce->rx_max_coalesced_frames_high ||
1039 	    ecoalesce->tx_coalesce_usecs_high ||
1040 	    ecoalesce->tx_max_coalesced_frames_high ||
1041 	    ecoalesce->rate_sample_interval)
1042 		return -EOPNOTSUPP;
1043 	if (ecoalesce->rx_max_coalesced_frames)
1044 		priv->coalesce_count_rx = ecoalesce->rx_max_coalesced_frames;
1045 	if (ecoalesce->tx_max_coalesced_frames)
1046 		priv->coalesce_count_tx = ecoalesce->tx_max_coalesced_frames;
1047 
1048 	return 0;
1049 }
1050 
1051 static int nixge_ethtools_set_phys_id(struct net_device *ndev,
1052 				      enum ethtool_phys_id_state state)
1053 {
1054 	struct nixge_priv *priv = netdev_priv(ndev);
1055 	u32 ctrl;
1056 
1057 	ctrl = nixge_ctrl_read_reg(priv, NIXGE_REG_LED_CTL);
1058 	switch (state) {
1059 	case ETHTOOL_ID_ACTIVE:
1060 		ctrl |= NIXGE_ID_LED_CTL_EN;
1061 		/* Enable identification LED override*/
1062 		nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1063 		return 2;
1064 
1065 	case ETHTOOL_ID_ON:
1066 		ctrl |= NIXGE_ID_LED_CTL_VAL;
1067 		nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1068 		break;
1069 
1070 	case ETHTOOL_ID_OFF:
1071 		ctrl &= ~NIXGE_ID_LED_CTL_VAL;
1072 		nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1073 		break;
1074 
1075 	case ETHTOOL_ID_INACTIVE:
1076 		/* Restore LED settings */
1077 		ctrl &= ~NIXGE_ID_LED_CTL_EN;
1078 		nixge_ctrl_write_reg(priv, NIXGE_REG_LED_CTL, ctrl);
1079 		break;
1080 	}
1081 
1082 	return 0;
1083 }
1084 
1085 static const struct ethtool_ops nixge_ethtool_ops = {
1086 	.get_drvinfo    = nixge_ethtools_get_drvinfo,
1087 	.get_coalesce   = nixge_ethtools_get_coalesce,
1088 	.set_coalesce   = nixge_ethtools_set_coalesce,
1089 	.set_phys_id    = nixge_ethtools_set_phys_id,
1090 	.get_link_ksettings     = phy_ethtool_get_link_ksettings,
1091 	.set_link_ksettings     = phy_ethtool_set_link_ksettings,
1092 	.get_link		= ethtool_op_get_link,
1093 };
1094 
1095 static int nixge_mdio_read(struct mii_bus *bus, int phy_id, int reg)
1096 {
1097 	struct nixge_priv *priv = bus->priv;
1098 	u32 status, tmp;
1099 	int err;
1100 	u16 device;
1101 
1102 	if (reg & MII_ADDR_C45) {
1103 		device = (reg >> 16) & 0x1f;
1104 
1105 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1106 
1107 		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
1108 			| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1109 
1110 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1111 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1112 
1113 		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1114 					      !status, 10, 1000);
1115 		if (err) {
1116 			dev_err(priv->dev, "timeout setting address");
1117 			return err;
1118 		}
1119 
1120 		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_READ) |
1121 			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1122 	} else {
1123 		device = reg & 0x1f;
1124 
1125 		tmp = NIXGE_MDIO_CLAUSE22 | NIXGE_MDIO_OP(NIXGE_MDIO_C22_READ) |
1126 			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1127 	}
1128 
1129 	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1130 	nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1131 
1132 	err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1133 				      !status, 10, 1000);
1134 	if (err) {
1135 		dev_err(priv->dev, "timeout setting read command");
1136 		return err;
1137 	}
1138 
1139 	status = nixge_ctrl_read_reg(priv, NIXGE_REG_MDIO_DATA);
1140 
1141 	return status;
1142 }
1143 
1144 static int nixge_mdio_write(struct mii_bus *bus, int phy_id, int reg, u16 val)
1145 {
1146 	struct nixge_priv *priv = bus->priv;
1147 	u32 status, tmp;
1148 	u16 device;
1149 	int err;
1150 
1151 	if (reg & MII_ADDR_C45) {
1152 		device = (reg >> 16) & 0x1f;
1153 
1154 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_ADDR, reg & 0xffff);
1155 
1156 		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_OP_ADDRESS)
1157 			| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1158 
1159 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1160 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1161 
1162 		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1163 					      !status, 10, 1000);
1164 		if (err) {
1165 			dev_err(priv->dev, "timeout setting address");
1166 			return err;
1167 		}
1168 
1169 		tmp = NIXGE_MDIO_CLAUSE45 | NIXGE_MDIO_OP(NIXGE_MDIO_C45_WRITE)
1170 			| NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1171 
1172 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1173 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1174 		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1175 					      !status, 10, 1000);
1176 		if (err)
1177 			dev_err(priv->dev, "timeout setting write command");
1178 	} else {
1179 		device = reg & 0x1f;
1180 
1181 		tmp = NIXGE_MDIO_CLAUSE22 |
1182 			NIXGE_MDIO_OP(NIXGE_MDIO_C22_WRITE) |
1183 			NIXGE_MDIO_ADDR(phy_id) | NIXGE_MDIO_MMD(device);
1184 
1185 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_DATA, val);
1186 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_OP, tmp);
1187 		nixge_ctrl_write_reg(priv, NIXGE_REG_MDIO_CTRL, 1);
1188 
1189 		err = nixge_ctrl_poll_timeout(priv, NIXGE_REG_MDIO_CTRL, status,
1190 					      !status, 10, 1000);
1191 		if (err)
1192 			dev_err(priv->dev, "timeout setting write command");
1193 	}
1194 
1195 	return err;
1196 }
1197 
1198 static int nixge_mdio_setup(struct nixge_priv *priv, struct device_node *np)
1199 {
1200 	struct mii_bus *bus;
1201 
1202 	bus = devm_mdiobus_alloc(priv->dev);
1203 	if (!bus)
1204 		return -ENOMEM;
1205 
1206 	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii", dev_name(priv->dev));
1207 	bus->priv = priv;
1208 	bus->name = "nixge_mii_bus";
1209 	bus->read = nixge_mdio_read;
1210 	bus->write = nixge_mdio_write;
1211 	bus->parent = priv->dev;
1212 
1213 	priv->mii_bus = bus;
1214 
1215 	return of_mdiobus_register(bus, np);
1216 }
1217 
1218 static void *nixge_get_nvmem_address(struct device *dev)
1219 {
1220 	struct nvmem_cell *cell;
1221 	size_t cell_size;
1222 	char *mac;
1223 
1224 	cell = nvmem_cell_get(dev, "address");
1225 	if (IS_ERR(cell))
1226 		return NULL;
1227 
1228 	mac = nvmem_cell_read(cell, &cell_size);
1229 	nvmem_cell_put(cell);
1230 
1231 	return mac;
1232 }
1233 
1234 /* Match table for of_platform binding */
1235 static const struct of_device_id nixge_dt_ids[] = {
1236 	{ .compatible = "ni,xge-enet-2.00", .data = (void *)NIXGE_V2 },
1237 	{ .compatible = "ni,xge-enet-3.00", .data = (void *)NIXGE_V3 },
1238 	{},
1239 };
1240 MODULE_DEVICE_TABLE(of, nixge_dt_ids);
1241 
1242 static int nixge_of_get_resources(struct platform_device *pdev)
1243 {
1244 	const struct of_device_id *of_id;
1245 	enum nixge_version version;
1246 	struct resource *ctrlres;
1247 	struct resource *dmares;
1248 	struct net_device *ndev;
1249 	struct nixge_priv *priv;
1250 
1251 	ndev = platform_get_drvdata(pdev);
1252 	priv = netdev_priv(ndev);
1253 	of_id = of_match_node(nixge_dt_ids, pdev->dev.of_node);
1254 	if (!of_id)
1255 		return -ENODEV;
1256 
1257 	version = (enum nixge_version)of_id->data;
1258 	if (version <= NIXGE_V2)
1259 		dmares = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1260 	else
1261 		dmares = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1262 						      "dma");
1263 
1264 	priv->dma_regs = devm_ioremap_resource(&pdev->dev, dmares);
1265 	if (IS_ERR(priv->dma_regs)) {
1266 		netdev_err(ndev, "failed to map dma regs\n");
1267 		return PTR_ERR(priv->dma_regs);
1268 	}
1269 	if (version <= NIXGE_V2) {
1270 		priv->ctrl_regs = priv->dma_regs + NIXGE_REG_CTRL_OFFSET;
1271 	} else {
1272 		ctrlres = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1273 						       "ctrl");
1274 		priv->ctrl_regs = devm_ioremap_resource(&pdev->dev, ctrlres);
1275 	}
1276 	if (IS_ERR(priv->ctrl_regs)) {
1277 		netdev_err(ndev, "failed to map ctrl regs\n");
1278 		return PTR_ERR(priv->ctrl_regs);
1279 	}
1280 	return 0;
1281 }
1282 
1283 static int nixge_probe(struct platform_device *pdev)
1284 {
1285 	struct device_node *mn, *phy_node;
1286 	struct nixge_priv *priv;
1287 	struct net_device *ndev;
1288 	const u8 *mac_addr;
1289 	int err;
1290 
1291 	ndev = alloc_etherdev(sizeof(*priv));
1292 	if (!ndev)
1293 		return -ENOMEM;
1294 
1295 	platform_set_drvdata(pdev, ndev);
1296 	SET_NETDEV_DEV(ndev, &pdev->dev);
1297 
1298 	ndev->features = NETIF_F_SG;
1299 	ndev->netdev_ops = &nixge_netdev_ops;
1300 	ndev->ethtool_ops = &nixge_ethtool_ops;
1301 
1302 	/* MTU range: 64 - 9000 */
1303 	ndev->min_mtu = 64;
1304 	ndev->max_mtu = NIXGE_JUMBO_MTU;
1305 
1306 	mac_addr = nixge_get_nvmem_address(&pdev->dev);
1307 	if (mac_addr && is_valid_ether_addr(mac_addr)) {
1308 		ether_addr_copy(ndev->dev_addr, mac_addr);
1309 		kfree(mac_addr);
1310 	} else {
1311 		eth_hw_addr_random(ndev);
1312 	}
1313 
1314 	priv = netdev_priv(ndev);
1315 	priv->ndev = ndev;
1316 	priv->dev = &pdev->dev;
1317 
1318 	netif_napi_add(ndev, &priv->napi, nixge_poll, NAPI_POLL_WEIGHT);
1319 	err = nixge_of_get_resources(pdev);
1320 	if (err)
1321 		return err;
1322 	__nixge_hw_set_mac_address(ndev);
1323 
1324 	priv->tx_irq = platform_get_irq_byname(pdev, "tx");
1325 	if (priv->tx_irq < 0) {
1326 		netdev_err(ndev, "could not find 'tx' irq");
1327 		return priv->tx_irq;
1328 	}
1329 
1330 	priv->rx_irq = platform_get_irq_byname(pdev, "rx");
1331 	if (priv->rx_irq < 0) {
1332 		netdev_err(ndev, "could not find 'rx' irq");
1333 		return priv->rx_irq;
1334 	}
1335 
1336 	priv->coalesce_count_rx = XAXIDMA_DFT_RX_THRESHOLD;
1337 	priv->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
1338 
1339 	mn = of_get_child_by_name(pdev->dev.of_node, "mdio");
1340 	if (mn) {
1341 		err = nixge_mdio_setup(priv, mn);
1342 		of_node_put(mn);
1343 		if (err) {
1344 			netdev_err(ndev, "error registering mdio bus");
1345 			goto free_netdev;
1346 		}
1347 	}
1348 
1349 	err = of_get_phy_mode(pdev->dev.of_node, &priv->phy_mode);
1350 	if (err) {
1351 		netdev_err(ndev, "not find \"phy-mode\" property\n");
1352 		goto unregister_mdio;
1353 	}
1354 
1355 	phy_node = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1356 	if (!phy_node && of_phy_is_fixed_link(pdev->dev.of_node)) {
1357 		err = of_phy_register_fixed_link(pdev->dev.of_node);
1358 		if (err < 0) {
1359 			netdev_err(ndev, "broken fixed-link specification\n");
1360 			goto unregister_mdio;
1361 		}
1362 		phy_node = of_node_get(pdev->dev.of_node);
1363 	}
1364 	priv->phy_node = phy_node;
1365 
1366 	err = register_netdev(priv->ndev);
1367 	if (err) {
1368 		netdev_err(ndev, "register_netdev() error (%i)\n", err);
1369 		goto free_phy;
1370 	}
1371 
1372 	return 0;
1373 
1374 free_phy:
1375 	if (of_phy_is_fixed_link(pdev->dev.of_node))
1376 		of_phy_deregister_fixed_link(pdev->dev.of_node);
1377 	of_node_put(phy_node);
1378 
1379 unregister_mdio:
1380 	if (priv->mii_bus)
1381 		mdiobus_unregister(priv->mii_bus);
1382 
1383 free_netdev:
1384 	free_netdev(ndev);
1385 
1386 	return err;
1387 }
1388 
1389 static int nixge_remove(struct platform_device *pdev)
1390 {
1391 	struct net_device *ndev = platform_get_drvdata(pdev);
1392 	struct nixge_priv *priv = netdev_priv(ndev);
1393 
1394 	unregister_netdev(ndev);
1395 
1396 	if (of_phy_is_fixed_link(pdev->dev.of_node))
1397 		of_phy_deregister_fixed_link(pdev->dev.of_node);
1398 	of_node_put(priv->phy_node);
1399 
1400 	if (priv->mii_bus)
1401 		mdiobus_unregister(priv->mii_bus);
1402 
1403 	free_netdev(ndev);
1404 
1405 	return 0;
1406 }
1407 
1408 static struct platform_driver nixge_driver = {
1409 	.probe		= nixge_probe,
1410 	.remove		= nixge_remove,
1411 	.driver		= {
1412 		.name		= "nixge",
1413 		.of_match_table	= of_match_ptr(nixge_dt_ids),
1414 	},
1415 };
1416 module_platform_driver(nixge_driver);
1417 
1418 MODULE_LICENSE("GPL v2");
1419 MODULE_DESCRIPTION("National Instruments XGE Management MAC");
1420 MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
1421