1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */ 3 4 /* nfp_net_ctrl.h 5 * Netronome network device driver: Control BAR layout 6 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 7 * Jason McMullan <jason.mcmullan@netronome.com> 8 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 9 * Brad Petrus <brad.petrus@netronome.com> 10 */ 11 12 #ifndef _NFP_NET_CTRL_H_ 13 #define _NFP_NET_CTRL_H_ 14 15 #include <linux/types.h> 16 17 /* Configuration BAR size. 18 * 19 * The configuration BAR is 8K in size, but due to 20 * THB-350, 32k needs to be reserved. 21 */ 22 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 23 24 /* Offset in Freelist buffer where packet starts on RX */ 25 #define NFP_NET_RX_OFFSET 32 26 27 /* LSO parameters 28 * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames 29 * %NFP_NET_LSO_MAX_SEGS: Maximum number of segments LSO frame can produce 30 */ 31 #define NFP_NET_LSO_MAX_HDR_SZ 255 32 #define NFP_NET_LSO_MAX_SEGS 64 33 34 /* Prepend field types */ 35 #define NFP_NET_META_FIELD_SIZE 4 36 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 37 #define NFP_NET_META_MARK 2 38 #define NFP_NET_META_PORTID 5 39 #define NFP_NET_META_CSUM 6 /* checksum complete type */ 40 #define NFP_NET_META_CONN_HANDLE 7 41 #define NFP_NET_META_RESYNC_INFO 8 /* RX resync info request */ 42 43 #define NFP_META_PORT_ID_CTRL ~0U 44 45 /* Hash type pre-pended when a RSS hash was computed */ 46 #define NFP_NET_RSS_NONE 0 47 #define NFP_NET_RSS_IPV4 1 48 #define NFP_NET_RSS_IPV6 2 49 #define NFP_NET_RSS_IPV6_EX 3 50 #define NFP_NET_RSS_IPV4_TCP 4 51 #define NFP_NET_RSS_IPV6_TCP 5 52 #define NFP_NET_RSS_IPV6_EX_TCP 6 53 #define NFP_NET_RSS_IPV4_UDP 7 54 #define NFP_NET_RSS_IPV6_UDP 8 55 #define NFP_NET_RSS_IPV6_EX_UDP 9 56 57 /* Ring counts 58 * %NFP_NET_TXR_MAX: Maximum number of TX rings 59 * %NFP_NET_RXR_MAX: Maximum number of RX rings 60 */ 61 #define NFP_NET_TXR_MAX 64 62 #define NFP_NET_RXR_MAX 64 63 64 /* Read/Write config words (0x0000 - 0x002c) 65 * %NFP_NET_CFG_CTRL: Global control 66 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated 67 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 68 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 69 * %NFP_NET_CFG_MTU: Set MTU size 70 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 71 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions 72 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes 73 * %NFP_NET_CFG_MACADDR: MAC address 74 * 75 * TODO: 76 * - define Error details in UPDATE 77 */ 78 #define NFP_NET_CFG_CTRL 0x0000 79 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 80 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 81 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 82 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 83 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 84 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 85 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 86 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 87 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 88 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 89 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */ 90 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */ 91 #define NFP_NET_CFG_CTRL_CMSG_DATA (0x1 << 12) /* RX cmsgs on data Qs */ 92 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 93 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */ 94 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 95 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 96 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 97 #define NFP_NET_CFG_CTRL_VEPA (0x1 << 22) /* Enable VEPA mode */ 98 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 99 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 100 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 101 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 102 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 103 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 104 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ 105 106 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \ 107 NFP_NET_CFG_CTRL_LSO2) 108 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \ 109 NFP_NET_CFG_CTRL_RSS2) 110 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \ 111 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 112 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 113 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 114 115 #define NFP_NET_CFG_UPDATE 0x0004 116 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 117 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 118 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 119 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 120 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 121 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 122 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 123 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 124 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 125 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 126 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 127 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 128 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 129 #define NFP_NET_CFG_UPDATE_CRYPTO (0x1 << 14) /* Crypto on/off */ 130 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 131 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 132 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 133 #define NFP_NET_CFG_MTU 0x0018 134 #define NFP_NET_CFG_FLBUFSZ 0x001c 135 #define NFP_NET_CFG_EXN 0x001f 136 #define NFP_NET_CFG_LSC 0x0020 137 #define NFP_NET_CFG_MACADDR 0x0024 138 139 /* Read-only words (0x0030 - 0x0050): 140 * %NFP_NET_CFG_VERSION: Firmware version number 141 * %NFP_NET_CFG_STS: Status 142 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL) 143 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 144 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 145 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU 146 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 147 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 148 * 149 * TODO: 150 * - define more STS bits 151 */ 152 #define NFP_NET_CFG_VERSION 0x0030 153 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xfe << 24) 154 #define NFP_NET_CFG_VERSION_DP_NFD3 0 155 #define NFP_NET_CFG_VERSION_DP_NFDK 1 156 #define NFP_NET_CFG_VERSION_DP_MASK 1 157 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 158 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 159 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 160 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 161 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 162 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 163 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 164 #define NFP_NET_CFG_STS 0x0034 165 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 166 /* Link rate */ 167 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 168 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 169 #define NFP_NET_CFG_STS_LINK_RATE \ 170 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT) 171 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 172 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 173 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 174 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 175 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 176 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 177 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 178 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 179 #define NFP_NET_CFG_CAP 0x0038 180 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 181 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 182 #define NFP_NET_CFG_MAX_MTU 0x0044 183 /* Next two words are being used by VFs for solving THB350 issue */ 184 #define NFP_NET_CFG_START_TXQ 0x0048 185 #define NFP_NET_CFG_START_RXQ 0x004c 186 187 /* Prepend configuration 188 */ 189 #define NFP_NET_CFG_RX_OFFSET 0x0050 190 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 191 192 /* RSS capabilities 193 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as 194 * %NFP_NET_CFG_RSS_HFUNC) 195 */ 196 #define NFP_NET_CFG_RSS_CAP 0x0054 197 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000 198 199 /* TLV area start 200 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area 201 */ 202 #define NFP_NET_CFG_TLV_BASE 0x0058 203 204 /* VXLAN/UDP encap configuration 205 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 206 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 207 */ 208 #define NFP_NET_CFG_VXLAN_PORT 0x0060 209 #define NFP_NET_CFG_VXLAN_SZ 0x0008 210 211 /* BPF section 212 * %NFP_NET_CFG_BPF_ABI: BPF ABI version 213 * %NFP_NET_CFG_BPF_CAP: BPF capabilities 214 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 215 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 216 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 217 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 218 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 219 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 220 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 221 */ 222 #define NFP_NET_CFG_BPF_ABI 0x0080 223 #define NFP_NET_CFG_BPF_CAP 0x0081 224 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 225 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 226 #define NFP_NET_CFG_BPF_START 0x0084 227 #define NFP_NET_CFG_BPF_DONE 0x0086 228 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 229 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 230 #define NFP_NET_CFG_BPF_SIZE 0x008e 231 #define NFP_NET_CFG_BPF_ADDR 0x0090 232 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 233 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 234 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 235 236 /* 40B reserved for future use (0x0098 - 0x00c0) 237 */ 238 #define NFP_NET_CFG_RESERVED 0x0098 239 #define NFP_NET_CFG_RESERVED_SZ 0x0028 240 241 /* RSS configuration (0x0100 - 0x01ac): 242 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 243 * %NFP_NET_CFG_RSS_CFG: RSS configuration word 244 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key 245 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table 246 */ 247 #define NFP_NET_CFG_RSS_BASE 0x0100 248 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 249 #define NFP_NET_CFG_RSS_MASK (0x7f) 250 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 251 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 252 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 253 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 254 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 255 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 256 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 257 #define NFP_NET_CFG_RSS_HFUNC 0xff000000 258 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 259 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */ 260 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */ 261 #define NFP_NET_CFG_RSS_HFUNCS 3 262 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 263 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 264 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 265 NFP_NET_CFG_RSS_KEY_SZ) 266 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 267 268 /* TX ring configuration (0x200 - 0x800) 269 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 270 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 271 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 272 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 273 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 274 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 275 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 276 */ 277 #define NFP_NET_CFG_TXR_BASE 0x0200 278 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 279 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 280 ((_x) * 0x8)) 281 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 282 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 283 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 284 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 285 ((_x) * 0x4)) 286 287 /* RX ring configuration (0x0800 - 0x0c00) 288 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 289 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 290 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 291 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 292 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 293 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 294 */ 295 #define NFP_NET_CFG_RXR_BASE 0x0800 296 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 297 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 298 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 299 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 300 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 301 ((_x) * 0x4)) 302 303 /* Interrupt Control/Cause registers (0x0c00 - 0x0d00) 304 * These registers are only used when MSI-X auto-masking is not 305 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 306 * by MSI-X entry and are 1B in size. If an entry is zero, the 307 * corresponding entry is enabled. If the FW generates an interrupt, 308 * it writes a cause into the corresponding field. This also masks 309 * the MSI-X entry and the host driver must clear the register to 310 * re-enable the interrupt. 311 */ 312 #define NFP_NET_CFG_ICR_BASE 0x0c00 313 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 314 #define NFP_NET_CFG_ICR_UNMASKED 0x0 315 #define NFP_NET_CFG_ICR_RXTX 0x1 316 #define NFP_NET_CFG_ICR_LSC 0x2 317 318 /* General device stats (0x0d00 - 0x0d90) 319 * all counters are 64bit. 320 */ 321 #define NFP_NET_CFG_STATS_BASE 0x0d00 322 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 323 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 324 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 325 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 326 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 327 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 328 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 329 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 330 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 331 332 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 333 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 334 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 335 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 336 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 337 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 338 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 339 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 340 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 341 342 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 343 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 344 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 345 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 346 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 347 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 348 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 349 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 350 351 /* Per ring stats (0x1000 - 0x1800) 352 * options, 64bit per entry 353 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 354 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 355 */ 356 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 357 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 358 ((_x) * 0x10)) 359 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 360 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 361 ((_x) * 0x10)) 362 363 /* General use mailbox area (0x1800 - 0x19ff) 364 * 4B used for update command and 4B return code 365 * followed by a max of 504B of variable length value 366 */ 367 #define NFP_NET_CFG_MBOX_BASE 0x1800 368 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8 369 370 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0 371 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4 372 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8 373 374 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1 375 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2 376 377 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET 5 378 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG 6 379 380 /* VLAN filtering using general use mailbox 381 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox 382 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter 383 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter 384 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes 385 */ 386 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL 387 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER 388 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2) 389 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004 390 391 /* TLV capabilities 392 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV 393 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV 394 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV 395 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments 396 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV 397 * 398 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE. 399 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs 400 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may 401 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs 402 * don't conflict with other features which allocate space beyond 403 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap 404 * space used by such features. 405 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH. 406 */ 407 #define NFP_NET_CFG_TLV_TYPE 0x00 408 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000 409 #define NFP_NET_CFG_TLV_LENGTH 0x02 410 #define NFP_NET_CFG_TLV_LENGTH_INC 4 411 #define NFP_NET_CFG_TLV_VALUE 0x04 412 413 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000 414 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000 415 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff 416 417 /* Capability TLV types 418 * 419 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN: 420 * Special TLV type to catch bugs, should never be encountered. Drivers should 421 * treat encountering this type as error and refuse to probe. 422 * 423 * %NFP_NET_CFG_TLV_TYPE_RESERVED: 424 * Reserved space, may contain legacy fixed-offset fields, or be used for 425 * padding. The use of this type should be otherwise avoided. 426 * 427 * %NFP_NET_CFG_TLV_TYPE_END: 428 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing 429 * further TLVs when encountered. 430 * 431 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ: 432 * Single word, ME frequency in MHz as used in calculation for 433 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD. 434 * 435 * %NFP_NET_CFG_TLV_TYPE_MBOX: 436 * Variable, mailbox area. Overwrites the default location which is 437 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ. 438 * 439 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0: 440 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1: 441 * Variable, experimental IDs. IDs designated for internal development and 442 * experiments before a stable TLV ID has been allocated to a feature. Should 443 * never be present in production firmware. 444 * 445 * %NFP_NET_CFG_TLV_TYPE_REPR_CAP: 446 * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which 447 * can be used on representors. 448 * 449 * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES: 450 * Variable, bitmap of control message types supported by the mailbox handler. 451 * Bit 0 corresponds to message type 0, bit 1 to 1, etc. Control messages are 452 * encapsulated into simple TLVs, with an end TLV and written to the Mailbox. 453 * 454 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS: 455 * 8 words, bitmaps of supported and enabled crypto operations. 456 * First 16B (4 words) contains a bitmap of supported crypto operations, 457 * and next 16B contain the enabled operations. 458 * This capability is made obsolete by ones with better sync methods. 459 * 460 * %NFP_NET_CFG_TLV_TYPE_VNIC_STATS: 461 * Variable, per-vNIC statistics, data should be 8B aligned (FW should insert 462 * zero-length RESERVED TLV to pad). 463 * TLV data has two sections. First is an array of statistics' IDs (2B each). 464 * Second 8B statistics themselves. Statistics are 8B aligned, meaning there 465 * may be a padding between sections. 466 * Number of statistics can be determined as floor(tlv.length / (2 + 8)). 467 * This TLV overwrites %NFP_NET_CFG_STATS_* values (statistics in this TLV 468 * duplicate the old ones, so driver should be careful not to unnecessarily 469 * render both). 470 * 471 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN: 472 * Same as %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS, but crypto TLS does stream scan 473 * RX sync, rather than kernel-assisted sync. 474 */ 475 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0 476 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1 477 #define NFP_NET_CFG_TLV_TYPE_END 2 478 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3 479 #define NFP_NET_CFG_TLV_TYPE_MBOX 4 480 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0 5 481 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1 6 482 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP 7 483 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES 10 484 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS 11 /* see crypto/fw.h */ 485 #define NFP_NET_CFG_TLV_TYPE_VNIC_STATS 12 486 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN 13 487 488 struct device; 489 490 /* struct nfp_net_tlv_caps - parsed control BAR TLV capabilities 491 * @me_freq_mhz: ME clock_freq (MHz) 492 * @mbox_off: vNIC mailbox area offset 493 * @mbox_len: vNIC mailbox area length 494 * @repr_cap: capabilities for representors 495 * @mbox_cmsg_types: cmsgs which can be passed through the mailbox 496 * @crypto_ops: supported crypto operations 497 * @crypto_enable_off: offset of crypto ops enable region 498 * @vnic_stats_off: offset of vNIC stats area 499 * @vnic_stats_cnt: number of vNIC stats 500 * @tls_resync_ss: TLS resync will be performed via stream scan 501 */ 502 struct nfp_net_tlv_caps { 503 u32 me_freq_mhz; 504 unsigned int mbox_off; 505 unsigned int mbox_len; 506 u32 repr_cap; 507 u32 mbox_cmsg_types; 508 u32 crypto_ops; 509 unsigned int crypto_enable_off; 510 unsigned int vnic_stats_off; 511 unsigned int vnic_stats_cnt; 512 unsigned int tls_resync_ss:1; 513 }; 514 515 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem, 516 struct nfp_net_tlv_caps *caps); 517 #endif /* _NFP_NET_CTRL_H_ */ 518