1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */ 3 4 /* 5 * nfp_net_ctrl.h 6 * Netronome network device driver: Control BAR layout 7 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 8 * Jason McMullan <jason.mcmullan@netronome.com> 9 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 10 * Brad Petrus <brad.petrus@netronome.com> 11 */ 12 13 #ifndef _NFP_NET_CTRL_H_ 14 #define _NFP_NET_CTRL_H_ 15 16 #include <linux/types.h> 17 18 /** 19 * Configuration BAR size. 20 * 21 * The configuration BAR is 8K in size, but due to 22 * THB-350, 32k needs to be reserved. 23 */ 24 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 25 26 /** 27 * Offset in Freelist buffer where packet starts on RX 28 */ 29 #define NFP_NET_RX_OFFSET 32 30 31 /** 32 * LSO parameters 33 * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames 34 * %NFP_NET_LSO_MAX_SEGS: Maximum number of segments LSO frame can produce 35 */ 36 #define NFP_NET_LSO_MAX_HDR_SZ 255 37 #define NFP_NET_LSO_MAX_SEGS 64 38 39 /** 40 * Prepend field types 41 */ 42 #define NFP_NET_META_FIELD_SIZE 4 43 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 44 #define NFP_NET_META_MARK 2 45 #define NFP_NET_META_PORTID 5 46 #define NFP_NET_META_CSUM 6 /* checksum complete type */ 47 48 #define NFP_META_PORT_ID_CTRL ~0U 49 50 /** 51 * Hash type pre-pended when a RSS hash was computed 52 */ 53 #define NFP_NET_RSS_NONE 0 54 #define NFP_NET_RSS_IPV4 1 55 #define NFP_NET_RSS_IPV6 2 56 #define NFP_NET_RSS_IPV6_EX 3 57 #define NFP_NET_RSS_IPV4_TCP 4 58 #define NFP_NET_RSS_IPV6_TCP 5 59 #define NFP_NET_RSS_IPV6_EX_TCP 6 60 #define NFP_NET_RSS_IPV4_UDP 7 61 #define NFP_NET_RSS_IPV6_UDP 8 62 #define NFP_NET_RSS_IPV6_EX_UDP 9 63 64 /** 65 * Ring counts 66 * %NFP_NET_TXR_MAX: Maximum number of TX rings 67 * %NFP_NET_RXR_MAX: Maximum number of RX rings 68 */ 69 #define NFP_NET_TXR_MAX 64 70 #define NFP_NET_RXR_MAX 64 71 72 /** 73 * Read/Write config words (0x0000 - 0x002c) 74 * %NFP_NET_CFG_CTRL: Global control 75 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated 76 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 77 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 78 * %NFP_NET_CFG_MTU: Set MTU size 79 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 80 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions 81 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes 82 * %NFP_NET_CFG_MACADDR: MAC address 83 * 84 * TODO: 85 * - define Error details in UPDATE 86 */ 87 #define NFP_NET_CFG_CTRL 0x0000 88 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 89 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 90 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 91 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 92 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 93 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 94 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 95 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 96 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 97 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 98 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */ 99 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */ 100 #define NFP_NET_CFG_CTRL_CMSG_DATA (0x1 << 12) /* RX cmsgs on data Qs */ 101 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 102 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */ 103 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 104 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 105 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 106 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 107 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 108 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 109 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 110 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 111 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 112 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 113 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 114 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 115 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ 116 117 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \ 118 NFP_NET_CFG_CTRL_LSO2) 119 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \ 120 NFP_NET_CFG_CTRL_RSS2) 121 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \ 122 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 123 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 124 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 125 126 #define NFP_NET_CFG_UPDATE 0x0004 127 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 128 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 129 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 130 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 131 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 132 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 133 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 134 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 135 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 136 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 137 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 138 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 139 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 140 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 141 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 142 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 143 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 144 #define NFP_NET_CFG_MTU 0x0018 145 #define NFP_NET_CFG_FLBUFSZ 0x001c 146 #define NFP_NET_CFG_EXN 0x001f 147 #define NFP_NET_CFG_LSC 0x0020 148 #define NFP_NET_CFG_MACADDR 0x0024 149 150 /** 151 * Read-only words (0x0030 - 0x0050): 152 * %NFP_NET_CFG_VERSION: Firmware version number 153 * %NFP_NET_CFG_STS: Status 154 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL) 155 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 156 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 157 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU 158 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 159 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 160 * 161 * TODO: 162 * - define more STS bits 163 */ 164 #define NFP_NET_CFG_VERSION 0x0030 165 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 166 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 167 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 168 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 169 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 170 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 171 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 172 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 173 #define NFP_NET_CFG_STS 0x0034 174 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 175 /* Link rate */ 176 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 177 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 178 #define NFP_NET_CFG_STS_LINK_RATE \ 179 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT) 180 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 181 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 182 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 183 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 184 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 185 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 186 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 187 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 188 #define NFP_NET_CFG_CAP 0x0038 189 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 190 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 191 #define NFP_NET_CFG_MAX_MTU 0x0044 192 /* Next two words are being used by VFs for solving THB350 issue */ 193 #define NFP_NET_CFG_START_TXQ 0x0048 194 #define NFP_NET_CFG_START_RXQ 0x004c 195 196 /** 197 * Prepend configuration 198 */ 199 #define NFP_NET_CFG_RX_OFFSET 0x0050 200 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 201 202 /** 203 * RSS capabilities 204 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as 205 * %NFP_NET_CFG_RSS_HFUNC) 206 */ 207 #define NFP_NET_CFG_RSS_CAP 0x0054 208 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000 209 210 /** 211 * TLV area start 212 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area 213 */ 214 #define NFP_NET_CFG_TLV_BASE 0x0058 215 216 /** 217 * VXLAN/UDP encap configuration 218 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 219 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 220 */ 221 #define NFP_NET_CFG_VXLAN_PORT 0x0060 222 #define NFP_NET_CFG_VXLAN_SZ 0x0008 223 224 /** 225 * BPF section 226 * %NFP_NET_CFG_BPF_ABI: BPF ABI version 227 * %NFP_NET_CFG_BPF_CAP: BPF capabilities 228 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 229 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 230 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 231 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 232 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 233 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 234 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 235 */ 236 #define NFP_NET_CFG_BPF_ABI 0x0080 237 #define NFP_NET_CFG_BPF_CAP 0x0081 238 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 239 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 240 #define NFP_NET_CFG_BPF_START 0x0084 241 #define NFP_NET_CFG_BPF_DONE 0x0086 242 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 243 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 244 #define NFP_NET_CFG_BPF_SIZE 0x008e 245 #define NFP_NET_CFG_BPF_ADDR 0x0090 246 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 247 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 248 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 249 250 /** 251 * 40B reserved for future use (0x0098 - 0x00c0) 252 */ 253 #define NFP_NET_CFG_RESERVED 0x0098 254 #define NFP_NET_CFG_RESERVED_SZ 0x0028 255 256 /** 257 * RSS configuration (0x0100 - 0x01ac): 258 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 259 * %NFP_NET_CFG_RSS_CFG: RSS configuration word 260 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key 261 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table 262 */ 263 #define NFP_NET_CFG_RSS_BASE 0x0100 264 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 265 #define NFP_NET_CFG_RSS_MASK (0x7f) 266 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 267 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 268 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 269 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 270 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 271 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 272 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 273 #define NFP_NET_CFG_RSS_HFUNC 0xff000000 274 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 275 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */ 276 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */ 277 #define NFP_NET_CFG_RSS_HFUNCS 3 278 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 279 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 280 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 281 NFP_NET_CFG_RSS_KEY_SZ) 282 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 283 284 /** 285 * TX ring configuration (0x200 - 0x800) 286 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 287 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 288 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 289 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 290 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 291 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 292 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 293 */ 294 #define NFP_NET_CFG_TXR_BASE 0x0200 295 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 296 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 297 ((_x) * 0x8)) 298 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 299 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 300 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 301 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 302 ((_x) * 0x4)) 303 304 /** 305 * RX ring configuration (0x0800 - 0x0c00) 306 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 307 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 308 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 309 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 310 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 311 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 312 */ 313 #define NFP_NET_CFG_RXR_BASE 0x0800 314 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 315 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 316 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 317 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 318 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 319 ((_x) * 0x4)) 320 321 /** 322 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 323 * These registers are only used when MSI-X auto-masking is not 324 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 325 * by MSI-X entry and are 1B in size. If an entry is zero, the 326 * corresponding entry is enabled. If the FW generates an interrupt, 327 * it writes a cause into the corresponding field. This also masks 328 * the MSI-X entry and the host driver must clear the register to 329 * re-enable the interrupt. 330 */ 331 #define NFP_NET_CFG_ICR_BASE 0x0c00 332 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 333 #define NFP_NET_CFG_ICR_UNMASKED 0x0 334 #define NFP_NET_CFG_ICR_RXTX 0x1 335 #define NFP_NET_CFG_ICR_LSC 0x2 336 337 /** 338 * General device stats (0x0d00 - 0x0d90) 339 * all counters are 64bit. 340 */ 341 #define NFP_NET_CFG_STATS_BASE 0x0d00 342 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 343 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 344 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 345 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 346 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 347 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 348 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 349 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 350 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 351 352 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 353 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 354 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 355 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 356 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 357 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 358 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 359 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 360 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 361 362 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 363 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 364 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 365 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 366 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 367 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 368 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 369 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 370 371 /** 372 * Per ring stats (0x1000 - 0x1800) 373 * options, 64bit per entry 374 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 375 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 376 */ 377 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 378 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 379 ((_x) * 0x10)) 380 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 381 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 382 ((_x) * 0x10)) 383 384 /** 385 * General use mailbox area (0x1800 - 0x19ff) 386 * 4B used for update command and 4B return code 387 * followed by a max of 504B of variable length value 388 */ 389 #define NFP_NET_CFG_MBOX_BASE 0x1800 390 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8 391 392 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0 393 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4 394 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8 395 #define NFP_NET_CFG_MBOX_SIMPLE_LEN 0x12 396 397 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1 398 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2 399 400 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET 5 401 402 /** 403 * VLAN filtering using general use mailbox 404 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox 405 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter 406 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter 407 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes 408 */ 409 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL 410 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER 411 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2) 412 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004 413 414 /** 415 * TLV capabilities 416 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV 417 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV 418 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV 419 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments 420 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV 421 * 422 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE. 423 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs 424 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may 425 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs 426 * don't conflict with other features which allocate space beyond 427 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap 428 * space used by such features. 429 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH. 430 */ 431 #define NFP_NET_CFG_TLV_TYPE 0x00 432 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000 433 #define NFP_NET_CFG_TLV_LENGTH 0x02 434 #define NFP_NET_CFG_TLV_LENGTH_INC 4 435 #define NFP_NET_CFG_TLV_VALUE 0x04 436 437 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000 438 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000 439 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff 440 441 /** 442 * Capability TLV types 443 * 444 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN: 445 * Special TLV type to catch bugs, should never be encountered. Drivers should 446 * treat encountering this type as error and refuse to probe. 447 * 448 * %NFP_NET_CFG_TLV_TYPE_RESERVED: 449 * Reserved space, may contain legacy fixed-offset fields, or be used for 450 * padding. The use of this type should be otherwise avoided. 451 * 452 * %NFP_NET_CFG_TLV_TYPE_END: 453 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing 454 * further TLVs when encountered. 455 * 456 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ: 457 * Single word, ME frequency in MHz as used in calculation for 458 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD. 459 * 460 * %NFP_NET_CFG_TLV_TYPE_MBOX: 461 * Variable, mailbox area. Overwrites the default location which is 462 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ. 463 * 464 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0: 465 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1: 466 * Variable, experimental IDs. IDs designated for internal development and 467 * experiments before a stable TLV ID has been allocated to a feature. Should 468 * never be present in production firmware. 469 * 470 * %NFP_NET_CFG_TLV_TYPE_REPR_CAP: 471 * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which 472 * can be used on representors. 473 */ 474 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0 475 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1 476 #define NFP_NET_CFG_TLV_TYPE_END 2 477 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3 478 #define NFP_NET_CFG_TLV_TYPE_MBOX 4 479 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0 5 480 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1 6 481 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP 7 482 483 struct device; 484 485 /** 486 * struct nfp_net_tlv_caps - parsed control BAR TLV capabilities 487 * @me_freq_mhz: ME clock_freq (MHz) 488 * @mbox_off: vNIC mailbox area offset 489 * @mbox_len: vNIC mailbox area length 490 * @repr_cap: capabilities for representors 491 */ 492 struct nfp_net_tlv_caps { 493 u32 me_freq_mhz; 494 unsigned int mbox_off; 495 unsigned int mbox_len; 496 u32 repr_cap; 497 }; 498 499 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem, 500 struct nfp_net_tlv_caps *caps); 501 502 static inline bool nfp_net_has_mbox(struct nfp_net_tlv_caps *caps) 503 { 504 return caps->mbox_len >= NFP_NET_CFG_MBOX_SIMPLE_LEN; 505 } 506 507 #endif /* _NFP_NET_CTRL_H_ */ 508