1 /* 2 * Copyright (C) 2015-2018 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net_ctrl.h 36 * Netronome network device driver: Control BAR layout 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 * Brad Petrus <brad.petrus@netronome.com> 41 */ 42 43 #ifndef _NFP_NET_CTRL_H_ 44 #define _NFP_NET_CTRL_H_ 45 46 #include <linux/types.h> 47 48 /** 49 * Configuration BAR size. 50 * 51 * The configuration BAR is 8K in size, but due to 52 * THB-350, 32k needs to be reserved. 53 */ 54 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 55 56 /** 57 * Offset in Freelist buffer where packet starts on RX 58 */ 59 #define NFP_NET_RX_OFFSET 32 60 61 /** 62 * LSO parameters 63 * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames 64 * %NFP_NET_LSO_MAX_SEGS: Maximum number of segments LSO frame can produce 65 */ 66 #define NFP_NET_LSO_MAX_HDR_SZ 255 67 #define NFP_NET_LSO_MAX_SEGS 64 68 69 /** 70 * Prepend field types 71 */ 72 #define NFP_NET_META_FIELD_SIZE 4 73 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 74 #define NFP_NET_META_MARK 2 75 #define NFP_NET_META_PORTID 5 76 #define NFP_NET_META_CSUM 6 /* checksum complete type */ 77 78 #define NFP_META_PORT_ID_CTRL ~0U 79 80 /** 81 * Hash type pre-pended when a RSS hash was computed 82 */ 83 #define NFP_NET_RSS_NONE 0 84 #define NFP_NET_RSS_IPV4 1 85 #define NFP_NET_RSS_IPV6 2 86 #define NFP_NET_RSS_IPV6_EX 3 87 #define NFP_NET_RSS_IPV4_TCP 4 88 #define NFP_NET_RSS_IPV6_TCP 5 89 #define NFP_NET_RSS_IPV6_EX_TCP 6 90 #define NFP_NET_RSS_IPV4_UDP 7 91 #define NFP_NET_RSS_IPV6_UDP 8 92 #define NFP_NET_RSS_IPV6_EX_UDP 9 93 94 /** 95 * Ring counts 96 * %NFP_NET_TXR_MAX: Maximum number of TX rings 97 * %NFP_NET_RXR_MAX: Maximum number of RX rings 98 */ 99 #define NFP_NET_TXR_MAX 64 100 #define NFP_NET_RXR_MAX 64 101 102 /** 103 * Read/Write config words (0x0000 - 0x002c) 104 * %NFP_NET_CFG_CTRL: Global control 105 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated 106 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 107 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 108 * %NFP_NET_CFG_MTU: Set MTU size 109 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 110 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions 111 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes 112 * %NFP_NET_CFG_MACADDR: MAC address 113 * 114 * TODO: 115 * - define Error details in UPDATE 116 */ 117 #define NFP_NET_CFG_CTRL 0x0000 118 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 119 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 120 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 121 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 122 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 123 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 124 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 125 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 126 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 127 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 128 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */ 129 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */ 130 #define NFP_NET_CFG_CTRL_CMSG_DATA (0x1 << 12) /* RX cmsgs on data Qs */ 131 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 132 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */ 133 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 134 #define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */ 135 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 136 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 137 #define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */ 138 #define NFP_NET_CFG_CTRL_L2SWITCH_LOCAL (0x1 << 23) /* Switch to local */ 139 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 140 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 141 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 142 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 143 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 144 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 145 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ 146 147 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \ 148 NFP_NET_CFG_CTRL_LSO2) 149 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \ 150 NFP_NET_CFG_CTRL_RSS2) 151 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \ 152 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 153 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 154 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 155 156 #define NFP_NET_CFG_UPDATE 0x0004 157 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 158 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 159 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 160 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 161 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 162 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 163 #define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */ 164 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 165 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 166 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 167 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 168 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 169 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 170 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 171 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 172 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 173 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 174 #define NFP_NET_CFG_MTU 0x0018 175 #define NFP_NET_CFG_FLBUFSZ 0x001c 176 #define NFP_NET_CFG_EXN 0x001f 177 #define NFP_NET_CFG_LSC 0x0020 178 #define NFP_NET_CFG_MACADDR 0x0024 179 180 /** 181 * Read-only words (0x0030 - 0x0050): 182 * %NFP_NET_CFG_VERSION: Firmware version number 183 * %NFP_NET_CFG_STS: Status 184 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL) 185 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 186 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 187 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU 188 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 189 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 190 * 191 * TODO: 192 * - define more STS bits 193 */ 194 #define NFP_NET_CFG_VERSION 0x0030 195 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xff << 24) 196 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 197 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 198 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 199 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 200 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 201 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 202 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 203 #define NFP_NET_CFG_STS 0x0034 204 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 205 /* Link rate */ 206 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 207 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 208 #define NFP_NET_CFG_STS_LINK_RATE \ 209 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT) 210 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 211 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 212 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 213 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 214 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 215 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 216 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 217 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 218 #define NFP_NET_CFG_CAP 0x0038 219 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 220 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 221 #define NFP_NET_CFG_MAX_MTU 0x0044 222 /* Next two words are being used by VFs for solving THB350 issue */ 223 #define NFP_NET_CFG_START_TXQ 0x0048 224 #define NFP_NET_CFG_START_RXQ 0x004c 225 226 /** 227 * Prepend configuration 228 */ 229 #define NFP_NET_CFG_RX_OFFSET 0x0050 230 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 231 232 /** 233 * RSS capabilities 234 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as 235 * %NFP_NET_CFG_RSS_HFUNC) 236 */ 237 #define NFP_NET_CFG_RSS_CAP 0x0054 238 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000 239 240 /** 241 * TLV area start 242 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area 243 */ 244 #define NFP_NET_CFG_TLV_BASE 0x0058 245 246 /** 247 * VXLAN/UDP encap configuration 248 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 249 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 250 */ 251 #define NFP_NET_CFG_VXLAN_PORT 0x0060 252 #define NFP_NET_CFG_VXLAN_SZ 0x0008 253 254 /** 255 * BPF section 256 * %NFP_NET_CFG_BPF_ABI: BPF ABI version 257 * %NFP_NET_CFG_BPF_CAP: BPF capabilities 258 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 259 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 260 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 261 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 262 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 263 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 264 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 265 */ 266 #define NFP_NET_CFG_BPF_ABI 0x0080 267 #define NFP_NET_BPF_ABI 2 268 #define NFP_NET_CFG_BPF_CAP 0x0081 269 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 270 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 271 #define NFP_NET_CFG_BPF_START 0x0084 272 #define NFP_NET_CFG_BPF_DONE 0x0086 273 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 274 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 275 #define NFP_NET_CFG_BPF_SIZE 0x008e 276 #define NFP_NET_CFG_BPF_ADDR 0x0090 277 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 278 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 279 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 280 281 /** 282 * 40B reserved for future use (0x0098 - 0x00c0) 283 */ 284 #define NFP_NET_CFG_RESERVED 0x0098 285 #define NFP_NET_CFG_RESERVED_SZ 0x0028 286 287 /** 288 * RSS configuration (0x0100 - 0x01ac): 289 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 290 * %NFP_NET_CFG_RSS_CFG: RSS configuration word 291 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key 292 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table 293 */ 294 #define NFP_NET_CFG_RSS_BASE 0x0100 295 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 296 #define NFP_NET_CFG_RSS_MASK (0x7f) 297 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 298 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 299 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 300 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 301 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 302 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 303 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 304 #define NFP_NET_CFG_RSS_HFUNC 0xff000000 305 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 306 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */ 307 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */ 308 #define NFP_NET_CFG_RSS_HFUNCS 3 309 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 310 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 311 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 312 NFP_NET_CFG_RSS_KEY_SZ) 313 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 314 315 /** 316 * TX ring configuration (0x200 - 0x800) 317 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 318 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 319 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 320 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 321 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 322 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 323 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 324 */ 325 #define NFP_NET_CFG_TXR_BASE 0x0200 326 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 327 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 328 ((_x) * 0x8)) 329 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 330 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 331 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 332 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 333 ((_x) * 0x4)) 334 335 /** 336 * RX ring configuration (0x0800 - 0x0c00) 337 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 338 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 339 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 340 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 341 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 342 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 343 */ 344 #define NFP_NET_CFG_RXR_BASE 0x0800 345 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 346 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 347 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 348 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 349 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 350 ((_x) * 0x4)) 351 352 /** 353 * Interrupt Control/Cause registers (0x0c00 - 0x0d00) 354 * These registers are only used when MSI-X auto-masking is not 355 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 356 * by MSI-X entry and are 1B in size. If an entry is zero, the 357 * corresponding entry is enabled. If the FW generates an interrupt, 358 * it writes a cause into the corresponding field. This also masks 359 * the MSI-X entry and the host driver must clear the register to 360 * re-enable the interrupt. 361 */ 362 #define NFP_NET_CFG_ICR_BASE 0x0c00 363 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 364 #define NFP_NET_CFG_ICR_UNMASKED 0x0 365 #define NFP_NET_CFG_ICR_RXTX 0x1 366 #define NFP_NET_CFG_ICR_LSC 0x2 367 368 /** 369 * General device stats (0x0d00 - 0x0d90) 370 * all counters are 64bit. 371 */ 372 #define NFP_NET_CFG_STATS_BASE 0x0d00 373 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 374 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 375 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 376 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 377 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 378 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 379 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 380 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 381 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 382 383 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 384 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 385 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 386 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 387 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 388 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 389 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 390 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 391 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 392 393 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 394 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 395 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 396 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 397 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 398 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 399 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 400 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 401 402 /** 403 * Per ring stats (0x1000 - 0x1800) 404 * options, 64bit per entry 405 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 406 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 407 */ 408 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 409 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 410 ((_x) * 0x10)) 411 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 412 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 413 ((_x) * 0x10)) 414 415 /** 416 * General use mailbox area (0x1800 - 0x19ff) 417 * 4B used for update command and 4B return code 418 * followed by a max of 504B of variable length value 419 */ 420 #define NFP_NET_CFG_MBOX_BASE 0x1800 421 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8 422 423 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0 424 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4 425 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8 426 #define NFP_NET_CFG_MBOX_SIMPLE_LEN 0x12 427 428 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1 429 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2 430 431 /** 432 * VLAN filtering using general use mailbox 433 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox 434 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter 435 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter 436 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes 437 */ 438 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL 439 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER 440 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2) 441 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004 442 443 /** 444 * TLV capabilities 445 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV 446 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV 447 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV 448 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments 449 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV 450 * 451 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE. 452 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs 453 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may 454 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs 455 * don't conflict with other features which allocate space beyond 456 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap 457 * space used by such features. 458 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH. 459 */ 460 #define NFP_NET_CFG_TLV_TYPE 0x00 461 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000 462 #define NFP_NET_CFG_TLV_LENGTH 0x02 463 #define NFP_NET_CFG_TLV_LENGTH_INC 4 464 #define NFP_NET_CFG_TLV_VALUE 0x04 465 466 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000 467 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000 468 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff 469 470 /** 471 * Capability TLV types 472 * 473 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN: 474 * Special TLV type to catch bugs, should never be encountered. Drivers should 475 * treat encountering this type as error and refuse to probe. 476 * 477 * %NFP_NET_CFG_TLV_TYPE_RESERVED: 478 * Reserved space, may contain legacy fixed-offset fields, or be used for 479 * padding. The use of this type should be otherwise avoided. 480 * 481 * %NFP_NET_CFG_TLV_TYPE_END: 482 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing 483 * further TLVs when encountered. 484 * 485 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ: 486 * Single word, ME frequency in MHz as used in calculation for 487 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD. 488 * 489 * %NFP_NET_CFG_TLV_TYPE_MBOX: 490 * Variable, mailbox area. Overwrites the default location which is 491 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ. 492 */ 493 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0 494 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1 495 #define NFP_NET_CFG_TLV_TYPE_END 2 496 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3 497 #define NFP_NET_CFG_TLV_TYPE_MBOX 4 498 499 struct device; 500 501 /** 502 * struct nfp_net_tlv_caps - parsed control BAR TLV capabilities 503 * @me_freq_mhz: ME clock_freq (MHz) 504 * @mbox_off: vNIC mailbox area offset 505 * @mbox_len: vNIC mailbox area length 506 */ 507 struct nfp_net_tlv_caps { 508 u32 me_freq_mhz; 509 unsigned int mbox_off; 510 unsigned int mbox_len; 511 }; 512 513 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem, 514 struct nfp_net_tlv_caps *caps); 515 516 static inline bool nfp_net_has_mbox(struct nfp_net_tlv_caps *caps) 517 { 518 return caps->mbox_len >= NFP_NET_CFG_MBOX_SIMPLE_LEN; 519 } 520 521 #endif /* _NFP_NET_CTRL_H_ */ 522