1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */ 3 4 /* nfp_net_ctrl.h 5 * Netronome network device driver: Control BAR layout 6 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 7 * Jason McMullan <jason.mcmullan@netronome.com> 8 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 9 * Brad Petrus <brad.petrus@netronome.com> 10 */ 11 12 #ifndef _NFP_NET_CTRL_H_ 13 #define _NFP_NET_CTRL_H_ 14 15 #include <linux/types.h> 16 17 /* Configuration BAR size. 18 * 19 * The configuration BAR is 8K in size, but due to 20 * THB-350, 32k needs to be reserved. 21 */ 22 #define NFP_NET_CFG_BAR_SZ (32 * 1024) 23 24 /* Offset in Freelist buffer where packet starts on RX */ 25 #define NFP_NET_RX_OFFSET 32 26 27 /* LSO parameters 28 * %NFP_NET_LSO_MAX_HDR_SZ: Maximum header size supported for LSO frames 29 * %NFP_NET_LSO_MAX_SEGS: Maximum number of segments LSO frame can produce 30 */ 31 #define NFP_NET_LSO_MAX_HDR_SZ 255 32 #define NFP_NET_LSO_MAX_SEGS 64 33 34 /* working with metadata vlan api (NFD version >= 2.0) */ 35 #define NFP_NET_META_VLAN_STRIP BIT(31) 36 #define NFP_NET_META_VLAN_TPID_MASK GENMASK(19, 16) 37 #define NFP_NET_META_VLAN_TCI_MASK GENMASK(15, 0) 38 39 /* Prepend field types */ 40 #define NFP_NET_META_FIELD_SIZE 4 41 #define NFP_NET_META_HASH 1 /* next field carries hash type */ 42 #define NFP_NET_META_MARK 2 43 #define NFP_NET_META_VLAN 4 /* ctag or stag type */ 44 #define NFP_NET_META_PORTID 5 45 #define NFP_NET_META_CSUM 6 /* checksum complete type */ 46 #define NFP_NET_META_CONN_HANDLE 7 47 #define NFP_NET_META_RESYNC_INFO 8 /* RX resync info request */ 48 49 #define NFP_META_PORT_ID_CTRL ~0U 50 51 /* Prepend field sizes */ 52 #define NFP_NET_META_VLAN_SIZE 4 53 #define NFP_NET_META_PORTID_SIZE 4 54 #define NFP_NET_META_CONN_HANDLE_SIZE 8 55 /* Hash type pre-pended when a RSS hash was computed */ 56 #define NFP_NET_RSS_NONE 0 57 #define NFP_NET_RSS_IPV4 1 58 #define NFP_NET_RSS_IPV6 2 59 #define NFP_NET_RSS_IPV6_EX 3 60 #define NFP_NET_RSS_IPV4_TCP 4 61 #define NFP_NET_RSS_IPV6_TCP 5 62 #define NFP_NET_RSS_IPV6_EX_TCP 6 63 #define NFP_NET_RSS_IPV4_UDP 7 64 #define NFP_NET_RSS_IPV6_UDP 8 65 #define NFP_NET_RSS_IPV6_EX_UDP 9 66 67 /* Ring counts 68 * %NFP_NET_TXR_MAX: Maximum number of TX rings 69 * %NFP_NET_RXR_MAX: Maximum number of RX rings 70 */ 71 #define NFP_NET_TXR_MAX 64 72 #define NFP_NET_RXR_MAX 64 73 74 /* Read/Write config words (0x0000 - 0x002c) 75 * %NFP_NET_CFG_CTRL: Global control 76 * %NFP_NET_CFG_UPDATE: Indicate which fields are updated 77 * %NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings 78 * %NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings 79 * %NFP_NET_CFG_MTU: Set MTU size 80 * %NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU) 81 * %NFP_NET_CFG_EXN: MSI-X table entry for exceptions 82 * %NFP_NET_CFG_LSC: MSI-X table entry for link state changes 83 * %NFP_NET_CFG_MACADDR: MAC address 84 * 85 * TODO: 86 * - define Error details in UPDATE 87 */ 88 #define NFP_NET_CFG_CTRL 0x0000 89 #define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */ 90 #define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */ 91 #define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */ 92 #define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */ 93 #define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */ 94 #define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */ 95 #define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */ 96 #define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */ 97 #define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */ 98 #define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */ 99 #define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO (version 1) */ 100 #define NFP_NET_CFG_CTRL_CTAG_FILTER (0x1 << 11) /* VLAN CTAG filtering */ 101 #define NFP_NET_CFG_CTRL_CMSG_DATA (0x1 << 12) /* RX cmsgs on data Qs */ 102 #define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable S-tag strip */ 103 #define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable C-tag strip */ 104 #define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */ 105 #define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS (version 1) */ 106 #define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */ 107 #define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */ 108 #define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring*/ 109 #define NFP_NET_CFG_CTRL_VEPA (0x1 << 22) /* Enable VEPA mode */ 110 #define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN C-tag insert*/ 111 #define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* VXLAN tunnel support */ 112 #define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* NVGRE tunnel support */ 113 #define NFP_NET_CFG_CTRL_BPF (0x1 << 27) /* BPF offload capable */ 114 #define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */ 115 #define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */ 116 #define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */ 117 #define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1 << 31) /* live MAC addr change */ 118 119 #define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | \ 120 NFP_NET_CFG_CTRL_LSO2) 121 #define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | \ 122 NFP_NET_CFG_CTRL_RSS2) 123 #define NFP_NET_CFG_CTRL_RXCSUM_ANY (NFP_NET_CFG_CTRL_RXCSUM | \ 124 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 125 #define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \ 126 NFP_NET_CFG_CTRL_CSUM_COMPLETE) 127 #define NFP_NET_CFG_CTRL_RXVLAN_ANY (NFP_NET_CFG_CTRL_RXVLAN | \ 128 NFP_NET_CFG_CTRL_RXVLAN_V2) 129 #define NFP_NET_CFG_CTRL_TXVLAN_ANY (NFP_NET_CFG_CTRL_TXVLAN | \ 130 NFP_NET_CFG_CTRL_TXVLAN_V2) 131 132 #define NFP_NET_CFG_UPDATE 0x0004 133 #define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */ 134 #define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */ 135 #define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */ 136 #define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */ 137 #define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */ 138 #define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */ 139 #define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */ 140 #define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */ 141 #define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */ 142 #define NFP_NET_CFG_UPDATE_BPF (0x1 << 10) /* BPF program load */ 143 #define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */ 144 #define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */ 145 #define NFP_NET_CFG_UPDATE_VF (0x1 << 13) /* VF settings change */ 146 #define NFP_NET_CFG_UPDATE_CRYPTO (0x1 << 14) /* Crypto on/off */ 147 #define NFP_NET_CFG_UPDATE_ERR (0x1 << 31) /* A error occurred */ 148 #define NFP_NET_CFG_TXRS_ENABLE 0x0008 149 #define NFP_NET_CFG_RXRS_ENABLE 0x0010 150 #define NFP_NET_CFG_MTU 0x0018 151 #define NFP_NET_CFG_FLBUFSZ 0x001c 152 #define NFP_NET_CFG_EXN 0x001f 153 #define NFP_NET_CFG_LSC 0x0020 154 #define NFP_NET_CFG_MACADDR 0x0024 155 156 /* Read-only words (0x0030 - 0x0050): 157 * %NFP_NET_CFG_VERSION: Firmware version number 158 * %NFP_NET_CFG_STS: Status 159 * %NFP_NET_CFG_CAP: Capabilities (same bits as %NFP_NET_CFG_CTRL) 160 * %NFP_NET_CFG_MAX_TXRINGS: Maximum number of TX rings 161 * %NFP_NET_CFG_MAX_RXRINGS: Maximum number of RX rings 162 * %NFP_NET_CFG_MAX_MTU: Maximum support MTU 163 * %NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only) 164 * %NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only) 165 * 166 * TODO: 167 * - define more STS bits 168 */ 169 #define NFP_NET_CFG_VERSION 0x0030 170 #define NFP_NET_CFG_VERSION_RESERVED_MASK (0xfe << 24) 171 #define NFP_NET_CFG_VERSION_DP_NFD3 0 172 #define NFP_NET_CFG_VERSION_DP_NFDK 1 173 #define NFP_NET_CFG_VERSION_DP_MASK 1 174 #define NFP_NET_CFG_VERSION_CLASS_MASK (0xff << 16) 175 #define NFP_NET_CFG_VERSION_CLASS(x) (((x) & 0xff) << 16) 176 #define NFP_NET_CFG_VERSION_CLASS_GENERIC 0 177 #define NFP_NET_CFG_VERSION_MAJOR_MASK (0xff << 8) 178 #define NFP_NET_CFG_VERSION_MAJOR(x) (((x) & 0xff) << 8) 179 #define NFP_NET_CFG_VERSION_MINOR_MASK (0xff << 0) 180 #define NFP_NET_CFG_VERSION_MINOR(x) (((x) & 0xff) << 0) 181 #define NFP_NET_CFG_STS 0x0034 182 #define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */ 183 /* Link rate */ 184 #define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1 185 #define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF 186 #define NFP_NET_CFG_STS_LINK_RATE \ 187 (NFP_NET_CFG_STS_LINK_RATE_MASK << NFP_NET_CFG_STS_LINK_RATE_SHIFT) 188 #define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0 189 #define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1 190 #define NFP_NET_CFG_STS_LINK_RATE_1G 2 191 #define NFP_NET_CFG_STS_LINK_RATE_10G 3 192 #define NFP_NET_CFG_STS_LINK_RATE_25G 4 193 #define NFP_NET_CFG_STS_LINK_RATE_40G 5 194 #define NFP_NET_CFG_STS_LINK_RATE_50G 6 195 #define NFP_NET_CFG_STS_LINK_RATE_100G 7 196 #define NFP_NET_CFG_CAP 0x0038 197 #define NFP_NET_CFG_MAX_TXRINGS 0x003c 198 #define NFP_NET_CFG_MAX_RXRINGS 0x0040 199 #define NFP_NET_CFG_MAX_MTU 0x0044 200 /* Next two words are being used by VFs for solving THB350 issue */ 201 #define NFP_NET_CFG_START_TXQ 0x0048 202 #define NFP_NET_CFG_START_RXQ 0x004c 203 204 /* Prepend configuration 205 */ 206 #define NFP_NET_CFG_RX_OFFSET 0x0050 207 #define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */ 208 209 /* RSS capabilities 210 * %NFP_NET_CFG_RSS_CAP_HFUNC: supported hash functions (same bits as 211 * %NFP_NET_CFG_RSS_HFUNC) 212 */ 213 #define NFP_NET_CFG_RSS_CAP 0x0054 214 #define NFP_NET_CFG_RSS_CAP_HFUNC 0xff000000 215 216 /* TLV area start 217 * %NFP_NET_CFG_TLV_BASE: start anchor of the TLV area 218 */ 219 #define NFP_NET_CFG_TLV_BASE 0x0058 220 221 /* VXLAN/UDP encap configuration 222 * %NFP_NET_CFG_VXLAN_PORT: Base address of table of tunnels' UDP dst ports 223 * %NFP_NET_CFG_VXLAN_SZ: Size of the UDP port table in bytes 224 */ 225 #define NFP_NET_CFG_VXLAN_PORT 0x0060 226 #define NFP_NET_CFG_VXLAN_SZ 0x0008 227 228 /* BPF section 229 * %NFP_NET_CFG_BPF_ABI: BPF ABI version 230 * %NFP_NET_CFG_BPF_CAP: BPF capabilities 231 * %NFP_NET_CFG_BPF_MAX_LEN: Maximum size of JITed BPF code in bytes 232 * %NFP_NET_CFG_BPF_START: Offset at which BPF will be loaded 233 * %NFP_NET_CFG_BPF_DONE: Offset to jump to on exit 234 * %NFP_NET_CFG_BPF_STACK_SZ: Total size of stack area in 64B chunks 235 * %NFP_NET_CFG_BPF_INL_MTU: Packet data split offset in 64B chunks 236 * %NFP_NET_CFG_BPF_SIZE: Size of the JITed BPF code in instructions 237 * %NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code 238 */ 239 #define NFP_NET_CFG_BPF_ABI 0x0080 240 #define NFP_NET_CFG_BPF_CAP 0x0081 241 #define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */ 242 #define NFP_NET_CFG_BPF_MAX_LEN 0x0082 243 #define NFP_NET_CFG_BPF_START 0x0084 244 #define NFP_NET_CFG_BPF_DONE 0x0086 245 #define NFP_NET_CFG_BPF_STACK_SZ 0x0088 246 #define NFP_NET_CFG_BPF_INL_MTU 0x0089 247 #define NFP_NET_CFG_BPF_SIZE 0x008e 248 #define NFP_NET_CFG_BPF_ADDR 0x0090 249 #define NFP_NET_CFG_BPF_CFG_8CTX (1 << 0) /* 8ctx mode */ 250 #define NFP_NET_CFG_BPF_CFG_MASK 7ULL 251 #define NFP_NET_CFG_BPF_ADDR_MASK (~NFP_NET_CFG_BPF_CFG_MASK) 252 253 /* 40B reserved for future use (0x0098 - 0x00c0) 254 */ 255 #define NFP_NET_CFG_RESERVED 0x0098 256 #define NFP_NET_CFG_RESERVED_SZ 0x0028 257 258 /* RSS configuration (0x0100 - 0x01ac): 259 * Used only when NFP_NET_CFG_CTRL_RSS is enabled 260 * %NFP_NET_CFG_RSS_CFG: RSS configuration word 261 * %NFP_NET_CFG_RSS_KEY: RSS "secret" key 262 * %NFP_NET_CFG_RSS_ITBL: RSS indirection table 263 */ 264 #define NFP_NET_CFG_RSS_BASE 0x0100 265 #define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE 266 #define NFP_NET_CFG_RSS_MASK (0x7f) 267 #define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f) 268 #define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */ 269 #define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */ 270 #define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */ 271 #define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */ 272 #define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */ 273 #define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */ 274 #define NFP_NET_CFG_RSS_HFUNC 0xff000000 275 #define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */ 276 #define NFP_NET_CFG_RSS_XOR (1 << 25) /* Use XOR as hash */ 277 #define NFP_NET_CFG_RSS_CRC32 (1 << 26) /* Use CRC32 as hash */ 278 #define NFP_NET_CFG_RSS_HFUNCS 3 279 #define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4) 280 #define NFP_NET_CFG_RSS_KEY_SZ 0x28 281 #define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \ 282 NFP_NET_CFG_RSS_KEY_SZ) 283 #define NFP_NET_CFG_RSS_ITBL_SZ 0x80 284 285 /* TX ring configuration (0x200 - 0x800) 286 * %NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration 287 * %NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries) 288 * %NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries) 289 * %NFP_NET_CFG_TXR_SZ: Per TX ring ring size (1B entries) 290 * %NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries) 291 * %NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries) 292 * %NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation packet 293 */ 294 #define NFP_NET_CFG_TXR_BASE 0x0200 295 #define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8)) 296 #define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \ 297 ((_x) * 0x8)) 298 #define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x)) 299 #define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x)) 300 #define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x)) 301 #define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \ 302 ((_x) * 0x4)) 303 304 /* RX ring configuration (0x0800 - 0x0c00) 305 * %NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration 306 * %NFP_NET_CFG_RXR_ADDR: Per RX ring DMA address (8B entries) 307 * %NFP_NET_CFG_RXR_SZ: Per RX ring ring size (1B entries) 308 * %NFP_NET_CFG_RXR_VEC: Per RX ring MSI-X table entry (1B entries) 309 * %NFP_NET_CFG_RXR_PRIO: Per RX ring priority (1B entries) 310 * %NFP_NET_CFG_RXR_IRQ_MOD: Per RX ring interrupt moderation (4B entries) 311 */ 312 #define NFP_NET_CFG_RXR_BASE 0x0800 313 #define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8)) 314 #define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x)) 315 #define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x)) 316 #define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x)) 317 #define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \ 318 ((_x) * 0x4)) 319 320 /* Interrupt Control/Cause registers (0x0c00 - 0x0d00) 321 * These registers are only used when MSI-X auto-masking is not 322 * enabled (%NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index 323 * by MSI-X entry and are 1B in size. If an entry is zero, the 324 * corresponding entry is enabled. If the FW generates an interrupt, 325 * it writes a cause into the corresponding field. This also masks 326 * the MSI-X entry and the host driver must clear the register to 327 * re-enable the interrupt. 328 */ 329 #define NFP_NET_CFG_ICR_BASE 0x0c00 330 #define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x)) 331 #define NFP_NET_CFG_ICR_UNMASKED 0x0 332 #define NFP_NET_CFG_ICR_RXTX 0x1 333 #define NFP_NET_CFG_ICR_LSC 0x2 334 335 /* General device stats (0x0d00 - 0x0d90) 336 * all counters are 64bit. 337 */ 338 #define NFP_NET_CFG_STATS_BASE 0x0d00 339 #define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00) 340 #define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08) 341 #define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10) 342 #define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18) 343 #define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20) 344 #define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28) 345 #define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30) 346 #define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38) 347 #define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40) 348 349 #define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48) 350 #define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50) 351 #define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58) 352 #define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60) 353 #define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68) 354 #define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70) 355 #define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78) 356 #define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80) 357 #define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88) 358 359 #define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90) 360 #define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98) 361 #define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0) 362 #define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8) 363 #define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0) 364 #define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8) 365 #define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0) 366 #define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8) 367 368 /* Per ring stats (0x1000 - 0x1800) 369 * options, 64bit per entry 370 * %NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count) 371 * %NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count) 372 */ 373 #define NFP_NET_CFG_TXR_STATS_BASE 0x1000 374 #define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \ 375 ((_x) * 0x10)) 376 #define NFP_NET_CFG_RXR_STATS_BASE 0x1400 377 #define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \ 378 ((_x) * 0x10)) 379 380 /* General use mailbox area (0x1800 - 0x19ff) 381 * 4B used for update command and 4B return code 382 * followed by a max of 504B of variable length value 383 */ 384 #define NFP_NET_CFG_MBOX_BASE 0x1800 385 #define NFP_NET_CFG_MBOX_VAL_MAX_SZ 0x1F8 386 387 #define NFP_NET_CFG_MBOX_SIMPLE_CMD 0x0 388 #define NFP_NET_CFG_MBOX_SIMPLE_RET 0x4 389 #define NFP_NET_CFG_MBOX_SIMPLE_VAL 0x8 390 391 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_ADD 1 392 #define NFP_NET_CFG_MBOX_CMD_CTAG_FILTER_KILL 2 393 394 #define NFP_NET_CFG_MBOX_CMD_PCI_DSCP_PRIOMAP_SET 5 395 #define NFP_NET_CFG_MBOX_CMD_TLV_CMSG 6 396 397 /* VLAN filtering using general use mailbox 398 * %NFP_NET_CFG_VLAN_FILTER: Base address of VLAN filter mailbox 399 * %NFP_NET_CFG_VLAN_FILTER_VID: VLAN ID to filter 400 * %NFP_NET_CFG_VLAN_FILTER_PROTO: VLAN proto to filter 401 * %NFP_NET_CFG_VXLAN_SZ: Size of the VLAN filter mailbox in bytes 402 */ 403 #define NFP_NET_CFG_VLAN_FILTER NFP_NET_CFG_MBOX_SIMPLE_VAL 404 #define NFP_NET_CFG_VLAN_FILTER_VID NFP_NET_CFG_VLAN_FILTER 405 #define NFP_NET_CFG_VLAN_FILTER_PROTO (NFP_NET_CFG_VLAN_FILTER + 2) 406 #define NFP_NET_CFG_VLAN_FILTER_SZ 0x0004 407 408 /* TLV capabilities 409 * %NFP_NET_CFG_TLV_TYPE: Offset of type within the TLV 410 * %NFP_NET_CFG_TLV_TYPE_REQUIRED: Driver must be able to parse the TLV 411 * %NFP_NET_CFG_TLV_LENGTH: Offset of length within the TLV 412 * %NFP_NET_CFG_TLV_LENGTH_INC: TLV length increments 413 * %NFP_NET_CFG_TLV_VALUE: Offset of value with the TLV 414 * 415 * List of simple TLV structures, first one starts at %NFP_NET_CFG_TLV_BASE. 416 * Last structure must be of type %NFP_NET_CFG_TLV_TYPE_END. Presence of TLVs 417 * is indicated by %NFP_NET_CFG_TLV_BASE being non-zero. TLV structures may 418 * fill the entire remainder of the BAR or be shorter. FW must make sure TLVs 419 * don't conflict with other features which allocate space beyond 420 * %NFP_NET_CFG_TLV_BASE. %NFP_NET_CFG_TLV_TYPE_RESERVED should be used to wrap 421 * space used by such features. 422 * Note that the 4 byte TLV header is not counted in %NFP_NET_CFG_TLV_LENGTH. 423 */ 424 #define NFP_NET_CFG_TLV_TYPE 0x00 425 #define NFP_NET_CFG_TLV_TYPE_REQUIRED 0x8000 426 #define NFP_NET_CFG_TLV_LENGTH 0x02 427 #define NFP_NET_CFG_TLV_LENGTH_INC 4 428 #define NFP_NET_CFG_TLV_VALUE 0x04 429 430 #define NFP_NET_CFG_TLV_HEADER_REQUIRED 0x80000000 431 #define NFP_NET_CFG_TLV_HEADER_TYPE 0x7fff0000 432 #define NFP_NET_CFG_TLV_HEADER_LENGTH 0x0000ffff 433 434 /* Capability TLV types 435 * 436 * %NFP_NET_CFG_TLV_TYPE_UNKNOWN: 437 * Special TLV type to catch bugs, should never be encountered. Drivers should 438 * treat encountering this type as error and refuse to probe. 439 * 440 * %NFP_NET_CFG_TLV_TYPE_RESERVED: 441 * Reserved space, may contain legacy fixed-offset fields, or be used for 442 * padding. The use of this type should be otherwise avoided. 443 * 444 * %NFP_NET_CFG_TLV_TYPE_END: 445 * Empty, end of TLV list. Must be the last TLV. Drivers will stop processing 446 * further TLVs when encountered. 447 * 448 * %NFP_NET_CFG_TLV_TYPE_ME_FREQ: 449 * Single word, ME frequency in MHz as used in calculation for 450 * %NFP_NET_CFG_RXR_IRQ_MOD and %NFP_NET_CFG_TXR_IRQ_MOD. 451 * 452 * %NFP_NET_CFG_TLV_TYPE_MBOX: 453 * Variable, mailbox area. Overwrites the default location which is 454 * %NFP_NET_CFG_MBOX_BASE and length %NFP_NET_CFG_MBOX_VAL_MAX_SZ. 455 * 456 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0: 457 * %NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1: 458 * Variable, experimental IDs. IDs designated for internal development and 459 * experiments before a stable TLV ID has been allocated to a feature. Should 460 * never be present in production firmware. 461 * 462 * %NFP_NET_CFG_TLV_TYPE_REPR_CAP: 463 * Single word, equivalent of %NFP_NET_CFG_CAP for representors, features which 464 * can be used on representors. 465 * 466 * %NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES: 467 * Variable, bitmap of control message types supported by the mailbox handler. 468 * Bit 0 corresponds to message type 0, bit 1 to 1, etc. Control messages are 469 * encapsulated into simple TLVs, with an end TLV and written to the Mailbox. 470 * 471 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS: 472 * 8 words, bitmaps of supported and enabled crypto operations. 473 * First 16B (4 words) contains a bitmap of supported crypto operations, 474 * and next 16B contain the enabled operations. 475 * This capability is made obsolete by ones with better sync methods. 476 * 477 * %NFP_NET_CFG_TLV_TYPE_VNIC_STATS: 478 * Variable, per-vNIC statistics, data should be 8B aligned (FW should insert 479 * zero-length RESERVED TLV to pad). 480 * TLV data has two sections. First is an array of statistics' IDs (2B each). 481 * Second 8B statistics themselves. Statistics are 8B aligned, meaning there 482 * may be a padding between sections. 483 * Number of statistics can be determined as floor(tlv.length / (2 + 8)). 484 * This TLV overwrites %NFP_NET_CFG_STATS_* values (statistics in this TLV 485 * duplicate the old ones, so driver should be careful not to unnecessarily 486 * render both). 487 * 488 * %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN: 489 * Same as %NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS, but crypto TLS does stream scan 490 * RX sync, rather than kernel-assisted sync. 491 */ 492 #define NFP_NET_CFG_TLV_TYPE_UNKNOWN 0 493 #define NFP_NET_CFG_TLV_TYPE_RESERVED 1 494 #define NFP_NET_CFG_TLV_TYPE_END 2 495 #define NFP_NET_CFG_TLV_TYPE_ME_FREQ 3 496 #define NFP_NET_CFG_TLV_TYPE_MBOX 4 497 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL0 5 498 #define NFP_NET_CFG_TLV_TYPE_EXPERIMENTAL1 6 499 #define NFP_NET_CFG_TLV_TYPE_REPR_CAP 7 500 #define NFP_NET_CFG_TLV_TYPE_MBOX_CMSG_TYPES 10 501 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS 11 /* see crypto/fw.h */ 502 #define NFP_NET_CFG_TLV_TYPE_VNIC_STATS 12 503 #define NFP_NET_CFG_TLV_TYPE_CRYPTO_OPS_RX_SCAN 13 504 505 struct device; 506 507 /* struct nfp_net_tlv_caps - parsed control BAR TLV capabilities 508 * @me_freq_mhz: ME clock_freq (MHz) 509 * @mbox_off: vNIC mailbox area offset 510 * @mbox_len: vNIC mailbox area length 511 * @repr_cap: capabilities for representors 512 * @mbox_cmsg_types: cmsgs which can be passed through the mailbox 513 * @crypto_ops: supported crypto operations 514 * @crypto_enable_off: offset of crypto ops enable region 515 * @vnic_stats_off: offset of vNIC stats area 516 * @vnic_stats_cnt: number of vNIC stats 517 * @tls_resync_ss: TLS resync will be performed via stream scan 518 */ 519 struct nfp_net_tlv_caps { 520 u32 me_freq_mhz; 521 unsigned int mbox_off; 522 unsigned int mbox_len; 523 u32 repr_cap; 524 u32 mbox_cmsg_types; 525 u32 crypto_ops; 526 unsigned int crypto_enable_off; 527 unsigned int vnic_stats_off; 528 unsigned int vnic_stats_cnt; 529 unsigned int tls_resync_ss:1; 530 }; 531 532 int nfp_net_tlv_caps_parse(struct device *dev, u8 __iomem *ctrl_mem, 533 struct nfp_net_tlv_caps *caps); 534 #endif /* _NFP_NET_CTRL_H_ */ 535