1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* Copyright (C) 2015-2018 Netronome Systems, Inc. */ 3 4 /* 5 * nfp_net.h 6 * Declarations for Netronome network device driver. 7 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 8 * Jason McMullan <jason.mcmullan@netronome.com> 9 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 10 */ 11 12 #ifndef _NFP_NET_H_ 13 #define _NFP_NET_H_ 14 15 #include <linux/interrupt.h> 16 #include <linux/list.h> 17 #include <linux/netdevice.h> 18 #include <linux/pci.h> 19 #include <linux/io-64-nonatomic-hi-lo.h> 20 #include <net/xdp.h> 21 22 #include "nfp_net_ctrl.h" 23 24 #define nn_pr(nn, lvl, fmt, args...) \ 25 ({ \ 26 struct nfp_net *__nn = (nn); \ 27 \ 28 if (__nn->dp.netdev) \ 29 netdev_printk(lvl, __nn->dp.netdev, fmt, ## args); \ 30 else \ 31 dev_printk(lvl, __nn->dp.dev, "ctrl: " fmt, ## args); \ 32 }) 33 34 #define nn_err(nn, fmt, args...) nn_pr(nn, KERN_ERR, fmt, ## args) 35 #define nn_warn(nn, fmt, args...) nn_pr(nn, KERN_WARNING, fmt, ## args) 36 #define nn_info(nn, fmt, args...) nn_pr(nn, KERN_INFO, fmt, ## args) 37 #define nn_dbg(nn, fmt, args...) nn_pr(nn, KERN_DEBUG, fmt, ## args) 38 39 #define nn_dp_warn(dp, fmt, args...) \ 40 ({ \ 41 struct nfp_net_dp *__dp = (dp); \ 42 \ 43 if (unlikely(net_ratelimit())) { \ 44 if (__dp->netdev) \ 45 netdev_warn(__dp->netdev, fmt, ## args); \ 46 else \ 47 dev_warn(__dp->dev, fmt, ## args); \ 48 } \ 49 }) 50 51 /* Max time to wait for NFP to respond on updates (in seconds) */ 52 #define NFP_NET_POLL_TIMEOUT 5 53 54 /* Interval for reading offloaded filter stats */ 55 #define NFP_NET_STAT_POLL_IVL msecs_to_jiffies(100) 56 57 /* Bar allocation */ 58 #define NFP_NET_CTRL_BAR 0 59 #define NFP_NET_Q0_BAR 2 60 #define NFP_NET_Q1_BAR 4 /* OBSOLETE */ 61 62 /* Max bits in DMA address */ 63 #define NFP_NET_MAX_DMA_BITS 40 64 65 /* Default size for MTU and freelist buffer sizes */ 66 #define NFP_NET_DEFAULT_MTU 1500 67 68 /* Maximum number of bytes prepended to a packet */ 69 #define NFP_NET_MAX_PREPEND 64 70 71 /* Interrupt definitions */ 72 #define NFP_NET_NON_Q_VECTORS 2 73 #define NFP_NET_IRQ_LSC_IDX 0 74 #define NFP_NET_IRQ_EXN_IDX 1 75 #define NFP_NET_MIN_VNIC_IRQS (NFP_NET_NON_Q_VECTORS + 1) 76 77 /* Queue/Ring definitions */ 78 #define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */ 79 #define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */ 80 #define NFP_NET_MAX_R_VECS (NFP_NET_MAX_TX_RINGS > NFP_NET_MAX_RX_RINGS ? \ 81 NFP_NET_MAX_TX_RINGS : NFP_NET_MAX_RX_RINGS) 82 #define NFP_NET_MAX_IRQS (NFP_NET_NON_Q_VECTORS + NFP_NET_MAX_R_VECS) 83 84 #define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */ 85 #define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */ 86 #define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */ 87 #define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */ 88 89 #define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */ 90 #define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */ 91 92 #define NFP_NET_FL_BATCH 16 /* Add freelist in this Batch size */ 93 #define NFP_NET_XDP_MAX_COMPLETE 2048 /* XDP bufs to reclaim in NAPI poll */ 94 95 /* Offload definitions */ 96 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(__be16)) 97 98 #define NFP_NET_RX_BUF_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 99 #define NFP_NET_RX_BUF_NON_DATA (NFP_NET_RX_BUF_HEADROOM + \ 100 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 101 102 /* Forward declarations */ 103 struct nfp_cpp; 104 struct nfp_eth_table_port; 105 struct nfp_net; 106 struct nfp_net_r_vector; 107 struct nfp_port; 108 109 /* Convenience macro for wrapping descriptor index on ring size */ 110 #define D_IDX(ring, idx) ((idx) & ((ring)->cnt - 1)) 111 112 /* Convenience macro for writing dma address into RX/TX descriptors */ 113 #define nfp_desc_set_dma_addr(desc, dma_addr) \ 114 do { \ 115 __typeof(desc) __d = (desc); \ 116 dma_addr_t __addr = (dma_addr); \ 117 \ 118 __d->dma_addr_lo = cpu_to_le32(lower_32_bits(__addr)); \ 119 __d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \ 120 } while (0) 121 122 /* TX descriptor format */ 123 124 #define PCIE_DESC_TX_EOP BIT(7) 125 #define PCIE_DESC_TX_OFFSET_MASK GENMASK(6, 0) 126 #define PCIE_DESC_TX_MSS_MASK GENMASK(13, 0) 127 128 /* Flags in the host TX descriptor */ 129 #define PCIE_DESC_TX_CSUM BIT(7) 130 #define PCIE_DESC_TX_IP4_CSUM BIT(6) 131 #define PCIE_DESC_TX_TCP_CSUM BIT(5) 132 #define PCIE_DESC_TX_UDP_CSUM BIT(4) 133 #define PCIE_DESC_TX_VLAN BIT(3) 134 #define PCIE_DESC_TX_LSO BIT(2) 135 #define PCIE_DESC_TX_ENCAP BIT(1) 136 #define PCIE_DESC_TX_O_IP4_CSUM BIT(0) 137 138 struct nfp_net_tx_desc { 139 union { 140 struct { 141 u8 dma_addr_hi; /* High bits of host buf address */ 142 __le16 dma_len; /* Length to DMA for this desc */ 143 u8 offset_eop; /* Offset in buf where pkt starts + 144 * highest bit is eop flag. 145 */ 146 __le32 dma_addr_lo; /* Low 32bit of host buf addr */ 147 148 __le16 mss; /* MSS to be used for LSO */ 149 u8 lso_hdrlen; /* LSO, TCP payload offset */ 150 u8 flags; /* TX Flags, see @PCIE_DESC_TX_* */ 151 union { 152 struct { 153 u8 l3_offset; /* L3 header offset */ 154 u8 l4_offset; /* L4 header offset */ 155 }; 156 __le16 vlan; /* VLAN tag to add if indicated */ 157 }; 158 __le16 data_len; /* Length of frame + meta data */ 159 } __packed; 160 __le32 vals[4]; 161 __le64 vals8[2]; 162 }; 163 }; 164 165 /** 166 * struct nfp_net_tx_buf - software TX buffer descriptor 167 * @skb: normal ring, sk_buff associated with this buffer 168 * @frag: XDP ring, page frag associated with this buffer 169 * @dma_addr: DMA mapping address of the buffer 170 * @fidx: Fragment index (-1 for the head and [0..nr_frags-1] for frags) 171 * @pkt_cnt: Number of packets to be produced out of the skb associated 172 * with this buffer (valid only on the head's buffer). 173 * Will be 1 for all non-TSO packets. 174 * @real_len: Number of bytes which to be produced out of the skb (valid only 175 * on the head's buffer). Equal to skb->len for non-TSO packets. 176 */ 177 struct nfp_net_tx_buf { 178 union { 179 struct sk_buff *skb; 180 void *frag; 181 }; 182 dma_addr_t dma_addr; 183 short int fidx; 184 u16 pkt_cnt; 185 u32 real_len; 186 }; 187 188 /** 189 * struct nfp_net_tx_ring - TX ring structure 190 * @r_vec: Back pointer to ring vector structure 191 * @idx: Ring index from Linux's perspective 192 * @qcidx: Queue Controller Peripheral (QCP) queue index for the TX queue 193 * @qcp_q: Pointer to base of the QCP TX queue 194 * @cnt: Size of the queue in number of descriptors 195 * @wr_p: TX ring write pointer (free running) 196 * @rd_p: TX ring read pointer (free running) 197 * @qcp_rd_p: Local copy of QCP TX queue read pointer 198 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer 199 * (used for .xmit_more delayed kick) 200 * @txbufs: Array of transmitted TX buffers, to free on transmit 201 * @txds: Virtual address of TX ring in host memory 202 * @dma: DMA address of the TX ring 203 * @size: Size, in bytes, of the TX ring (needed to free) 204 * @is_xdp: Is this a XDP TX ring? 205 */ 206 struct nfp_net_tx_ring { 207 struct nfp_net_r_vector *r_vec; 208 209 u32 idx; 210 int qcidx; 211 u8 __iomem *qcp_q; 212 213 u32 cnt; 214 u32 wr_p; 215 u32 rd_p; 216 u32 qcp_rd_p; 217 218 u32 wr_ptr_add; 219 220 struct nfp_net_tx_buf *txbufs; 221 struct nfp_net_tx_desc *txds; 222 223 dma_addr_t dma; 224 size_t size; 225 bool is_xdp; 226 } ____cacheline_aligned; 227 228 /* RX and freelist descriptor format */ 229 230 #define PCIE_DESC_RX_DD BIT(7) 231 #define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0) 232 233 /* Flags in the RX descriptor */ 234 #define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15)) 235 #define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14)) 236 #define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13)) 237 #define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12)) 238 #define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11)) 239 #define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10)) 240 #define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9)) 241 #define PCIE_DESC_RX_BPF cpu_to_le16(BIT(8)) 242 #define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7)) 243 #define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6)) 244 #define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5)) 245 #define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4)) 246 #define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3)) 247 #define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2)) 248 #define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1)) 249 #define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0)) 250 251 #define PCIE_DESC_RX_CSUM_ALL (PCIE_DESC_RX_IP4_CSUM | \ 252 PCIE_DESC_RX_TCP_CSUM | \ 253 PCIE_DESC_RX_UDP_CSUM | \ 254 PCIE_DESC_RX_I_IP4_CSUM | \ 255 PCIE_DESC_RX_I_TCP_CSUM | \ 256 PCIE_DESC_RX_I_UDP_CSUM) 257 #define PCIE_DESC_RX_CSUM_OK_SHIFT 1 258 #define __PCIE_DESC_RX_CSUM_ALL le16_to_cpu(PCIE_DESC_RX_CSUM_ALL) 259 #define __PCIE_DESC_RX_CSUM_ALL_OK (__PCIE_DESC_RX_CSUM_ALL >> \ 260 PCIE_DESC_RX_CSUM_OK_SHIFT) 261 262 struct nfp_net_rx_desc { 263 union { 264 struct { 265 u8 dma_addr_hi; /* High bits of the buf address */ 266 __le16 reserved; /* Must be zero */ 267 u8 meta_len_dd; /* Must be zero */ 268 269 __le32 dma_addr_lo; /* Low bits of the buffer address */ 270 } __packed fld; 271 272 struct { 273 __le16 data_len; /* Length of the frame + meta data */ 274 u8 reserved; 275 u8 meta_len_dd; /* Length of meta data prepended + 276 * descriptor done flag. 277 */ 278 279 __le16 flags; /* RX flags. See @PCIE_DESC_RX_* */ 280 __le16 vlan; /* VLAN if stripped */ 281 } __packed rxd; 282 283 __le32 vals[2]; 284 }; 285 }; 286 287 #define NFP_NET_META_FIELD_MASK GENMASK(NFP_NET_META_FIELD_SIZE - 1, 0) 288 289 struct nfp_meta_parsed { 290 u8 hash_type; 291 u8 csum_type; 292 u32 hash; 293 u32 mark; 294 u32 portid; 295 __wsum csum; 296 }; 297 298 struct nfp_net_rx_hash { 299 __be32 hash_type; 300 __be32 hash; 301 }; 302 303 /** 304 * struct nfp_net_rx_buf - software RX buffer descriptor 305 * @frag: page fragment buffer 306 * @dma_addr: DMA mapping address of the buffer 307 */ 308 struct nfp_net_rx_buf { 309 void *frag; 310 dma_addr_t dma_addr; 311 }; 312 313 /** 314 * struct nfp_net_rx_ring - RX ring structure 315 * @r_vec: Back pointer to ring vector structure 316 * @cnt: Size of the queue in number of descriptors 317 * @wr_p: FL/RX ring write pointer (free running) 318 * @rd_p: FL/RX ring read pointer (free running) 319 * @idx: Ring index from Linux's perspective 320 * @fl_qcidx: Queue Controller Peripheral (QCP) queue index for the freelist 321 * @qcp_fl: Pointer to base of the QCP freelist queue 322 * @rxbufs: Array of transmitted FL/RX buffers 323 * @rxds: Virtual address of FL/RX ring in host memory 324 * @xdp_rxq: RX-ring info avail for XDP 325 * @dma: DMA address of the FL/RX ring 326 * @size: Size, in bytes, of the FL/RX ring (needed to free) 327 */ 328 struct nfp_net_rx_ring { 329 struct nfp_net_r_vector *r_vec; 330 331 u32 cnt; 332 u32 wr_p; 333 u32 rd_p; 334 335 u32 idx; 336 337 int fl_qcidx; 338 u8 __iomem *qcp_fl; 339 340 struct nfp_net_rx_buf *rxbufs; 341 struct nfp_net_rx_desc *rxds; 342 343 struct xdp_rxq_info xdp_rxq; 344 345 dma_addr_t dma; 346 size_t size; 347 } ____cacheline_aligned; 348 349 /** 350 * struct nfp_net_r_vector - Per ring interrupt vector configuration 351 * @nfp_net: Backpointer to nfp_net structure 352 * @napi: NAPI structure for this ring vec 353 * @tasklet: ctrl vNIC, tasklet for servicing the r_vec 354 * @queue: ctrl vNIC, send queue 355 * @lock: ctrl vNIC, r_vec lock protects @queue 356 * @tx_ring: Pointer to TX ring 357 * @rx_ring: Pointer to RX ring 358 * @xdp_ring: Pointer to an extra TX ring for XDP 359 * @irq_entry: MSI-X table entry (use for talking to the device) 360 * @rx_sync: Seqlock for atomic updates of RX stats 361 * @rx_pkts: Number of received packets 362 * @rx_bytes: Number of received bytes 363 * @rx_drops: Number of packets dropped on RX due to lack of resources 364 * @hw_csum_rx_ok: Counter of packets where the HW checksum was OK 365 * @hw_csum_rx_inner_ok: Counter of packets where the inner HW checksum was OK 366 * @hw_csum_rx_complete: Counter of packets with CHECKSUM_COMPLETE reported 367 * @hw_csum_rx_error: Counter of packets with bad checksums 368 * @tx_sync: Seqlock for atomic updates of TX stats 369 * @tx_pkts: Number of Transmitted packets 370 * @tx_bytes: Number of Transmitted bytes 371 * @hw_csum_tx: Counter of packets with TX checksum offload requested 372 * @hw_csum_tx_inner: Counter of inner TX checksum offload requests 373 * @tx_gather: Counter of packets with Gather DMA 374 * @tx_lso: Counter of LSO packets sent 375 * @tx_errors: How many TX errors were encountered 376 * @tx_busy: How often was TX busy (no space)? 377 * @rx_replace_buf_alloc_fail: Counter of RX buffer allocation failures 378 * @irq_vector: Interrupt vector number (use for talking to the OS) 379 * @handler: Interrupt handler for this ring vector 380 * @name: Name of the interrupt vector 381 * @affinity_mask: SMP affinity mask for this vector 382 * 383 * This structure ties RX and TX rings to interrupt vectors and a NAPI 384 * context. This currently only supports one RX and TX ring per 385 * interrupt vector but might be extended in the future to allow 386 * association of multiple rings per vector. 387 */ 388 struct nfp_net_r_vector { 389 struct nfp_net *nfp_net; 390 union { 391 struct napi_struct napi; 392 struct { 393 struct tasklet_struct tasklet; 394 struct sk_buff_head queue; 395 struct spinlock lock; 396 }; 397 }; 398 399 struct nfp_net_tx_ring *tx_ring; 400 struct nfp_net_rx_ring *rx_ring; 401 402 u16 irq_entry; 403 404 struct u64_stats_sync rx_sync; 405 u64 rx_pkts; 406 u64 rx_bytes; 407 u64 rx_drops; 408 u64 hw_csum_rx_ok; 409 u64 hw_csum_rx_inner_ok; 410 u64 hw_csum_rx_complete; 411 412 struct nfp_net_tx_ring *xdp_ring; 413 414 struct u64_stats_sync tx_sync; 415 u64 tx_pkts; 416 u64 tx_bytes; 417 u64 hw_csum_tx; 418 u64 hw_csum_tx_inner; 419 u64 tx_gather; 420 u64 tx_lso; 421 422 u64 hw_csum_rx_error; 423 u64 rx_replace_buf_alloc_fail; 424 u64 tx_errors; 425 u64 tx_busy; 426 427 u32 irq_vector; 428 irq_handler_t handler; 429 char name[IFNAMSIZ + 8]; 430 cpumask_t affinity_mask; 431 } ____cacheline_aligned; 432 433 /* Firmware version as it is written in the 32bit value in the BAR */ 434 struct nfp_net_fw_version { 435 u8 minor; 436 u8 major; 437 u8 class; 438 u8 resv; 439 } __packed; 440 441 static inline bool nfp_net_fw_ver_eq(struct nfp_net_fw_version *fw_ver, 442 u8 resv, u8 class, u8 major, u8 minor) 443 { 444 return fw_ver->resv == resv && 445 fw_ver->class == class && 446 fw_ver->major == major && 447 fw_ver->minor == minor; 448 } 449 450 struct nfp_stat_pair { 451 u64 pkts; 452 u64 bytes; 453 }; 454 455 /** 456 * struct nfp_net_dp - NFP network device datapath data structure 457 * @dev: Backpointer to struct device 458 * @netdev: Backpointer to net_device structure 459 * @is_vf: Is the driver attached to a VF? 460 * @chained_metadata_format: Firemware will use new metadata format 461 * @rx_dma_dir: Mapping direction for RX buffers 462 * @rx_dma_off: Offset at which DMA packets (for XDP headroom) 463 * @rx_offset: Offset in the RX buffers where packet data starts 464 * @ctrl: Local copy of the control register/word. 465 * @fl_bufsz: Currently configured size of the freelist buffers 466 * @xdp_prog: Installed XDP program 467 * @tx_rings: Array of pre-allocated TX ring structures 468 * @rx_rings: Array of pre-allocated RX ring structures 469 * @ctrl_bar: Pointer to mapped control BAR 470 * 471 * @txd_cnt: Size of the TX ring in number of descriptors 472 * @rxd_cnt: Size of the RX ring in number of descriptors 473 * @num_r_vecs: Number of used ring vectors 474 * @num_tx_rings: Currently configured number of TX rings 475 * @num_stack_tx_rings: Number of TX rings used by the stack (not XDP) 476 * @num_rx_rings: Currently configured number of RX rings 477 * @mtu: Device MTU 478 */ 479 struct nfp_net_dp { 480 struct device *dev; 481 struct net_device *netdev; 482 483 u8 is_vf:1; 484 u8 chained_metadata_format:1; 485 486 u8 rx_dma_dir; 487 u8 rx_offset; 488 489 u32 rx_dma_off; 490 491 u32 ctrl; 492 u32 fl_bufsz; 493 494 struct bpf_prog *xdp_prog; 495 496 struct nfp_net_tx_ring *tx_rings; 497 struct nfp_net_rx_ring *rx_rings; 498 499 u8 __iomem *ctrl_bar; 500 501 /* Cold data follows */ 502 503 unsigned int txd_cnt; 504 unsigned int rxd_cnt; 505 506 unsigned int num_r_vecs; 507 508 unsigned int num_tx_rings; 509 unsigned int num_stack_tx_rings; 510 unsigned int num_rx_rings; 511 512 unsigned int mtu; 513 }; 514 515 /** 516 * struct nfp_net - NFP network device structure 517 * @dp: Datapath structure 518 * @id: vNIC id within the PF (0 for VFs) 519 * @fw_ver: Firmware version 520 * @cap: Capabilities advertised by the Firmware 521 * @max_mtu: Maximum support MTU advertised by the Firmware 522 * @rss_hfunc: RSS selected hash function 523 * @rss_cfg: RSS configuration 524 * @rss_key: RSS secret key 525 * @rss_itbl: RSS indirection table 526 * @xdp: Information about the driver XDP program 527 * @xdp_hw: Information about the HW XDP program 528 * @max_r_vecs: Number of allocated interrupt vectors for RX/TX 529 * @max_tx_rings: Maximum number of TX rings supported by the Firmware 530 * @max_rx_rings: Maximum number of RX rings supported by the Firmware 531 * @stride_rx: Queue controller RX queue spacing 532 * @stride_tx: Queue controller TX queue spacing 533 * @r_vecs: Pre-allocated array of ring vectors 534 * @irq_entries: Pre-allocated array of MSI-X entries 535 * @lsc_handler: Handler for Link State Change interrupt 536 * @lsc_name: Name for Link State Change interrupt 537 * @exn_handler: Handler for Exception interrupt 538 * @exn_name: Name for Exception interrupt 539 * @shared_handler: Handler for shared interrupts 540 * @shared_name: Name for shared interrupt 541 * @me_freq_mhz: ME clock_freq (MHz) 542 * @reconfig_lock: Protects @reconfig_posted, @reconfig_timer_active, 543 * @reconfig_sync_present and HW reconfiguration request 544 * regs/machinery from async requests (sync must take 545 * @bar_lock) 546 * @reconfig_posted: Pending reconfig bits coming from async sources 547 * @reconfig_timer_active: Timer for reading reconfiguration results is pending 548 * @reconfig_sync_present: Some thread is performing synchronous reconfig 549 * @reconfig_timer: Timer for async reading of reconfig results 550 * @reconfig_in_progress_update: Update FW is processing now (debug only) 551 * @bar_lock: vNIC config BAR access lock, protects: update, 552 * mailbox area 553 * @link_up: Is the link up? 554 * @link_status_lock: Protects @link_* and ensures atomicity with BAR reading 555 * @rx_coalesce_usecs: RX interrupt moderation usecs delay parameter 556 * @rx_coalesce_max_frames: RX interrupt moderation frame count parameter 557 * @tx_coalesce_usecs: TX interrupt moderation usecs delay parameter 558 * @tx_coalesce_max_frames: TX interrupt moderation frame count parameter 559 * @vxlan_ports: VXLAN ports for RX inner csum offload communicated to HW 560 * @vxlan_usecnt: IPv4/IPv6 VXLAN port use counts 561 * @qcp_cfg: Pointer to QCP queue used for configuration notification 562 * @tx_bar: Pointer to mapped TX queues 563 * @rx_bar: Pointer to mapped FL/RX queues 564 * @tlv_caps: Parsed TLV capabilities 565 * @debugfs_dir: Device directory in debugfs 566 * @vnic_list: Entry on device vNIC list 567 * @pdev: Backpointer to PCI device 568 * @app: APP handle if available 569 * @vnic_no_name: For non-port PF vNIC make ndo_get_phys_port_name return 570 * -EOPNOTSUPP to keep backwards compatibility (set by app) 571 * @port: Pointer to nfp_port structure if vNIC is a port 572 * @app_priv: APP private data for this vNIC 573 */ 574 struct nfp_net { 575 struct nfp_net_dp dp; 576 577 struct nfp_net_fw_version fw_ver; 578 579 u32 id; 580 581 u32 cap; 582 u32 max_mtu; 583 584 u8 rss_hfunc; 585 u32 rss_cfg; 586 u8 rss_key[NFP_NET_CFG_RSS_KEY_SZ]; 587 u8 rss_itbl[NFP_NET_CFG_RSS_ITBL_SZ]; 588 589 struct xdp_attachment_info xdp; 590 struct xdp_attachment_info xdp_hw; 591 592 unsigned int max_tx_rings; 593 unsigned int max_rx_rings; 594 595 int stride_tx; 596 int stride_rx; 597 598 unsigned int max_r_vecs; 599 struct nfp_net_r_vector r_vecs[NFP_NET_MAX_R_VECS]; 600 struct msix_entry irq_entries[NFP_NET_MAX_IRQS]; 601 602 irq_handler_t lsc_handler; 603 char lsc_name[IFNAMSIZ + 8]; 604 605 irq_handler_t exn_handler; 606 char exn_name[IFNAMSIZ + 8]; 607 608 irq_handler_t shared_handler; 609 char shared_name[IFNAMSIZ + 8]; 610 611 u32 me_freq_mhz; 612 613 bool link_up; 614 spinlock_t link_status_lock; 615 616 spinlock_t reconfig_lock; 617 u32 reconfig_posted; 618 bool reconfig_timer_active; 619 bool reconfig_sync_present; 620 struct timer_list reconfig_timer; 621 u32 reconfig_in_progress_update; 622 623 struct mutex bar_lock; 624 625 u32 rx_coalesce_usecs; 626 u32 rx_coalesce_max_frames; 627 u32 tx_coalesce_usecs; 628 u32 tx_coalesce_max_frames; 629 630 __be16 vxlan_ports[NFP_NET_N_VXLAN_PORTS]; 631 u8 vxlan_usecnt[NFP_NET_N_VXLAN_PORTS]; 632 633 u8 __iomem *qcp_cfg; 634 635 u8 __iomem *tx_bar; 636 u8 __iomem *rx_bar; 637 638 struct nfp_net_tlv_caps tlv_caps; 639 640 struct dentry *debugfs_dir; 641 642 struct list_head vnic_list; 643 644 struct pci_dev *pdev; 645 struct nfp_app *app; 646 647 bool vnic_no_name; 648 649 struct nfp_port *port; 650 651 void *app_priv; 652 }; 653 654 /* Functions to read/write from/to a BAR 655 * Performs any endian conversion necessary. 656 */ 657 static inline u16 nn_readb(struct nfp_net *nn, int off) 658 { 659 return readb(nn->dp.ctrl_bar + off); 660 } 661 662 static inline void nn_writeb(struct nfp_net *nn, int off, u8 val) 663 { 664 writeb(val, nn->dp.ctrl_bar + off); 665 } 666 667 static inline u16 nn_readw(struct nfp_net *nn, int off) 668 { 669 return readw(nn->dp.ctrl_bar + off); 670 } 671 672 static inline void nn_writew(struct nfp_net *nn, int off, u16 val) 673 { 674 writew(val, nn->dp.ctrl_bar + off); 675 } 676 677 static inline u32 nn_readl(struct nfp_net *nn, int off) 678 { 679 return readl(nn->dp.ctrl_bar + off); 680 } 681 682 static inline void nn_writel(struct nfp_net *nn, int off, u32 val) 683 { 684 writel(val, nn->dp.ctrl_bar + off); 685 } 686 687 static inline u64 nn_readq(struct nfp_net *nn, int off) 688 { 689 return readq(nn->dp.ctrl_bar + off); 690 } 691 692 static inline void nn_writeq(struct nfp_net *nn, int off, u64 val) 693 { 694 writeq(val, nn->dp.ctrl_bar + off); 695 } 696 697 /* Flush posted PCI writes by reading something without side effects */ 698 static inline void nn_pci_flush(struct nfp_net *nn) 699 { 700 nn_readl(nn, NFP_NET_CFG_VERSION); 701 } 702 703 /* Queue Controller Peripheral access functions and definitions. 704 * 705 * Some of the BARs of the NFP are mapped to portions of the Queue 706 * Controller Peripheral (QCP) address space on the NFP. A QCP queue 707 * has a read and a write pointer (as well as a size and flags, 708 * indicating overflow etc). The QCP offers a number of different 709 * operation on queue pointers, but here we only offer function to 710 * either add to a pointer or to read the pointer value. 711 */ 712 #define NFP_QCP_QUEUE_ADDR_SZ 0x800 713 #define NFP_QCP_QUEUE_AREA_SZ 0x80000 714 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * NFP_QCP_QUEUE_ADDR_SZ) 715 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000 716 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004 717 #define NFP_QCP_QUEUE_STS_LO 0x0008 718 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask 0x3ffff 719 #define NFP_QCP_QUEUE_STS_HI 0x000c 720 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask 0x3ffff 721 722 /* The offset of a QCP queues in the PCIe Target */ 723 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff))) 724 725 /* nfp_qcp_ptr - Read or Write Pointer of a queue */ 726 enum nfp_qcp_ptr { 727 NFP_QCP_READ_PTR = 0, 728 NFP_QCP_WRITE_PTR 729 }; 730 731 /* There appear to be an *undocumented* upper limit on the value which 732 * one can add to a queue and that value is either 0x3f or 0x7f. We 733 * go with 0x3f as a conservative measure. 734 */ 735 #define NFP_QCP_MAX_ADD 0x3f 736 737 static inline void _nfp_qcp_ptr_add(u8 __iomem *q, 738 enum nfp_qcp_ptr ptr, u32 val) 739 { 740 u32 off; 741 742 if (ptr == NFP_QCP_READ_PTR) 743 off = NFP_QCP_QUEUE_ADD_RPTR; 744 else 745 off = NFP_QCP_QUEUE_ADD_WPTR; 746 747 while (val > NFP_QCP_MAX_ADD) { 748 writel(NFP_QCP_MAX_ADD, q + off); 749 val -= NFP_QCP_MAX_ADD; 750 } 751 752 writel(val, q + off); 753 } 754 755 /** 756 * nfp_qcp_rd_ptr_add() - Add the value to the read pointer of a queue 757 * 758 * @q: Base address for queue structure 759 * @val: Value to add to the queue pointer 760 * 761 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 762 */ 763 static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val) 764 { 765 _nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val); 766 } 767 768 /** 769 * nfp_qcp_wr_ptr_add() - Add the value to the write pointer of a queue 770 * 771 * @q: Base address for queue structure 772 * @val: Value to add to the queue pointer 773 * 774 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 775 */ 776 static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val) 777 { 778 _nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val); 779 } 780 781 static inline u32 _nfp_qcp_read(u8 __iomem *q, enum nfp_qcp_ptr ptr) 782 { 783 u32 off; 784 u32 val; 785 786 if (ptr == NFP_QCP_READ_PTR) 787 off = NFP_QCP_QUEUE_STS_LO; 788 else 789 off = NFP_QCP_QUEUE_STS_HI; 790 791 val = readl(q + off); 792 793 if (ptr == NFP_QCP_READ_PTR) 794 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask; 795 else 796 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask; 797 } 798 799 /** 800 * nfp_qcp_rd_ptr_read() - Read the current read pointer value for a queue 801 * @q: Base address for queue structure 802 * 803 * Return: Value read. 804 */ 805 static inline u32 nfp_qcp_rd_ptr_read(u8 __iomem *q) 806 { 807 return _nfp_qcp_read(q, NFP_QCP_READ_PTR); 808 } 809 810 /** 811 * nfp_qcp_wr_ptr_read() - Read the current write pointer value for a queue 812 * @q: Base address for queue structure 813 * 814 * Return: Value read. 815 */ 816 static inline u32 nfp_qcp_wr_ptr_read(u8 __iomem *q) 817 { 818 return _nfp_qcp_read(q, NFP_QCP_WRITE_PTR); 819 } 820 821 static inline bool nfp_net_is_data_vnic(struct nfp_net *nn) 822 { 823 WARN_ON_ONCE(!nn->dp.netdev && nn->port); 824 return !!nn->dp.netdev; 825 } 826 827 static inline bool nfp_net_running(struct nfp_net *nn) 828 { 829 return nn->dp.ctrl & NFP_NET_CFG_CTRL_ENABLE; 830 } 831 832 static inline const char *nfp_net_name(struct nfp_net *nn) 833 { 834 return nn->dp.netdev ? nn->dp.netdev->name : "ctrl"; 835 } 836 837 static inline void nfp_ctrl_lock(struct nfp_net *nn) 838 __acquires(&nn->r_vecs[0].lock) 839 { 840 spin_lock_bh(&nn->r_vecs[0].lock); 841 } 842 843 static inline void nfp_ctrl_unlock(struct nfp_net *nn) 844 __releases(&nn->r_vecs[0].lock) 845 { 846 spin_unlock_bh(&nn->r_vecs[0].lock); 847 } 848 849 static inline void nn_ctrl_bar_lock(struct nfp_net *nn) 850 { 851 mutex_lock(&nn->bar_lock); 852 } 853 854 static inline void nn_ctrl_bar_unlock(struct nfp_net *nn) 855 { 856 mutex_unlock(&nn->bar_lock); 857 } 858 859 /* Globals */ 860 extern const char nfp_driver_version[]; 861 862 extern const struct net_device_ops nfp_net_netdev_ops; 863 864 static inline bool nfp_netdev_is_nfp_net(struct net_device *netdev) 865 { 866 return netdev->netdev_ops == &nfp_net_netdev_ops; 867 } 868 869 /* Prototypes */ 870 void nfp_net_get_fw_version(struct nfp_net_fw_version *fw_ver, 871 void __iomem *ctrl_bar); 872 873 struct nfp_net * 874 nfp_net_alloc(struct pci_dev *pdev, void __iomem *ctrl_bar, bool needs_netdev, 875 unsigned int max_tx_rings, unsigned int max_rx_rings); 876 void nfp_net_free(struct nfp_net *nn); 877 878 int nfp_net_init(struct nfp_net *nn); 879 void nfp_net_clean(struct nfp_net *nn); 880 881 int nfp_ctrl_open(struct nfp_net *nn); 882 void nfp_ctrl_close(struct nfp_net *nn); 883 884 void nfp_net_set_ethtool_ops(struct net_device *netdev); 885 void nfp_net_info(struct nfp_net *nn); 886 int nfp_net_reconfig(struct nfp_net *nn, u32 update); 887 unsigned int nfp_net_rss_key_sz(struct nfp_net *nn); 888 void nfp_net_rss_write_itbl(struct nfp_net *nn); 889 void nfp_net_rss_write_key(struct nfp_net *nn); 890 void nfp_net_coalesce_write_cfg(struct nfp_net *nn); 891 int nfp_net_mbox_lock(struct nfp_net *nn, unsigned int data_size); 892 int nfp_net_mbox_reconfig(struct nfp_net *nn, u32 mbox_cmd); 893 int nfp_net_mbox_reconfig_and_unlock(struct nfp_net *nn, u32 mbox_cmd); 894 895 unsigned int 896 nfp_net_irqs_alloc(struct pci_dev *pdev, struct msix_entry *irq_entries, 897 unsigned int min_irqs, unsigned int want_irqs); 898 void nfp_net_irqs_disable(struct pci_dev *pdev); 899 void 900 nfp_net_irqs_assign(struct nfp_net *nn, struct msix_entry *irq_entries, 901 unsigned int n); 902 903 struct nfp_net_dp *nfp_net_clone_dp(struct nfp_net *nn); 904 int nfp_net_ring_reconfig(struct nfp_net *nn, struct nfp_net_dp *new, 905 struct netlink_ext_ack *extack); 906 907 #ifdef CONFIG_NFP_DEBUG 908 void nfp_net_debugfs_create(void); 909 void nfp_net_debugfs_destroy(void); 910 struct dentry *nfp_net_debugfs_device_add(struct pci_dev *pdev); 911 void nfp_net_debugfs_vnic_add(struct nfp_net *nn, struct dentry *ddir); 912 void nfp_net_debugfs_dir_clean(struct dentry **dir); 913 #else 914 static inline void nfp_net_debugfs_create(void) 915 { 916 } 917 918 static inline void nfp_net_debugfs_destroy(void) 919 { 920 } 921 922 static inline struct dentry *nfp_net_debugfs_device_add(struct pci_dev *pdev) 923 { 924 return NULL; 925 } 926 927 static inline void 928 nfp_net_debugfs_vnic_add(struct nfp_net *nn, struct dentry *ddir) 929 { 930 } 931 932 static inline void nfp_net_debugfs_dir_clean(struct dentry **dir) 933 { 934 } 935 #endif /* CONFIG_NFP_DEBUG */ 936 937 #endif /* _NFP_NET_H_ */ 938