1 /* 2 * Copyright (C) 2015 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 /* 35 * nfp_net.h 36 * Declarations for Netronome network device driver. 37 * Authors: Jakub Kicinski <jakub.kicinski@netronome.com> 38 * Jason McMullan <jason.mcmullan@netronome.com> 39 * Rolf Neugebauer <rolf.neugebauer@netronome.com> 40 */ 41 42 #ifndef _NFP_NET_H_ 43 #define _NFP_NET_H_ 44 45 #include <linux/interrupt.h> 46 #include <linux/netdevice.h> 47 #include <linux/pci.h> 48 #include <linux/io-64-nonatomic-hi-lo.h> 49 50 #include "nfp_net_ctrl.h" 51 52 #define nn_err(nn, fmt, args...) netdev_err((nn)->netdev, fmt, ## args) 53 #define nn_warn(nn, fmt, args...) netdev_warn((nn)->netdev, fmt, ## args) 54 #define nn_info(nn, fmt, args...) netdev_info((nn)->netdev, fmt, ## args) 55 #define nn_dbg(nn, fmt, args...) netdev_dbg((nn)->netdev, fmt, ## args) 56 #define nn_warn_ratelimit(nn, fmt, args...) \ 57 do { \ 58 if (unlikely(net_ratelimit())) \ 59 netdev_warn((nn)->netdev, fmt, ## args); \ 60 } while (0) 61 62 /* Max time to wait for NFP to respond on updates (in seconds) */ 63 #define NFP_NET_POLL_TIMEOUT 5 64 65 /* Interval for reading offloaded filter stats */ 66 #define NFP_NET_STAT_POLL_IVL msecs_to_jiffies(100) 67 68 /* Bar allocation */ 69 #define NFP_NET_CTRL_BAR 0 70 #define NFP_NET_Q0_BAR 2 71 #define NFP_NET_Q1_BAR 4 /* OBSOLETE */ 72 73 /* Max bits in DMA address */ 74 #define NFP_NET_MAX_DMA_BITS 40 75 76 /* Default size for MTU and freelist buffer sizes */ 77 #define NFP_NET_DEFAULT_MTU 1500 78 79 /* Maximum number of bytes prepended to a packet */ 80 #define NFP_NET_MAX_PREPEND 64 81 82 /* Interrupt definitions */ 83 #define NFP_NET_NON_Q_VECTORS 2 84 #define NFP_NET_IRQ_LSC_IDX 0 85 #define NFP_NET_IRQ_EXN_IDX 1 86 87 /* Queue/Ring definitions */ 88 #define NFP_NET_MAX_TX_RINGS 64 /* Max. # of Tx rings per device */ 89 #define NFP_NET_MAX_RX_RINGS 64 /* Max. # of Rx rings per device */ 90 #define NFP_NET_MAX_R_VECS (NFP_NET_MAX_TX_RINGS > NFP_NET_MAX_RX_RINGS ? \ 91 NFP_NET_MAX_TX_RINGS : NFP_NET_MAX_RX_RINGS) 92 #define NFP_NET_MAX_IRQS (NFP_NET_NON_Q_VECTORS + NFP_NET_MAX_R_VECS) 93 94 #define NFP_NET_MIN_TX_DESCS 256 /* Min. # of Tx descs per ring */ 95 #define NFP_NET_MIN_RX_DESCS 256 /* Min. # of Rx descs per ring */ 96 #define NFP_NET_MAX_TX_DESCS (256 * 1024) /* Max. # of Tx descs per ring */ 97 #define NFP_NET_MAX_RX_DESCS (256 * 1024) /* Max. # of Rx descs per ring */ 98 99 #define NFP_NET_TX_DESCS_DEFAULT 4096 /* Default # of Tx descs per ring */ 100 #define NFP_NET_RX_DESCS_DEFAULT 4096 /* Default # of Rx descs per ring */ 101 102 #define NFP_NET_FL_BATCH 16 /* Add freelist in this Batch size */ 103 104 /* Offload definitions */ 105 #define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(__be16)) 106 107 #define NFP_NET_RX_BUF_HEADROOM (NET_SKB_PAD + NET_IP_ALIGN) 108 #define NFP_NET_RX_BUF_NON_DATA (NFP_NET_RX_BUF_HEADROOM + \ 109 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))) 110 111 /* Forward declarations */ 112 struct nfp_net; 113 struct nfp_net_r_vector; 114 115 /* Convenience macro for writing dma address into RX/TX descriptors */ 116 #define nfp_desc_set_dma_addr(desc, dma_addr) \ 117 do { \ 118 __typeof(desc) __d = (desc); \ 119 dma_addr_t __addr = (dma_addr); \ 120 \ 121 __d->dma_addr_lo = cpu_to_le32(lower_32_bits(__addr)); \ 122 __d->dma_addr_hi = upper_32_bits(__addr) & 0xff; \ 123 } while (0) 124 125 /* TX descriptor format */ 126 127 #define PCIE_DESC_TX_EOP BIT(7) 128 #define PCIE_DESC_TX_OFFSET_MASK GENMASK(6, 0) 129 #define PCIE_DESC_TX_MSS_MASK GENMASK(13, 0) 130 131 /* Flags in the host TX descriptor */ 132 #define PCIE_DESC_TX_CSUM BIT(7) 133 #define PCIE_DESC_TX_IP4_CSUM BIT(6) 134 #define PCIE_DESC_TX_TCP_CSUM BIT(5) 135 #define PCIE_DESC_TX_UDP_CSUM BIT(4) 136 #define PCIE_DESC_TX_VLAN BIT(3) 137 #define PCIE_DESC_TX_LSO BIT(2) 138 #define PCIE_DESC_TX_ENCAP BIT(1) 139 #define PCIE_DESC_TX_O_IP4_CSUM BIT(0) 140 141 struct nfp_net_tx_desc { 142 union { 143 struct { 144 u8 dma_addr_hi; /* High bits of host buf address */ 145 __le16 dma_len; /* Length to DMA for this desc */ 146 u8 offset_eop; /* Offset in buf where pkt starts + 147 * highest bit is eop flag. 148 */ 149 __le32 dma_addr_lo; /* Low 32bit of host buf addr */ 150 151 __le16 mss; /* MSS to be used for LSO */ 152 u8 l4_offset; /* LSO, where the L4 data starts */ 153 u8 flags; /* TX Flags, see @PCIE_DESC_TX_* */ 154 155 __le16 vlan; /* VLAN tag to add if indicated */ 156 __le16 data_len; /* Length of frame + meta data */ 157 } __packed; 158 __le32 vals[4]; 159 }; 160 }; 161 162 /** 163 * struct nfp_net_tx_buf - software TX buffer descriptor 164 * @skb: sk_buff associated with this buffer 165 * @dma_addr: DMA mapping address of the buffer 166 * @fidx: Fragment index (-1 for the head and [0..nr_frags-1] for frags) 167 * @pkt_cnt: Number of packets to be produced out of the skb associated 168 * with this buffer (valid only on the head's buffer). 169 * Will be 1 for all non-TSO packets. 170 * @real_len: Number of bytes which to be produced out of the skb (valid only 171 * on the head's buffer). Equal to skb->len for non-TSO packets. 172 */ 173 struct nfp_net_tx_buf { 174 union { 175 struct sk_buff *skb; 176 void *frag; 177 }; 178 dma_addr_t dma_addr; 179 short int fidx; 180 u16 pkt_cnt; 181 u32 real_len; 182 }; 183 184 /** 185 * struct nfp_net_tx_ring - TX ring structure 186 * @r_vec: Back pointer to ring vector structure 187 * @idx: Ring index from Linux's perspective 188 * @qcidx: Queue Controller Peripheral (QCP) queue index for the TX queue 189 * @qcp_q: Pointer to base of the QCP TX queue 190 * @cnt: Size of the queue in number of descriptors 191 * @wr_p: TX ring write pointer (free running) 192 * @rd_p: TX ring read pointer (free running) 193 * @qcp_rd_p: Local copy of QCP TX queue read pointer 194 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer 195 * (used for .xmit_more delayed kick) 196 * @txbufs: Array of transmitted TX buffers, to free on transmit 197 * @txds: Virtual address of TX ring in host memory 198 * @dma: DMA address of the TX ring 199 * @size: Size, in bytes, of the TX ring (needed to free) 200 */ 201 struct nfp_net_tx_ring { 202 struct nfp_net_r_vector *r_vec; 203 204 u32 idx; 205 int qcidx; 206 u8 __iomem *qcp_q; 207 208 u32 cnt; 209 u32 wr_p; 210 u32 rd_p; 211 u32 qcp_rd_p; 212 213 u32 wr_ptr_add; 214 215 struct nfp_net_tx_buf *txbufs; 216 struct nfp_net_tx_desc *txds; 217 218 dma_addr_t dma; 219 unsigned int size; 220 } ____cacheline_aligned; 221 222 /* RX and freelist descriptor format */ 223 224 #define PCIE_DESC_RX_DD BIT(7) 225 #define PCIE_DESC_RX_META_LEN_MASK GENMASK(6, 0) 226 227 /* Flags in the RX descriptor */ 228 #define PCIE_DESC_RX_RSS cpu_to_le16(BIT(15)) 229 #define PCIE_DESC_RX_I_IP4_CSUM cpu_to_le16(BIT(14)) 230 #define PCIE_DESC_RX_I_IP4_CSUM_OK cpu_to_le16(BIT(13)) 231 #define PCIE_DESC_RX_I_TCP_CSUM cpu_to_le16(BIT(12)) 232 #define PCIE_DESC_RX_I_TCP_CSUM_OK cpu_to_le16(BIT(11)) 233 #define PCIE_DESC_RX_I_UDP_CSUM cpu_to_le16(BIT(10)) 234 #define PCIE_DESC_RX_I_UDP_CSUM_OK cpu_to_le16(BIT(9)) 235 #define PCIE_DESC_RX_BPF cpu_to_le16(BIT(8)) 236 #define PCIE_DESC_RX_EOP cpu_to_le16(BIT(7)) 237 #define PCIE_DESC_RX_IP4_CSUM cpu_to_le16(BIT(6)) 238 #define PCIE_DESC_RX_IP4_CSUM_OK cpu_to_le16(BIT(5)) 239 #define PCIE_DESC_RX_TCP_CSUM cpu_to_le16(BIT(4)) 240 #define PCIE_DESC_RX_TCP_CSUM_OK cpu_to_le16(BIT(3)) 241 #define PCIE_DESC_RX_UDP_CSUM cpu_to_le16(BIT(2)) 242 #define PCIE_DESC_RX_UDP_CSUM_OK cpu_to_le16(BIT(1)) 243 #define PCIE_DESC_RX_VLAN cpu_to_le16(BIT(0)) 244 245 #define PCIE_DESC_RX_CSUM_ALL (PCIE_DESC_RX_IP4_CSUM | \ 246 PCIE_DESC_RX_TCP_CSUM | \ 247 PCIE_DESC_RX_UDP_CSUM | \ 248 PCIE_DESC_RX_I_IP4_CSUM | \ 249 PCIE_DESC_RX_I_TCP_CSUM | \ 250 PCIE_DESC_RX_I_UDP_CSUM) 251 #define PCIE_DESC_RX_CSUM_OK_SHIFT 1 252 #define __PCIE_DESC_RX_CSUM_ALL le16_to_cpu(PCIE_DESC_RX_CSUM_ALL) 253 #define __PCIE_DESC_RX_CSUM_ALL_OK (__PCIE_DESC_RX_CSUM_ALL >> \ 254 PCIE_DESC_RX_CSUM_OK_SHIFT) 255 256 struct nfp_net_rx_desc { 257 union { 258 struct { 259 u8 dma_addr_hi; /* High bits of the buf address */ 260 __le16 reserved; /* Must be zero */ 261 u8 meta_len_dd; /* Must be zero */ 262 263 __le32 dma_addr_lo; /* Low bits of the buffer address */ 264 } __packed fld; 265 266 struct { 267 __le16 data_len; /* Length of the frame + meta data */ 268 u8 reserved; 269 u8 meta_len_dd; /* Length of meta data prepended + 270 * descriptor done flag. 271 */ 272 273 __le16 flags; /* RX flags. See @PCIE_DESC_RX_* */ 274 __le16 vlan; /* VLAN if stripped */ 275 } __packed rxd; 276 277 __le32 vals[2]; 278 }; 279 }; 280 281 #define NFP_NET_META_FIELD_MASK GENMASK(NFP_NET_META_FIELD_SIZE - 1, 0) 282 283 struct nfp_net_rx_hash { 284 __be32 hash_type; 285 __be32 hash; 286 }; 287 288 /** 289 * struct nfp_net_rx_buf - software RX buffer descriptor 290 * @frag: page fragment buffer 291 * @dma_addr: DMA mapping address of the buffer 292 */ 293 struct nfp_net_rx_buf { 294 void *frag; 295 dma_addr_t dma_addr; 296 }; 297 298 /** 299 * struct nfp_net_rx_ring - RX ring structure 300 * @r_vec: Back pointer to ring vector structure 301 * @cnt: Size of the queue in number of descriptors 302 * @wr_p: FL/RX ring write pointer (free running) 303 * @rd_p: FL/RX ring read pointer (free running) 304 * @idx: Ring index from Linux's perspective 305 * @fl_qcidx: Queue Controller Peripheral (QCP) queue index for the freelist 306 * @rx_qcidx: Queue Controller Peripheral (QCP) queue index for the RX queue 307 * @qcp_fl: Pointer to base of the QCP freelist queue 308 * @qcp_rx: Pointer to base of the QCP RX queue 309 * @wr_ptr_add: Accumulated number of buffers to add to QCP write pointer 310 * (used for free list batching) 311 * @rxbufs: Array of transmitted FL/RX buffers 312 * @rxds: Virtual address of FL/RX ring in host memory 313 * @dma: DMA address of the FL/RX ring 314 * @size: Size, in bytes, of the FL/RX ring (needed to free) 315 * @bufsz: Buffer allocation size for convenience of management routines 316 * (NOTE: this is in second cache line, do not use on fast path!) 317 */ 318 struct nfp_net_rx_ring { 319 struct nfp_net_r_vector *r_vec; 320 321 u32 cnt; 322 u32 wr_p; 323 u32 rd_p; 324 325 u16 idx; 326 u16 wr_ptr_add; 327 328 int fl_qcidx; 329 int rx_qcidx; 330 u8 __iomem *qcp_fl; 331 u8 __iomem *qcp_rx; 332 333 struct nfp_net_rx_buf *rxbufs; 334 struct nfp_net_rx_desc *rxds; 335 336 dma_addr_t dma; 337 unsigned int size; 338 unsigned int bufsz; 339 } ____cacheline_aligned; 340 341 /** 342 * struct nfp_net_r_vector - Per ring interrupt vector configuration 343 * @nfp_net: Backpointer to nfp_net structure 344 * @napi: NAPI structure for this ring vec 345 * @tx_ring: Pointer to TX ring 346 * @rx_ring: Pointer to RX ring 347 * @xdp_ring: Pointer to an extra TX ring for XDP 348 * @irq_idx: Index into MSI-X table 349 * @rx_sync: Seqlock for atomic updates of RX stats 350 * @rx_pkts: Number of received packets 351 * @rx_bytes: Number of received bytes 352 * @rx_drops: Number of packets dropped on RX due to lack of resources 353 * @hw_csum_rx_ok: Counter of packets where the HW checksum was OK 354 * @hw_csum_rx_inner_ok: Counter of packets where the inner HW checksum was OK 355 * @hw_csum_rx_error: Counter of packets with bad checksums 356 * @tx_sync: Seqlock for atomic updates of TX stats 357 * @tx_pkts: Number of Transmitted packets 358 * @tx_bytes: Number of Transmitted bytes 359 * @hw_csum_tx: Counter of packets with TX checksum offload requested 360 * @hw_csum_tx_inner: Counter of inner TX checksum offload requests 361 * @tx_gather: Counter of packets with Gather DMA 362 * @tx_lso: Counter of LSO packets sent 363 * @tx_errors: How many TX errors were encountered 364 * @tx_busy: How often was TX busy (no space)? 365 * @handler: Interrupt handler for this ring vector 366 * @name: Name of the interrupt vector 367 * @affinity_mask: SMP affinity mask for this vector 368 * 369 * This structure ties RX and TX rings to interrupt vectors and a NAPI 370 * context. This currently only supports one RX and TX ring per 371 * interrupt vector but might be extended in the future to allow 372 * association of multiple rings per vector. 373 */ 374 struct nfp_net_r_vector { 375 struct nfp_net *nfp_net; 376 struct napi_struct napi; 377 378 struct nfp_net_tx_ring *tx_ring; 379 struct nfp_net_rx_ring *rx_ring; 380 381 int irq_idx; 382 383 struct u64_stats_sync rx_sync; 384 u64 rx_pkts; 385 u64 rx_bytes; 386 u64 rx_drops; 387 u64 hw_csum_rx_ok; 388 u64 hw_csum_rx_inner_ok; 389 u64 hw_csum_rx_error; 390 391 struct nfp_net_tx_ring *xdp_ring; 392 393 struct u64_stats_sync tx_sync; 394 u64 tx_pkts; 395 u64 tx_bytes; 396 u64 hw_csum_tx; 397 u64 hw_csum_tx_inner; 398 u64 tx_gather; 399 u64 tx_lso; 400 u64 tx_errors; 401 u64 tx_busy; 402 403 irq_handler_t handler; 404 char name[IFNAMSIZ + 8]; 405 cpumask_t affinity_mask; 406 } ____cacheline_aligned; 407 408 /* Firmware version as it is written in the 32bit value in the BAR */ 409 struct nfp_net_fw_version { 410 u8 minor; 411 u8 major; 412 u8 class; 413 u8 resv; 414 } __packed; 415 416 static inline bool nfp_net_fw_ver_eq(struct nfp_net_fw_version *fw_ver, 417 u8 resv, u8 class, u8 major, u8 minor) 418 { 419 return fw_ver->resv == resv && 420 fw_ver->class == class && 421 fw_ver->major == major && 422 fw_ver->minor == minor; 423 } 424 425 struct nfp_stat_pair { 426 u64 pkts; 427 u64 bytes; 428 }; 429 430 /** 431 * struct nfp_net - NFP network device structure 432 * @pdev: Backpointer to PCI device 433 * @netdev: Backpointer to net_device structure 434 * @nfp_fallback: Is the driver used in fallback mode? 435 * @is_vf: Is the driver attached to a VF? 436 * @fw_loaded: Is the firmware loaded? 437 * @bpf_offload_skip_sw: Offloaded BPF program will not be rerun by cls_bpf 438 * @bpf_offload_xdp: Offloaded BPF program is XDP 439 * @ctrl: Local copy of the control register/word. 440 * @fl_bufsz: Currently configured size of the freelist buffers 441 * @rx_offset: Offset in the RX buffers where packet data starts 442 * @xdp_prog: Installed XDP program 443 * @cpp: Pointer to the CPP handle 444 * @nfp_dev_cpp: Pointer to the NFP Device handle 445 * @ctrl_area: Pointer to the CPP area for the control BAR 446 * @tx_area: Pointer to the CPP area for the TX queues 447 * @rx_area: Pointer to the CPP area for the FL/RX queues 448 * @fw_ver: Firmware version 449 * @cap: Capabilities advertised by the Firmware 450 * @max_mtu: Maximum support MTU advertised by the Firmware 451 * @rss_cfg: RSS configuration 452 * @rss_key: RSS secret key 453 * @rss_itbl: RSS indirection table 454 * @rx_filter: Filter offload statistics - dropped packets/bytes 455 * @rx_filter_prev: Filter offload statistics - values from previous update 456 * @rx_filter_change: Jiffies when statistics last changed 457 * @rx_filter_stats_timer: Timer for polling filter offload statistics 458 * @rx_filter_lock: Lock protecting timer state changes (teardown) 459 * @max_tx_rings: Maximum number of TX rings supported by the Firmware 460 * @max_rx_rings: Maximum number of RX rings supported by the Firmware 461 * @num_tx_rings: Currently configured number of TX rings 462 * @num_stack_tx_rings: Number of TX rings used by the stack (not XDP) 463 * @num_rx_rings: Currently configured number of RX rings 464 * @txd_cnt: Size of the TX ring in number of descriptors 465 * @rxd_cnt: Size of the RX ring in number of descriptors 466 * @tx_rings: Array of pre-allocated TX ring structures 467 * @rx_rings: Array of pre-allocated RX ring structures 468 * @max_r_vecs: Number of allocated interrupt vectors for RX/TX 469 * @num_r_vecs: Number of used ring vectors 470 * @r_vecs: Pre-allocated array of ring vectors 471 * @irq_entries: Pre-allocated array of MSI-X entries 472 * @lsc_handler: Handler for Link State Change interrupt 473 * @lsc_name: Name for Link State Change interrupt 474 * @exn_handler: Handler for Exception interrupt 475 * @exn_name: Name for Exception interrupt 476 * @shared_handler: Handler for shared interrupts 477 * @shared_name: Name for shared interrupt 478 * @me_freq_mhz: ME clock_freq (MHz) 479 * @reconfig_lock: Protects HW reconfiguration request regs/machinery 480 * @reconfig_posted: Pending reconfig bits coming from async sources 481 * @reconfig_timer_active: Timer for reading reconfiguration results is pending 482 * @reconfig_sync_present: Some thread is performing synchronous reconfig 483 * @reconfig_timer: Timer for async reading of reconfig results 484 * @link_up: Is the link up? 485 * @link_status_lock: Protects @link_up and ensures atomicity with BAR reading 486 * @rx_coalesce_usecs: RX interrupt moderation usecs delay parameter 487 * @rx_coalesce_max_frames: RX interrupt moderation frame count parameter 488 * @tx_coalesce_usecs: TX interrupt moderation usecs delay parameter 489 * @tx_coalesce_max_frames: TX interrupt moderation frame count parameter 490 * @vxlan_ports: VXLAN ports for RX inner csum offload communicated to HW 491 * @vxlan_usecnt: IPv4/IPv6 VXLAN port use counts 492 * @qcp_cfg: Pointer to QCP queue used for configuration notification 493 * @ctrl_bar: Pointer to mapped control BAR 494 * @tx_bar: Pointer to mapped TX queues 495 * @rx_bar: Pointer to mapped FL/RX queues 496 * @debugfs_dir: Device directory in debugfs 497 */ 498 struct nfp_net { 499 struct pci_dev *pdev; 500 struct net_device *netdev; 501 502 unsigned nfp_fallback:1; 503 unsigned is_vf:1; 504 unsigned fw_loaded:1; 505 unsigned bpf_offload_skip_sw:1; 506 unsigned bpf_offload_xdp:1; 507 508 u32 ctrl; 509 u32 fl_bufsz; 510 511 u32 rx_offset; 512 513 struct bpf_prog *xdp_prog; 514 515 struct nfp_net_tx_ring *tx_rings; 516 struct nfp_net_rx_ring *rx_rings; 517 518 #ifdef CONFIG_PCI_IOV 519 unsigned int num_vfs; 520 struct vf_data_storage *vfinfo; 521 int vf_rate_link_speed; 522 #endif 523 524 struct nfp_cpp *cpp; 525 struct platform_device *nfp_dev_cpp; 526 struct nfp_cpp_area *ctrl_area; 527 struct nfp_cpp_area *tx_area; 528 struct nfp_cpp_area *rx_area; 529 530 struct nfp_net_fw_version fw_ver; 531 u32 cap; 532 u32 max_mtu; 533 534 u32 rss_cfg; 535 u8 rss_key[NFP_NET_CFG_RSS_KEY_SZ]; 536 u8 rss_itbl[NFP_NET_CFG_RSS_ITBL_SZ]; 537 538 struct nfp_stat_pair rx_filter, rx_filter_prev; 539 unsigned long rx_filter_change; 540 struct timer_list rx_filter_stats_timer; 541 spinlock_t rx_filter_lock; 542 543 unsigned int max_tx_rings; 544 unsigned int max_rx_rings; 545 546 unsigned int num_tx_rings; 547 unsigned int num_stack_tx_rings; 548 unsigned int num_rx_rings; 549 550 int stride_tx; 551 int stride_rx; 552 553 int txd_cnt; 554 int rxd_cnt; 555 556 unsigned int max_r_vecs; 557 unsigned int num_r_vecs; 558 struct nfp_net_r_vector r_vecs[NFP_NET_MAX_R_VECS]; 559 struct msix_entry irq_entries[NFP_NET_MAX_IRQS]; 560 561 irq_handler_t lsc_handler; 562 char lsc_name[IFNAMSIZ + 8]; 563 564 irq_handler_t exn_handler; 565 char exn_name[IFNAMSIZ + 8]; 566 567 irq_handler_t shared_handler; 568 char shared_name[IFNAMSIZ + 8]; 569 570 u32 me_freq_mhz; 571 572 bool link_up; 573 spinlock_t link_status_lock; 574 575 spinlock_t reconfig_lock; 576 u32 reconfig_posted; 577 bool reconfig_timer_active; 578 bool reconfig_sync_present; 579 struct timer_list reconfig_timer; 580 581 u32 rx_coalesce_usecs; 582 u32 rx_coalesce_max_frames; 583 u32 tx_coalesce_usecs; 584 u32 tx_coalesce_max_frames; 585 586 __be16 vxlan_ports[NFP_NET_N_VXLAN_PORTS]; 587 u8 vxlan_usecnt[NFP_NET_N_VXLAN_PORTS]; 588 589 u8 __iomem *qcp_cfg; 590 591 u8 __iomem *ctrl_bar; 592 u8 __iomem *q_bar; 593 u8 __iomem *tx_bar; 594 u8 __iomem *rx_bar; 595 596 struct dentry *debugfs_dir; 597 }; 598 599 struct nfp_net_ring_set { 600 unsigned int n_rings; 601 unsigned int mtu; 602 unsigned int dcnt; 603 void *rings; 604 }; 605 606 /* Functions to read/write from/to a BAR 607 * Performs any endian conversion necessary. 608 */ 609 static inline u16 nn_readb(struct nfp_net *nn, int off) 610 { 611 return readb(nn->ctrl_bar + off); 612 } 613 614 static inline void nn_writeb(struct nfp_net *nn, int off, u8 val) 615 { 616 writeb(val, nn->ctrl_bar + off); 617 } 618 619 static inline u16 nn_readw(struct nfp_net *nn, int off) 620 { 621 return readw(nn->ctrl_bar + off); 622 } 623 624 static inline void nn_writew(struct nfp_net *nn, int off, u16 val) 625 { 626 writew(val, nn->ctrl_bar + off); 627 } 628 629 static inline u32 nn_readl(struct nfp_net *nn, int off) 630 { 631 return readl(nn->ctrl_bar + off); 632 } 633 634 static inline void nn_writel(struct nfp_net *nn, int off, u32 val) 635 { 636 writel(val, nn->ctrl_bar + off); 637 } 638 639 static inline u64 nn_readq(struct nfp_net *nn, int off) 640 { 641 return readq(nn->ctrl_bar + off); 642 } 643 644 static inline void nn_writeq(struct nfp_net *nn, int off, u64 val) 645 { 646 writeq(val, nn->ctrl_bar + off); 647 } 648 649 /* Flush posted PCI writes by reading something without side effects */ 650 static inline void nn_pci_flush(struct nfp_net *nn) 651 { 652 nn_readl(nn, NFP_NET_CFG_VERSION); 653 } 654 655 /* Queue Controller Peripheral access functions and definitions. 656 * 657 * Some of the BARs of the NFP are mapped to portions of the Queue 658 * Controller Peripheral (QCP) address space on the NFP. A QCP queue 659 * has a read and a write pointer (as well as a size and flags, 660 * indicating overflow etc). The QCP offers a number of different 661 * operation on queue pointers, but here we only offer function to 662 * either add to a pointer or to read the pointer value. 663 */ 664 #define NFP_QCP_QUEUE_ADDR_SZ 0x800 665 #define NFP_QCP_QUEUE_OFF(_x) ((_x) * NFP_QCP_QUEUE_ADDR_SZ) 666 #define NFP_QCP_QUEUE_ADD_RPTR 0x0000 667 #define NFP_QCP_QUEUE_ADD_WPTR 0x0004 668 #define NFP_QCP_QUEUE_STS_LO 0x0008 669 #define NFP_QCP_QUEUE_STS_LO_READPTR_mask 0x3ffff 670 #define NFP_QCP_QUEUE_STS_HI 0x000c 671 #define NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask 0x3ffff 672 673 /* The offset of a QCP queues in the PCIe Target */ 674 #define NFP_PCIE_QUEUE(_q) (0x80000 + (NFP_QCP_QUEUE_ADDR_SZ * ((_q) & 0xff))) 675 676 /* nfp_qcp_ptr - Read or Write Pointer of a queue */ 677 enum nfp_qcp_ptr { 678 NFP_QCP_READ_PTR = 0, 679 NFP_QCP_WRITE_PTR 680 }; 681 682 /* There appear to be an *undocumented* upper limit on the value which 683 * one can add to a queue and that value is either 0x3f or 0x7f. We 684 * go with 0x3f as a conservative measure. 685 */ 686 #define NFP_QCP_MAX_ADD 0x3f 687 688 static inline void _nfp_qcp_ptr_add(u8 __iomem *q, 689 enum nfp_qcp_ptr ptr, u32 val) 690 { 691 u32 off; 692 693 if (ptr == NFP_QCP_READ_PTR) 694 off = NFP_QCP_QUEUE_ADD_RPTR; 695 else 696 off = NFP_QCP_QUEUE_ADD_WPTR; 697 698 while (val > NFP_QCP_MAX_ADD) { 699 writel(NFP_QCP_MAX_ADD, q + off); 700 val -= NFP_QCP_MAX_ADD; 701 } 702 703 writel(val, q + off); 704 } 705 706 /** 707 * nfp_qcp_rd_ptr_add() - Add the value to the read pointer of a queue 708 * 709 * @q: Base address for queue structure 710 * @val: Value to add to the queue pointer 711 * 712 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 713 */ 714 static inline void nfp_qcp_rd_ptr_add(u8 __iomem *q, u32 val) 715 { 716 _nfp_qcp_ptr_add(q, NFP_QCP_READ_PTR, val); 717 } 718 719 /** 720 * nfp_qcp_wr_ptr_add() - Add the value to the write pointer of a queue 721 * 722 * @q: Base address for queue structure 723 * @val: Value to add to the queue pointer 724 * 725 * If @val is greater than @NFP_QCP_MAX_ADD multiple writes are performed. 726 */ 727 static inline void nfp_qcp_wr_ptr_add(u8 __iomem *q, u32 val) 728 { 729 _nfp_qcp_ptr_add(q, NFP_QCP_WRITE_PTR, val); 730 } 731 732 static inline u32 _nfp_qcp_read(u8 __iomem *q, enum nfp_qcp_ptr ptr) 733 { 734 u32 off; 735 u32 val; 736 737 if (ptr == NFP_QCP_READ_PTR) 738 off = NFP_QCP_QUEUE_STS_LO; 739 else 740 off = NFP_QCP_QUEUE_STS_HI; 741 742 val = readl(q + off); 743 744 if (ptr == NFP_QCP_READ_PTR) 745 return val & NFP_QCP_QUEUE_STS_LO_READPTR_mask; 746 else 747 return val & NFP_QCP_QUEUE_STS_HI_WRITEPTR_mask; 748 } 749 750 /** 751 * nfp_qcp_rd_ptr_read() - Read the current read pointer value for a queue 752 * @q: Base address for queue structure 753 * 754 * Return: Value read. 755 */ 756 static inline u32 nfp_qcp_rd_ptr_read(u8 __iomem *q) 757 { 758 return _nfp_qcp_read(q, NFP_QCP_READ_PTR); 759 } 760 761 /** 762 * nfp_qcp_wr_ptr_read() - Read the current write pointer value for a queue 763 * @q: Base address for queue structure 764 * 765 * Return: Value read. 766 */ 767 static inline u32 nfp_qcp_wr_ptr_read(u8 __iomem *q) 768 { 769 return _nfp_qcp_read(q, NFP_QCP_WRITE_PTR); 770 } 771 772 /* Globals */ 773 extern const char nfp_net_driver_name[]; 774 extern const char nfp_net_driver_version[]; 775 776 /* Prototypes */ 777 void nfp_net_get_fw_version(struct nfp_net_fw_version *fw_ver, 778 void __iomem *ctrl_bar); 779 780 struct nfp_net * 781 nfp_net_netdev_alloc(struct pci_dev *pdev, 782 unsigned int max_tx_rings, unsigned int max_rx_rings); 783 void nfp_net_netdev_free(struct nfp_net *nn); 784 int nfp_net_netdev_init(struct net_device *netdev); 785 void nfp_net_netdev_clean(struct net_device *netdev); 786 void nfp_net_set_ethtool_ops(struct net_device *netdev); 787 void nfp_net_info(struct nfp_net *nn); 788 int nfp_net_reconfig(struct nfp_net *nn, u32 update); 789 void nfp_net_rss_write_itbl(struct nfp_net *nn); 790 void nfp_net_rss_write_key(struct nfp_net *nn); 791 void nfp_net_coalesce_write_cfg(struct nfp_net *nn); 792 int nfp_net_irqs_alloc(struct nfp_net *nn); 793 void nfp_net_irqs_disable(struct nfp_net *nn); 794 int 795 nfp_net_ring_reconfig(struct nfp_net *nn, struct bpf_prog **xdp_prog, 796 struct nfp_net_ring_set *rx, struct nfp_net_ring_set *tx); 797 798 #ifdef CONFIG_NFP_NET_DEBUG 799 void nfp_net_debugfs_create(void); 800 void nfp_net_debugfs_destroy(void); 801 void nfp_net_debugfs_adapter_add(struct nfp_net *nn); 802 void nfp_net_debugfs_adapter_del(struct nfp_net *nn); 803 #else 804 static inline void nfp_net_debugfs_create(void) 805 { 806 } 807 808 static inline void nfp_net_debugfs_destroy(void) 809 { 810 } 811 812 static inline void nfp_net_debugfs_adapter_add(struct nfp_net *nn) 813 { 814 } 815 816 static inline void nfp_net_debugfs_adapter_del(struct nfp_net *nn) 817 { 818 } 819 #endif /* CONFIG_NFP_NET_DEBUG */ 820 821 void nfp_net_filter_stats_timer(unsigned long data); 822 int nfp_net_bpf_offload(struct nfp_net *nn, struct tc_cls_bpf_offload *cls_bpf); 823 824 #endif /* _NFP_NET_H_ */ 825