1 /* 2 * Copyright (C) 2016-2017 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef __NFP_ASM_H__ 35 #define __NFP_ASM_H__ 1 36 37 #include <linux/bitfield.h> 38 #include <linux/bug.h> 39 #include <linux/types.h> 40 41 #define REG_NONE 0 42 #define REG_WIDTH 4 43 44 #define RE_REG_NO_DST 0x020 45 #define RE_REG_IMM 0x020 46 #define RE_REG_IMM_encode(x) \ 47 (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1)) 48 #define RE_REG_IMM_MAX 0x07fULL 49 #define RE_REG_LM 0x050 50 #define RE_REG_LM_IDX 0x008 51 #define RE_REG_LM_IDX_MAX 0x7 52 #define RE_REG_XFR 0x080 53 54 #define UR_REG_XFR 0x180 55 #define UR_REG_LM 0x200 56 #define UR_REG_LM_IDX 0x020 57 #define UR_REG_LM_POST_MOD 0x010 58 #define UR_REG_LM_POST_MOD_DEC 0x001 59 #define UR_REG_LM_IDX_MAX 0xf 60 #define UR_REG_NN 0x280 61 #define UR_REG_NO_DST 0x300 62 #define UR_REG_IMM UR_REG_NO_DST 63 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x)) 64 #define UR_REG_IMM_MAX 0x0ffULL 65 66 #define OP_BR_BASE 0x0d800000020ULL 67 #define OP_BR_BASE_MASK 0x0f8000c3ce0ULL 68 #define OP_BR_MASK 0x0000000001fULL 69 #define OP_BR_EV_PIP 0x00000000300ULL 70 #define OP_BR_CSS 0x0000003c000ULL 71 #define OP_BR_DEFBR 0x00000300000ULL 72 #define OP_BR_ADDR_LO 0x007ffc00000ULL 73 #define OP_BR_ADDR_HI 0x10000000000ULL 74 75 #define OP_BR_BIT_BASE 0x0d000000000ULL 76 #define OP_BR_BIT_BASE_MASK 0x0f800080300ULL 77 #define OP_BR_BIT_A_SRC 0x000000000ffULL 78 #define OP_BR_BIT_B_SRC 0x0000003fc00ULL 79 #define OP_BR_BIT_BV 0x00000040000ULL 80 #define OP_BR_BIT_SRC_LMEXTN 0x40000000000ULL 81 #define OP_BR_BIT_DEFBR OP_BR_DEFBR 82 #define OP_BR_BIT_ADDR_LO OP_BR_ADDR_LO 83 #define OP_BR_BIT_ADDR_HI OP_BR_ADDR_HI 84 85 static inline bool nfp_is_br(u64 insn) 86 { 87 return (insn & OP_BR_BASE_MASK) == OP_BR_BASE || 88 (insn & OP_BR_BIT_BASE_MASK) == OP_BR_BIT_BASE; 89 } 90 91 enum br_mask { 92 BR_BEQ = 0x00, 93 BR_BNE = 0x01, 94 BR_BMI = 0x02, 95 BR_BHS = 0x04, 96 BR_BLO = 0x05, 97 BR_BGE = 0x08, 98 BR_BLT = 0x09, 99 BR_UNC = 0x18, 100 }; 101 102 enum br_ev_pip { 103 BR_EV_PIP_UNCOND = 0, 104 BR_EV_PIP_COND = 1, 105 }; 106 107 enum br_ctx_signal_state { 108 BR_CSS_NONE = 2, 109 }; 110 111 u16 br_get_offset(u64 instr); 112 void br_set_offset(u64 *instr, u16 offset); 113 void br_add_offset(u64 *instr, u16 offset); 114 115 #define OP_BBYTE_BASE 0x0c800000000ULL 116 #define OP_BB_A_SRC 0x000000000ffULL 117 #define OP_BB_BYTE 0x00000000300ULL 118 #define OP_BB_B_SRC 0x0000003fc00ULL 119 #define OP_BB_I8 0x00000040000ULL 120 #define OP_BB_EQ 0x00000080000ULL 121 #define OP_BB_DEFBR 0x00000300000ULL 122 #define OP_BB_ADDR_LO 0x007ffc00000ULL 123 #define OP_BB_ADDR_HI 0x10000000000ULL 124 #define OP_BB_SRC_LMEXTN 0x40000000000ULL 125 126 #define OP_BALU_BASE 0x0e800000000ULL 127 #define OP_BA_A_SRC 0x000000003ffULL 128 #define OP_BA_B_SRC 0x000000ffc00ULL 129 #define OP_BA_DEFBR 0x00000300000ULL 130 #define OP_BA_ADDR_HI 0x0007fc00000ULL 131 132 #define OP_IMMED_A_SRC 0x000000003ffULL 133 #define OP_IMMED_B_SRC 0x000000ffc00ULL 134 #define OP_IMMED_IMM 0x0000ff00000ULL 135 #define OP_IMMED_WIDTH 0x00060000000ULL 136 #define OP_IMMED_INV 0x00080000000ULL 137 #define OP_IMMED_SHIFT 0x00600000000ULL 138 #define OP_IMMED_BASE 0x0f000000000ULL 139 #define OP_IMMED_WR_AB 0x20000000000ULL 140 #define OP_IMMED_SRC_LMEXTN 0x40000000000ULL 141 #define OP_IMMED_DST_LMEXTN 0x80000000000ULL 142 143 enum immed_width { 144 IMMED_WIDTH_ALL = 0, 145 IMMED_WIDTH_BYTE = 1, 146 IMMED_WIDTH_WORD = 2, 147 }; 148 149 enum immed_shift { 150 IMMED_SHIFT_0B = 0, 151 IMMED_SHIFT_1B = 1, 152 IMMED_SHIFT_2B = 2, 153 }; 154 155 u16 immed_get_value(u64 instr); 156 void immed_set_value(u64 *instr, u16 immed); 157 void immed_add_value(u64 *instr, u16 offset); 158 159 #define OP_SHF_BASE 0x08000000000ULL 160 #define OP_SHF_A_SRC 0x000000000ffULL 161 #define OP_SHF_SC 0x00000000300ULL 162 #define OP_SHF_B_SRC 0x0000003fc00ULL 163 #define OP_SHF_I8 0x00000040000ULL 164 #define OP_SHF_SW 0x00000080000ULL 165 #define OP_SHF_DST 0x0000ff00000ULL 166 #define OP_SHF_SHIFT 0x001f0000000ULL 167 #define OP_SHF_OP 0x00e00000000ULL 168 #define OP_SHF_DST_AB 0x01000000000ULL 169 #define OP_SHF_WR_AB 0x20000000000ULL 170 #define OP_SHF_SRC_LMEXTN 0x40000000000ULL 171 #define OP_SHF_DST_LMEXTN 0x80000000000ULL 172 173 enum shf_op { 174 SHF_OP_NONE = 0, 175 SHF_OP_AND = 2, 176 SHF_OP_OR = 5, 177 SHF_OP_ASHR = 6, 178 }; 179 180 enum shf_sc { 181 SHF_SC_R_ROT = 0, 182 SHF_SC_NONE = SHF_SC_R_ROT, 183 SHF_SC_R_SHF = 1, 184 SHF_SC_L_SHF = 2, 185 SHF_SC_R_DSHF = 3, 186 }; 187 188 #define OP_ALU_A_SRC 0x000000003ffULL 189 #define OP_ALU_B_SRC 0x000000ffc00ULL 190 #define OP_ALU_DST 0x0003ff00000ULL 191 #define OP_ALU_SW 0x00040000000ULL 192 #define OP_ALU_OP 0x00f80000000ULL 193 #define OP_ALU_DST_AB 0x01000000000ULL 194 #define OP_ALU_BASE 0x0a000000000ULL 195 #define OP_ALU_WR_AB 0x20000000000ULL 196 #define OP_ALU_SRC_LMEXTN 0x40000000000ULL 197 #define OP_ALU_DST_LMEXTN 0x80000000000ULL 198 199 enum alu_op { 200 ALU_OP_NONE = 0x00, 201 ALU_OP_ADD = 0x01, 202 ALU_OP_NOT = 0x04, 203 ALU_OP_ADD_2B = 0x05, 204 ALU_OP_AND = 0x08, 205 ALU_OP_AND_NOT_A = 0x0c, 206 ALU_OP_SUB_C = 0x0d, 207 ALU_OP_AND_NOT_B = 0x10, 208 ALU_OP_ADD_C = 0x11, 209 ALU_OP_OR = 0x14, 210 ALU_OP_SUB = 0x15, 211 ALU_OP_XOR = 0x18, 212 }; 213 214 enum alu_dst_ab { 215 ALU_DST_A = 0, 216 ALU_DST_B = 1, 217 }; 218 219 #define OP_LDF_BASE 0x0c000000000ULL 220 #define OP_LDF_A_SRC 0x000000000ffULL 221 #define OP_LDF_SC 0x00000000300ULL 222 #define OP_LDF_B_SRC 0x0000003fc00ULL 223 #define OP_LDF_I8 0x00000040000ULL 224 #define OP_LDF_SW 0x00000080000ULL 225 #define OP_LDF_ZF 0x00000100000ULL 226 #define OP_LDF_BMASK 0x0000f000000ULL 227 #define OP_LDF_SHF 0x001f0000000ULL 228 #define OP_LDF_WR_AB 0x20000000000ULL 229 #define OP_LDF_SRC_LMEXTN 0x40000000000ULL 230 #define OP_LDF_DST_LMEXTN 0x80000000000ULL 231 232 #define OP_CMD_A_SRC 0x000000000ffULL 233 #define OP_CMD_CTX 0x00000000300ULL 234 #define OP_CMD_B_SRC 0x0000003fc00ULL 235 #define OP_CMD_TOKEN 0x000000c0000ULL 236 #define OP_CMD_XFER 0x00001f00000ULL 237 #define OP_CMD_CNT 0x0000e000000ULL 238 #define OP_CMD_SIG 0x000f0000000ULL 239 #define OP_CMD_TGT_CMD 0x07f00000000ULL 240 #define OP_CMD_INDIR 0x20000000000ULL 241 #define OP_CMD_MODE 0x1c0000000000ULL 242 243 struct cmd_tgt_act { 244 u8 token; 245 u8 tgt_cmd; 246 }; 247 248 enum cmd_tgt_map { 249 CMD_TGT_READ8, 250 CMD_TGT_WRITE8_SWAP, 251 CMD_TGT_WRITE32_SWAP, 252 CMD_TGT_READ32, 253 CMD_TGT_READ32_LE, 254 CMD_TGT_READ32_SWAP, 255 CMD_TGT_READ_LE, 256 CMD_TGT_READ_SWAP_LE, 257 CMD_TGT_ADD, 258 CMD_TGT_ADD_IMM, 259 __CMD_TGT_MAP_SIZE, 260 }; 261 262 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE]; 263 264 enum cmd_mode { 265 CMD_MODE_40b_AB = 0, 266 CMD_MODE_40b_BA = 1, 267 CMD_MODE_32b = 4, 268 }; 269 270 enum cmd_ctx_swap { 271 CMD_CTX_SWAP = 0, 272 CMD_CTX_SWAP_DEFER1 = 1, 273 CMD_CTX_SWAP_DEFER2 = 2, 274 CMD_CTX_NO_SWAP = 3, 275 }; 276 277 #define CMD_OVE_DATA GENMASK(5, 3) 278 #define CMD_OVE_LEN BIT(7) 279 #define CMD_OV_LEN GENMASK(12, 8) 280 281 #define OP_LCSR_BASE 0x0fc00000000ULL 282 #define OP_LCSR_A_SRC 0x000000003ffULL 283 #define OP_LCSR_B_SRC 0x000000ffc00ULL 284 #define OP_LCSR_WRITE 0x00000200000ULL 285 #define OP_LCSR_ADDR 0x001ffc00000ULL 286 #define OP_LCSR_SRC_LMEXTN 0x40000000000ULL 287 #define OP_LCSR_DST_LMEXTN 0x80000000000ULL 288 289 enum lcsr_wr_src { 290 LCSR_WR_AREG, 291 LCSR_WR_BREG, 292 LCSR_WR_IMM, 293 }; 294 295 #define OP_CARB_BASE 0x0e000000000ULL 296 #define OP_CARB_OR 0x00000010000ULL 297 298 #define NFP_CSR_CTX_PTR 0x20 299 #define NFP_CSR_ACT_LM_ADDR0 0x64 300 #define NFP_CSR_ACT_LM_ADDR1 0x6c 301 #define NFP_CSR_ACT_LM_ADDR2 0x94 302 #define NFP_CSR_ACT_LM_ADDR3 0x9c 303 #define NFP_CSR_PSEUDO_RND_NUM 0x148 304 305 /* Software register representation, independent of operand type */ 306 #define NN_REG_TYPE GENMASK(31, 24) 307 #define NN_REG_LM_IDX GENMASK(23, 22) 308 #define NN_REG_LM_IDX_HI BIT(23) 309 #define NN_REG_LM_IDX_LO BIT(22) 310 #define NN_REG_LM_MOD GENMASK(21, 20) 311 #define NN_REG_VAL GENMASK(7, 0) 312 313 enum nfp_bpf_reg_type { 314 NN_REG_GPR_A = BIT(0), 315 NN_REG_GPR_B = BIT(1), 316 NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B, 317 NN_REG_NNR = BIT(2), 318 NN_REG_XFER = BIT(3), 319 NN_REG_IMM = BIT(4), 320 NN_REG_NONE = BIT(5), 321 NN_REG_LMEM = BIT(6), 322 }; 323 324 enum nfp_bpf_lm_mode { 325 NN_LM_MOD_NONE = 0, 326 NN_LM_MOD_INC, 327 NN_LM_MOD_DEC, 328 }; 329 330 #define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH) 331 #define reg_a(x) __enc_swreg((x), NN_REG_GPR_A) 332 #define reg_b(x) __enc_swreg((x), NN_REG_GPR_B) 333 #define reg_nnr(x) __enc_swreg((x), NN_REG_NNR) 334 #define reg_xfer(x) __enc_swreg((x), NN_REG_XFER) 335 #define reg_imm(x) __enc_swreg((x), NN_REG_IMM) 336 #define reg_none() __enc_swreg(0, NN_REG_NONE) 337 #define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off)) 338 #define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0) 339 #define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0) 340 #define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off)) 341 342 typedef __u32 __bitwise swreg; 343 344 static inline swreg __enc_swreg(u16 id, u8 type) 345 { 346 return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type)); 347 } 348 349 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off) 350 { 351 WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE)); 352 353 return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) | 354 FIELD_PREP(NN_REG_LM_IDX, id) | 355 FIELD_PREP(NN_REG_LM_MOD, mode) | 356 off); 357 } 358 359 static inline u32 swreg_raw(swreg reg) 360 { 361 return (__force u32)reg; 362 } 363 364 static inline enum nfp_bpf_reg_type swreg_type(swreg reg) 365 { 366 return FIELD_GET(NN_REG_TYPE, swreg_raw(reg)); 367 } 368 369 static inline u16 swreg_value(swreg reg) 370 { 371 return FIELD_GET(NN_REG_VAL, swreg_raw(reg)); 372 } 373 374 static inline bool swreg_lm_idx(swreg reg) 375 { 376 return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg)); 377 } 378 379 static inline bool swreg_lmextn(swreg reg) 380 { 381 return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg)); 382 } 383 384 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg) 385 { 386 return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg)); 387 } 388 389 struct nfp_insn_ur_regs { 390 enum alu_dst_ab dst_ab; 391 u16 dst; 392 u16 areg, breg; 393 bool swap; 394 bool wr_both; 395 bool dst_lmextn; 396 bool src_lmextn; 397 }; 398 399 struct nfp_insn_re_regs { 400 enum alu_dst_ab dst_ab; 401 u8 dst; 402 u8 areg, breg; 403 bool swap; 404 bool wr_both; 405 bool i8; 406 bool dst_lmextn; 407 bool src_lmextn; 408 }; 409 410 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg, 411 struct nfp_insn_ur_regs *reg); 412 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg, 413 struct nfp_insn_re_regs *reg, bool has_imm8); 414 415 #define NFP_USTORE_PREFETCH_WINDOW 8 416 417 int nfp_ustore_check_valid_no_ecc(u64 insn); 418 u64 nfp_ustore_calc_ecc_insn(u64 insn); 419 420 #define NFP_IND_ME_REFL_WR_SIG_INIT 3 421 #define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0) 422 #define NFP_IND_NUM_CONTEXTS 8 423 424 static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset) 425 { 426 return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR; 427 } 428 429 #endif 430