1 /* 2 * Copyright (C) 2016-2017 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef __NFP_ASM_H__ 35 #define __NFP_ASM_H__ 1 36 37 #include <linux/bitfield.h> 38 #include <linux/bug.h> 39 #include <linux/types.h> 40 41 #define REG_NONE 0 42 43 #define RE_REG_NO_DST 0x020 44 #define RE_REG_IMM 0x020 45 #define RE_REG_IMM_encode(x) \ 46 (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1)) 47 #define RE_REG_IMM_MAX 0x07fULL 48 #define RE_REG_LM 0x050 49 #define RE_REG_LM_IDX 0x008 50 #define RE_REG_LM_IDX_MAX 0x7 51 #define RE_REG_XFR 0x080 52 53 #define UR_REG_XFR 0x180 54 #define UR_REG_LM 0x200 55 #define UR_REG_LM_IDX 0x020 56 #define UR_REG_LM_POST_MOD 0x010 57 #define UR_REG_LM_POST_MOD_DEC 0x001 58 #define UR_REG_LM_IDX_MAX 0xf 59 #define UR_REG_NN 0x280 60 #define UR_REG_NO_DST 0x300 61 #define UR_REG_IMM UR_REG_NO_DST 62 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x)) 63 #define UR_REG_IMM_MAX 0x0ffULL 64 65 #define OP_BR_BASE 0x0d800000020ULL 66 #define OP_BR_BASE_MASK 0x0f8000c3ce0ULL 67 #define OP_BR_MASK 0x0000000001fULL 68 #define OP_BR_EV_PIP 0x00000000300ULL 69 #define OP_BR_CSS 0x0000003c000ULL 70 #define OP_BR_DEFBR 0x00000300000ULL 71 #define OP_BR_ADDR_LO 0x007ffc00000ULL 72 #define OP_BR_ADDR_HI 0x10000000000ULL 73 74 #define nfp_is_br(_insn) \ 75 (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE) 76 77 enum br_mask { 78 BR_BEQ = 0x00, 79 BR_BNE = 0x01, 80 BR_BMI = 0x02, 81 BR_BHS = 0x04, 82 BR_BLO = 0x05, 83 BR_BGE = 0x08, 84 BR_UNC = 0x18, 85 }; 86 87 enum br_ev_pip { 88 BR_EV_PIP_UNCOND = 0, 89 BR_EV_PIP_COND = 1, 90 }; 91 92 enum br_ctx_signal_state { 93 BR_CSS_NONE = 2, 94 }; 95 96 #define OP_BBYTE_BASE 0x0c800000000ULL 97 #define OP_BB_A_SRC 0x000000000ffULL 98 #define OP_BB_BYTE 0x00000000300ULL 99 #define OP_BB_B_SRC 0x0000003fc00ULL 100 #define OP_BB_I8 0x00000040000ULL 101 #define OP_BB_EQ 0x00000080000ULL 102 #define OP_BB_DEFBR 0x00000300000ULL 103 #define OP_BB_ADDR_LO 0x007ffc00000ULL 104 #define OP_BB_ADDR_HI 0x10000000000ULL 105 #define OP_BB_SRC_LMEXTN 0x40000000000ULL 106 107 #define OP_BALU_BASE 0x0e800000000ULL 108 #define OP_BA_A_SRC 0x000000003ffULL 109 #define OP_BA_B_SRC 0x000000ffc00ULL 110 #define OP_BA_DEFBR 0x00000300000ULL 111 #define OP_BA_ADDR_HI 0x0007fc00000ULL 112 113 #define OP_IMMED_A_SRC 0x000000003ffULL 114 #define OP_IMMED_B_SRC 0x000000ffc00ULL 115 #define OP_IMMED_IMM 0x0000ff00000ULL 116 #define OP_IMMED_WIDTH 0x00060000000ULL 117 #define OP_IMMED_INV 0x00080000000ULL 118 #define OP_IMMED_SHIFT 0x00600000000ULL 119 #define OP_IMMED_BASE 0x0f000000000ULL 120 #define OP_IMMED_WR_AB 0x20000000000ULL 121 #define OP_IMMED_SRC_LMEXTN 0x40000000000ULL 122 #define OP_IMMED_DST_LMEXTN 0x80000000000ULL 123 124 enum immed_width { 125 IMMED_WIDTH_ALL = 0, 126 IMMED_WIDTH_BYTE = 1, 127 IMMED_WIDTH_WORD = 2, 128 }; 129 130 enum immed_shift { 131 IMMED_SHIFT_0B = 0, 132 IMMED_SHIFT_1B = 1, 133 IMMED_SHIFT_2B = 2, 134 }; 135 136 #define OP_SHF_BASE 0x08000000000ULL 137 #define OP_SHF_A_SRC 0x000000000ffULL 138 #define OP_SHF_SC 0x00000000300ULL 139 #define OP_SHF_B_SRC 0x0000003fc00ULL 140 #define OP_SHF_I8 0x00000040000ULL 141 #define OP_SHF_SW 0x00000080000ULL 142 #define OP_SHF_DST 0x0000ff00000ULL 143 #define OP_SHF_SHIFT 0x001f0000000ULL 144 #define OP_SHF_OP 0x00e00000000ULL 145 #define OP_SHF_DST_AB 0x01000000000ULL 146 #define OP_SHF_WR_AB 0x20000000000ULL 147 #define OP_SHF_SRC_LMEXTN 0x40000000000ULL 148 #define OP_SHF_DST_LMEXTN 0x80000000000ULL 149 150 enum shf_op { 151 SHF_OP_NONE = 0, 152 SHF_OP_AND = 2, 153 SHF_OP_OR = 5, 154 }; 155 156 enum shf_sc { 157 SHF_SC_R_ROT = 0, 158 SHF_SC_NONE = SHF_SC_R_ROT, 159 SHF_SC_R_SHF = 1, 160 SHF_SC_L_SHF = 2, 161 SHF_SC_R_DSHF = 3, 162 }; 163 164 #define OP_ALU_A_SRC 0x000000003ffULL 165 #define OP_ALU_B_SRC 0x000000ffc00ULL 166 #define OP_ALU_DST 0x0003ff00000ULL 167 #define OP_ALU_SW 0x00040000000ULL 168 #define OP_ALU_OP 0x00f80000000ULL 169 #define OP_ALU_DST_AB 0x01000000000ULL 170 #define OP_ALU_BASE 0x0a000000000ULL 171 #define OP_ALU_WR_AB 0x20000000000ULL 172 #define OP_ALU_SRC_LMEXTN 0x40000000000ULL 173 #define OP_ALU_DST_LMEXTN 0x80000000000ULL 174 175 enum alu_op { 176 ALU_OP_NONE = 0x00, 177 ALU_OP_ADD = 0x01, 178 ALU_OP_NOT = 0x04, 179 ALU_OP_ADD_2B = 0x05, 180 ALU_OP_AND = 0x08, 181 ALU_OP_SUB_C = 0x0d, 182 ALU_OP_ADD_C = 0x11, 183 ALU_OP_OR = 0x14, 184 ALU_OP_SUB = 0x15, 185 ALU_OP_XOR = 0x18, 186 }; 187 188 enum alu_dst_ab { 189 ALU_DST_A = 0, 190 ALU_DST_B = 1, 191 }; 192 193 #define OP_LDF_BASE 0x0c000000000ULL 194 #define OP_LDF_A_SRC 0x000000000ffULL 195 #define OP_LDF_SC 0x00000000300ULL 196 #define OP_LDF_B_SRC 0x0000003fc00ULL 197 #define OP_LDF_I8 0x00000040000ULL 198 #define OP_LDF_SW 0x00000080000ULL 199 #define OP_LDF_ZF 0x00000100000ULL 200 #define OP_LDF_BMASK 0x0000f000000ULL 201 #define OP_LDF_SHF 0x001f0000000ULL 202 #define OP_LDF_WR_AB 0x20000000000ULL 203 #define OP_LDF_SRC_LMEXTN 0x40000000000ULL 204 #define OP_LDF_DST_LMEXTN 0x80000000000ULL 205 206 #define OP_CMD_A_SRC 0x000000000ffULL 207 #define OP_CMD_CTX 0x00000000300ULL 208 #define OP_CMD_B_SRC 0x0000003fc00ULL 209 #define OP_CMD_TOKEN 0x000000c0000ULL 210 #define OP_CMD_XFER 0x00001f00000ULL 211 #define OP_CMD_CNT 0x0000e000000ULL 212 #define OP_CMD_SIG 0x000f0000000ULL 213 #define OP_CMD_TGT_CMD 0x07f00000000ULL 214 #define OP_CMD_INDIR 0x20000000000ULL 215 #define OP_CMD_MODE 0x1c0000000000ULL 216 217 struct cmd_tgt_act { 218 u8 token; 219 u8 tgt_cmd; 220 }; 221 222 enum cmd_tgt_map { 223 CMD_TGT_READ8, 224 CMD_TGT_WRITE8_SWAP, 225 CMD_TGT_WRITE32_SWAP, 226 CMD_TGT_READ32, 227 CMD_TGT_READ32_LE, 228 CMD_TGT_READ32_SWAP, 229 CMD_TGT_READ_LE, 230 CMD_TGT_READ_SWAP_LE, 231 __CMD_TGT_MAP_SIZE, 232 }; 233 234 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE]; 235 236 enum cmd_mode { 237 CMD_MODE_40b_AB = 0, 238 CMD_MODE_40b_BA = 1, 239 CMD_MODE_32b = 4, 240 }; 241 242 enum cmd_ctx_swap { 243 CMD_CTX_SWAP = 0, 244 CMD_CTX_NO_SWAP = 3, 245 }; 246 247 #define CMD_OVE_LEN BIT(7) 248 #define CMD_OV_LEN GENMASK(12, 8) 249 250 #define OP_LCSR_BASE 0x0fc00000000ULL 251 #define OP_LCSR_A_SRC 0x000000003ffULL 252 #define OP_LCSR_B_SRC 0x000000ffc00ULL 253 #define OP_LCSR_WRITE 0x00000200000ULL 254 #define OP_LCSR_ADDR 0x001ffc00000ULL 255 #define OP_LCSR_SRC_LMEXTN 0x40000000000ULL 256 #define OP_LCSR_DST_LMEXTN 0x80000000000ULL 257 258 enum lcsr_wr_src { 259 LCSR_WR_AREG, 260 LCSR_WR_BREG, 261 LCSR_WR_IMM, 262 }; 263 264 #define OP_CARB_BASE 0x0e000000000ULL 265 #define OP_CARB_OR 0x00000010000ULL 266 267 #define NFP_CSR_CTX_PTR 0x20 268 #define NFP_CSR_ACT_LM_ADDR0 0x64 269 #define NFP_CSR_ACT_LM_ADDR1 0x6c 270 #define NFP_CSR_ACT_LM_ADDR2 0x94 271 #define NFP_CSR_ACT_LM_ADDR3 0x9c 272 273 /* Software register representation, independent of operand type */ 274 #define NN_REG_TYPE GENMASK(31, 24) 275 #define NN_REG_LM_IDX GENMASK(23, 22) 276 #define NN_REG_LM_IDX_HI BIT(23) 277 #define NN_REG_LM_IDX_LO BIT(22) 278 #define NN_REG_LM_MOD GENMASK(21, 20) 279 #define NN_REG_VAL GENMASK(7, 0) 280 281 enum nfp_bpf_reg_type { 282 NN_REG_GPR_A = BIT(0), 283 NN_REG_GPR_B = BIT(1), 284 NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B, 285 NN_REG_NNR = BIT(2), 286 NN_REG_XFER = BIT(3), 287 NN_REG_IMM = BIT(4), 288 NN_REG_NONE = BIT(5), 289 NN_REG_LMEM = BIT(6), 290 }; 291 292 enum nfp_bpf_lm_mode { 293 NN_LM_MOD_NONE = 0, 294 NN_LM_MOD_INC, 295 NN_LM_MOD_DEC, 296 }; 297 298 #define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH) 299 #define reg_a(x) __enc_swreg((x), NN_REG_GPR_A) 300 #define reg_b(x) __enc_swreg((x), NN_REG_GPR_B) 301 #define reg_nnr(x) __enc_swreg((x), NN_REG_NNR) 302 #define reg_xfer(x) __enc_swreg((x), NN_REG_XFER) 303 #define reg_imm(x) __enc_swreg((x), NN_REG_IMM) 304 #define reg_none() __enc_swreg(0, NN_REG_NONE) 305 #define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off)) 306 #define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0) 307 #define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0) 308 #define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off)) 309 310 typedef __u32 __bitwise swreg; 311 312 static inline swreg __enc_swreg(u16 id, u8 type) 313 { 314 return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type)); 315 } 316 317 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off) 318 { 319 WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE)); 320 321 return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) | 322 FIELD_PREP(NN_REG_LM_IDX, id) | 323 FIELD_PREP(NN_REG_LM_MOD, mode) | 324 off); 325 } 326 327 static inline u32 swreg_raw(swreg reg) 328 { 329 return (__force u32)reg; 330 } 331 332 static inline enum nfp_bpf_reg_type swreg_type(swreg reg) 333 { 334 return FIELD_GET(NN_REG_TYPE, swreg_raw(reg)); 335 } 336 337 static inline u16 swreg_value(swreg reg) 338 { 339 return FIELD_GET(NN_REG_VAL, swreg_raw(reg)); 340 } 341 342 static inline bool swreg_lm_idx(swreg reg) 343 { 344 return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg)); 345 } 346 347 static inline bool swreg_lmextn(swreg reg) 348 { 349 return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg)); 350 } 351 352 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg) 353 { 354 return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg)); 355 } 356 357 struct nfp_insn_ur_regs { 358 enum alu_dst_ab dst_ab; 359 u16 dst; 360 u16 areg, breg; 361 bool swap; 362 bool wr_both; 363 bool dst_lmextn; 364 bool src_lmextn; 365 }; 366 367 struct nfp_insn_re_regs { 368 enum alu_dst_ab dst_ab; 369 u8 dst; 370 u8 areg, breg; 371 bool swap; 372 bool wr_both; 373 bool i8; 374 bool dst_lmextn; 375 bool src_lmextn; 376 }; 377 378 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg, 379 struct nfp_insn_ur_regs *reg); 380 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg, 381 struct nfp_insn_re_regs *reg, bool has_imm8); 382 383 #define NFP_USTORE_PREFETCH_WINDOW 8 384 385 int nfp_ustore_check_valid_no_ecc(u64 insn); 386 u64 nfp_ustore_calc_ecc_insn(u64 insn); 387 388 #define NFP_IND_ME_REFL_WR_SIG_INIT 3 389 #define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0) 390 #define NFP_IND_NUM_CONTEXTS 8 391 392 static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset) 393 { 394 return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR; 395 } 396 397 #endif 398