1 /* 2 * Copyright (C) 2016 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef __NFP_ASM_H__ 35 #define __NFP_ASM_H__ 1 36 37 #include <linux/bitfield.h> 38 #include <linux/bug.h> 39 #include <linux/types.h> 40 41 #define REG_NONE 0 42 43 #define RE_REG_NO_DST 0x020 44 #define RE_REG_IMM 0x020 45 #define RE_REG_IMM_encode(x) \ 46 (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1)) 47 #define RE_REG_IMM_MAX 0x07fULL 48 #define RE_REG_LM 0x050 49 #define RE_REG_LM_IDX 0x008 50 #define RE_REG_LM_IDX_MAX 0x7 51 #define RE_REG_XFR 0x080 52 53 #define UR_REG_XFR 0x180 54 #define UR_REG_LM 0x200 55 #define UR_REG_LM_IDX 0x020 56 #define UR_REG_LM_POST_MOD 0x010 57 #define UR_REG_LM_POST_MOD_DEC 0x001 58 #define UR_REG_LM_IDX_MAX 0xf 59 #define UR_REG_NN 0x280 60 #define UR_REG_NO_DST 0x300 61 #define UR_REG_IMM UR_REG_NO_DST 62 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x)) 63 #define UR_REG_IMM_MAX 0x0ffULL 64 65 #define OP_BR_BASE 0x0d800000020ULL 66 #define OP_BR_BASE_MASK 0x0f8000c3ce0ULL 67 #define OP_BR_MASK 0x0000000001fULL 68 #define OP_BR_EV_PIP 0x00000000300ULL 69 #define OP_BR_CSS 0x0000003c000ULL 70 #define OP_BR_DEFBR 0x00000300000ULL 71 #define OP_BR_ADDR_LO 0x007ffc00000ULL 72 #define OP_BR_ADDR_HI 0x10000000000ULL 73 74 #define nfp_is_br(_insn) \ 75 (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE) 76 77 enum br_mask { 78 BR_BEQ = 0x00, 79 BR_BNE = 0x01, 80 BR_BHS = 0x04, 81 BR_BLO = 0x05, 82 BR_BGE = 0x08, 83 BR_UNC = 0x18, 84 }; 85 86 enum br_ev_pip { 87 BR_EV_PIP_UNCOND = 0, 88 BR_EV_PIP_COND = 1, 89 }; 90 91 enum br_ctx_signal_state { 92 BR_CSS_NONE = 2, 93 }; 94 95 #define OP_BBYTE_BASE 0x0c800000000ULL 96 #define OP_BB_A_SRC 0x000000000ffULL 97 #define OP_BB_BYTE 0x00000000300ULL 98 #define OP_BB_B_SRC 0x0000003fc00ULL 99 #define OP_BB_I8 0x00000040000ULL 100 #define OP_BB_EQ 0x00000080000ULL 101 #define OP_BB_DEFBR 0x00000300000ULL 102 #define OP_BB_ADDR_LO 0x007ffc00000ULL 103 #define OP_BB_ADDR_HI 0x10000000000ULL 104 #define OP_BB_SRC_LMEXTN 0x40000000000ULL 105 106 #define OP_BALU_BASE 0x0e800000000ULL 107 #define OP_BA_A_SRC 0x000000003ffULL 108 #define OP_BA_B_SRC 0x000000ffc00ULL 109 #define OP_BA_DEFBR 0x00000300000ULL 110 #define OP_BA_ADDR_HI 0x0007fc00000ULL 111 112 #define OP_IMMED_A_SRC 0x000000003ffULL 113 #define OP_IMMED_B_SRC 0x000000ffc00ULL 114 #define OP_IMMED_IMM 0x0000ff00000ULL 115 #define OP_IMMED_WIDTH 0x00060000000ULL 116 #define OP_IMMED_INV 0x00080000000ULL 117 #define OP_IMMED_SHIFT 0x00600000000ULL 118 #define OP_IMMED_BASE 0x0f000000000ULL 119 #define OP_IMMED_WR_AB 0x20000000000ULL 120 #define OP_IMMED_SRC_LMEXTN 0x40000000000ULL 121 #define OP_IMMED_DST_LMEXTN 0x80000000000ULL 122 123 enum immed_width { 124 IMMED_WIDTH_ALL = 0, 125 IMMED_WIDTH_BYTE = 1, 126 IMMED_WIDTH_WORD = 2, 127 }; 128 129 enum immed_shift { 130 IMMED_SHIFT_0B = 0, 131 IMMED_SHIFT_1B = 1, 132 IMMED_SHIFT_2B = 2, 133 }; 134 135 #define OP_SHF_BASE 0x08000000000ULL 136 #define OP_SHF_A_SRC 0x000000000ffULL 137 #define OP_SHF_SC 0x00000000300ULL 138 #define OP_SHF_B_SRC 0x0000003fc00ULL 139 #define OP_SHF_I8 0x00000040000ULL 140 #define OP_SHF_SW 0x00000080000ULL 141 #define OP_SHF_DST 0x0000ff00000ULL 142 #define OP_SHF_SHIFT 0x001f0000000ULL 143 #define OP_SHF_OP 0x00e00000000ULL 144 #define OP_SHF_DST_AB 0x01000000000ULL 145 #define OP_SHF_WR_AB 0x20000000000ULL 146 #define OP_SHF_SRC_LMEXTN 0x40000000000ULL 147 #define OP_SHF_DST_LMEXTN 0x80000000000ULL 148 149 enum shf_op { 150 SHF_OP_NONE = 0, 151 SHF_OP_AND = 2, 152 SHF_OP_OR = 5, 153 }; 154 155 enum shf_sc { 156 SHF_SC_R_ROT = 0, 157 SHF_SC_NONE = SHF_SC_R_ROT, 158 SHF_SC_R_SHF = 1, 159 SHF_SC_L_SHF = 2, 160 SHF_SC_R_DSHF = 3, 161 }; 162 163 #define OP_ALU_A_SRC 0x000000003ffULL 164 #define OP_ALU_B_SRC 0x000000ffc00ULL 165 #define OP_ALU_DST 0x0003ff00000ULL 166 #define OP_ALU_SW 0x00040000000ULL 167 #define OP_ALU_OP 0x00f80000000ULL 168 #define OP_ALU_DST_AB 0x01000000000ULL 169 #define OP_ALU_BASE 0x0a000000000ULL 170 #define OP_ALU_WR_AB 0x20000000000ULL 171 #define OP_ALU_SRC_LMEXTN 0x40000000000ULL 172 #define OP_ALU_DST_LMEXTN 0x80000000000ULL 173 174 enum alu_op { 175 ALU_OP_NONE = 0x00, 176 ALU_OP_ADD = 0x01, 177 ALU_OP_NOT = 0x04, 178 ALU_OP_AND = 0x08, 179 ALU_OP_SUB_C = 0x0d, 180 ALU_OP_ADD_C = 0x11, 181 ALU_OP_OR = 0x14, 182 ALU_OP_SUB = 0x15, 183 ALU_OP_XOR = 0x18, 184 }; 185 186 enum alu_dst_ab { 187 ALU_DST_A = 0, 188 ALU_DST_B = 1, 189 }; 190 191 #define OP_LDF_BASE 0x0c000000000ULL 192 #define OP_LDF_A_SRC 0x000000000ffULL 193 #define OP_LDF_SC 0x00000000300ULL 194 #define OP_LDF_B_SRC 0x0000003fc00ULL 195 #define OP_LDF_I8 0x00000040000ULL 196 #define OP_LDF_SW 0x00000080000ULL 197 #define OP_LDF_ZF 0x00000100000ULL 198 #define OP_LDF_BMASK 0x0000f000000ULL 199 #define OP_LDF_SHF 0x001f0000000ULL 200 #define OP_LDF_WR_AB 0x20000000000ULL 201 #define OP_LDF_SRC_LMEXTN 0x40000000000ULL 202 #define OP_LDF_DST_LMEXTN 0x80000000000ULL 203 204 #define OP_CMD_A_SRC 0x000000000ffULL 205 #define OP_CMD_CTX 0x00000000300ULL 206 #define OP_CMD_B_SRC 0x0000003fc00ULL 207 #define OP_CMD_TOKEN 0x000000c0000ULL 208 #define OP_CMD_XFER 0x00001f00000ULL 209 #define OP_CMD_CNT 0x0000e000000ULL 210 #define OP_CMD_SIG 0x000f0000000ULL 211 #define OP_CMD_TGT_CMD 0x07f00000000ULL 212 #define OP_CMD_MODE 0x1c0000000000ULL 213 214 struct cmd_tgt_act { 215 u8 token; 216 u8 tgt_cmd; 217 }; 218 219 enum cmd_tgt_map { 220 CMD_TGT_READ8, 221 CMD_TGT_WRITE8_SWAP, 222 CMD_TGT_READ32, 223 CMD_TGT_READ32_LE, 224 CMD_TGT_READ32_SWAP, 225 CMD_TGT_READ_LE, 226 CMD_TGT_READ_SWAP_LE, 227 __CMD_TGT_MAP_SIZE, 228 }; 229 230 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE]; 231 232 enum cmd_mode { 233 CMD_MODE_40b_AB = 0, 234 CMD_MODE_40b_BA = 1, 235 CMD_MODE_32b = 4, 236 }; 237 238 enum cmd_ctx_swap { 239 CMD_CTX_SWAP = 0, 240 CMD_CTX_NO_SWAP = 3, 241 }; 242 243 #define OP_LCSR_BASE 0x0fc00000000ULL 244 #define OP_LCSR_A_SRC 0x000000003ffULL 245 #define OP_LCSR_B_SRC 0x000000ffc00ULL 246 #define OP_LCSR_WRITE 0x00000200000ULL 247 #define OP_LCSR_ADDR 0x001ffc00000ULL 248 #define OP_LCSR_SRC_LMEXTN 0x40000000000ULL 249 #define OP_LCSR_DST_LMEXTN 0x80000000000ULL 250 251 enum lcsr_wr_src { 252 LCSR_WR_AREG, 253 LCSR_WR_BREG, 254 LCSR_WR_IMM, 255 }; 256 257 #define OP_CARB_BASE 0x0e000000000ULL 258 #define OP_CARB_OR 0x00000010000ULL 259 260 #define NFP_CSR_ACT_LM_ADDR0 0x64 261 #define NFP_CSR_ACT_LM_ADDR1 0x6c 262 #define NFP_CSR_ACT_LM_ADDR2 0x94 263 #define NFP_CSR_ACT_LM_ADDR3 0x9c 264 265 /* Software register representation, independent of operand type */ 266 #define NN_REG_TYPE GENMASK(31, 24) 267 #define NN_REG_LM_IDX GENMASK(23, 22) 268 #define NN_REG_LM_IDX_HI BIT(23) 269 #define NN_REG_LM_IDX_LO BIT(22) 270 #define NN_REG_LM_MOD GENMASK(21, 20) 271 #define NN_REG_VAL GENMASK(7, 0) 272 273 enum nfp_bpf_reg_type { 274 NN_REG_GPR_A = BIT(0), 275 NN_REG_GPR_B = BIT(1), 276 NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B, 277 NN_REG_NNR = BIT(2), 278 NN_REG_XFER = BIT(3), 279 NN_REG_IMM = BIT(4), 280 NN_REG_NONE = BIT(5), 281 NN_REG_LMEM = BIT(6), 282 }; 283 284 enum nfp_bpf_lm_mode { 285 NN_LM_MOD_NONE = 0, 286 NN_LM_MOD_INC, 287 NN_LM_MOD_DEC, 288 }; 289 290 #define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH) 291 #define reg_a(x) __enc_swreg((x), NN_REG_GPR_A) 292 #define reg_b(x) __enc_swreg((x), NN_REG_GPR_B) 293 #define reg_nnr(x) __enc_swreg((x), NN_REG_NNR) 294 #define reg_xfer(x) __enc_swreg((x), NN_REG_XFER) 295 #define reg_imm(x) __enc_swreg((x), NN_REG_IMM) 296 #define reg_none() __enc_swreg(0, NN_REG_NONE) 297 #define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off)) 298 #define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0) 299 #define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0) 300 #define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off)) 301 302 typedef __u32 __bitwise swreg; 303 304 static inline swreg __enc_swreg(u16 id, u8 type) 305 { 306 return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type)); 307 } 308 309 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off) 310 { 311 WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE)); 312 313 return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) | 314 FIELD_PREP(NN_REG_LM_IDX, id) | 315 FIELD_PREP(NN_REG_LM_MOD, mode) | 316 off); 317 } 318 319 static inline u32 swreg_raw(swreg reg) 320 { 321 return (__force u32)reg; 322 } 323 324 static inline enum nfp_bpf_reg_type swreg_type(swreg reg) 325 { 326 return FIELD_GET(NN_REG_TYPE, swreg_raw(reg)); 327 } 328 329 static inline u16 swreg_value(swreg reg) 330 { 331 return FIELD_GET(NN_REG_VAL, swreg_raw(reg)); 332 } 333 334 static inline bool swreg_lm_idx(swreg reg) 335 { 336 return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg)); 337 } 338 339 static inline bool swreg_lmextn(swreg reg) 340 { 341 return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg)); 342 } 343 344 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg) 345 { 346 return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg)); 347 } 348 349 struct nfp_insn_ur_regs { 350 enum alu_dst_ab dst_ab; 351 u16 dst; 352 u16 areg, breg; 353 bool swap; 354 bool wr_both; 355 bool dst_lmextn; 356 bool src_lmextn; 357 }; 358 359 struct nfp_insn_re_regs { 360 enum alu_dst_ab dst_ab; 361 u8 dst; 362 u8 areg, breg; 363 bool swap; 364 bool wr_both; 365 bool i8; 366 bool dst_lmextn; 367 bool src_lmextn; 368 }; 369 370 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg, 371 struct nfp_insn_ur_regs *reg); 372 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg, 373 struct nfp_insn_re_regs *reg, bool has_imm8); 374 375 #define NFP_USTORE_PREFETCH_WINDOW 8 376 377 int nfp_ustore_check_valid_no_ecc(u64 insn); 378 u64 nfp_ustore_calc_ecc_insn(u64 insn); 379 380 #endif 381