1 /* 2 * Copyright (C) 2016-2017 Netronome Systems, Inc. 3 * 4 * This software is dual licensed under the GNU General License Version 2, 5 * June 1991 as shown in the file COPYING in the top-level directory of this 6 * source tree or the BSD 2-Clause License provided below. You have the 7 * option to license this software under the complete terms of either license. 8 * 9 * The BSD 2-Clause License: 10 * 11 * Redistribution and use in source and binary forms, with or 12 * without modification, are permitted provided that the following 13 * conditions are met: 14 * 15 * 1. Redistributions of source code must retain the above 16 * copyright notice, this list of conditions and the following 17 * disclaimer. 18 * 19 * 2. Redistributions in binary form must reproduce the above 20 * copyright notice, this list of conditions and the following 21 * disclaimer in the documentation and/or other materials 22 * provided with the distribution. 23 * 24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 31 * SOFTWARE. 32 */ 33 34 #ifndef __NFP_ASM_H__ 35 #define __NFP_ASM_H__ 1 36 37 #include <linux/bitfield.h> 38 #include <linux/bug.h> 39 #include <linux/types.h> 40 41 #define REG_NONE 0 42 #define REG_WIDTH 4 43 44 #define RE_REG_NO_DST 0x020 45 #define RE_REG_IMM 0x020 46 #define RE_REG_IMM_encode(x) \ 47 (RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1)) 48 #define RE_REG_IMM_MAX 0x07fULL 49 #define RE_REG_LM 0x050 50 #define RE_REG_LM_IDX 0x008 51 #define RE_REG_LM_IDX_MAX 0x7 52 #define RE_REG_XFR 0x080 53 54 #define UR_REG_XFR 0x180 55 #define UR_REG_LM 0x200 56 #define UR_REG_LM_IDX 0x020 57 #define UR_REG_LM_POST_MOD 0x010 58 #define UR_REG_LM_POST_MOD_DEC 0x001 59 #define UR_REG_LM_IDX_MAX 0xf 60 #define UR_REG_NN 0x280 61 #define UR_REG_NO_DST 0x300 62 #define UR_REG_IMM UR_REG_NO_DST 63 #define UR_REG_IMM_encode(x) (UR_REG_IMM | (x)) 64 #define UR_REG_IMM_MAX 0x0ffULL 65 66 #define OP_BR_BASE 0x0d800000020ULL 67 #define OP_BR_BASE_MASK 0x0f8000c3ce0ULL 68 #define OP_BR_MASK 0x0000000001fULL 69 #define OP_BR_EV_PIP 0x00000000300ULL 70 #define OP_BR_CSS 0x0000003c000ULL 71 #define OP_BR_DEFBR 0x00000300000ULL 72 #define OP_BR_ADDR_LO 0x007ffc00000ULL 73 #define OP_BR_ADDR_HI 0x10000000000ULL 74 75 #define nfp_is_br(_insn) \ 76 (((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE) 77 78 enum br_mask { 79 BR_BEQ = 0x00, 80 BR_BNE = 0x01, 81 BR_BMI = 0x02, 82 BR_BHS = 0x04, 83 BR_BLO = 0x05, 84 BR_BGE = 0x08, 85 BR_BLT = 0x09, 86 BR_UNC = 0x18, 87 }; 88 89 enum br_ev_pip { 90 BR_EV_PIP_UNCOND = 0, 91 BR_EV_PIP_COND = 1, 92 }; 93 94 enum br_ctx_signal_state { 95 BR_CSS_NONE = 2, 96 }; 97 98 u16 br_get_offset(u64 instr); 99 void br_set_offset(u64 *instr, u16 offset); 100 void br_add_offset(u64 *instr, u16 offset); 101 102 #define OP_BBYTE_BASE 0x0c800000000ULL 103 #define OP_BB_A_SRC 0x000000000ffULL 104 #define OP_BB_BYTE 0x00000000300ULL 105 #define OP_BB_B_SRC 0x0000003fc00ULL 106 #define OP_BB_I8 0x00000040000ULL 107 #define OP_BB_EQ 0x00000080000ULL 108 #define OP_BB_DEFBR 0x00000300000ULL 109 #define OP_BB_ADDR_LO 0x007ffc00000ULL 110 #define OP_BB_ADDR_HI 0x10000000000ULL 111 #define OP_BB_SRC_LMEXTN 0x40000000000ULL 112 113 #define OP_BALU_BASE 0x0e800000000ULL 114 #define OP_BA_A_SRC 0x000000003ffULL 115 #define OP_BA_B_SRC 0x000000ffc00ULL 116 #define OP_BA_DEFBR 0x00000300000ULL 117 #define OP_BA_ADDR_HI 0x0007fc00000ULL 118 119 #define OP_IMMED_A_SRC 0x000000003ffULL 120 #define OP_IMMED_B_SRC 0x000000ffc00ULL 121 #define OP_IMMED_IMM 0x0000ff00000ULL 122 #define OP_IMMED_WIDTH 0x00060000000ULL 123 #define OP_IMMED_INV 0x00080000000ULL 124 #define OP_IMMED_SHIFT 0x00600000000ULL 125 #define OP_IMMED_BASE 0x0f000000000ULL 126 #define OP_IMMED_WR_AB 0x20000000000ULL 127 #define OP_IMMED_SRC_LMEXTN 0x40000000000ULL 128 #define OP_IMMED_DST_LMEXTN 0x80000000000ULL 129 130 enum immed_width { 131 IMMED_WIDTH_ALL = 0, 132 IMMED_WIDTH_BYTE = 1, 133 IMMED_WIDTH_WORD = 2, 134 }; 135 136 enum immed_shift { 137 IMMED_SHIFT_0B = 0, 138 IMMED_SHIFT_1B = 1, 139 IMMED_SHIFT_2B = 2, 140 }; 141 142 u16 immed_get_value(u64 instr); 143 void immed_set_value(u64 *instr, u16 immed); 144 void immed_add_value(u64 *instr, u16 offset); 145 146 #define OP_SHF_BASE 0x08000000000ULL 147 #define OP_SHF_A_SRC 0x000000000ffULL 148 #define OP_SHF_SC 0x00000000300ULL 149 #define OP_SHF_B_SRC 0x0000003fc00ULL 150 #define OP_SHF_I8 0x00000040000ULL 151 #define OP_SHF_SW 0x00000080000ULL 152 #define OP_SHF_DST 0x0000ff00000ULL 153 #define OP_SHF_SHIFT 0x001f0000000ULL 154 #define OP_SHF_OP 0x00e00000000ULL 155 #define OP_SHF_DST_AB 0x01000000000ULL 156 #define OP_SHF_WR_AB 0x20000000000ULL 157 #define OP_SHF_SRC_LMEXTN 0x40000000000ULL 158 #define OP_SHF_DST_LMEXTN 0x80000000000ULL 159 160 enum shf_op { 161 SHF_OP_NONE = 0, 162 SHF_OP_AND = 2, 163 SHF_OP_OR = 5, 164 }; 165 166 enum shf_sc { 167 SHF_SC_R_ROT = 0, 168 SHF_SC_NONE = SHF_SC_R_ROT, 169 SHF_SC_R_SHF = 1, 170 SHF_SC_L_SHF = 2, 171 SHF_SC_R_DSHF = 3, 172 }; 173 174 #define OP_ALU_A_SRC 0x000000003ffULL 175 #define OP_ALU_B_SRC 0x000000ffc00ULL 176 #define OP_ALU_DST 0x0003ff00000ULL 177 #define OP_ALU_SW 0x00040000000ULL 178 #define OP_ALU_OP 0x00f80000000ULL 179 #define OP_ALU_DST_AB 0x01000000000ULL 180 #define OP_ALU_BASE 0x0a000000000ULL 181 #define OP_ALU_WR_AB 0x20000000000ULL 182 #define OP_ALU_SRC_LMEXTN 0x40000000000ULL 183 #define OP_ALU_DST_LMEXTN 0x80000000000ULL 184 185 enum alu_op { 186 ALU_OP_NONE = 0x00, 187 ALU_OP_ADD = 0x01, 188 ALU_OP_NOT = 0x04, 189 ALU_OP_ADD_2B = 0x05, 190 ALU_OP_AND = 0x08, 191 ALU_OP_SUB_C = 0x0d, 192 ALU_OP_ADD_C = 0x11, 193 ALU_OP_OR = 0x14, 194 ALU_OP_SUB = 0x15, 195 ALU_OP_XOR = 0x18, 196 }; 197 198 enum alu_dst_ab { 199 ALU_DST_A = 0, 200 ALU_DST_B = 1, 201 }; 202 203 #define OP_LDF_BASE 0x0c000000000ULL 204 #define OP_LDF_A_SRC 0x000000000ffULL 205 #define OP_LDF_SC 0x00000000300ULL 206 #define OP_LDF_B_SRC 0x0000003fc00ULL 207 #define OP_LDF_I8 0x00000040000ULL 208 #define OP_LDF_SW 0x00000080000ULL 209 #define OP_LDF_ZF 0x00000100000ULL 210 #define OP_LDF_BMASK 0x0000f000000ULL 211 #define OP_LDF_SHF 0x001f0000000ULL 212 #define OP_LDF_WR_AB 0x20000000000ULL 213 #define OP_LDF_SRC_LMEXTN 0x40000000000ULL 214 #define OP_LDF_DST_LMEXTN 0x80000000000ULL 215 216 #define OP_CMD_A_SRC 0x000000000ffULL 217 #define OP_CMD_CTX 0x00000000300ULL 218 #define OP_CMD_B_SRC 0x0000003fc00ULL 219 #define OP_CMD_TOKEN 0x000000c0000ULL 220 #define OP_CMD_XFER 0x00001f00000ULL 221 #define OP_CMD_CNT 0x0000e000000ULL 222 #define OP_CMD_SIG 0x000f0000000ULL 223 #define OP_CMD_TGT_CMD 0x07f00000000ULL 224 #define OP_CMD_INDIR 0x20000000000ULL 225 #define OP_CMD_MODE 0x1c0000000000ULL 226 227 struct cmd_tgt_act { 228 u8 token; 229 u8 tgt_cmd; 230 }; 231 232 enum cmd_tgt_map { 233 CMD_TGT_READ8, 234 CMD_TGT_WRITE8_SWAP, 235 CMD_TGT_WRITE32_SWAP, 236 CMD_TGT_READ32, 237 CMD_TGT_READ32_LE, 238 CMD_TGT_READ32_SWAP, 239 CMD_TGT_READ_LE, 240 CMD_TGT_READ_SWAP_LE, 241 CMD_TGT_ADD, 242 CMD_TGT_ADD_IMM, 243 __CMD_TGT_MAP_SIZE, 244 }; 245 246 extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE]; 247 248 enum cmd_mode { 249 CMD_MODE_40b_AB = 0, 250 CMD_MODE_40b_BA = 1, 251 CMD_MODE_32b = 4, 252 }; 253 254 enum cmd_ctx_swap { 255 CMD_CTX_SWAP = 0, 256 CMD_CTX_SWAP_DEFER1 = 1, 257 CMD_CTX_SWAP_DEFER2 = 2, 258 CMD_CTX_NO_SWAP = 3, 259 }; 260 261 #define CMD_OVE_DATA GENMASK(5, 3) 262 #define CMD_OVE_LEN BIT(7) 263 #define CMD_OV_LEN GENMASK(12, 8) 264 265 #define OP_LCSR_BASE 0x0fc00000000ULL 266 #define OP_LCSR_A_SRC 0x000000003ffULL 267 #define OP_LCSR_B_SRC 0x000000ffc00ULL 268 #define OP_LCSR_WRITE 0x00000200000ULL 269 #define OP_LCSR_ADDR 0x001ffc00000ULL 270 #define OP_LCSR_SRC_LMEXTN 0x40000000000ULL 271 #define OP_LCSR_DST_LMEXTN 0x80000000000ULL 272 273 enum lcsr_wr_src { 274 LCSR_WR_AREG, 275 LCSR_WR_BREG, 276 LCSR_WR_IMM, 277 }; 278 279 #define OP_CARB_BASE 0x0e000000000ULL 280 #define OP_CARB_OR 0x00000010000ULL 281 282 #define NFP_CSR_CTX_PTR 0x20 283 #define NFP_CSR_ACT_LM_ADDR0 0x64 284 #define NFP_CSR_ACT_LM_ADDR1 0x6c 285 #define NFP_CSR_ACT_LM_ADDR2 0x94 286 #define NFP_CSR_ACT_LM_ADDR3 0x9c 287 #define NFP_CSR_PSEUDO_RND_NUM 0x148 288 289 /* Software register representation, independent of operand type */ 290 #define NN_REG_TYPE GENMASK(31, 24) 291 #define NN_REG_LM_IDX GENMASK(23, 22) 292 #define NN_REG_LM_IDX_HI BIT(23) 293 #define NN_REG_LM_IDX_LO BIT(22) 294 #define NN_REG_LM_MOD GENMASK(21, 20) 295 #define NN_REG_VAL GENMASK(7, 0) 296 297 enum nfp_bpf_reg_type { 298 NN_REG_GPR_A = BIT(0), 299 NN_REG_GPR_B = BIT(1), 300 NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B, 301 NN_REG_NNR = BIT(2), 302 NN_REG_XFER = BIT(3), 303 NN_REG_IMM = BIT(4), 304 NN_REG_NONE = BIT(5), 305 NN_REG_LMEM = BIT(6), 306 }; 307 308 enum nfp_bpf_lm_mode { 309 NN_LM_MOD_NONE = 0, 310 NN_LM_MOD_INC, 311 NN_LM_MOD_DEC, 312 }; 313 314 #define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH) 315 #define reg_a(x) __enc_swreg((x), NN_REG_GPR_A) 316 #define reg_b(x) __enc_swreg((x), NN_REG_GPR_B) 317 #define reg_nnr(x) __enc_swreg((x), NN_REG_NNR) 318 #define reg_xfer(x) __enc_swreg((x), NN_REG_XFER) 319 #define reg_imm(x) __enc_swreg((x), NN_REG_IMM) 320 #define reg_none() __enc_swreg(0, NN_REG_NONE) 321 #define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off)) 322 #define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0) 323 #define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0) 324 #define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off)) 325 326 typedef __u32 __bitwise swreg; 327 328 static inline swreg __enc_swreg(u16 id, u8 type) 329 { 330 return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type)); 331 } 332 333 static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off) 334 { 335 WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE)); 336 337 return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) | 338 FIELD_PREP(NN_REG_LM_IDX, id) | 339 FIELD_PREP(NN_REG_LM_MOD, mode) | 340 off); 341 } 342 343 static inline u32 swreg_raw(swreg reg) 344 { 345 return (__force u32)reg; 346 } 347 348 static inline enum nfp_bpf_reg_type swreg_type(swreg reg) 349 { 350 return FIELD_GET(NN_REG_TYPE, swreg_raw(reg)); 351 } 352 353 static inline u16 swreg_value(swreg reg) 354 { 355 return FIELD_GET(NN_REG_VAL, swreg_raw(reg)); 356 } 357 358 static inline bool swreg_lm_idx(swreg reg) 359 { 360 return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg)); 361 } 362 363 static inline bool swreg_lmextn(swreg reg) 364 { 365 return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg)); 366 } 367 368 static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg) 369 { 370 return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg)); 371 } 372 373 struct nfp_insn_ur_regs { 374 enum alu_dst_ab dst_ab; 375 u16 dst; 376 u16 areg, breg; 377 bool swap; 378 bool wr_both; 379 bool dst_lmextn; 380 bool src_lmextn; 381 }; 382 383 struct nfp_insn_re_regs { 384 enum alu_dst_ab dst_ab; 385 u8 dst; 386 u8 areg, breg; 387 bool swap; 388 bool wr_both; 389 bool i8; 390 bool dst_lmextn; 391 bool src_lmextn; 392 }; 393 394 int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg, 395 struct nfp_insn_ur_regs *reg); 396 int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg, 397 struct nfp_insn_re_regs *reg, bool has_imm8); 398 399 #define NFP_USTORE_PREFETCH_WINDOW 8 400 401 int nfp_ustore_check_valid_no_ecc(u64 insn); 402 u64 nfp_ustore_calc_ecc_insn(u64 insn); 403 404 #define NFP_IND_ME_REFL_WR_SIG_INIT 3 405 #define NFP_IND_ME_CTX_PTR_BASE_MASK GENMASK(9, 0) 406 #define NFP_IND_NUM_CONTEXTS 8 407 408 static inline u32 nfp_get_ind_csr_ctx_ptr_offs(u32 read_offset) 409 { 410 return (read_offset & ~NFP_IND_ME_CTX_PTR_BASE_MASK) | NFP_CSR_CTX_PTR; 411 } 412 413 #endif 414