1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2 /* Copyright (C) 2016-2018 Netronome Systems, Inc. */ 3 4 #define pr_fmt(fmt) "NFP net bpf: " fmt 5 6 #include <linux/bug.h> 7 #include <linux/bpf.h> 8 #include <linux/filter.h> 9 #include <linux/kernel.h> 10 #include <linux/pkt_cls.h> 11 #include <linux/reciprocal_div.h> 12 #include <linux/unistd.h> 13 14 #include "main.h" 15 #include "../nfp_asm.h" 16 #include "../nfp_net_ctrl.h" 17 18 /* --- NFP prog --- */ 19 /* Foreach "multiple" entries macros provide pos and next<n> pointers. 20 * It's safe to modify the next pointers (but not pos). 21 */ 22 #define nfp_for_each_insn_walk2(nfp_prog, pos, next) \ 23 for (pos = list_first_entry(&(nfp_prog)->insns, typeof(*pos), l), \ 24 next = list_next_entry(pos, l); \ 25 &(nfp_prog)->insns != &pos->l && \ 26 &(nfp_prog)->insns != &next->l; \ 27 pos = nfp_meta_next(pos), \ 28 next = nfp_meta_next(pos)) 29 30 #define nfp_for_each_insn_walk3(nfp_prog, pos, next, next2) \ 31 for (pos = list_first_entry(&(nfp_prog)->insns, typeof(*pos), l), \ 32 next = list_next_entry(pos, l), \ 33 next2 = list_next_entry(next, l); \ 34 &(nfp_prog)->insns != &pos->l && \ 35 &(nfp_prog)->insns != &next->l && \ 36 &(nfp_prog)->insns != &next2->l; \ 37 pos = nfp_meta_next(pos), \ 38 next = nfp_meta_next(pos), \ 39 next2 = nfp_meta_next(next)) 40 41 static bool 42 nfp_meta_has_prev(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 43 { 44 return meta->l.prev != &nfp_prog->insns; 45 } 46 47 static void nfp_prog_push(struct nfp_prog *nfp_prog, u64 insn) 48 { 49 if (nfp_prog->__prog_alloc_len / sizeof(u64) == nfp_prog->prog_len) { 50 pr_warn("instruction limit reached (%u NFP instructions)\n", 51 nfp_prog->prog_len); 52 nfp_prog->error = -ENOSPC; 53 return; 54 } 55 56 nfp_prog->prog[nfp_prog->prog_len] = insn; 57 nfp_prog->prog_len++; 58 } 59 60 static unsigned int nfp_prog_current_offset(struct nfp_prog *nfp_prog) 61 { 62 return nfp_prog->prog_len; 63 } 64 65 static bool 66 nfp_prog_confirm_current_offset(struct nfp_prog *nfp_prog, unsigned int off) 67 { 68 /* If there is a recorded error we may have dropped instructions; 69 * that doesn't have to be due to translator bug, and the translation 70 * will fail anyway, so just return OK. 71 */ 72 if (nfp_prog->error) 73 return true; 74 return !WARN_ON_ONCE(nfp_prog_current_offset(nfp_prog) != off); 75 } 76 77 /* --- Emitters --- */ 78 static void 79 __emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op, 80 u8 mode, u8 xfer, u8 areg, u8 breg, u8 size, enum cmd_ctx_swap ctx, 81 bool indir) 82 { 83 u64 insn; 84 85 insn = FIELD_PREP(OP_CMD_A_SRC, areg) | 86 FIELD_PREP(OP_CMD_CTX, ctx) | 87 FIELD_PREP(OP_CMD_B_SRC, breg) | 88 FIELD_PREP(OP_CMD_TOKEN, cmd_tgt_act[op].token) | 89 FIELD_PREP(OP_CMD_XFER, xfer) | 90 FIELD_PREP(OP_CMD_CNT, size) | 91 FIELD_PREP(OP_CMD_SIG, ctx != CMD_CTX_NO_SWAP) | 92 FIELD_PREP(OP_CMD_TGT_CMD, cmd_tgt_act[op].tgt_cmd) | 93 FIELD_PREP(OP_CMD_INDIR, indir) | 94 FIELD_PREP(OP_CMD_MODE, mode); 95 96 nfp_prog_push(nfp_prog, insn); 97 } 98 99 static void 100 emit_cmd_any(struct nfp_prog *nfp_prog, enum cmd_tgt_map op, u8 mode, u8 xfer, 101 swreg lreg, swreg rreg, u8 size, enum cmd_ctx_swap ctx, bool indir) 102 { 103 struct nfp_insn_re_regs reg; 104 int err; 105 106 err = swreg_to_restricted(reg_none(), lreg, rreg, ®, false); 107 if (err) { 108 nfp_prog->error = err; 109 return; 110 } 111 if (reg.swap) { 112 pr_err("cmd can't swap arguments\n"); 113 nfp_prog->error = -EFAULT; 114 return; 115 } 116 if (reg.dst_lmextn || reg.src_lmextn) { 117 pr_err("cmd can't use LMextn\n"); 118 nfp_prog->error = -EFAULT; 119 return; 120 } 121 122 __emit_cmd(nfp_prog, op, mode, xfer, reg.areg, reg.breg, size, ctx, 123 indir); 124 } 125 126 static void 127 emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op, u8 mode, u8 xfer, 128 swreg lreg, swreg rreg, u8 size, enum cmd_ctx_swap ctx) 129 { 130 emit_cmd_any(nfp_prog, op, mode, xfer, lreg, rreg, size, ctx, false); 131 } 132 133 static void 134 emit_cmd_indir(struct nfp_prog *nfp_prog, enum cmd_tgt_map op, u8 mode, u8 xfer, 135 swreg lreg, swreg rreg, u8 size, enum cmd_ctx_swap ctx) 136 { 137 emit_cmd_any(nfp_prog, op, mode, xfer, lreg, rreg, size, ctx, true); 138 } 139 140 static void 141 __emit_br(struct nfp_prog *nfp_prog, enum br_mask mask, enum br_ev_pip ev_pip, 142 enum br_ctx_signal_state css, u16 addr, u8 defer) 143 { 144 u16 addr_lo, addr_hi; 145 u64 insn; 146 147 addr_lo = addr & (OP_BR_ADDR_LO >> __bf_shf(OP_BR_ADDR_LO)); 148 addr_hi = addr != addr_lo; 149 150 insn = OP_BR_BASE | 151 FIELD_PREP(OP_BR_MASK, mask) | 152 FIELD_PREP(OP_BR_EV_PIP, ev_pip) | 153 FIELD_PREP(OP_BR_CSS, css) | 154 FIELD_PREP(OP_BR_DEFBR, defer) | 155 FIELD_PREP(OP_BR_ADDR_LO, addr_lo) | 156 FIELD_PREP(OP_BR_ADDR_HI, addr_hi); 157 158 nfp_prog_push(nfp_prog, insn); 159 } 160 161 static void 162 emit_br_relo(struct nfp_prog *nfp_prog, enum br_mask mask, u16 addr, u8 defer, 163 enum nfp_relo_type relo) 164 { 165 if (mask == BR_UNC && defer > 2) { 166 pr_err("BUG: branch defer out of bounds %d\n", defer); 167 nfp_prog->error = -EFAULT; 168 return; 169 } 170 171 __emit_br(nfp_prog, mask, 172 mask != BR_UNC ? BR_EV_PIP_COND : BR_EV_PIP_UNCOND, 173 BR_CSS_NONE, addr, defer); 174 175 nfp_prog->prog[nfp_prog->prog_len - 1] |= 176 FIELD_PREP(OP_RELO_TYPE, relo); 177 } 178 179 static void 180 emit_br(struct nfp_prog *nfp_prog, enum br_mask mask, u16 addr, u8 defer) 181 { 182 emit_br_relo(nfp_prog, mask, addr, defer, RELO_BR_REL); 183 } 184 185 static void 186 __emit_br_bit(struct nfp_prog *nfp_prog, u16 areg, u16 breg, u16 addr, u8 defer, 187 bool set, bool src_lmextn) 188 { 189 u16 addr_lo, addr_hi; 190 u64 insn; 191 192 addr_lo = addr & (OP_BR_BIT_ADDR_LO >> __bf_shf(OP_BR_BIT_ADDR_LO)); 193 addr_hi = addr != addr_lo; 194 195 insn = OP_BR_BIT_BASE | 196 FIELD_PREP(OP_BR_BIT_A_SRC, areg) | 197 FIELD_PREP(OP_BR_BIT_B_SRC, breg) | 198 FIELD_PREP(OP_BR_BIT_BV, set) | 199 FIELD_PREP(OP_BR_BIT_DEFBR, defer) | 200 FIELD_PREP(OP_BR_BIT_ADDR_LO, addr_lo) | 201 FIELD_PREP(OP_BR_BIT_ADDR_HI, addr_hi) | 202 FIELD_PREP(OP_BR_BIT_SRC_LMEXTN, src_lmextn); 203 204 nfp_prog_push(nfp_prog, insn); 205 } 206 207 static void 208 emit_br_bit_relo(struct nfp_prog *nfp_prog, swreg src, u8 bit, u16 addr, 209 u8 defer, bool set, enum nfp_relo_type relo) 210 { 211 struct nfp_insn_re_regs reg; 212 int err; 213 214 /* NOTE: The bit to test is specified as an rotation amount, such that 215 * the bit to test will be placed on the MSB of the result when 216 * doing a rotate right. For bit X, we need right rotate X + 1. 217 */ 218 bit += 1; 219 220 err = swreg_to_restricted(reg_none(), src, reg_imm(bit), ®, false); 221 if (err) { 222 nfp_prog->error = err; 223 return; 224 } 225 226 __emit_br_bit(nfp_prog, reg.areg, reg.breg, addr, defer, set, 227 reg.src_lmextn); 228 229 nfp_prog->prog[nfp_prog->prog_len - 1] |= 230 FIELD_PREP(OP_RELO_TYPE, relo); 231 } 232 233 static void 234 emit_br_bset(struct nfp_prog *nfp_prog, swreg src, u8 bit, u16 addr, u8 defer) 235 { 236 emit_br_bit_relo(nfp_prog, src, bit, addr, defer, true, RELO_BR_REL); 237 } 238 239 static void 240 __emit_br_alu(struct nfp_prog *nfp_prog, u16 areg, u16 breg, u16 imm_hi, 241 u8 defer, bool dst_lmextn, bool src_lmextn) 242 { 243 u64 insn; 244 245 insn = OP_BR_ALU_BASE | 246 FIELD_PREP(OP_BR_ALU_A_SRC, areg) | 247 FIELD_PREP(OP_BR_ALU_B_SRC, breg) | 248 FIELD_PREP(OP_BR_ALU_DEFBR, defer) | 249 FIELD_PREP(OP_BR_ALU_IMM_HI, imm_hi) | 250 FIELD_PREP(OP_BR_ALU_SRC_LMEXTN, src_lmextn) | 251 FIELD_PREP(OP_BR_ALU_DST_LMEXTN, dst_lmextn); 252 253 nfp_prog_push(nfp_prog, insn); 254 } 255 256 static void emit_rtn(struct nfp_prog *nfp_prog, swreg base, u8 defer) 257 { 258 struct nfp_insn_ur_regs reg; 259 int err; 260 261 err = swreg_to_unrestricted(reg_none(), base, reg_imm(0), ®); 262 if (err) { 263 nfp_prog->error = err; 264 return; 265 } 266 267 __emit_br_alu(nfp_prog, reg.areg, reg.breg, 0, defer, reg.dst_lmextn, 268 reg.src_lmextn); 269 } 270 271 static void 272 __emit_immed(struct nfp_prog *nfp_prog, u16 areg, u16 breg, u16 imm_hi, 273 enum immed_width width, bool invert, 274 enum immed_shift shift, bool wr_both, 275 bool dst_lmextn, bool src_lmextn) 276 { 277 u64 insn; 278 279 insn = OP_IMMED_BASE | 280 FIELD_PREP(OP_IMMED_A_SRC, areg) | 281 FIELD_PREP(OP_IMMED_B_SRC, breg) | 282 FIELD_PREP(OP_IMMED_IMM, imm_hi) | 283 FIELD_PREP(OP_IMMED_WIDTH, width) | 284 FIELD_PREP(OP_IMMED_INV, invert) | 285 FIELD_PREP(OP_IMMED_SHIFT, shift) | 286 FIELD_PREP(OP_IMMED_WR_AB, wr_both) | 287 FIELD_PREP(OP_IMMED_SRC_LMEXTN, src_lmextn) | 288 FIELD_PREP(OP_IMMED_DST_LMEXTN, dst_lmextn); 289 290 nfp_prog_push(nfp_prog, insn); 291 } 292 293 static void 294 emit_immed(struct nfp_prog *nfp_prog, swreg dst, u16 imm, 295 enum immed_width width, bool invert, enum immed_shift shift) 296 { 297 struct nfp_insn_ur_regs reg; 298 int err; 299 300 if (swreg_type(dst) == NN_REG_IMM) { 301 nfp_prog->error = -EFAULT; 302 return; 303 } 304 305 err = swreg_to_unrestricted(dst, dst, reg_imm(imm & 0xff), ®); 306 if (err) { 307 nfp_prog->error = err; 308 return; 309 } 310 311 /* Use reg.dst when destination is No-Dest. */ 312 __emit_immed(nfp_prog, 313 swreg_type(dst) == NN_REG_NONE ? reg.dst : reg.areg, 314 reg.breg, imm >> 8, width, invert, shift, 315 reg.wr_both, reg.dst_lmextn, reg.src_lmextn); 316 } 317 318 static void 319 __emit_shf(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab, 320 enum shf_sc sc, u8 shift, 321 u16 areg, enum shf_op op, u16 breg, bool i8, bool sw, bool wr_both, 322 bool dst_lmextn, bool src_lmextn) 323 { 324 u64 insn; 325 326 if (!FIELD_FIT(OP_SHF_SHIFT, shift)) { 327 nfp_prog->error = -EFAULT; 328 return; 329 } 330 331 if (sc == SHF_SC_L_SHF) 332 shift = 32 - shift; 333 334 insn = OP_SHF_BASE | 335 FIELD_PREP(OP_SHF_A_SRC, areg) | 336 FIELD_PREP(OP_SHF_SC, sc) | 337 FIELD_PREP(OP_SHF_B_SRC, breg) | 338 FIELD_PREP(OP_SHF_I8, i8) | 339 FIELD_PREP(OP_SHF_SW, sw) | 340 FIELD_PREP(OP_SHF_DST, dst) | 341 FIELD_PREP(OP_SHF_SHIFT, shift) | 342 FIELD_PREP(OP_SHF_OP, op) | 343 FIELD_PREP(OP_SHF_DST_AB, dst_ab) | 344 FIELD_PREP(OP_SHF_WR_AB, wr_both) | 345 FIELD_PREP(OP_SHF_SRC_LMEXTN, src_lmextn) | 346 FIELD_PREP(OP_SHF_DST_LMEXTN, dst_lmextn); 347 348 nfp_prog_push(nfp_prog, insn); 349 } 350 351 static void 352 emit_shf(struct nfp_prog *nfp_prog, swreg dst, 353 swreg lreg, enum shf_op op, swreg rreg, enum shf_sc sc, u8 shift) 354 { 355 struct nfp_insn_re_regs reg; 356 int err; 357 358 err = swreg_to_restricted(dst, lreg, rreg, ®, true); 359 if (err) { 360 nfp_prog->error = err; 361 return; 362 } 363 364 __emit_shf(nfp_prog, reg.dst, reg.dst_ab, sc, shift, 365 reg.areg, op, reg.breg, reg.i8, reg.swap, reg.wr_both, 366 reg.dst_lmextn, reg.src_lmextn); 367 } 368 369 static void 370 emit_shf_indir(struct nfp_prog *nfp_prog, swreg dst, 371 swreg lreg, enum shf_op op, swreg rreg, enum shf_sc sc) 372 { 373 if (sc == SHF_SC_R_ROT) { 374 pr_err("indirect shift is not allowed on rotation\n"); 375 nfp_prog->error = -EFAULT; 376 return; 377 } 378 379 emit_shf(nfp_prog, dst, lreg, op, rreg, sc, 0); 380 } 381 382 static void 383 __emit_alu(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab, 384 u16 areg, enum alu_op op, u16 breg, bool swap, bool wr_both, 385 bool dst_lmextn, bool src_lmextn) 386 { 387 u64 insn; 388 389 insn = OP_ALU_BASE | 390 FIELD_PREP(OP_ALU_A_SRC, areg) | 391 FIELD_PREP(OP_ALU_B_SRC, breg) | 392 FIELD_PREP(OP_ALU_DST, dst) | 393 FIELD_PREP(OP_ALU_SW, swap) | 394 FIELD_PREP(OP_ALU_OP, op) | 395 FIELD_PREP(OP_ALU_DST_AB, dst_ab) | 396 FIELD_PREP(OP_ALU_WR_AB, wr_both) | 397 FIELD_PREP(OP_ALU_SRC_LMEXTN, src_lmextn) | 398 FIELD_PREP(OP_ALU_DST_LMEXTN, dst_lmextn); 399 400 nfp_prog_push(nfp_prog, insn); 401 } 402 403 static void 404 emit_alu(struct nfp_prog *nfp_prog, swreg dst, 405 swreg lreg, enum alu_op op, swreg rreg) 406 { 407 struct nfp_insn_ur_regs reg; 408 int err; 409 410 err = swreg_to_unrestricted(dst, lreg, rreg, ®); 411 if (err) { 412 nfp_prog->error = err; 413 return; 414 } 415 416 __emit_alu(nfp_prog, reg.dst, reg.dst_ab, 417 reg.areg, op, reg.breg, reg.swap, reg.wr_both, 418 reg.dst_lmextn, reg.src_lmextn); 419 } 420 421 static void 422 __emit_mul(struct nfp_prog *nfp_prog, enum alu_dst_ab dst_ab, u16 areg, 423 enum mul_type type, enum mul_step step, u16 breg, bool swap, 424 bool wr_both, bool dst_lmextn, bool src_lmextn) 425 { 426 u64 insn; 427 428 insn = OP_MUL_BASE | 429 FIELD_PREP(OP_MUL_A_SRC, areg) | 430 FIELD_PREP(OP_MUL_B_SRC, breg) | 431 FIELD_PREP(OP_MUL_STEP, step) | 432 FIELD_PREP(OP_MUL_DST_AB, dst_ab) | 433 FIELD_PREP(OP_MUL_SW, swap) | 434 FIELD_PREP(OP_MUL_TYPE, type) | 435 FIELD_PREP(OP_MUL_WR_AB, wr_both) | 436 FIELD_PREP(OP_MUL_SRC_LMEXTN, src_lmextn) | 437 FIELD_PREP(OP_MUL_DST_LMEXTN, dst_lmextn); 438 439 nfp_prog_push(nfp_prog, insn); 440 } 441 442 static void 443 emit_mul(struct nfp_prog *nfp_prog, swreg lreg, enum mul_type type, 444 enum mul_step step, swreg rreg) 445 { 446 struct nfp_insn_ur_regs reg; 447 u16 areg; 448 int err; 449 450 if (type == MUL_TYPE_START && step != MUL_STEP_NONE) { 451 nfp_prog->error = -EINVAL; 452 return; 453 } 454 455 if (step == MUL_LAST || step == MUL_LAST_2) { 456 /* When type is step and step Number is LAST or LAST2, left 457 * source is used as destination. 458 */ 459 err = swreg_to_unrestricted(lreg, reg_none(), rreg, ®); 460 areg = reg.dst; 461 } else { 462 err = swreg_to_unrestricted(reg_none(), lreg, rreg, ®); 463 areg = reg.areg; 464 } 465 466 if (err) { 467 nfp_prog->error = err; 468 return; 469 } 470 471 __emit_mul(nfp_prog, reg.dst_ab, areg, type, step, reg.breg, reg.swap, 472 reg.wr_both, reg.dst_lmextn, reg.src_lmextn); 473 } 474 475 static void 476 __emit_ld_field(struct nfp_prog *nfp_prog, enum shf_sc sc, 477 u8 areg, u8 bmask, u8 breg, u8 shift, bool imm8, 478 bool zero, bool swap, bool wr_both, 479 bool dst_lmextn, bool src_lmextn) 480 { 481 u64 insn; 482 483 insn = OP_LDF_BASE | 484 FIELD_PREP(OP_LDF_A_SRC, areg) | 485 FIELD_PREP(OP_LDF_SC, sc) | 486 FIELD_PREP(OP_LDF_B_SRC, breg) | 487 FIELD_PREP(OP_LDF_I8, imm8) | 488 FIELD_PREP(OP_LDF_SW, swap) | 489 FIELD_PREP(OP_LDF_ZF, zero) | 490 FIELD_PREP(OP_LDF_BMASK, bmask) | 491 FIELD_PREP(OP_LDF_SHF, shift) | 492 FIELD_PREP(OP_LDF_WR_AB, wr_both) | 493 FIELD_PREP(OP_LDF_SRC_LMEXTN, src_lmextn) | 494 FIELD_PREP(OP_LDF_DST_LMEXTN, dst_lmextn); 495 496 nfp_prog_push(nfp_prog, insn); 497 } 498 499 static void 500 emit_ld_field_any(struct nfp_prog *nfp_prog, swreg dst, u8 bmask, swreg src, 501 enum shf_sc sc, u8 shift, bool zero) 502 { 503 struct nfp_insn_re_regs reg; 504 int err; 505 506 /* Note: ld_field is special as it uses one of the src regs as dst */ 507 err = swreg_to_restricted(dst, dst, src, ®, true); 508 if (err) { 509 nfp_prog->error = err; 510 return; 511 } 512 513 __emit_ld_field(nfp_prog, sc, reg.areg, bmask, reg.breg, shift, 514 reg.i8, zero, reg.swap, reg.wr_both, 515 reg.dst_lmextn, reg.src_lmextn); 516 } 517 518 static void 519 emit_ld_field(struct nfp_prog *nfp_prog, swreg dst, u8 bmask, swreg src, 520 enum shf_sc sc, u8 shift) 521 { 522 emit_ld_field_any(nfp_prog, dst, bmask, src, sc, shift, false); 523 } 524 525 static void 526 __emit_lcsr(struct nfp_prog *nfp_prog, u16 areg, u16 breg, bool wr, u16 addr, 527 bool dst_lmextn, bool src_lmextn) 528 { 529 u64 insn; 530 531 insn = OP_LCSR_BASE | 532 FIELD_PREP(OP_LCSR_A_SRC, areg) | 533 FIELD_PREP(OP_LCSR_B_SRC, breg) | 534 FIELD_PREP(OP_LCSR_WRITE, wr) | 535 FIELD_PREP(OP_LCSR_ADDR, addr / 4) | 536 FIELD_PREP(OP_LCSR_SRC_LMEXTN, src_lmextn) | 537 FIELD_PREP(OP_LCSR_DST_LMEXTN, dst_lmextn); 538 539 nfp_prog_push(nfp_prog, insn); 540 } 541 542 static void emit_csr_wr(struct nfp_prog *nfp_prog, swreg src, u16 addr) 543 { 544 struct nfp_insn_ur_regs reg; 545 int err; 546 547 /* This instruction takes immeds instead of reg_none() for the ignored 548 * operand, but we can't encode 2 immeds in one instr with our normal 549 * swreg infra so if param is an immed, we encode as reg_none() and 550 * copy the immed to both operands. 551 */ 552 if (swreg_type(src) == NN_REG_IMM) { 553 err = swreg_to_unrestricted(reg_none(), src, reg_none(), ®); 554 reg.breg = reg.areg; 555 } else { 556 err = swreg_to_unrestricted(reg_none(), src, reg_imm(0), ®); 557 } 558 if (err) { 559 nfp_prog->error = err; 560 return; 561 } 562 563 __emit_lcsr(nfp_prog, reg.areg, reg.breg, true, addr, 564 false, reg.src_lmextn); 565 } 566 567 /* CSR value is read in following immed[gpr, 0] */ 568 static void __emit_csr_rd(struct nfp_prog *nfp_prog, u16 addr) 569 { 570 __emit_lcsr(nfp_prog, 0, 0, false, addr, false, false); 571 } 572 573 static void emit_nop(struct nfp_prog *nfp_prog) 574 { 575 __emit_immed(nfp_prog, UR_REG_IMM, UR_REG_IMM, 0, 0, 0, 0, 0, 0, 0); 576 } 577 578 /* --- Wrappers --- */ 579 static bool pack_immed(u32 imm, u16 *val, enum immed_shift *shift) 580 { 581 if (!(imm & 0xffff0000)) { 582 *val = imm; 583 *shift = IMMED_SHIFT_0B; 584 } else if (!(imm & 0xff0000ff)) { 585 *val = imm >> 8; 586 *shift = IMMED_SHIFT_1B; 587 } else if (!(imm & 0x0000ffff)) { 588 *val = imm >> 16; 589 *shift = IMMED_SHIFT_2B; 590 } else { 591 return false; 592 } 593 594 return true; 595 } 596 597 static void wrp_immed(struct nfp_prog *nfp_prog, swreg dst, u32 imm) 598 { 599 enum immed_shift shift; 600 u16 val; 601 602 if (pack_immed(imm, &val, &shift)) { 603 emit_immed(nfp_prog, dst, val, IMMED_WIDTH_ALL, false, shift); 604 } else if (pack_immed(~imm, &val, &shift)) { 605 emit_immed(nfp_prog, dst, val, IMMED_WIDTH_ALL, true, shift); 606 } else { 607 emit_immed(nfp_prog, dst, imm & 0xffff, IMMED_WIDTH_ALL, 608 false, IMMED_SHIFT_0B); 609 emit_immed(nfp_prog, dst, imm >> 16, IMMED_WIDTH_WORD, 610 false, IMMED_SHIFT_2B); 611 } 612 } 613 614 static void 615 wrp_immed_relo(struct nfp_prog *nfp_prog, swreg dst, u32 imm, 616 enum nfp_relo_type relo) 617 { 618 if (imm > 0xffff) { 619 pr_err("relocation of a large immediate!\n"); 620 nfp_prog->error = -EFAULT; 621 return; 622 } 623 emit_immed(nfp_prog, dst, imm, IMMED_WIDTH_ALL, false, IMMED_SHIFT_0B); 624 625 nfp_prog->prog[nfp_prog->prog_len - 1] |= 626 FIELD_PREP(OP_RELO_TYPE, relo); 627 } 628 629 /* ur_load_imm_any() - encode immediate or use tmp register (unrestricted) 630 * If the @imm is small enough encode it directly in operand and return 631 * otherwise load @imm to a spare register and return its encoding. 632 */ 633 static swreg ur_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, swreg tmp_reg) 634 { 635 if (FIELD_FIT(UR_REG_IMM_MAX, imm)) 636 return reg_imm(imm); 637 638 wrp_immed(nfp_prog, tmp_reg, imm); 639 return tmp_reg; 640 } 641 642 /* re_load_imm_any() - encode immediate or use tmp register (restricted) 643 * If the @imm is small enough encode it directly in operand and return 644 * otherwise load @imm to a spare register and return its encoding. 645 */ 646 static swreg re_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, swreg tmp_reg) 647 { 648 if (FIELD_FIT(RE_REG_IMM_MAX, imm)) 649 return reg_imm(imm); 650 651 wrp_immed(nfp_prog, tmp_reg, imm); 652 return tmp_reg; 653 } 654 655 static void wrp_nops(struct nfp_prog *nfp_prog, unsigned int count) 656 { 657 while (count--) 658 emit_nop(nfp_prog); 659 } 660 661 static void wrp_mov(struct nfp_prog *nfp_prog, swreg dst, swreg src) 662 { 663 emit_alu(nfp_prog, dst, reg_none(), ALU_OP_NONE, src); 664 } 665 666 static void wrp_reg_mov(struct nfp_prog *nfp_prog, u16 dst, u16 src) 667 { 668 wrp_mov(nfp_prog, reg_both(dst), reg_b(src)); 669 } 670 671 /* wrp_reg_subpart() - load @field_len bytes from @offset of @src, write the 672 * result to @dst from low end. 673 */ 674 static void 675 wrp_reg_subpart(struct nfp_prog *nfp_prog, swreg dst, swreg src, u8 field_len, 676 u8 offset) 677 { 678 enum shf_sc sc = offset ? SHF_SC_R_SHF : SHF_SC_NONE; 679 u8 mask = (1 << field_len) - 1; 680 681 emit_ld_field_any(nfp_prog, dst, mask, src, sc, offset * 8, true); 682 } 683 684 /* wrp_reg_or_subpart() - load @field_len bytes from low end of @src, or the 685 * result to @dst from offset, there is no change on the other bits of @dst. 686 */ 687 static void 688 wrp_reg_or_subpart(struct nfp_prog *nfp_prog, swreg dst, swreg src, 689 u8 field_len, u8 offset) 690 { 691 enum shf_sc sc = offset ? SHF_SC_L_SHF : SHF_SC_NONE; 692 u8 mask = ((1 << field_len) - 1) << offset; 693 694 emit_ld_field(nfp_prog, dst, mask, src, sc, 32 - offset * 8); 695 } 696 697 static void 698 addr40_offset(struct nfp_prog *nfp_prog, u8 src_gpr, swreg offset, 699 swreg *rega, swreg *regb) 700 { 701 if (offset == reg_imm(0)) { 702 *rega = reg_a(src_gpr); 703 *regb = reg_b(src_gpr + 1); 704 return; 705 } 706 707 emit_alu(nfp_prog, imm_a(nfp_prog), reg_a(src_gpr), ALU_OP_ADD, offset); 708 emit_alu(nfp_prog, imm_b(nfp_prog), reg_b(src_gpr + 1), ALU_OP_ADD_C, 709 reg_imm(0)); 710 *rega = imm_a(nfp_prog); 711 *regb = imm_b(nfp_prog); 712 } 713 714 /* NFP has Command Push Pull bus which supports bluk memory operations. */ 715 static int nfp_cpp_memcpy(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 716 { 717 bool descending_seq = meta->ldst_gather_len < 0; 718 s16 len = abs(meta->ldst_gather_len); 719 swreg src_base, off; 720 bool src_40bit_addr; 721 unsigned int i; 722 u8 xfer_num; 723 724 off = re_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 725 src_40bit_addr = meta->ptr.type == PTR_TO_MAP_VALUE; 726 src_base = reg_a(meta->insn.src_reg * 2); 727 xfer_num = round_up(len, 4) / 4; 728 729 if (src_40bit_addr) 730 addr40_offset(nfp_prog, meta->insn.src_reg * 2, off, &src_base, 731 &off); 732 733 /* Setup PREV_ALU fields to override memory read length. */ 734 if (len > 32) 735 wrp_immed(nfp_prog, reg_none(), 736 CMD_OVE_LEN | FIELD_PREP(CMD_OV_LEN, xfer_num - 1)); 737 738 /* Memory read from source addr into transfer-in registers. */ 739 emit_cmd_any(nfp_prog, CMD_TGT_READ32_SWAP, 740 src_40bit_addr ? CMD_MODE_40b_BA : CMD_MODE_32b, 0, 741 src_base, off, xfer_num - 1, CMD_CTX_SWAP, len > 32); 742 743 /* Move from transfer-in to transfer-out. */ 744 for (i = 0; i < xfer_num; i++) 745 wrp_mov(nfp_prog, reg_xfer(i), reg_xfer(i)); 746 747 off = re_load_imm_any(nfp_prog, meta->paired_st->off, imm_b(nfp_prog)); 748 749 if (len <= 8) { 750 /* Use single direct_ref write8. */ 751 emit_cmd(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 0, 752 reg_a(meta->paired_st->dst_reg * 2), off, len - 1, 753 CMD_CTX_SWAP); 754 } else if (len <= 32 && IS_ALIGNED(len, 4)) { 755 /* Use single direct_ref write32. */ 756 emit_cmd(nfp_prog, CMD_TGT_WRITE32_SWAP, CMD_MODE_32b, 0, 757 reg_a(meta->paired_st->dst_reg * 2), off, xfer_num - 1, 758 CMD_CTX_SWAP); 759 } else if (len <= 32) { 760 /* Use single indirect_ref write8. */ 761 wrp_immed(nfp_prog, reg_none(), 762 CMD_OVE_LEN | FIELD_PREP(CMD_OV_LEN, len - 1)); 763 emit_cmd_indir(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 0, 764 reg_a(meta->paired_st->dst_reg * 2), off, 765 len - 1, CMD_CTX_SWAP); 766 } else if (IS_ALIGNED(len, 4)) { 767 /* Use single indirect_ref write32. */ 768 wrp_immed(nfp_prog, reg_none(), 769 CMD_OVE_LEN | FIELD_PREP(CMD_OV_LEN, xfer_num - 1)); 770 emit_cmd_indir(nfp_prog, CMD_TGT_WRITE32_SWAP, CMD_MODE_32b, 0, 771 reg_a(meta->paired_st->dst_reg * 2), off, 772 xfer_num - 1, CMD_CTX_SWAP); 773 } else if (len <= 40) { 774 /* Use one direct_ref write32 to write the first 32-bytes, then 775 * another direct_ref write8 to write the remaining bytes. 776 */ 777 emit_cmd(nfp_prog, CMD_TGT_WRITE32_SWAP, CMD_MODE_32b, 0, 778 reg_a(meta->paired_st->dst_reg * 2), off, 7, 779 CMD_CTX_SWAP); 780 781 off = re_load_imm_any(nfp_prog, meta->paired_st->off + 32, 782 imm_b(nfp_prog)); 783 emit_cmd(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 8, 784 reg_a(meta->paired_st->dst_reg * 2), off, len - 33, 785 CMD_CTX_SWAP); 786 } else { 787 /* Use one indirect_ref write32 to write 4-bytes aligned length, 788 * then another direct_ref write8 to write the remaining bytes. 789 */ 790 u8 new_off; 791 792 wrp_immed(nfp_prog, reg_none(), 793 CMD_OVE_LEN | FIELD_PREP(CMD_OV_LEN, xfer_num - 2)); 794 emit_cmd_indir(nfp_prog, CMD_TGT_WRITE32_SWAP, CMD_MODE_32b, 0, 795 reg_a(meta->paired_st->dst_reg * 2), off, 796 xfer_num - 2, CMD_CTX_SWAP); 797 new_off = meta->paired_st->off + (xfer_num - 1) * 4; 798 off = re_load_imm_any(nfp_prog, new_off, imm_b(nfp_prog)); 799 emit_cmd(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 800 xfer_num - 1, reg_a(meta->paired_st->dst_reg * 2), off, 801 (len & 0x3) - 1, CMD_CTX_SWAP); 802 } 803 804 /* TODO: The following extra load is to make sure data flow be identical 805 * before and after we do memory copy optimization. 806 * 807 * The load destination register is not guaranteed to be dead, so we 808 * need to make sure it is loaded with the value the same as before 809 * this transformation. 810 * 811 * These extra loads could be removed once we have accurate register 812 * usage information. 813 */ 814 if (descending_seq) 815 xfer_num = 0; 816 else if (BPF_SIZE(meta->insn.code) != BPF_DW) 817 xfer_num = xfer_num - 1; 818 else 819 xfer_num = xfer_num - 2; 820 821 switch (BPF_SIZE(meta->insn.code)) { 822 case BPF_B: 823 wrp_reg_subpart(nfp_prog, reg_both(meta->insn.dst_reg * 2), 824 reg_xfer(xfer_num), 1, 825 IS_ALIGNED(len, 4) ? 3 : (len & 3) - 1); 826 break; 827 case BPF_H: 828 wrp_reg_subpart(nfp_prog, reg_both(meta->insn.dst_reg * 2), 829 reg_xfer(xfer_num), 2, (len & 3) ^ 2); 830 break; 831 case BPF_W: 832 wrp_mov(nfp_prog, reg_both(meta->insn.dst_reg * 2), 833 reg_xfer(0)); 834 break; 835 case BPF_DW: 836 wrp_mov(nfp_prog, reg_both(meta->insn.dst_reg * 2), 837 reg_xfer(xfer_num)); 838 wrp_mov(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 839 reg_xfer(xfer_num + 1)); 840 break; 841 } 842 843 if (BPF_SIZE(meta->insn.code) != BPF_DW) 844 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 0); 845 846 return 0; 847 } 848 849 static int 850 data_ld(struct nfp_prog *nfp_prog, swreg offset, u8 dst_gpr, int size) 851 { 852 unsigned int i; 853 u16 shift, sz; 854 855 /* We load the value from the address indicated in @offset and then 856 * shift out the data we don't need. Note: this is big endian! 857 */ 858 sz = max(size, 4); 859 shift = size < 4 ? 4 - size : 0; 860 861 emit_cmd(nfp_prog, CMD_TGT_READ8, CMD_MODE_32b, 0, 862 pptr_reg(nfp_prog), offset, sz - 1, CMD_CTX_SWAP); 863 864 i = 0; 865 if (shift) 866 emit_shf(nfp_prog, reg_both(dst_gpr), reg_none(), SHF_OP_NONE, 867 reg_xfer(0), SHF_SC_R_SHF, shift * 8); 868 else 869 for (; i * 4 < size; i++) 870 wrp_mov(nfp_prog, reg_both(dst_gpr + i), reg_xfer(i)); 871 872 if (i < 2) 873 wrp_immed(nfp_prog, reg_both(dst_gpr + 1), 0); 874 875 return 0; 876 } 877 878 static int 879 data_ld_host_order(struct nfp_prog *nfp_prog, u8 dst_gpr, 880 swreg lreg, swreg rreg, int size, enum cmd_mode mode) 881 { 882 unsigned int i; 883 u8 mask, sz; 884 885 /* We load the value from the address indicated in rreg + lreg and then 886 * mask out the data we don't need. Note: this is little endian! 887 */ 888 sz = max(size, 4); 889 mask = size < 4 ? GENMASK(size - 1, 0) : 0; 890 891 emit_cmd(nfp_prog, CMD_TGT_READ32_SWAP, mode, 0, 892 lreg, rreg, sz / 4 - 1, CMD_CTX_SWAP); 893 894 i = 0; 895 if (mask) 896 emit_ld_field_any(nfp_prog, reg_both(dst_gpr), mask, 897 reg_xfer(0), SHF_SC_NONE, 0, true); 898 else 899 for (; i * 4 < size; i++) 900 wrp_mov(nfp_prog, reg_both(dst_gpr + i), reg_xfer(i)); 901 902 if (i < 2) 903 wrp_immed(nfp_prog, reg_both(dst_gpr + 1), 0); 904 905 return 0; 906 } 907 908 static int 909 data_ld_host_order_addr32(struct nfp_prog *nfp_prog, u8 src_gpr, swreg offset, 910 u8 dst_gpr, u8 size) 911 { 912 return data_ld_host_order(nfp_prog, dst_gpr, reg_a(src_gpr), offset, 913 size, CMD_MODE_32b); 914 } 915 916 static int 917 data_ld_host_order_addr40(struct nfp_prog *nfp_prog, u8 src_gpr, swreg offset, 918 u8 dst_gpr, u8 size) 919 { 920 swreg rega, regb; 921 922 addr40_offset(nfp_prog, src_gpr, offset, ®a, ®b); 923 924 return data_ld_host_order(nfp_prog, dst_gpr, rega, regb, 925 size, CMD_MODE_40b_BA); 926 } 927 928 static int 929 construct_data_ind_ld(struct nfp_prog *nfp_prog, u16 offset, u16 src, u8 size) 930 { 931 swreg tmp_reg; 932 933 /* Calculate the true offset (src_reg + imm) */ 934 tmp_reg = ur_load_imm_any(nfp_prog, offset, imm_b(nfp_prog)); 935 emit_alu(nfp_prog, imm_both(nfp_prog), reg_a(src), ALU_OP_ADD, tmp_reg); 936 937 /* Check packet length (size guaranteed to fit b/c it's u8) */ 938 emit_alu(nfp_prog, imm_a(nfp_prog), 939 imm_a(nfp_prog), ALU_OP_ADD, reg_imm(size)); 940 emit_alu(nfp_prog, reg_none(), 941 plen_reg(nfp_prog), ALU_OP_SUB, imm_a(nfp_prog)); 942 emit_br_relo(nfp_prog, BR_BLO, BR_OFF_RELO, 0, RELO_BR_GO_ABORT); 943 944 /* Load data */ 945 return data_ld(nfp_prog, imm_b(nfp_prog), 0, size); 946 } 947 948 static int construct_data_ld(struct nfp_prog *nfp_prog, u16 offset, u8 size) 949 { 950 swreg tmp_reg; 951 952 /* Check packet length */ 953 tmp_reg = ur_load_imm_any(nfp_prog, offset + size, imm_a(nfp_prog)); 954 emit_alu(nfp_prog, reg_none(), plen_reg(nfp_prog), ALU_OP_SUB, tmp_reg); 955 emit_br_relo(nfp_prog, BR_BLO, BR_OFF_RELO, 0, RELO_BR_GO_ABORT); 956 957 /* Load data */ 958 tmp_reg = re_load_imm_any(nfp_prog, offset, imm_b(nfp_prog)); 959 return data_ld(nfp_prog, tmp_reg, 0, size); 960 } 961 962 static int 963 data_stx_host_order(struct nfp_prog *nfp_prog, u8 dst_gpr, swreg offset, 964 u8 src_gpr, u8 size) 965 { 966 unsigned int i; 967 968 for (i = 0; i * 4 < size; i++) 969 wrp_mov(nfp_prog, reg_xfer(i), reg_a(src_gpr + i)); 970 971 emit_cmd(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 0, 972 reg_a(dst_gpr), offset, size - 1, CMD_CTX_SWAP); 973 974 return 0; 975 } 976 977 static int 978 data_st_host_order(struct nfp_prog *nfp_prog, u8 dst_gpr, swreg offset, 979 u64 imm, u8 size) 980 { 981 wrp_immed(nfp_prog, reg_xfer(0), imm); 982 if (size == 8) 983 wrp_immed(nfp_prog, reg_xfer(1), imm >> 32); 984 985 emit_cmd(nfp_prog, CMD_TGT_WRITE8_SWAP, CMD_MODE_32b, 0, 986 reg_a(dst_gpr), offset, size - 1, CMD_CTX_SWAP); 987 988 return 0; 989 } 990 991 typedef int 992 (*lmem_step)(struct nfp_prog *nfp_prog, u8 gpr, u8 gpr_byte, s32 off, 993 unsigned int size, bool first, bool new_gpr, bool last, bool lm3, 994 bool needs_inc); 995 996 static int 997 wrp_lmem_load(struct nfp_prog *nfp_prog, u8 dst, u8 dst_byte, s32 off, 998 unsigned int size, bool first, bool new_gpr, bool last, bool lm3, 999 bool needs_inc) 1000 { 1001 bool should_inc = needs_inc && new_gpr && !last; 1002 u32 idx, src_byte; 1003 enum shf_sc sc; 1004 swreg reg; 1005 int shf; 1006 u8 mask; 1007 1008 if (WARN_ON_ONCE(dst_byte + size > 4 || off % 4 + size > 4)) 1009 return -EOPNOTSUPP; 1010 1011 idx = off / 4; 1012 1013 /* Move the entire word */ 1014 if (size == 4) { 1015 wrp_mov(nfp_prog, reg_both(dst), 1016 should_inc ? reg_lm_inc(3) : reg_lm(lm3 ? 3 : 0, idx)); 1017 return 0; 1018 } 1019 1020 if (WARN_ON_ONCE(lm3 && idx > RE_REG_LM_IDX_MAX)) 1021 return -EOPNOTSUPP; 1022 1023 src_byte = off % 4; 1024 1025 mask = (1 << size) - 1; 1026 mask <<= dst_byte; 1027 1028 if (WARN_ON_ONCE(mask > 0xf)) 1029 return -EOPNOTSUPP; 1030 1031 shf = abs(src_byte - dst_byte) * 8; 1032 if (src_byte == dst_byte) { 1033 sc = SHF_SC_NONE; 1034 } else if (src_byte < dst_byte) { 1035 shf = 32 - shf; 1036 sc = SHF_SC_L_SHF; 1037 } else { 1038 sc = SHF_SC_R_SHF; 1039 } 1040 1041 /* ld_field can address fewer indexes, if offset too large do RMW. 1042 * Because we RMV twice we waste 2 cycles on unaligned 8 byte writes. 1043 */ 1044 if (idx <= RE_REG_LM_IDX_MAX) { 1045 reg = reg_lm(lm3 ? 3 : 0, idx); 1046 } else { 1047 reg = imm_a(nfp_prog); 1048 /* If it's not the first part of the load and we start a new GPR 1049 * that means we are loading a second part of the LMEM word into 1050 * a new GPR. IOW we've already looked that LMEM word and 1051 * therefore it has been loaded into imm_a(). 1052 */ 1053 if (first || !new_gpr) 1054 wrp_mov(nfp_prog, reg, reg_lm(0, idx)); 1055 } 1056 1057 emit_ld_field_any(nfp_prog, reg_both(dst), mask, reg, sc, shf, new_gpr); 1058 1059 if (should_inc) 1060 wrp_mov(nfp_prog, reg_none(), reg_lm_inc(3)); 1061 1062 return 0; 1063 } 1064 1065 static int 1066 wrp_lmem_store(struct nfp_prog *nfp_prog, u8 src, u8 src_byte, s32 off, 1067 unsigned int size, bool first, bool new_gpr, bool last, bool lm3, 1068 bool needs_inc) 1069 { 1070 bool should_inc = needs_inc && new_gpr && !last; 1071 u32 idx, dst_byte; 1072 enum shf_sc sc; 1073 swreg reg; 1074 int shf; 1075 u8 mask; 1076 1077 if (WARN_ON_ONCE(src_byte + size > 4 || off % 4 + size > 4)) 1078 return -EOPNOTSUPP; 1079 1080 idx = off / 4; 1081 1082 /* Move the entire word */ 1083 if (size == 4) { 1084 wrp_mov(nfp_prog, 1085 should_inc ? reg_lm_inc(3) : reg_lm(lm3 ? 3 : 0, idx), 1086 reg_b(src)); 1087 return 0; 1088 } 1089 1090 if (WARN_ON_ONCE(lm3 && idx > RE_REG_LM_IDX_MAX)) 1091 return -EOPNOTSUPP; 1092 1093 dst_byte = off % 4; 1094 1095 mask = (1 << size) - 1; 1096 mask <<= dst_byte; 1097 1098 if (WARN_ON_ONCE(mask > 0xf)) 1099 return -EOPNOTSUPP; 1100 1101 shf = abs(src_byte - dst_byte) * 8; 1102 if (src_byte == dst_byte) { 1103 sc = SHF_SC_NONE; 1104 } else if (src_byte < dst_byte) { 1105 shf = 32 - shf; 1106 sc = SHF_SC_L_SHF; 1107 } else { 1108 sc = SHF_SC_R_SHF; 1109 } 1110 1111 /* ld_field can address fewer indexes, if offset too large do RMW. 1112 * Because we RMV twice we waste 2 cycles on unaligned 8 byte writes. 1113 */ 1114 if (idx <= RE_REG_LM_IDX_MAX) { 1115 reg = reg_lm(lm3 ? 3 : 0, idx); 1116 } else { 1117 reg = imm_a(nfp_prog); 1118 /* Only first and last LMEM locations are going to need RMW, 1119 * the middle location will be overwritten fully. 1120 */ 1121 if (first || last) 1122 wrp_mov(nfp_prog, reg, reg_lm(0, idx)); 1123 } 1124 1125 emit_ld_field(nfp_prog, reg, mask, reg_b(src), sc, shf); 1126 1127 if (new_gpr || last) { 1128 if (idx > RE_REG_LM_IDX_MAX) 1129 wrp_mov(nfp_prog, reg_lm(0, idx), reg); 1130 if (should_inc) 1131 wrp_mov(nfp_prog, reg_none(), reg_lm_inc(3)); 1132 } 1133 1134 return 0; 1135 } 1136 1137 static int 1138 mem_op_stack(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1139 unsigned int size, unsigned int ptr_off, u8 gpr, u8 ptr_gpr, 1140 bool clr_gpr, lmem_step step) 1141 { 1142 s32 off = nfp_prog->stack_frame_depth + meta->insn.off + ptr_off; 1143 bool first = true, last; 1144 bool needs_inc = false; 1145 swreg stack_off_reg; 1146 u8 prev_gpr = 255; 1147 u32 gpr_byte = 0; 1148 bool lm3 = true; 1149 int ret; 1150 1151 if (meta->ptr_not_const || 1152 meta->flags & FLAG_INSN_PTR_CALLER_STACK_FRAME) { 1153 /* Use of the last encountered ptr_off is OK, they all have 1154 * the same alignment. Depend on low bits of value being 1155 * discarded when written to LMaddr register. 1156 */ 1157 stack_off_reg = ur_load_imm_any(nfp_prog, meta->insn.off, 1158 stack_imm(nfp_prog)); 1159 1160 emit_alu(nfp_prog, imm_b(nfp_prog), 1161 reg_a(ptr_gpr), ALU_OP_ADD, stack_off_reg); 1162 1163 needs_inc = true; 1164 } else if (off + size <= 64) { 1165 /* We can reach bottom 64B with LMaddr0 */ 1166 lm3 = false; 1167 } else if (round_down(off, 32) == round_down(off + size - 1, 32)) { 1168 /* We have to set up a new pointer. If we know the offset 1169 * and the entire access falls into a single 32 byte aligned 1170 * window we won't have to increment the LM pointer. 1171 * The 32 byte alignment is imporant because offset is ORed in 1172 * not added when doing *l$indexN[off]. 1173 */ 1174 stack_off_reg = ur_load_imm_any(nfp_prog, round_down(off, 32), 1175 stack_imm(nfp_prog)); 1176 emit_alu(nfp_prog, imm_b(nfp_prog), 1177 stack_reg(nfp_prog), ALU_OP_ADD, stack_off_reg); 1178 1179 off %= 32; 1180 } else { 1181 stack_off_reg = ur_load_imm_any(nfp_prog, round_down(off, 4), 1182 stack_imm(nfp_prog)); 1183 1184 emit_alu(nfp_prog, imm_b(nfp_prog), 1185 stack_reg(nfp_prog), ALU_OP_ADD, stack_off_reg); 1186 1187 needs_inc = true; 1188 } 1189 if (lm3) { 1190 emit_csr_wr(nfp_prog, imm_b(nfp_prog), NFP_CSR_ACT_LM_ADDR3); 1191 /* For size < 4 one slot will be filled by zeroing of upper. */ 1192 wrp_nops(nfp_prog, clr_gpr && size < 8 ? 2 : 3); 1193 } 1194 1195 if (clr_gpr && size < 8) 1196 wrp_immed(nfp_prog, reg_both(gpr + 1), 0); 1197 1198 while (size) { 1199 u32 slice_end; 1200 u8 slice_size; 1201 1202 slice_size = min(size, 4 - gpr_byte); 1203 slice_end = min(off + slice_size, round_up(off + 1, 4)); 1204 slice_size = slice_end - off; 1205 1206 last = slice_size == size; 1207 1208 if (needs_inc) 1209 off %= 4; 1210 1211 ret = step(nfp_prog, gpr, gpr_byte, off, slice_size, 1212 first, gpr != prev_gpr, last, lm3, needs_inc); 1213 if (ret) 1214 return ret; 1215 1216 prev_gpr = gpr; 1217 first = false; 1218 1219 gpr_byte += slice_size; 1220 if (gpr_byte >= 4) { 1221 gpr_byte -= 4; 1222 gpr++; 1223 } 1224 1225 size -= slice_size; 1226 off += slice_size; 1227 } 1228 1229 return 0; 1230 } 1231 1232 static void 1233 wrp_alu_imm(struct nfp_prog *nfp_prog, u8 dst, enum alu_op alu_op, u32 imm) 1234 { 1235 swreg tmp_reg; 1236 1237 if (alu_op == ALU_OP_AND) { 1238 if (!imm) 1239 wrp_immed(nfp_prog, reg_both(dst), 0); 1240 if (!imm || !~imm) 1241 return; 1242 } 1243 if (alu_op == ALU_OP_OR) { 1244 if (!~imm) 1245 wrp_immed(nfp_prog, reg_both(dst), ~0U); 1246 if (!imm || !~imm) 1247 return; 1248 } 1249 if (alu_op == ALU_OP_XOR) { 1250 if (!~imm) 1251 emit_alu(nfp_prog, reg_both(dst), reg_none(), 1252 ALU_OP_NOT, reg_b(dst)); 1253 if (!imm || !~imm) 1254 return; 1255 } 1256 1257 tmp_reg = ur_load_imm_any(nfp_prog, imm, imm_b(nfp_prog)); 1258 emit_alu(nfp_prog, reg_both(dst), reg_a(dst), alu_op, tmp_reg); 1259 } 1260 1261 static int 1262 wrp_alu64_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1263 enum alu_op alu_op, bool skip) 1264 { 1265 const struct bpf_insn *insn = &meta->insn; 1266 u64 imm = insn->imm; /* sign extend */ 1267 1268 if (skip) { 1269 meta->flags |= FLAG_INSN_SKIP_NOOP; 1270 return 0; 1271 } 1272 1273 wrp_alu_imm(nfp_prog, insn->dst_reg * 2, alu_op, imm & ~0U); 1274 wrp_alu_imm(nfp_prog, insn->dst_reg * 2 + 1, alu_op, imm >> 32); 1275 1276 return 0; 1277 } 1278 1279 static int 1280 wrp_alu64_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1281 enum alu_op alu_op) 1282 { 1283 u8 dst = meta->insn.dst_reg * 2, src = meta->insn.src_reg * 2; 1284 1285 emit_alu(nfp_prog, reg_both(dst), reg_a(dst), alu_op, reg_b(src)); 1286 emit_alu(nfp_prog, reg_both(dst + 1), 1287 reg_a(dst + 1), alu_op, reg_b(src + 1)); 1288 1289 return 0; 1290 } 1291 1292 static int 1293 wrp_alu32_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1294 enum alu_op alu_op, bool skip) 1295 { 1296 const struct bpf_insn *insn = &meta->insn; 1297 1298 if (skip) { 1299 meta->flags |= FLAG_INSN_SKIP_NOOP; 1300 return 0; 1301 } 1302 1303 wrp_alu_imm(nfp_prog, insn->dst_reg * 2, alu_op, insn->imm); 1304 wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0); 1305 1306 return 0; 1307 } 1308 1309 static int 1310 wrp_alu32_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1311 enum alu_op alu_op) 1312 { 1313 u8 dst = meta->insn.dst_reg * 2, src = meta->insn.src_reg * 2; 1314 1315 emit_alu(nfp_prog, reg_both(dst), reg_a(dst), alu_op, reg_b(src)); 1316 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 0); 1317 1318 return 0; 1319 } 1320 1321 static void 1322 wrp_test_reg_one(struct nfp_prog *nfp_prog, u8 dst, enum alu_op alu_op, u8 src, 1323 enum br_mask br_mask, u16 off) 1324 { 1325 emit_alu(nfp_prog, reg_none(), reg_a(dst), alu_op, reg_b(src)); 1326 emit_br(nfp_prog, br_mask, off, 0); 1327 } 1328 1329 static int 1330 wrp_test_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1331 enum alu_op alu_op, enum br_mask br_mask) 1332 { 1333 const struct bpf_insn *insn = &meta->insn; 1334 1335 wrp_test_reg_one(nfp_prog, insn->dst_reg * 2, alu_op, 1336 insn->src_reg * 2, br_mask, insn->off); 1337 if (is_mbpf_jmp64(meta)) 1338 wrp_test_reg_one(nfp_prog, insn->dst_reg * 2 + 1, alu_op, 1339 insn->src_reg * 2 + 1, br_mask, insn->off); 1340 1341 return 0; 1342 } 1343 1344 static const struct jmp_code_map { 1345 enum br_mask br_mask; 1346 bool swap; 1347 } jmp_code_map[] = { 1348 [BPF_JGT >> 4] = { BR_BLO, true }, 1349 [BPF_JGE >> 4] = { BR_BHS, false }, 1350 [BPF_JLT >> 4] = { BR_BLO, false }, 1351 [BPF_JLE >> 4] = { BR_BHS, true }, 1352 [BPF_JSGT >> 4] = { BR_BLT, true }, 1353 [BPF_JSGE >> 4] = { BR_BGE, false }, 1354 [BPF_JSLT >> 4] = { BR_BLT, false }, 1355 [BPF_JSLE >> 4] = { BR_BGE, true }, 1356 }; 1357 1358 static const struct jmp_code_map *nfp_jmp_code_get(struct nfp_insn_meta *meta) 1359 { 1360 unsigned int op; 1361 1362 op = BPF_OP(meta->insn.code) >> 4; 1363 /* br_mask of 0 is BR_BEQ which we don't use in jump code table */ 1364 if (WARN_ONCE(op >= ARRAY_SIZE(jmp_code_map) || 1365 !jmp_code_map[op].br_mask, 1366 "no code found for jump instruction")) 1367 return NULL; 1368 1369 return &jmp_code_map[op]; 1370 } 1371 1372 static int cmp_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1373 { 1374 const struct bpf_insn *insn = &meta->insn; 1375 u64 imm = insn->imm; /* sign extend */ 1376 const struct jmp_code_map *code; 1377 enum alu_op alu_op, carry_op; 1378 u8 reg = insn->dst_reg * 2; 1379 swreg tmp_reg; 1380 1381 code = nfp_jmp_code_get(meta); 1382 if (!code) 1383 return -EINVAL; 1384 1385 alu_op = meta->jump_neg_op ? ALU_OP_ADD : ALU_OP_SUB; 1386 carry_op = meta->jump_neg_op ? ALU_OP_ADD_C : ALU_OP_SUB_C; 1387 1388 tmp_reg = ur_load_imm_any(nfp_prog, imm & ~0U, imm_b(nfp_prog)); 1389 if (!code->swap) 1390 emit_alu(nfp_prog, reg_none(), reg_a(reg), alu_op, tmp_reg); 1391 else 1392 emit_alu(nfp_prog, reg_none(), tmp_reg, alu_op, reg_a(reg)); 1393 1394 if (is_mbpf_jmp64(meta)) { 1395 tmp_reg = ur_load_imm_any(nfp_prog, imm >> 32, imm_b(nfp_prog)); 1396 if (!code->swap) 1397 emit_alu(nfp_prog, reg_none(), 1398 reg_a(reg + 1), carry_op, tmp_reg); 1399 else 1400 emit_alu(nfp_prog, reg_none(), 1401 tmp_reg, carry_op, reg_a(reg + 1)); 1402 } 1403 1404 emit_br(nfp_prog, code->br_mask, insn->off, 0); 1405 1406 return 0; 1407 } 1408 1409 static int cmp_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1410 { 1411 const struct bpf_insn *insn = &meta->insn; 1412 const struct jmp_code_map *code; 1413 u8 areg, breg; 1414 1415 code = nfp_jmp_code_get(meta); 1416 if (!code) 1417 return -EINVAL; 1418 1419 areg = insn->dst_reg * 2; 1420 breg = insn->src_reg * 2; 1421 1422 if (code->swap) { 1423 areg ^= breg; 1424 breg ^= areg; 1425 areg ^= breg; 1426 } 1427 1428 emit_alu(nfp_prog, reg_none(), reg_a(areg), ALU_OP_SUB, reg_b(breg)); 1429 if (is_mbpf_jmp64(meta)) 1430 emit_alu(nfp_prog, reg_none(), 1431 reg_a(areg + 1), ALU_OP_SUB_C, reg_b(breg + 1)); 1432 emit_br(nfp_prog, code->br_mask, insn->off, 0); 1433 1434 return 0; 1435 } 1436 1437 static void wrp_end32(struct nfp_prog *nfp_prog, swreg reg_in, u8 gpr_out) 1438 { 1439 emit_ld_field(nfp_prog, reg_both(gpr_out), 0xf, reg_in, 1440 SHF_SC_R_ROT, 8); 1441 emit_ld_field(nfp_prog, reg_both(gpr_out), 0x5, reg_a(gpr_out), 1442 SHF_SC_R_ROT, 16); 1443 } 1444 1445 static void 1446 wrp_mul_u32(struct nfp_prog *nfp_prog, swreg dst_hi, swreg dst_lo, swreg lreg, 1447 swreg rreg, bool gen_high_half) 1448 { 1449 emit_mul(nfp_prog, lreg, MUL_TYPE_START, MUL_STEP_NONE, rreg); 1450 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_32x32, MUL_STEP_1, rreg); 1451 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_32x32, MUL_STEP_2, rreg); 1452 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_32x32, MUL_STEP_3, rreg); 1453 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_32x32, MUL_STEP_4, rreg); 1454 emit_mul(nfp_prog, dst_lo, MUL_TYPE_STEP_32x32, MUL_LAST, reg_none()); 1455 if (gen_high_half) 1456 emit_mul(nfp_prog, dst_hi, MUL_TYPE_STEP_32x32, MUL_LAST_2, 1457 reg_none()); 1458 else 1459 wrp_immed(nfp_prog, dst_hi, 0); 1460 } 1461 1462 static void 1463 wrp_mul_u16(struct nfp_prog *nfp_prog, swreg dst_hi, swreg dst_lo, swreg lreg, 1464 swreg rreg) 1465 { 1466 emit_mul(nfp_prog, lreg, MUL_TYPE_START, MUL_STEP_NONE, rreg); 1467 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_16x16, MUL_STEP_1, rreg); 1468 emit_mul(nfp_prog, lreg, MUL_TYPE_STEP_16x16, MUL_STEP_2, rreg); 1469 emit_mul(nfp_prog, dst_lo, MUL_TYPE_STEP_16x16, MUL_LAST, reg_none()); 1470 } 1471 1472 static int 1473 wrp_mul(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 1474 bool gen_high_half, bool ropnd_from_reg) 1475 { 1476 swreg multiplier, multiplicand, dst_hi, dst_lo; 1477 const struct bpf_insn *insn = &meta->insn; 1478 u32 lopnd_max, ropnd_max; 1479 u8 dst_reg; 1480 1481 dst_reg = insn->dst_reg; 1482 multiplicand = reg_a(dst_reg * 2); 1483 dst_hi = reg_both(dst_reg * 2 + 1); 1484 dst_lo = reg_both(dst_reg * 2); 1485 lopnd_max = meta->umax_dst; 1486 if (ropnd_from_reg) { 1487 multiplier = reg_b(insn->src_reg * 2); 1488 ropnd_max = meta->umax_src; 1489 } else { 1490 u32 imm = insn->imm; 1491 1492 multiplier = ur_load_imm_any(nfp_prog, imm, imm_b(nfp_prog)); 1493 ropnd_max = imm; 1494 } 1495 if (lopnd_max > U16_MAX || ropnd_max > U16_MAX) 1496 wrp_mul_u32(nfp_prog, dst_hi, dst_lo, multiplicand, multiplier, 1497 gen_high_half); 1498 else 1499 wrp_mul_u16(nfp_prog, dst_hi, dst_lo, multiplicand, multiplier); 1500 1501 return 0; 1502 } 1503 1504 static int wrp_div_imm(struct nfp_prog *nfp_prog, u8 dst, u64 imm) 1505 { 1506 swreg dst_both = reg_both(dst), dst_a = reg_a(dst), dst_b = reg_a(dst); 1507 struct reciprocal_value_adv rvalue; 1508 u8 pre_shift, exp; 1509 swreg magic; 1510 1511 if (imm > U32_MAX) { 1512 wrp_immed(nfp_prog, dst_both, 0); 1513 return 0; 1514 } 1515 1516 /* NOTE: because we are using "reciprocal_value_adv" which doesn't 1517 * support "divisor > (1u << 31)", we need to JIT separate NFP sequence 1518 * to handle such case which actually equals to the result of unsigned 1519 * comparison "dst >= imm" which could be calculated using the following 1520 * NFP sequence: 1521 * 1522 * alu[--, dst, -, imm] 1523 * immed[imm, 0] 1524 * alu[dst, imm, +carry, 0] 1525 * 1526 */ 1527 if (imm > 1U << 31) { 1528 swreg tmp_b = ur_load_imm_any(nfp_prog, imm, imm_b(nfp_prog)); 1529 1530 emit_alu(nfp_prog, reg_none(), dst_a, ALU_OP_SUB, tmp_b); 1531 wrp_immed(nfp_prog, imm_a(nfp_prog), 0); 1532 emit_alu(nfp_prog, dst_both, imm_a(nfp_prog), ALU_OP_ADD_C, 1533 reg_imm(0)); 1534 return 0; 1535 } 1536 1537 rvalue = reciprocal_value_adv(imm, 32); 1538 exp = rvalue.exp; 1539 if (rvalue.is_wide_m && !(imm & 1)) { 1540 pre_shift = fls(imm & -imm) - 1; 1541 rvalue = reciprocal_value_adv(imm >> pre_shift, 32 - pre_shift); 1542 } else { 1543 pre_shift = 0; 1544 } 1545 magic = ur_load_imm_any(nfp_prog, rvalue.m, imm_b(nfp_prog)); 1546 if (imm == 1U << exp) { 1547 emit_shf(nfp_prog, dst_both, reg_none(), SHF_OP_NONE, dst_b, 1548 SHF_SC_R_SHF, exp); 1549 } else if (rvalue.is_wide_m) { 1550 wrp_mul_u32(nfp_prog, imm_both(nfp_prog), reg_none(), dst_a, 1551 magic, true); 1552 emit_alu(nfp_prog, dst_both, dst_a, ALU_OP_SUB, 1553 imm_b(nfp_prog)); 1554 emit_shf(nfp_prog, dst_both, reg_none(), SHF_OP_NONE, dst_b, 1555 SHF_SC_R_SHF, 1); 1556 emit_alu(nfp_prog, dst_both, dst_a, ALU_OP_ADD, 1557 imm_b(nfp_prog)); 1558 emit_shf(nfp_prog, dst_both, reg_none(), SHF_OP_NONE, dst_b, 1559 SHF_SC_R_SHF, rvalue.sh - 1); 1560 } else { 1561 if (pre_shift) 1562 emit_shf(nfp_prog, dst_both, reg_none(), SHF_OP_NONE, 1563 dst_b, SHF_SC_R_SHF, pre_shift); 1564 wrp_mul_u32(nfp_prog, dst_both, reg_none(), dst_a, magic, true); 1565 emit_shf(nfp_prog, dst_both, reg_none(), SHF_OP_NONE, 1566 dst_b, SHF_SC_R_SHF, rvalue.sh); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int adjust_head(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1573 { 1574 swreg tmp = imm_a(nfp_prog), tmp_len = imm_b(nfp_prog); 1575 struct nfp_bpf_cap_adjust_head *adjust_head; 1576 u32 ret_einval, end; 1577 1578 adjust_head = &nfp_prog->bpf->adjust_head; 1579 1580 /* Optimized version - 5 vs 14 cycles */ 1581 if (nfp_prog->adjust_head_location != UINT_MAX) { 1582 if (WARN_ON_ONCE(nfp_prog->adjust_head_location != meta->n)) 1583 return -EINVAL; 1584 1585 emit_alu(nfp_prog, pptr_reg(nfp_prog), 1586 reg_a(2 * 2), ALU_OP_ADD, pptr_reg(nfp_prog)); 1587 emit_alu(nfp_prog, plen_reg(nfp_prog), 1588 plen_reg(nfp_prog), ALU_OP_SUB, reg_a(2 * 2)); 1589 emit_alu(nfp_prog, pv_len(nfp_prog), 1590 pv_len(nfp_prog), ALU_OP_SUB, reg_a(2 * 2)); 1591 1592 wrp_immed(nfp_prog, reg_both(0), 0); 1593 wrp_immed(nfp_prog, reg_both(1), 0); 1594 1595 /* TODO: when adjust head is guaranteed to succeed we can 1596 * also eliminate the following if (r0 == 0) branch. 1597 */ 1598 1599 return 0; 1600 } 1601 1602 ret_einval = nfp_prog_current_offset(nfp_prog) + 14; 1603 end = ret_einval + 2; 1604 1605 /* We need to use a temp because offset is just a part of the pkt ptr */ 1606 emit_alu(nfp_prog, tmp, 1607 reg_a(2 * 2), ALU_OP_ADD_2B, pptr_reg(nfp_prog)); 1608 1609 /* Validate result will fit within FW datapath constraints */ 1610 emit_alu(nfp_prog, reg_none(), 1611 tmp, ALU_OP_SUB, reg_imm(adjust_head->off_min)); 1612 emit_br(nfp_prog, BR_BLO, ret_einval, 0); 1613 emit_alu(nfp_prog, reg_none(), 1614 reg_imm(adjust_head->off_max), ALU_OP_SUB, tmp); 1615 emit_br(nfp_prog, BR_BLO, ret_einval, 0); 1616 1617 /* Validate the length is at least ETH_HLEN */ 1618 emit_alu(nfp_prog, tmp_len, 1619 plen_reg(nfp_prog), ALU_OP_SUB, reg_a(2 * 2)); 1620 emit_alu(nfp_prog, reg_none(), 1621 tmp_len, ALU_OP_SUB, reg_imm(ETH_HLEN)); 1622 emit_br(nfp_prog, BR_BMI, ret_einval, 0); 1623 1624 /* Load the ret code */ 1625 wrp_immed(nfp_prog, reg_both(0), 0); 1626 wrp_immed(nfp_prog, reg_both(1), 0); 1627 1628 /* Modify the packet metadata */ 1629 emit_ld_field(nfp_prog, pptr_reg(nfp_prog), 0x3, tmp, SHF_SC_NONE, 0); 1630 1631 /* Skip over the -EINVAL ret code (defer 2) */ 1632 emit_br(nfp_prog, BR_UNC, end, 2); 1633 1634 emit_alu(nfp_prog, plen_reg(nfp_prog), 1635 plen_reg(nfp_prog), ALU_OP_SUB, reg_a(2 * 2)); 1636 emit_alu(nfp_prog, pv_len(nfp_prog), 1637 pv_len(nfp_prog), ALU_OP_SUB, reg_a(2 * 2)); 1638 1639 /* return -EINVAL target */ 1640 if (!nfp_prog_confirm_current_offset(nfp_prog, ret_einval)) 1641 return -EINVAL; 1642 1643 wrp_immed(nfp_prog, reg_both(0), -22); 1644 wrp_immed(nfp_prog, reg_both(1), ~0); 1645 1646 if (!nfp_prog_confirm_current_offset(nfp_prog, end)) 1647 return -EINVAL; 1648 1649 return 0; 1650 } 1651 1652 static int adjust_tail(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1653 { 1654 u32 ret_einval, end; 1655 swreg plen, delta; 1656 1657 BUILD_BUG_ON(plen_reg(nfp_prog) != reg_b(STATIC_REG_PKT_LEN)); 1658 1659 plen = imm_a(nfp_prog); 1660 delta = reg_a(2 * 2); 1661 1662 ret_einval = nfp_prog_current_offset(nfp_prog) + 9; 1663 end = nfp_prog_current_offset(nfp_prog) + 11; 1664 1665 /* Calculate resulting length */ 1666 emit_alu(nfp_prog, plen, plen_reg(nfp_prog), ALU_OP_ADD, delta); 1667 /* delta == 0 is not allowed by the kernel, add must overflow to make 1668 * length smaller. 1669 */ 1670 emit_br(nfp_prog, BR_BCC, ret_einval, 0); 1671 1672 /* if (new_len < 14) then -EINVAL */ 1673 emit_alu(nfp_prog, reg_none(), plen, ALU_OP_SUB, reg_imm(ETH_HLEN)); 1674 emit_br(nfp_prog, BR_BMI, ret_einval, 0); 1675 1676 emit_alu(nfp_prog, plen_reg(nfp_prog), 1677 plen_reg(nfp_prog), ALU_OP_ADD, delta); 1678 emit_alu(nfp_prog, pv_len(nfp_prog), 1679 pv_len(nfp_prog), ALU_OP_ADD, delta); 1680 1681 emit_br(nfp_prog, BR_UNC, end, 2); 1682 wrp_immed(nfp_prog, reg_both(0), 0); 1683 wrp_immed(nfp_prog, reg_both(1), 0); 1684 1685 if (!nfp_prog_confirm_current_offset(nfp_prog, ret_einval)) 1686 return -EINVAL; 1687 1688 wrp_immed(nfp_prog, reg_both(0), -22); 1689 wrp_immed(nfp_prog, reg_both(1), ~0); 1690 1691 if (!nfp_prog_confirm_current_offset(nfp_prog, end)) 1692 return -EINVAL; 1693 1694 return 0; 1695 } 1696 1697 static int 1698 map_call_stack_common(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1699 { 1700 bool load_lm_ptr; 1701 u32 ret_tgt; 1702 s64 lm_off; 1703 1704 /* We only have to reload LM0 if the key is not at start of stack */ 1705 lm_off = nfp_prog->stack_frame_depth; 1706 lm_off += meta->arg2.reg.var_off.value + meta->arg2.reg.off; 1707 load_lm_ptr = meta->arg2.var_off || lm_off; 1708 1709 /* Set LM0 to start of key */ 1710 if (load_lm_ptr) 1711 emit_csr_wr(nfp_prog, reg_b(2 * 2), NFP_CSR_ACT_LM_ADDR0); 1712 if (meta->func_id == BPF_FUNC_map_update_elem) 1713 emit_csr_wr(nfp_prog, reg_b(3 * 2), NFP_CSR_ACT_LM_ADDR2); 1714 1715 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO + meta->func_id, 1716 2, RELO_BR_HELPER); 1717 ret_tgt = nfp_prog_current_offset(nfp_prog) + 2; 1718 1719 /* Load map ID into A0 */ 1720 wrp_mov(nfp_prog, reg_a(0), reg_a(2)); 1721 1722 /* Load the return address into B0 */ 1723 wrp_immed_relo(nfp_prog, reg_b(0), ret_tgt, RELO_IMMED_REL); 1724 1725 if (!nfp_prog_confirm_current_offset(nfp_prog, ret_tgt)) 1726 return -EINVAL; 1727 1728 /* Reset the LM0 pointer */ 1729 if (!load_lm_ptr) 1730 return 0; 1731 1732 emit_csr_wr(nfp_prog, stack_reg(nfp_prog), NFP_CSR_ACT_LM_ADDR0); 1733 wrp_nops(nfp_prog, 3); 1734 1735 return 0; 1736 } 1737 1738 static int 1739 nfp_get_prandom_u32(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1740 { 1741 __emit_csr_rd(nfp_prog, NFP_CSR_PSEUDO_RND_NUM); 1742 /* CSR value is read in following immed[gpr, 0] */ 1743 emit_immed(nfp_prog, reg_both(0), 0, 1744 IMMED_WIDTH_ALL, false, IMMED_SHIFT_0B); 1745 emit_immed(nfp_prog, reg_both(1), 0, 1746 IMMED_WIDTH_ALL, false, IMMED_SHIFT_0B); 1747 return 0; 1748 } 1749 1750 static int 1751 nfp_perf_event_output(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1752 { 1753 swreg ptr_type; 1754 u32 ret_tgt; 1755 1756 ptr_type = ur_load_imm_any(nfp_prog, meta->arg1.type, imm_a(nfp_prog)); 1757 1758 ret_tgt = nfp_prog_current_offset(nfp_prog) + 3; 1759 1760 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO + meta->func_id, 1761 2, RELO_BR_HELPER); 1762 1763 /* Load ptr type into A1 */ 1764 wrp_mov(nfp_prog, reg_a(1), ptr_type); 1765 1766 /* Load the return address into B0 */ 1767 wrp_immed_relo(nfp_prog, reg_b(0), ret_tgt, RELO_IMMED_REL); 1768 1769 if (!nfp_prog_confirm_current_offset(nfp_prog, ret_tgt)) 1770 return -EINVAL; 1771 1772 return 0; 1773 } 1774 1775 static int 1776 nfp_queue_select(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1777 { 1778 u32 jmp_tgt; 1779 1780 jmp_tgt = nfp_prog_current_offset(nfp_prog) + 5; 1781 1782 /* Make sure the queue id fits into FW field */ 1783 emit_alu(nfp_prog, reg_none(), reg_a(meta->insn.src_reg * 2), 1784 ALU_OP_AND_NOT_B, reg_imm(0xff)); 1785 emit_br(nfp_prog, BR_BEQ, jmp_tgt, 2); 1786 1787 /* Set the 'queue selected' bit and the queue value */ 1788 emit_shf(nfp_prog, pv_qsel_set(nfp_prog), 1789 pv_qsel_set(nfp_prog), SHF_OP_OR, reg_imm(1), 1790 SHF_SC_L_SHF, PKT_VEL_QSEL_SET_BIT); 1791 emit_ld_field(nfp_prog, 1792 pv_qsel_val(nfp_prog), 0x1, reg_b(meta->insn.src_reg * 2), 1793 SHF_SC_NONE, 0); 1794 /* Delay slots end here, we will jump over next instruction if queue 1795 * value fits into the field. 1796 */ 1797 emit_ld_field(nfp_prog, 1798 pv_qsel_val(nfp_prog), 0x1, reg_imm(NFP_NET_RXR_MAX), 1799 SHF_SC_NONE, 0); 1800 1801 if (!nfp_prog_confirm_current_offset(nfp_prog, jmp_tgt)) 1802 return -EINVAL; 1803 1804 return 0; 1805 } 1806 1807 /* --- Callbacks --- */ 1808 static int mov_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1809 { 1810 const struct bpf_insn *insn = &meta->insn; 1811 u8 dst = insn->dst_reg * 2; 1812 u8 src = insn->src_reg * 2; 1813 1814 if (insn->src_reg == BPF_REG_10) { 1815 swreg stack_depth_reg; 1816 1817 stack_depth_reg = ur_load_imm_any(nfp_prog, 1818 nfp_prog->stack_frame_depth, 1819 stack_imm(nfp_prog)); 1820 emit_alu(nfp_prog, reg_both(dst), stack_reg(nfp_prog), 1821 ALU_OP_ADD, stack_depth_reg); 1822 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 1823 } else { 1824 wrp_reg_mov(nfp_prog, dst, src); 1825 wrp_reg_mov(nfp_prog, dst + 1, src + 1); 1826 } 1827 1828 return 0; 1829 } 1830 1831 static int mov_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1832 { 1833 u64 imm = meta->insn.imm; /* sign extend */ 1834 1835 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2), imm & ~0U); 1836 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), imm >> 32); 1837 1838 return 0; 1839 } 1840 1841 static int xor_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1842 { 1843 return wrp_alu64_reg(nfp_prog, meta, ALU_OP_XOR); 1844 } 1845 1846 static int xor_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1847 { 1848 return wrp_alu64_imm(nfp_prog, meta, ALU_OP_XOR, !meta->insn.imm); 1849 } 1850 1851 static int and_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1852 { 1853 return wrp_alu64_reg(nfp_prog, meta, ALU_OP_AND); 1854 } 1855 1856 static int and_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1857 { 1858 return wrp_alu64_imm(nfp_prog, meta, ALU_OP_AND, !~meta->insn.imm); 1859 } 1860 1861 static int or_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1862 { 1863 return wrp_alu64_reg(nfp_prog, meta, ALU_OP_OR); 1864 } 1865 1866 static int or_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1867 { 1868 return wrp_alu64_imm(nfp_prog, meta, ALU_OP_OR, !meta->insn.imm); 1869 } 1870 1871 static int add_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1872 { 1873 const struct bpf_insn *insn = &meta->insn; 1874 1875 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2), 1876 reg_a(insn->dst_reg * 2), ALU_OP_ADD, 1877 reg_b(insn->src_reg * 2)); 1878 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 1879 reg_a(insn->dst_reg * 2 + 1), ALU_OP_ADD_C, 1880 reg_b(insn->src_reg * 2 + 1)); 1881 1882 return 0; 1883 } 1884 1885 static int add_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1886 { 1887 const struct bpf_insn *insn = &meta->insn; 1888 u64 imm = insn->imm; /* sign extend */ 1889 1890 wrp_alu_imm(nfp_prog, insn->dst_reg * 2, ALU_OP_ADD, imm & ~0U); 1891 wrp_alu_imm(nfp_prog, insn->dst_reg * 2 + 1, ALU_OP_ADD_C, imm >> 32); 1892 1893 return 0; 1894 } 1895 1896 static int sub_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1897 { 1898 const struct bpf_insn *insn = &meta->insn; 1899 1900 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2), 1901 reg_a(insn->dst_reg * 2), ALU_OP_SUB, 1902 reg_b(insn->src_reg * 2)); 1903 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 1904 reg_a(insn->dst_reg * 2 + 1), ALU_OP_SUB_C, 1905 reg_b(insn->src_reg * 2 + 1)); 1906 1907 return 0; 1908 } 1909 1910 static int sub_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1911 { 1912 const struct bpf_insn *insn = &meta->insn; 1913 u64 imm = insn->imm; /* sign extend */ 1914 1915 wrp_alu_imm(nfp_prog, insn->dst_reg * 2, ALU_OP_SUB, imm & ~0U); 1916 wrp_alu_imm(nfp_prog, insn->dst_reg * 2 + 1, ALU_OP_SUB_C, imm >> 32); 1917 1918 return 0; 1919 } 1920 1921 static int mul_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1922 { 1923 return wrp_mul(nfp_prog, meta, true, true); 1924 } 1925 1926 static int mul_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1927 { 1928 return wrp_mul(nfp_prog, meta, true, false); 1929 } 1930 1931 static int div_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1932 { 1933 const struct bpf_insn *insn = &meta->insn; 1934 1935 return wrp_div_imm(nfp_prog, insn->dst_reg * 2, insn->imm); 1936 } 1937 1938 static int div_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1939 { 1940 /* NOTE: verifier hook has rejected cases for which verifier doesn't 1941 * know whether the source operand is constant or not. 1942 */ 1943 return wrp_div_imm(nfp_prog, meta->insn.dst_reg * 2, meta->umin_src); 1944 } 1945 1946 static int neg_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1947 { 1948 const struct bpf_insn *insn = &meta->insn; 1949 1950 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2), reg_imm(0), 1951 ALU_OP_SUB, reg_b(insn->dst_reg * 2)); 1952 emit_alu(nfp_prog, reg_both(insn->dst_reg * 2 + 1), reg_imm(0), 1953 ALU_OP_SUB_C, reg_b(insn->dst_reg * 2 + 1)); 1954 1955 return 0; 1956 } 1957 1958 /* Pseudo code: 1959 * if shift_amt >= 32 1960 * dst_high = dst_low << shift_amt[4:0] 1961 * dst_low = 0; 1962 * else 1963 * dst_high = (dst_high, dst_low) >> (32 - shift_amt) 1964 * dst_low = dst_low << shift_amt 1965 * 1966 * The indirect shift will use the same logic at runtime. 1967 */ 1968 static int __shl_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 1969 { 1970 if (!shift_amt) 1971 return 0; 1972 1973 if (shift_amt < 32) { 1974 emit_shf(nfp_prog, reg_both(dst + 1), reg_a(dst + 1), 1975 SHF_OP_NONE, reg_b(dst), SHF_SC_R_DSHF, 1976 32 - shift_amt); 1977 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 1978 reg_b(dst), SHF_SC_L_SHF, shift_amt); 1979 } else if (shift_amt == 32) { 1980 wrp_reg_mov(nfp_prog, dst + 1, dst); 1981 wrp_immed(nfp_prog, reg_both(dst), 0); 1982 } else if (shift_amt > 32) { 1983 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_NONE, 1984 reg_b(dst), SHF_SC_L_SHF, shift_amt - 32); 1985 wrp_immed(nfp_prog, reg_both(dst), 0); 1986 } 1987 1988 return 0; 1989 } 1990 1991 static int shl_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 1992 { 1993 const struct bpf_insn *insn = &meta->insn; 1994 u8 dst = insn->dst_reg * 2; 1995 1996 return __shl_imm64(nfp_prog, dst, insn->imm); 1997 } 1998 1999 static void shl_reg64_lt32_high(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2000 { 2001 emit_alu(nfp_prog, imm_both(nfp_prog), reg_imm(32), ALU_OP_SUB, 2002 reg_b(src)); 2003 emit_alu(nfp_prog, reg_none(), imm_a(nfp_prog), ALU_OP_OR, reg_imm(0)); 2004 emit_shf_indir(nfp_prog, reg_both(dst + 1), reg_a(dst + 1), SHF_OP_NONE, 2005 reg_b(dst), SHF_SC_R_DSHF); 2006 } 2007 2008 /* NOTE: for indirect left shift, HIGH part should be calculated first. */ 2009 static void shl_reg64_lt32_low(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2010 { 2011 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2012 emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2013 reg_b(dst), SHF_SC_L_SHF); 2014 } 2015 2016 static void shl_reg64_lt32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2017 { 2018 shl_reg64_lt32_high(nfp_prog, dst, src); 2019 shl_reg64_lt32_low(nfp_prog, dst, src); 2020 } 2021 2022 static void shl_reg64_ge32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2023 { 2024 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2025 emit_shf_indir(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_NONE, 2026 reg_b(dst), SHF_SC_L_SHF); 2027 wrp_immed(nfp_prog, reg_both(dst), 0); 2028 } 2029 2030 static int shl_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2031 { 2032 const struct bpf_insn *insn = &meta->insn; 2033 u64 umin, umax; 2034 u8 dst, src; 2035 2036 dst = insn->dst_reg * 2; 2037 umin = meta->umin_src; 2038 umax = meta->umax_src; 2039 if (umin == umax) 2040 return __shl_imm64(nfp_prog, dst, umin); 2041 2042 src = insn->src_reg * 2; 2043 if (umax < 32) { 2044 shl_reg64_lt32(nfp_prog, dst, src); 2045 } else if (umin >= 32) { 2046 shl_reg64_ge32(nfp_prog, dst, src); 2047 } else { 2048 /* Generate different instruction sequences depending on runtime 2049 * value of shift amount. 2050 */ 2051 u16 label_ge32, label_end; 2052 2053 label_ge32 = nfp_prog_current_offset(nfp_prog) + 7; 2054 emit_br_bset(nfp_prog, reg_a(src), 5, label_ge32, 0); 2055 2056 shl_reg64_lt32_high(nfp_prog, dst, src); 2057 label_end = nfp_prog_current_offset(nfp_prog) + 6; 2058 emit_br(nfp_prog, BR_UNC, label_end, 2); 2059 /* shl_reg64_lt32_low packed in delay slot. */ 2060 shl_reg64_lt32_low(nfp_prog, dst, src); 2061 2062 if (!nfp_prog_confirm_current_offset(nfp_prog, label_ge32)) 2063 return -EINVAL; 2064 shl_reg64_ge32(nfp_prog, dst, src); 2065 2066 if (!nfp_prog_confirm_current_offset(nfp_prog, label_end)) 2067 return -EINVAL; 2068 } 2069 2070 return 0; 2071 } 2072 2073 /* Pseudo code: 2074 * if shift_amt >= 32 2075 * dst_high = 0; 2076 * dst_low = dst_high >> shift_amt[4:0] 2077 * else 2078 * dst_high = dst_high >> shift_amt 2079 * dst_low = (dst_high, dst_low) >> shift_amt 2080 * 2081 * The indirect shift will use the same logic at runtime. 2082 */ 2083 static int __shr_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 2084 { 2085 if (!shift_amt) 2086 return 0; 2087 2088 if (shift_amt < 32) { 2089 emit_shf(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE, 2090 reg_b(dst), SHF_SC_R_DSHF, shift_amt); 2091 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_NONE, 2092 reg_b(dst + 1), SHF_SC_R_SHF, shift_amt); 2093 } else if (shift_amt == 32) { 2094 wrp_reg_mov(nfp_prog, dst, dst + 1); 2095 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2096 } else if (shift_amt > 32) { 2097 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2098 reg_b(dst + 1), SHF_SC_R_SHF, shift_amt - 32); 2099 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2100 } 2101 2102 return 0; 2103 } 2104 2105 static int shr_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2106 { 2107 const struct bpf_insn *insn = &meta->insn; 2108 u8 dst = insn->dst_reg * 2; 2109 2110 return __shr_imm64(nfp_prog, dst, insn->imm); 2111 } 2112 2113 /* NOTE: for indirect right shift, LOW part should be calculated first. */ 2114 static void shr_reg64_lt32_high(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2115 { 2116 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2117 emit_shf_indir(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_NONE, 2118 reg_b(dst + 1), SHF_SC_R_SHF); 2119 } 2120 2121 static void shr_reg64_lt32_low(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2122 { 2123 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2124 emit_shf_indir(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE, 2125 reg_b(dst), SHF_SC_R_DSHF); 2126 } 2127 2128 static void shr_reg64_lt32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2129 { 2130 shr_reg64_lt32_low(nfp_prog, dst, src); 2131 shr_reg64_lt32_high(nfp_prog, dst, src); 2132 } 2133 2134 static void shr_reg64_ge32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2135 { 2136 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2137 emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2138 reg_b(dst + 1), SHF_SC_R_SHF); 2139 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2140 } 2141 2142 static int shr_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2143 { 2144 const struct bpf_insn *insn = &meta->insn; 2145 u64 umin, umax; 2146 u8 dst, src; 2147 2148 dst = insn->dst_reg * 2; 2149 umin = meta->umin_src; 2150 umax = meta->umax_src; 2151 if (umin == umax) 2152 return __shr_imm64(nfp_prog, dst, umin); 2153 2154 src = insn->src_reg * 2; 2155 if (umax < 32) { 2156 shr_reg64_lt32(nfp_prog, dst, src); 2157 } else if (umin >= 32) { 2158 shr_reg64_ge32(nfp_prog, dst, src); 2159 } else { 2160 /* Generate different instruction sequences depending on runtime 2161 * value of shift amount. 2162 */ 2163 u16 label_ge32, label_end; 2164 2165 label_ge32 = nfp_prog_current_offset(nfp_prog) + 6; 2166 emit_br_bset(nfp_prog, reg_a(src), 5, label_ge32, 0); 2167 shr_reg64_lt32_low(nfp_prog, dst, src); 2168 label_end = nfp_prog_current_offset(nfp_prog) + 6; 2169 emit_br(nfp_prog, BR_UNC, label_end, 2); 2170 /* shr_reg64_lt32_high packed in delay slot. */ 2171 shr_reg64_lt32_high(nfp_prog, dst, src); 2172 2173 if (!nfp_prog_confirm_current_offset(nfp_prog, label_ge32)) 2174 return -EINVAL; 2175 shr_reg64_ge32(nfp_prog, dst, src); 2176 2177 if (!nfp_prog_confirm_current_offset(nfp_prog, label_end)) 2178 return -EINVAL; 2179 } 2180 2181 return 0; 2182 } 2183 2184 /* Code logic is the same as __shr_imm64 except ashr requires signedness bit 2185 * told through PREV_ALU result. 2186 */ 2187 static int __ashr_imm64(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 2188 { 2189 if (!shift_amt) 2190 return 0; 2191 2192 if (shift_amt < 32) { 2193 emit_shf(nfp_prog, reg_both(dst), reg_a(dst + 1), SHF_OP_NONE, 2194 reg_b(dst), SHF_SC_R_DSHF, shift_amt); 2195 /* Set signedness bit. */ 2196 emit_alu(nfp_prog, reg_none(), reg_a(dst + 1), ALU_OP_OR, 2197 reg_imm(0)); 2198 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR, 2199 reg_b(dst + 1), SHF_SC_R_SHF, shift_amt); 2200 } else if (shift_amt == 32) { 2201 /* NOTE: this also helps setting signedness bit. */ 2202 wrp_reg_mov(nfp_prog, dst, dst + 1); 2203 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR, 2204 reg_b(dst + 1), SHF_SC_R_SHF, 31); 2205 } else if (shift_amt > 32) { 2206 emit_alu(nfp_prog, reg_none(), reg_a(dst + 1), ALU_OP_OR, 2207 reg_imm(0)); 2208 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, 2209 reg_b(dst + 1), SHF_SC_R_SHF, shift_amt - 32); 2210 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR, 2211 reg_b(dst + 1), SHF_SC_R_SHF, 31); 2212 } 2213 2214 return 0; 2215 } 2216 2217 static int ashr_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2218 { 2219 const struct bpf_insn *insn = &meta->insn; 2220 u8 dst = insn->dst_reg * 2; 2221 2222 return __ashr_imm64(nfp_prog, dst, insn->imm); 2223 } 2224 2225 static void ashr_reg64_lt32_high(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2226 { 2227 /* NOTE: the first insn will set both indirect shift amount (source A) 2228 * and signedness bit (MSB of result). 2229 */ 2230 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst + 1)); 2231 emit_shf_indir(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR, 2232 reg_b(dst + 1), SHF_SC_R_SHF); 2233 } 2234 2235 static void ashr_reg64_lt32_low(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2236 { 2237 /* NOTE: it is the same as logic shift because we don't need to shift in 2238 * signedness bit when the shift amount is less than 32. 2239 */ 2240 return shr_reg64_lt32_low(nfp_prog, dst, src); 2241 } 2242 2243 static void ashr_reg64_lt32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2244 { 2245 ashr_reg64_lt32_low(nfp_prog, dst, src); 2246 ashr_reg64_lt32_high(nfp_prog, dst, src); 2247 } 2248 2249 static void ashr_reg64_ge32(struct nfp_prog *nfp_prog, u8 dst, u8 src) 2250 { 2251 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst + 1)); 2252 emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, 2253 reg_b(dst + 1), SHF_SC_R_SHF); 2254 emit_shf(nfp_prog, reg_both(dst + 1), reg_none(), SHF_OP_ASHR, 2255 reg_b(dst + 1), SHF_SC_R_SHF, 31); 2256 } 2257 2258 /* Like ashr_imm64, but need to use indirect shift. */ 2259 static int ashr_reg64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2260 { 2261 const struct bpf_insn *insn = &meta->insn; 2262 u64 umin, umax; 2263 u8 dst, src; 2264 2265 dst = insn->dst_reg * 2; 2266 umin = meta->umin_src; 2267 umax = meta->umax_src; 2268 if (umin == umax) 2269 return __ashr_imm64(nfp_prog, dst, umin); 2270 2271 src = insn->src_reg * 2; 2272 if (umax < 32) { 2273 ashr_reg64_lt32(nfp_prog, dst, src); 2274 } else if (umin >= 32) { 2275 ashr_reg64_ge32(nfp_prog, dst, src); 2276 } else { 2277 u16 label_ge32, label_end; 2278 2279 label_ge32 = nfp_prog_current_offset(nfp_prog) + 6; 2280 emit_br_bset(nfp_prog, reg_a(src), 5, label_ge32, 0); 2281 ashr_reg64_lt32_low(nfp_prog, dst, src); 2282 label_end = nfp_prog_current_offset(nfp_prog) + 6; 2283 emit_br(nfp_prog, BR_UNC, label_end, 2); 2284 /* ashr_reg64_lt32_high packed in delay slot. */ 2285 ashr_reg64_lt32_high(nfp_prog, dst, src); 2286 2287 if (!nfp_prog_confirm_current_offset(nfp_prog, label_ge32)) 2288 return -EINVAL; 2289 ashr_reg64_ge32(nfp_prog, dst, src); 2290 2291 if (!nfp_prog_confirm_current_offset(nfp_prog, label_end)) 2292 return -EINVAL; 2293 } 2294 2295 return 0; 2296 } 2297 2298 static int mov_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2299 { 2300 const struct bpf_insn *insn = &meta->insn; 2301 2302 wrp_reg_mov(nfp_prog, insn->dst_reg * 2, insn->src_reg * 2); 2303 wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0); 2304 2305 return 0; 2306 } 2307 2308 static int mov_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2309 { 2310 const struct bpf_insn *insn = &meta->insn; 2311 2312 wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2), insn->imm); 2313 wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0); 2314 2315 return 0; 2316 } 2317 2318 static int xor_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2319 { 2320 return wrp_alu32_reg(nfp_prog, meta, ALU_OP_XOR); 2321 } 2322 2323 static int xor_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2324 { 2325 return wrp_alu32_imm(nfp_prog, meta, ALU_OP_XOR, !~meta->insn.imm); 2326 } 2327 2328 static int and_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2329 { 2330 return wrp_alu32_reg(nfp_prog, meta, ALU_OP_AND); 2331 } 2332 2333 static int and_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2334 { 2335 return wrp_alu32_imm(nfp_prog, meta, ALU_OP_AND, !~meta->insn.imm); 2336 } 2337 2338 static int or_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2339 { 2340 return wrp_alu32_reg(nfp_prog, meta, ALU_OP_OR); 2341 } 2342 2343 static int or_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2344 { 2345 return wrp_alu32_imm(nfp_prog, meta, ALU_OP_OR, !meta->insn.imm); 2346 } 2347 2348 static int add_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2349 { 2350 return wrp_alu32_reg(nfp_prog, meta, ALU_OP_ADD); 2351 } 2352 2353 static int add_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2354 { 2355 return wrp_alu32_imm(nfp_prog, meta, ALU_OP_ADD, !meta->insn.imm); 2356 } 2357 2358 static int sub_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2359 { 2360 return wrp_alu32_reg(nfp_prog, meta, ALU_OP_SUB); 2361 } 2362 2363 static int sub_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2364 { 2365 return wrp_alu32_imm(nfp_prog, meta, ALU_OP_SUB, !meta->insn.imm); 2366 } 2367 2368 static int mul_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2369 { 2370 return wrp_mul(nfp_prog, meta, false, true); 2371 } 2372 2373 static int mul_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2374 { 2375 return wrp_mul(nfp_prog, meta, false, false); 2376 } 2377 2378 static int div_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2379 { 2380 return div_reg64(nfp_prog, meta); 2381 } 2382 2383 static int div_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2384 { 2385 return div_imm64(nfp_prog, meta); 2386 } 2387 2388 static int neg_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2389 { 2390 u8 dst = meta->insn.dst_reg * 2; 2391 2392 emit_alu(nfp_prog, reg_both(dst), reg_imm(0), ALU_OP_SUB, reg_b(dst)); 2393 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 0); 2394 2395 return 0; 2396 } 2397 2398 static int __ashr_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 2399 { 2400 if (shift_amt) { 2401 /* Set signedness bit (MSB of result). */ 2402 emit_alu(nfp_prog, reg_none(), reg_a(dst), ALU_OP_OR, 2403 reg_imm(0)); 2404 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, 2405 reg_b(dst), SHF_SC_R_SHF, shift_amt); 2406 } 2407 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2408 2409 return 0; 2410 } 2411 2412 static int ashr_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2413 { 2414 const struct bpf_insn *insn = &meta->insn; 2415 u64 umin, umax; 2416 u8 dst, src; 2417 2418 dst = insn->dst_reg * 2; 2419 umin = meta->umin_src; 2420 umax = meta->umax_src; 2421 if (umin == umax) 2422 return __ashr_imm(nfp_prog, dst, umin); 2423 2424 src = insn->src_reg * 2; 2425 /* NOTE: the first insn will set both indirect shift amount (source A) 2426 * and signedness bit (MSB of result). 2427 */ 2428 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_b(dst)); 2429 emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_ASHR, 2430 reg_b(dst), SHF_SC_R_SHF); 2431 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2432 2433 return 0; 2434 } 2435 2436 static int ashr_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2437 { 2438 const struct bpf_insn *insn = &meta->insn; 2439 u8 dst = insn->dst_reg * 2; 2440 2441 return __ashr_imm(nfp_prog, dst, insn->imm); 2442 } 2443 2444 static int __shr_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 2445 { 2446 if (shift_amt) 2447 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2448 reg_b(dst), SHF_SC_R_SHF, shift_amt); 2449 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2450 return 0; 2451 } 2452 2453 static int shr_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2454 { 2455 const struct bpf_insn *insn = &meta->insn; 2456 u8 dst = insn->dst_reg * 2; 2457 2458 return __shr_imm(nfp_prog, dst, insn->imm); 2459 } 2460 2461 static int shr_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2462 { 2463 const struct bpf_insn *insn = &meta->insn; 2464 u64 umin, umax; 2465 u8 dst, src; 2466 2467 dst = insn->dst_reg * 2; 2468 umin = meta->umin_src; 2469 umax = meta->umax_src; 2470 if (umin == umax) 2471 return __shr_imm(nfp_prog, dst, umin); 2472 2473 src = insn->src_reg * 2; 2474 emit_alu(nfp_prog, reg_none(), reg_a(src), ALU_OP_OR, reg_imm(0)); 2475 emit_shf_indir(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2476 reg_b(dst), SHF_SC_R_SHF); 2477 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2478 return 0; 2479 } 2480 2481 static int __shl_imm(struct nfp_prog *nfp_prog, u8 dst, u8 shift_amt) 2482 { 2483 if (shift_amt) 2484 emit_shf(nfp_prog, reg_both(dst), reg_none(), SHF_OP_NONE, 2485 reg_b(dst), SHF_SC_L_SHF, shift_amt); 2486 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2487 return 0; 2488 } 2489 2490 static int shl_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2491 { 2492 const struct bpf_insn *insn = &meta->insn; 2493 u8 dst = insn->dst_reg * 2; 2494 2495 return __shl_imm(nfp_prog, dst, insn->imm); 2496 } 2497 2498 static int shl_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2499 { 2500 const struct bpf_insn *insn = &meta->insn; 2501 u64 umin, umax; 2502 u8 dst, src; 2503 2504 dst = insn->dst_reg * 2; 2505 umin = meta->umin_src; 2506 umax = meta->umax_src; 2507 if (umin == umax) 2508 return __shl_imm(nfp_prog, dst, umin); 2509 2510 src = insn->src_reg * 2; 2511 shl_reg64_lt32_low(nfp_prog, dst, src); 2512 wrp_immed(nfp_prog, reg_both(dst + 1), 0); 2513 return 0; 2514 } 2515 2516 static int end_reg32(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2517 { 2518 const struct bpf_insn *insn = &meta->insn; 2519 u8 gpr = insn->dst_reg * 2; 2520 2521 switch (insn->imm) { 2522 case 16: 2523 emit_ld_field(nfp_prog, reg_both(gpr), 0x9, reg_b(gpr), 2524 SHF_SC_R_ROT, 8); 2525 emit_ld_field(nfp_prog, reg_both(gpr), 0xe, reg_a(gpr), 2526 SHF_SC_R_SHF, 16); 2527 2528 wrp_immed(nfp_prog, reg_both(gpr + 1), 0); 2529 break; 2530 case 32: 2531 wrp_end32(nfp_prog, reg_a(gpr), gpr); 2532 wrp_immed(nfp_prog, reg_both(gpr + 1), 0); 2533 break; 2534 case 64: 2535 wrp_mov(nfp_prog, imm_a(nfp_prog), reg_b(gpr + 1)); 2536 2537 wrp_end32(nfp_prog, reg_a(gpr), gpr + 1); 2538 wrp_end32(nfp_prog, imm_a(nfp_prog), gpr); 2539 break; 2540 } 2541 2542 return 0; 2543 } 2544 2545 static int imm_ld8_part2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2546 { 2547 struct nfp_insn_meta *prev = nfp_meta_prev(meta); 2548 u32 imm_lo, imm_hi; 2549 u8 dst; 2550 2551 dst = prev->insn.dst_reg * 2; 2552 imm_lo = prev->insn.imm; 2553 imm_hi = meta->insn.imm; 2554 2555 wrp_immed(nfp_prog, reg_both(dst), imm_lo); 2556 2557 /* mov is always 1 insn, load imm may be two, so try to use mov */ 2558 if (imm_hi == imm_lo) 2559 wrp_mov(nfp_prog, reg_both(dst + 1), reg_a(dst)); 2560 else 2561 wrp_immed(nfp_prog, reg_both(dst + 1), imm_hi); 2562 2563 return 0; 2564 } 2565 2566 static int imm_ld8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2567 { 2568 meta->double_cb = imm_ld8_part2; 2569 return 0; 2570 } 2571 2572 static int data_ld1(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2573 { 2574 return construct_data_ld(nfp_prog, meta->insn.imm, 1); 2575 } 2576 2577 static int data_ld2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2578 { 2579 return construct_data_ld(nfp_prog, meta->insn.imm, 2); 2580 } 2581 2582 static int data_ld4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2583 { 2584 return construct_data_ld(nfp_prog, meta->insn.imm, 4); 2585 } 2586 2587 static int data_ind_ld1(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2588 { 2589 return construct_data_ind_ld(nfp_prog, meta->insn.imm, 2590 meta->insn.src_reg * 2, 1); 2591 } 2592 2593 static int data_ind_ld2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2594 { 2595 return construct_data_ind_ld(nfp_prog, meta->insn.imm, 2596 meta->insn.src_reg * 2, 2); 2597 } 2598 2599 static int data_ind_ld4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2600 { 2601 return construct_data_ind_ld(nfp_prog, meta->insn.imm, 2602 meta->insn.src_reg * 2, 4); 2603 } 2604 2605 static int 2606 mem_ldx_stack(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2607 unsigned int size, unsigned int ptr_off) 2608 { 2609 return mem_op_stack(nfp_prog, meta, size, ptr_off, 2610 meta->insn.dst_reg * 2, meta->insn.src_reg * 2, 2611 true, wrp_lmem_load); 2612 } 2613 2614 static int mem_ldx_skb(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2615 u8 size) 2616 { 2617 swreg dst = reg_both(meta->insn.dst_reg * 2); 2618 2619 switch (meta->insn.off) { 2620 case offsetof(struct __sk_buff, len): 2621 if (size != FIELD_SIZEOF(struct __sk_buff, len)) 2622 return -EOPNOTSUPP; 2623 wrp_mov(nfp_prog, dst, plen_reg(nfp_prog)); 2624 break; 2625 case offsetof(struct __sk_buff, data): 2626 if (size != FIELD_SIZEOF(struct __sk_buff, data)) 2627 return -EOPNOTSUPP; 2628 wrp_mov(nfp_prog, dst, pptr_reg(nfp_prog)); 2629 break; 2630 case offsetof(struct __sk_buff, data_end): 2631 if (size != FIELD_SIZEOF(struct __sk_buff, data_end)) 2632 return -EOPNOTSUPP; 2633 emit_alu(nfp_prog, dst, 2634 plen_reg(nfp_prog), ALU_OP_ADD, pptr_reg(nfp_prog)); 2635 break; 2636 default: 2637 return -EOPNOTSUPP; 2638 } 2639 2640 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 0); 2641 2642 return 0; 2643 } 2644 2645 static int mem_ldx_xdp(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2646 u8 size) 2647 { 2648 swreg dst = reg_both(meta->insn.dst_reg * 2); 2649 2650 switch (meta->insn.off) { 2651 case offsetof(struct xdp_md, data): 2652 if (size != FIELD_SIZEOF(struct xdp_md, data)) 2653 return -EOPNOTSUPP; 2654 wrp_mov(nfp_prog, dst, pptr_reg(nfp_prog)); 2655 break; 2656 case offsetof(struct xdp_md, data_end): 2657 if (size != FIELD_SIZEOF(struct xdp_md, data_end)) 2658 return -EOPNOTSUPP; 2659 emit_alu(nfp_prog, dst, 2660 plen_reg(nfp_prog), ALU_OP_ADD, pptr_reg(nfp_prog)); 2661 break; 2662 default: 2663 return -EOPNOTSUPP; 2664 } 2665 2666 wrp_immed(nfp_prog, reg_both(meta->insn.dst_reg * 2 + 1), 0); 2667 2668 return 0; 2669 } 2670 2671 static int 2672 mem_ldx_data(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2673 unsigned int size) 2674 { 2675 swreg tmp_reg; 2676 2677 tmp_reg = re_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 2678 2679 return data_ld_host_order_addr32(nfp_prog, meta->insn.src_reg * 2, 2680 tmp_reg, meta->insn.dst_reg * 2, size); 2681 } 2682 2683 static int 2684 mem_ldx_emem(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2685 unsigned int size) 2686 { 2687 swreg tmp_reg; 2688 2689 tmp_reg = re_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 2690 2691 return data_ld_host_order_addr40(nfp_prog, meta->insn.src_reg * 2, 2692 tmp_reg, meta->insn.dst_reg * 2, size); 2693 } 2694 2695 static void 2696 mem_ldx_data_init_pktcache(struct nfp_prog *nfp_prog, 2697 struct nfp_insn_meta *meta) 2698 { 2699 s16 range_start = meta->pkt_cache.range_start; 2700 s16 range_end = meta->pkt_cache.range_end; 2701 swreg src_base, off; 2702 u8 xfer_num, len; 2703 bool indir; 2704 2705 off = re_load_imm_any(nfp_prog, range_start, imm_b(nfp_prog)); 2706 src_base = reg_a(meta->insn.src_reg * 2); 2707 len = range_end - range_start; 2708 xfer_num = round_up(len, REG_WIDTH) / REG_WIDTH; 2709 2710 indir = len > 8 * REG_WIDTH; 2711 /* Setup PREV_ALU for indirect mode. */ 2712 if (indir) 2713 wrp_immed(nfp_prog, reg_none(), 2714 CMD_OVE_LEN | FIELD_PREP(CMD_OV_LEN, xfer_num - 1)); 2715 2716 /* Cache memory into transfer-in registers. */ 2717 emit_cmd_any(nfp_prog, CMD_TGT_READ32_SWAP, CMD_MODE_32b, 0, src_base, 2718 off, xfer_num - 1, CMD_CTX_SWAP, indir); 2719 } 2720 2721 static int 2722 mem_ldx_data_from_pktcache_unaligned(struct nfp_prog *nfp_prog, 2723 struct nfp_insn_meta *meta, 2724 unsigned int size) 2725 { 2726 s16 range_start = meta->pkt_cache.range_start; 2727 s16 insn_off = meta->insn.off - range_start; 2728 swreg dst_lo, dst_hi, src_lo, src_mid; 2729 u8 dst_gpr = meta->insn.dst_reg * 2; 2730 u8 len_lo = size, len_mid = 0; 2731 u8 idx = insn_off / REG_WIDTH; 2732 u8 off = insn_off % REG_WIDTH; 2733 2734 dst_hi = reg_both(dst_gpr + 1); 2735 dst_lo = reg_both(dst_gpr); 2736 src_lo = reg_xfer(idx); 2737 2738 /* The read length could involve as many as three registers. */ 2739 if (size > REG_WIDTH - off) { 2740 /* Calculate the part in the second register. */ 2741 len_lo = REG_WIDTH - off; 2742 len_mid = size - len_lo; 2743 2744 /* Calculate the part in the third register. */ 2745 if (size > 2 * REG_WIDTH - off) 2746 len_mid = REG_WIDTH; 2747 } 2748 2749 wrp_reg_subpart(nfp_prog, dst_lo, src_lo, len_lo, off); 2750 2751 if (!len_mid) { 2752 wrp_immed(nfp_prog, dst_hi, 0); 2753 return 0; 2754 } 2755 2756 src_mid = reg_xfer(idx + 1); 2757 2758 if (size <= REG_WIDTH) { 2759 wrp_reg_or_subpart(nfp_prog, dst_lo, src_mid, len_mid, len_lo); 2760 wrp_immed(nfp_prog, dst_hi, 0); 2761 } else { 2762 swreg src_hi = reg_xfer(idx + 2); 2763 2764 wrp_reg_or_subpart(nfp_prog, dst_lo, src_mid, 2765 REG_WIDTH - len_lo, len_lo); 2766 wrp_reg_subpart(nfp_prog, dst_hi, src_mid, len_lo, 2767 REG_WIDTH - len_lo); 2768 wrp_reg_or_subpart(nfp_prog, dst_hi, src_hi, REG_WIDTH - len_lo, 2769 len_lo); 2770 } 2771 2772 return 0; 2773 } 2774 2775 static int 2776 mem_ldx_data_from_pktcache_aligned(struct nfp_prog *nfp_prog, 2777 struct nfp_insn_meta *meta, 2778 unsigned int size) 2779 { 2780 swreg dst_lo, dst_hi, src_lo; 2781 u8 dst_gpr, idx; 2782 2783 idx = (meta->insn.off - meta->pkt_cache.range_start) / REG_WIDTH; 2784 dst_gpr = meta->insn.dst_reg * 2; 2785 dst_hi = reg_both(dst_gpr + 1); 2786 dst_lo = reg_both(dst_gpr); 2787 src_lo = reg_xfer(idx); 2788 2789 if (size < REG_WIDTH) { 2790 wrp_reg_subpart(nfp_prog, dst_lo, src_lo, size, 0); 2791 wrp_immed(nfp_prog, dst_hi, 0); 2792 } else if (size == REG_WIDTH) { 2793 wrp_mov(nfp_prog, dst_lo, src_lo); 2794 wrp_immed(nfp_prog, dst_hi, 0); 2795 } else { 2796 swreg src_hi = reg_xfer(idx + 1); 2797 2798 wrp_mov(nfp_prog, dst_lo, src_lo); 2799 wrp_mov(nfp_prog, dst_hi, src_hi); 2800 } 2801 2802 return 0; 2803 } 2804 2805 static int 2806 mem_ldx_data_from_pktcache(struct nfp_prog *nfp_prog, 2807 struct nfp_insn_meta *meta, unsigned int size) 2808 { 2809 u8 off = meta->insn.off - meta->pkt_cache.range_start; 2810 2811 if (IS_ALIGNED(off, REG_WIDTH)) 2812 return mem_ldx_data_from_pktcache_aligned(nfp_prog, meta, size); 2813 2814 return mem_ldx_data_from_pktcache_unaligned(nfp_prog, meta, size); 2815 } 2816 2817 static int 2818 mem_ldx(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2819 unsigned int size) 2820 { 2821 if (meta->ldst_gather_len) 2822 return nfp_cpp_memcpy(nfp_prog, meta); 2823 2824 if (meta->ptr.type == PTR_TO_CTX) { 2825 if (nfp_prog->type == BPF_PROG_TYPE_XDP) 2826 return mem_ldx_xdp(nfp_prog, meta, size); 2827 else 2828 return mem_ldx_skb(nfp_prog, meta, size); 2829 } 2830 2831 if (meta->ptr.type == PTR_TO_PACKET) { 2832 if (meta->pkt_cache.range_end) { 2833 if (meta->pkt_cache.do_init) 2834 mem_ldx_data_init_pktcache(nfp_prog, meta); 2835 2836 return mem_ldx_data_from_pktcache(nfp_prog, meta, size); 2837 } else { 2838 return mem_ldx_data(nfp_prog, meta, size); 2839 } 2840 } 2841 2842 if (meta->ptr.type == PTR_TO_STACK) 2843 return mem_ldx_stack(nfp_prog, meta, size, 2844 meta->ptr.off + meta->ptr.var_off.value); 2845 2846 if (meta->ptr.type == PTR_TO_MAP_VALUE) 2847 return mem_ldx_emem(nfp_prog, meta, size); 2848 2849 return -EOPNOTSUPP; 2850 } 2851 2852 static int mem_ldx1(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2853 { 2854 return mem_ldx(nfp_prog, meta, 1); 2855 } 2856 2857 static int mem_ldx2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2858 { 2859 return mem_ldx(nfp_prog, meta, 2); 2860 } 2861 2862 static int mem_ldx4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2863 { 2864 return mem_ldx(nfp_prog, meta, 4); 2865 } 2866 2867 static int mem_ldx8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2868 { 2869 return mem_ldx(nfp_prog, meta, 8); 2870 } 2871 2872 static int 2873 mem_st_data(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2874 unsigned int size) 2875 { 2876 u64 imm = meta->insn.imm; /* sign extend */ 2877 swreg off_reg; 2878 2879 off_reg = re_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 2880 2881 return data_st_host_order(nfp_prog, meta->insn.dst_reg * 2, off_reg, 2882 imm, size); 2883 } 2884 2885 static int mem_st(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2886 unsigned int size) 2887 { 2888 if (meta->ptr.type == PTR_TO_PACKET) 2889 return mem_st_data(nfp_prog, meta, size); 2890 2891 return -EOPNOTSUPP; 2892 } 2893 2894 static int mem_st1(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2895 { 2896 return mem_st(nfp_prog, meta, 1); 2897 } 2898 2899 static int mem_st2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2900 { 2901 return mem_st(nfp_prog, meta, 2); 2902 } 2903 2904 static int mem_st4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2905 { 2906 return mem_st(nfp_prog, meta, 4); 2907 } 2908 2909 static int mem_st8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2910 { 2911 return mem_st(nfp_prog, meta, 8); 2912 } 2913 2914 static int 2915 mem_stx_data(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2916 unsigned int size) 2917 { 2918 swreg off_reg; 2919 2920 off_reg = re_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 2921 2922 return data_stx_host_order(nfp_prog, meta->insn.dst_reg * 2, off_reg, 2923 meta->insn.src_reg * 2, size); 2924 } 2925 2926 static int 2927 mem_stx_stack(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2928 unsigned int size, unsigned int ptr_off) 2929 { 2930 return mem_op_stack(nfp_prog, meta, size, ptr_off, 2931 meta->insn.src_reg * 2, meta->insn.dst_reg * 2, 2932 false, wrp_lmem_store); 2933 } 2934 2935 static int mem_stx_xdp(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2936 { 2937 switch (meta->insn.off) { 2938 case offsetof(struct xdp_md, rx_queue_index): 2939 return nfp_queue_select(nfp_prog, meta); 2940 } 2941 2942 WARN_ON_ONCE(1); /* verifier should have rejected bad accesses */ 2943 return -EOPNOTSUPP; 2944 } 2945 2946 static int 2947 mem_stx(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 2948 unsigned int size) 2949 { 2950 if (meta->ptr.type == PTR_TO_PACKET) 2951 return mem_stx_data(nfp_prog, meta, size); 2952 2953 if (meta->ptr.type == PTR_TO_STACK) 2954 return mem_stx_stack(nfp_prog, meta, size, 2955 meta->ptr.off + meta->ptr.var_off.value); 2956 2957 return -EOPNOTSUPP; 2958 } 2959 2960 static int mem_stx1(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2961 { 2962 return mem_stx(nfp_prog, meta, 1); 2963 } 2964 2965 static int mem_stx2(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2966 { 2967 return mem_stx(nfp_prog, meta, 2); 2968 } 2969 2970 static int mem_stx4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2971 { 2972 if (meta->ptr.type == PTR_TO_CTX) 2973 if (nfp_prog->type == BPF_PROG_TYPE_XDP) 2974 return mem_stx_xdp(nfp_prog, meta); 2975 return mem_stx(nfp_prog, meta, 4); 2976 } 2977 2978 static int mem_stx8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 2979 { 2980 return mem_stx(nfp_prog, meta, 8); 2981 } 2982 2983 static int 2984 mem_xadd(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, bool is64) 2985 { 2986 u8 dst_gpr = meta->insn.dst_reg * 2; 2987 u8 src_gpr = meta->insn.src_reg * 2; 2988 unsigned int full_add, out; 2989 swreg addra, addrb, off; 2990 2991 off = ur_load_imm_any(nfp_prog, meta->insn.off, imm_b(nfp_prog)); 2992 2993 /* We can fit 16 bits into command immediate, if we know the immediate 2994 * is guaranteed to either always or never fit into 16 bit we only 2995 * generate code to handle that particular case, otherwise generate 2996 * code for both. 2997 */ 2998 out = nfp_prog_current_offset(nfp_prog); 2999 full_add = nfp_prog_current_offset(nfp_prog); 3000 3001 if (meta->insn.off) { 3002 out += 2; 3003 full_add += 2; 3004 } 3005 if (meta->xadd_maybe_16bit) { 3006 out += 3; 3007 full_add += 3; 3008 } 3009 if (meta->xadd_over_16bit) 3010 out += 2 + is64; 3011 if (meta->xadd_maybe_16bit && meta->xadd_over_16bit) { 3012 out += 5; 3013 full_add += 5; 3014 } 3015 3016 /* Generate the branch for choosing add_imm vs add */ 3017 if (meta->xadd_maybe_16bit && meta->xadd_over_16bit) { 3018 swreg max_imm = imm_a(nfp_prog); 3019 3020 wrp_immed(nfp_prog, max_imm, 0xffff); 3021 emit_alu(nfp_prog, reg_none(), 3022 max_imm, ALU_OP_SUB, reg_b(src_gpr)); 3023 emit_alu(nfp_prog, reg_none(), 3024 reg_imm(0), ALU_OP_SUB_C, reg_b(src_gpr + 1)); 3025 emit_br(nfp_prog, BR_BLO, full_add, meta->insn.off ? 2 : 0); 3026 /* defer for add */ 3027 } 3028 3029 /* If insn has an offset add to the address */ 3030 if (!meta->insn.off) { 3031 addra = reg_a(dst_gpr); 3032 addrb = reg_b(dst_gpr + 1); 3033 } else { 3034 emit_alu(nfp_prog, imma_a(nfp_prog), 3035 reg_a(dst_gpr), ALU_OP_ADD, off); 3036 emit_alu(nfp_prog, imma_b(nfp_prog), 3037 reg_a(dst_gpr + 1), ALU_OP_ADD_C, reg_imm(0)); 3038 addra = imma_a(nfp_prog); 3039 addrb = imma_b(nfp_prog); 3040 } 3041 3042 /* Generate the add_imm if 16 bits are possible */ 3043 if (meta->xadd_maybe_16bit) { 3044 swreg prev_alu = imm_a(nfp_prog); 3045 3046 wrp_immed(nfp_prog, prev_alu, 3047 FIELD_PREP(CMD_OVE_DATA, 2) | 3048 CMD_OVE_LEN | 3049 FIELD_PREP(CMD_OV_LEN, 0x8 | is64 << 2)); 3050 wrp_reg_or_subpart(nfp_prog, prev_alu, reg_b(src_gpr), 2, 2); 3051 emit_cmd_indir(nfp_prog, CMD_TGT_ADD_IMM, CMD_MODE_40b_BA, 0, 3052 addra, addrb, 0, CMD_CTX_NO_SWAP); 3053 3054 if (meta->xadd_over_16bit) 3055 emit_br(nfp_prog, BR_UNC, out, 0); 3056 } 3057 3058 if (!nfp_prog_confirm_current_offset(nfp_prog, full_add)) 3059 return -EINVAL; 3060 3061 /* Generate the add if 16 bits are not guaranteed */ 3062 if (meta->xadd_over_16bit) { 3063 emit_cmd(nfp_prog, CMD_TGT_ADD, CMD_MODE_40b_BA, 0, 3064 addra, addrb, is64 << 2, 3065 is64 ? CMD_CTX_SWAP_DEFER2 : CMD_CTX_SWAP_DEFER1); 3066 3067 wrp_mov(nfp_prog, reg_xfer(0), reg_a(src_gpr)); 3068 if (is64) 3069 wrp_mov(nfp_prog, reg_xfer(1), reg_a(src_gpr + 1)); 3070 } 3071 3072 if (!nfp_prog_confirm_current_offset(nfp_prog, out)) 3073 return -EINVAL; 3074 3075 return 0; 3076 } 3077 3078 static int mem_xadd4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3079 { 3080 return mem_xadd(nfp_prog, meta, false); 3081 } 3082 3083 static int mem_xadd8(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3084 { 3085 return mem_xadd(nfp_prog, meta, true); 3086 } 3087 3088 static int jump(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3089 { 3090 emit_br(nfp_prog, BR_UNC, meta->insn.off, 0); 3091 3092 return 0; 3093 } 3094 3095 static int jeq_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3096 { 3097 const struct bpf_insn *insn = &meta->insn; 3098 u64 imm = insn->imm; /* sign extend */ 3099 swreg or1, or2, tmp_reg; 3100 3101 or1 = reg_a(insn->dst_reg * 2); 3102 or2 = reg_b(insn->dst_reg * 2 + 1); 3103 3104 if (imm & ~0U) { 3105 tmp_reg = ur_load_imm_any(nfp_prog, imm & ~0U, imm_b(nfp_prog)); 3106 emit_alu(nfp_prog, imm_a(nfp_prog), 3107 reg_a(insn->dst_reg * 2), ALU_OP_XOR, tmp_reg); 3108 or1 = imm_a(nfp_prog); 3109 } 3110 3111 if (imm >> 32) { 3112 tmp_reg = ur_load_imm_any(nfp_prog, imm >> 32, imm_b(nfp_prog)); 3113 emit_alu(nfp_prog, imm_b(nfp_prog), 3114 reg_a(insn->dst_reg * 2 + 1), ALU_OP_XOR, tmp_reg); 3115 or2 = imm_b(nfp_prog); 3116 } 3117 3118 emit_alu(nfp_prog, reg_none(), or1, ALU_OP_OR, or2); 3119 emit_br(nfp_prog, BR_BEQ, insn->off, 0); 3120 3121 return 0; 3122 } 3123 3124 static int jeq32_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3125 { 3126 const struct bpf_insn *insn = &meta->insn; 3127 swreg tmp_reg; 3128 3129 tmp_reg = ur_load_imm_any(nfp_prog, insn->imm, imm_b(nfp_prog)); 3130 emit_alu(nfp_prog, reg_none(), 3131 reg_a(insn->dst_reg * 2), ALU_OP_XOR, tmp_reg); 3132 emit_br(nfp_prog, BR_BEQ, insn->off, 0); 3133 3134 return 0; 3135 } 3136 3137 static int jset_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3138 { 3139 const struct bpf_insn *insn = &meta->insn; 3140 u64 imm = insn->imm; /* sign extend */ 3141 u8 dst_gpr = insn->dst_reg * 2; 3142 swreg tmp_reg; 3143 3144 tmp_reg = ur_load_imm_any(nfp_prog, imm & ~0U, imm_b(nfp_prog)); 3145 emit_alu(nfp_prog, imm_b(nfp_prog), 3146 reg_a(dst_gpr), ALU_OP_AND, tmp_reg); 3147 /* Upper word of the mask can only be 0 or ~0 from sign extension, 3148 * so either ignore it or OR the whole thing in. 3149 */ 3150 if (is_mbpf_jmp64(meta) && imm >> 32) { 3151 emit_alu(nfp_prog, reg_none(), 3152 reg_a(dst_gpr + 1), ALU_OP_OR, imm_b(nfp_prog)); 3153 } 3154 emit_br(nfp_prog, BR_BNE, insn->off, 0); 3155 3156 return 0; 3157 } 3158 3159 static int jne_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3160 { 3161 const struct bpf_insn *insn = &meta->insn; 3162 u64 imm = insn->imm; /* sign extend */ 3163 bool is_jmp32 = is_mbpf_jmp32(meta); 3164 swreg tmp_reg; 3165 3166 if (!imm) { 3167 if (is_jmp32) 3168 emit_alu(nfp_prog, reg_none(), reg_none(), ALU_OP_NONE, 3169 reg_b(insn->dst_reg * 2)); 3170 else 3171 emit_alu(nfp_prog, reg_none(), reg_a(insn->dst_reg * 2), 3172 ALU_OP_OR, reg_b(insn->dst_reg * 2 + 1)); 3173 emit_br(nfp_prog, BR_BNE, insn->off, 0); 3174 return 0; 3175 } 3176 3177 tmp_reg = ur_load_imm_any(nfp_prog, imm & ~0U, imm_b(nfp_prog)); 3178 emit_alu(nfp_prog, reg_none(), 3179 reg_a(insn->dst_reg * 2), ALU_OP_XOR, tmp_reg); 3180 emit_br(nfp_prog, BR_BNE, insn->off, 0); 3181 3182 if (is_jmp32) 3183 return 0; 3184 3185 tmp_reg = ur_load_imm_any(nfp_prog, imm >> 32, imm_b(nfp_prog)); 3186 emit_alu(nfp_prog, reg_none(), 3187 reg_a(insn->dst_reg * 2 + 1), ALU_OP_XOR, tmp_reg); 3188 emit_br(nfp_prog, BR_BNE, insn->off, 0); 3189 3190 return 0; 3191 } 3192 3193 static int jeq_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3194 { 3195 const struct bpf_insn *insn = &meta->insn; 3196 3197 emit_alu(nfp_prog, imm_a(nfp_prog), reg_a(insn->dst_reg * 2), 3198 ALU_OP_XOR, reg_b(insn->src_reg * 2)); 3199 if (is_mbpf_jmp64(meta)) { 3200 emit_alu(nfp_prog, imm_b(nfp_prog), 3201 reg_a(insn->dst_reg * 2 + 1), ALU_OP_XOR, 3202 reg_b(insn->src_reg * 2 + 1)); 3203 emit_alu(nfp_prog, reg_none(), imm_a(nfp_prog), ALU_OP_OR, 3204 imm_b(nfp_prog)); 3205 } 3206 emit_br(nfp_prog, BR_BEQ, insn->off, 0); 3207 3208 return 0; 3209 } 3210 3211 static int jset_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3212 { 3213 return wrp_test_reg(nfp_prog, meta, ALU_OP_AND, BR_BNE); 3214 } 3215 3216 static int jne_reg(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3217 { 3218 return wrp_test_reg(nfp_prog, meta, ALU_OP_XOR, BR_BNE); 3219 } 3220 3221 static int 3222 bpf_to_bpf_call(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3223 { 3224 u32 ret_tgt, stack_depth, offset_br; 3225 swreg tmp_reg; 3226 3227 stack_depth = round_up(nfp_prog->stack_frame_depth, STACK_FRAME_ALIGN); 3228 /* Space for saving the return address is accounted for by the callee, 3229 * so stack_depth can be zero for the main function. 3230 */ 3231 if (stack_depth) { 3232 tmp_reg = ur_load_imm_any(nfp_prog, stack_depth, 3233 stack_imm(nfp_prog)); 3234 emit_alu(nfp_prog, stack_reg(nfp_prog), 3235 stack_reg(nfp_prog), ALU_OP_ADD, tmp_reg); 3236 emit_csr_wr(nfp_prog, stack_reg(nfp_prog), 3237 NFP_CSR_ACT_LM_ADDR0); 3238 } 3239 3240 /* Two cases for jumping to the callee: 3241 * 3242 * - If callee uses and needs to save R6~R9 then: 3243 * 1. Put the start offset of the callee into imm_b(). This will 3244 * require a fixup step, as we do not necessarily know this 3245 * address yet. 3246 * 2. Put the return address from the callee to the caller into 3247 * register ret_reg(). 3248 * 3. (After defer slots are consumed) Jump to the subroutine that 3249 * pushes the registers to the stack. 3250 * The subroutine acts as a trampoline, and returns to the address in 3251 * imm_b(), i.e. jumps to the callee. 3252 * 3253 * - If callee does not need to save R6~R9 then just load return 3254 * address to the caller in ret_reg(), and jump to the callee 3255 * directly. 3256 * 3257 * Using ret_reg() to pass the return address to the callee is set here 3258 * as a convention. The callee can then push this address onto its 3259 * stack frame in its prologue. The advantages of passing the return 3260 * address through ret_reg(), instead of pushing it to the stack right 3261 * here, are the following: 3262 * - It looks cleaner. 3263 * - If the called function is called multiple time, we get a lower 3264 * program size. 3265 * - We save two no-op instructions that should be added just before 3266 * the emit_br() when stack depth is not null otherwise. 3267 * - If we ever find a register to hold the return address during whole 3268 * execution of the callee, we will not have to push the return 3269 * address to the stack for leaf functions. 3270 */ 3271 if (!meta->jmp_dst) { 3272 pr_err("BUG: BPF-to-BPF call has no destination recorded\n"); 3273 return -ELOOP; 3274 } 3275 if (nfp_prog->subprog[meta->jmp_dst->subprog_idx].needs_reg_push) { 3276 ret_tgt = nfp_prog_current_offset(nfp_prog) + 3; 3277 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 2, 3278 RELO_BR_GO_CALL_PUSH_REGS); 3279 offset_br = nfp_prog_current_offset(nfp_prog); 3280 wrp_immed_relo(nfp_prog, imm_b(nfp_prog), 0, RELO_IMMED_REL); 3281 } else { 3282 ret_tgt = nfp_prog_current_offset(nfp_prog) + 2; 3283 emit_br(nfp_prog, BR_UNC, meta->insn.imm, 1); 3284 offset_br = nfp_prog_current_offset(nfp_prog); 3285 } 3286 wrp_immed_relo(nfp_prog, ret_reg(nfp_prog), ret_tgt, RELO_IMMED_REL); 3287 3288 if (!nfp_prog_confirm_current_offset(nfp_prog, ret_tgt)) 3289 return -EINVAL; 3290 3291 if (stack_depth) { 3292 tmp_reg = ur_load_imm_any(nfp_prog, stack_depth, 3293 stack_imm(nfp_prog)); 3294 emit_alu(nfp_prog, stack_reg(nfp_prog), 3295 stack_reg(nfp_prog), ALU_OP_SUB, tmp_reg); 3296 emit_csr_wr(nfp_prog, stack_reg(nfp_prog), 3297 NFP_CSR_ACT_LM_ADDR0); 3298 wrp_nops(nfp_prog, 3); 3299 } 3300 3301 meta->num_insns_after_br = nfp_prog_current_offset(nfp_prog); 3302 meta->num_insns_after_br -= offset_br; 3303 3304 return 0; 3305 } 3306 3307 static int helper_call(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3308 { 3309 switch (meta->insn.imm) { 3310 case BPF_FUNC_xdp_adjust_head: 3311 return adjust_head(nfp_prog, meta); 3312 case BPF_FUNC_xdp_adjust_tail: 3313 return adjust_tail(nfp_prog, meta); 3314 case BPF_FUNC_map_lookup_elem: 3315 case BPF_FUNC_map_update_elem: 3316 case BPF_FUNC_map_delete_elem: 3317 return map_call_stack_common(nfp_prog, meta); 3318 case BPF_FUNC_get_prandom_u32: 3319 return nfp_get_prandom_u32(nfp_prog, meta); 3320 case BPF_FUNC_perf_event_output: 3321 return nfp_perf_event_output(nfp_prog, meta); 3322 default: 3323 WARN_ONCE(1, "verifier allowed unsupported function\n"); 3324 return -EOPNOTSUPP; 3325 } 3326 } 3327 3328 static int call(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3329 { 3330 if (is_mbpf_pseudo_call(meta)) 3331 return bpf_to_bpf_call(nfp_prog, meta); 3332 else 3333 return helper_call(nfp_prog, meta); 3334 } 3335 3336 static bool nfp_is_main_function(struct nfp_insn_meta *meta) 3337 { 3338 return meta->subprog_idx == 0; 3339 } 3340 3341 static int goto_out(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3342 { 3343 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 0, RELO_BR_GO_OUT); 3344 3345 return 0; 3346 } 3347 3348 static int 3349 nfp_subprog_epilogue(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3350 { 3351 if (nfp_prog->subprog[meta->subprog_idx].needs_reg_push) { 3352 /* Pop R6~R9 to the stack via related subroutine. 3353 * We loaded the return address to the caller into ret_reg(). 3354 * This means that the subroutine does not come back here, we 3355 * make it jump back to the subprogram caller directly! 3356 */ 3357 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 1, 3358 RELO_BR_GO_CALL_POP_REGS); 3359 /* Pop return address from the stack. */ 3360 wrp_mov(nfp_prog, ret_reg(nfp_prog), reg_lm(0, 0)); 3361 } else { 3362 /* Pop return address from the stack. */ 3363 wrp_mov(nfp_prog, ret_reg(nfp_prog), reg_lm(0, 0)); 3364 /* Jump back to caller if no callee-saved registers were used 3365 * by the subprogram. 3366 */ 3367 emit_rtn(nfp_prog, ret_reg(nfp_prog), 0); 3368 } 3369 3370 return 0; 3371 } 3372 3373 static int jmp_exit(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3374 { 3375 if (nfp_is_main_function(meta)) 3376 return goto_out(nfp_prog, meta); 3377 else 3378 return nfp_subprog_epilogue(nfp_prog, meta); 3379 } 3380 3381 static const instr_cb_t instr_cb[256] = { 3382 [BPF_ALU64 | BPF_MOV | BPF_X] = mov_reg64, 3383 [BPF_ALU64 | BPF_MOV | BPF_K] = mov_imm64, 3384 [BPF_ALU64 | BPF_XOR | BPF_X] = xor_reg64, 3385 [BPF_ALU64 | BPF_XOR | BPF_K] = xor_imm64, 3386 [BPF_ALU64 | BPF_AND | BPF_X] = and_reg64, 3387 [BPF_ALU64 | BPF_AND | BPF_K] = and_imm64, 3388 [BPF_ALU64 | BPF_OR | BPF_X] = or_reg64, 3389 [BPF_ALU64 | BPF_OR | BPF_K] = or_imm64, 3390 [BPF_ALU64 | BPF_ADD | BPF_X] = add_reg64, 3391 [BPF_ALU64 | BPF_ADD | BPF_K] = add_imm64, 3392 [BPF_ALU64 | BPF_SUB | BPF_X] = sub_reg64, 3393 [BPF_ALU64 | BPF_SUB | BPF_K] = sub_imm64, 3394 [BPF_ALU64 | BPF_MUL | BPF_X] = mul_reg64, 3395 [BPF_ALU64 | BPF_MUL | BPF_K] = mul_imm64, 3396 [BPF_ALU64 | BPF_DIV | BPF_X] = div_reg64, 3397 [BPF_ALU64 | BPF_DIV | BPF_K] = div_imm64, 3398 [BPF_ALU64 | BPF_NEG] = neg_reg64, 3399 [BPF_ALU64 | BPF_LSH | BPF_X] = shl_reg64, 3400 [BPF_ALU64 | BPF_LSH | BPF_K] = shl_imm64, 3401 [BPF_ALU64 | BPF_RSH | BPF_X] = shr_reg64, 3402 [BPF_ALU64 | BPF_RSH | BPF_K] = shr_imm64, 3403 [BPF_ALU64 | BPF_ARSH | BPF_X] = ashr_reg64, 3404 [BPF_ALU64 | BPF_ARSH | BPF_K] = ashr_imm64, 3405 [BPF_ALU | BPF_MOV | BPF_X] = mov_reg, 3406 [BPF_ALU | BPF_MOV | BPF_K] = mov_imm, 3407 [BPF_ALU | BPF_XOR | BPF_X] = xor_reg, 3408 [BPF_ALU | BPF_XOR | BPF_K] = xor_imm, 3409 [BPF_ALU | BPF_AND | BPF_X] = and_reg, 3410 [BPF_ALU | BPF_AND | BPF_K] = and_imm, 3411 [BPF_ALU | BPF_OR | BPF_X] = or_reg, 3412 [BPF_ALU | BPF_OR | BPF_K] = or_imm, 3413 [BPF_ALU | BPF_ADD | BPF_X] = add_reg, 3414 [BPF_ALU | BPF_ADD | BPF_K] = add_imm, 3415 [BPF_ALU | BPF_SUB | BPF_X] = sub_reg, 3416 [BPF_ALU | BPF_SUB | BPF_K] = sub_imm, 3417 [BPF_ALU | BPF_MUL | BPF_X] = mul_reg, 3418 [BPF_ALU | BPF_MUL | BPF_K] = mul_imm, 3419 [BPF_ALU | BPF_DIV | BPF_X] = div_reg, 3420 [BPF_ALU | BPF_DIV | BPF_K] = div_imm, 3421 [BPF_ALU | BPF_NEG] = neg_reg, 3422 [BPF_ALU | BPF_LSH | BPF_X] = shl_reg, 3423 [BPF_ALU | BPF_LSH | BPF_K] = shl_imm, 3424 [BPF_ALU | BPF_RSH | BPF_X] = shr_reg, 3425 [BPF_ALU | BPF_RSH | BPF_K] = shr_imm, 3426 [BPF_ALU | BPF_ARSH | BPF_X] = ashr_reg, 3427 [BPF_ALU | BPF_ARSH | BPF_K] = ashr_imm, 3428 [BPF_ALU | BPF_END | BPF_X] = end_reg32, 3429 [BPF_LD | BPF_IMM | BPF_DW] = imm_ld8, 3430 [BPF_LD | BPF_ABS | BPF_B] = data_ld1, 3431 [BPF_LD | BPF_ABS | BPF_H] = data_ld2, 3432 [BPF_LD | BPF_ABS | BPF_W] = data_ld4, 3433 [BPF_LD | BPF_IND | BPF_B] = data_ind_ld1, 3434 [BPF_LD | BPF_IND | BPF_H] = data_ind_ld2, 3435 [BPF_LD | BPF_IND | BPF_W] = data_ind_ld4, 3436 [BPF_LDX | BPF_MEM | BPF_B] = mem_ldx1, 3437 [BPF_LDX | BPF_MEM | BPF_H] = mem_ldx2, 3438 [BPF_LDX | BPF_MEM | BPF_W] = mem_ldx4, 3439 [BPF_LDX | BPF_MEM | BPF_DW] = mem_ldx8, 3440 [BPF_STX | BPF_MEM | BPF_B] = mem_stx1, 3441 [BPF_STX | BPF_MEM | BPF_H] = mem_stx2, 3442 [BPF_STX | BPF_MEM | BPF_W] = mem_stx4, 3443 [BPF_STX | BPF_MEM | BPF_DW] = mem_stx8, 3444 [BPF_STX | BPF_XADD | BPF_W] = mem_xadd4, 3445 [BPF_STX | BPF_XADD | BPF_DW] = mem_xadd8, 3446 [BPF_ST | BPF_MEM | BPF_B] = mem_st1, 3447 [BPF_ST | BPF_MEM | BPF_H] = mem_st2, 3448 [BPF_ST | BPF_MEM | BPF_W] = mem_st4, 3449 [BPF_ST | BPF_MEM | BPF_DW] = mem_st8, 3450 [BPF_JMP | BPF_JA | BPF_K] = jump, 3451 [BPF_JMP | BPF_JEQ | BPF_K] = jeq_imm, 3452 [BPF_JMP | BPF_JGT | BPF_K] = cmp_imm, 3453 [BPF_JMP | BPF_JGE | BPF_K] = cmp_imm, 3454 [BPF_JMP | BPF_JLT | BPF_K] = cmp_imm, 3455 [BPF_JMP | BPF_JLE | BPF_K] = cmp_imm, 3456 [BPF_JMP | BPF_JSGT | BPF_K] = cmp_imm, 3457 [BPF_JMP | BPF_JSGE | BPF_K] = cmp_imm, 3458 [BPF_JMP | BPF_JSLT | BPF_K] = cmp_imm, 3459 [BPF_JMP | BPF_JSLE | BPF_K] = cmp_imm, 3460 [BPF_JMP | BPF_JSET | BPF_K] = jset_imm, 3461 [BPF_JMP | BPF_JNE | BPF_K] = jne_imm, 3462 [BPF_JMP | BPF_JEQ | BPF_X] = jeq_reg, 3463 [BPF_JMP | BPF_JGT | BPF_X] = cmp_reg, 3464 [BPF_JMP | BPF_JGE | BPF_X] = cmp_reg, 3465 [BPF_JMP | BPF_JLT | BPF_X] = cmp_reg, 3466 [BPF_JMP | BPF_JLE | BPF_X] = cmp_reg, 3467 [BPF_JMP | BPF_JSGT | BPF_X] = cmp_reg, 3468 [BPF_JMP | BPF_JSGE | BPF_X] = cmp_reg, 3469 [BPF_JMP | BPF_JSLT | BPF_X] = cmp_reg, 3470 [BPF_JMP | BPF_JSLE | BPF_X] = cmp_reg, 3471 [BPF_JMP | BPF_JSET | BPF_X] = jset_reg, 3472 [BPF_JMP | BPF_JNE | BPF_X] = jne_reg, 3473 [BPF_JMP32 | BPF_JEQ | BPF_K] = jeq32_imm, 3474 [BPF_JMP32 | BPF_JGT | BPF_K] = cmp_imm, 3475 [BPF_JMP32 | BPF_JGE | BPF_K] = cmp_imm, 3476 [BPF_JMP32 | BPF_JLT | BPF_K] = cmp_imm, 3477 [BPF_JMP32 | BPF_JLE | BPF_K] = cmp_imm, 3478 [BPF_JMP32 | BPF_JSGT | BPF_K] =cmp_imm, 3479 [BPF_JMP32 | BPF_JSGE | BPF_K] =cmp_imm, 3480 [BPF_JMP32 | BPF_JSLT | BPF_K] =cmp_imm, 3481 [BPF_JMP32 | BPF_JSLE | BPF_K] =cmp_imm, 3482 [BPF_JMP32 | BPF_JSET | BPF_K] =jset_imm, 3483 [BPF_JMP32 | BPF_JNE | BPF_K] = jne_imm, 3484 [BPF_JMP32 | BPF_JEQ | BPF_X] = jeq_reg, 3485 [BPF_JMP32 | BPF_JGT | BPF_X] = cmp_reg, 3486 [BPF_JMP32 | BPF_JGE | BPF_X] = cmp_reg, 3487 [BPF_JMP32 | BPF_JLT | BPF_X] = cmp_reg, 3488 [BPF_JMP32 | BPF_JLE | BPF_X] = cmp_reg, 3489 [BPF_JMP32 | BPF_JSGT | BPF_X] =cmp_reg, 3490 [BPF_JMP32 | BPF_JSGE | BPF_X] =cmp_reg, 3491 [BPF_JMP32 | BPF_JSLT | BPF_X] =cmp_reg, 3492 [BPF_JMP32 | BPF_JSLE | BPF_X] =cmp_reg, 3493 [BPF_JMP32 | BPF_JSET | BPF_X] =jset_reg, 3494 [BPF_JMP32 | BPF_JNE | BPF_X] = jne_reg, 3495 [BPF_JMP | BPF_CALL] = call, 3496 [BPF_JMP | BPF_EXIT] = jmp_exit, 3497 }; 3498 3499 /* --- Assembler logic --- */ 3500 static int 3501 nfp_fixup_immed_relo(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta, 3502 struct nfp_insn_meta *jmp_dst, u32 br_idx) 3503 { 3504 if (immed_get_value(nfp_prog->prog[br_idx + 1])) { 3505 pr_err("BUG: failed to fix up callee register saving\n"); 3506 return -EINVAL; 3507 } 3508 3509 immed_set_value(&nfp_prog->prog[br_idx + 1], jmp_dst->off); 3510 3511 return 0; 3512 } 3513 3514 static int nfp_fixup_branches(struct nfp_prog *nfp_prog) 3515 { 3516 struct nfp_insn_meta *meta, *jmp_dst; 3517 u32 idx, br_idx; 3518 int err; 3519 3520 list_for_each_entry(meta, &nfp_prog->insns, l) { 3521 if (meta->flags & FLAG_INSN_SKIP_MASK) 3522 continue; 3523 if (!is_mbpf_jmp(meta)) 3524 continue; 3525 if (meta->insn.code == (BPF_JMP | BPF_EXIT) && 3526 !nfp_is_main_function(meta)) 3527 continue; 3528 if (is_mbpf_helper_call(meta)) 3529 continue; 3530 3531 if (list_is_last(&meta->l, &nfp_prog->insns)) 3532 br_idx = nfp_prog->last_bpf_off; 3533 else 3534 br_idx = list_next_entry(meta, l)->off - 1; 3535 3536 /* For BPF-to-BPF function call, a stack adjustment sequence is 3537 * generated after the return instruction. Therefore, we must 3538 * withdraw the length of this sequence to have br_idx pointing 3539 * to where the "branch" NFP instruction is expected to be. 3540 */ 3541 if (is_mbpf_pseudo_call(meta)) 3542 br_idx -= meta->num_insns_after_br; 3543 3544 if (!nfp_is_br(nfp_prog->prog[br_idx])) { 3545 pr_err("Fixup found block not ending in branch %d %02x %016llx!!\n", 3546 br_idx, meta->insn.code, nfp_prog->prog[br_idx]); 3547 return -ELOOP; 3548 } 3549 3550 if (meta->insn.code == (BPF_JMP | BPF_EXIT)) 3551 continue; 3552 3553 /* Leave special branches for later */ 3554 if (FIELD_GET(OP_RELO_TYPE, nfp_prog->prog[br_idx]) != 3555 RELO_BR_REL && !is_mbpf_pseudo_call(meta)) 3556 continue; 3557 3558 if (!meta->jmp_dst) { 3559 pr_err("Non-exit jump doesn't have destination info recorded!!\n"); 3560 return -ELOOP; 3561 } 3562 3563 jmp_dst = meta->jmp_dst; 3564 3565 if (jmp_dst->flags & FLAG_INSN_SKIP_PREC_DEPENDENT) { 3566 pr_err("Branch landing on removed instruction!!\n"); 3567 return -ELOOP; 3568 } 3569 3570 if (is_mbpf_pseudo_call(meta) && 3571 nfp_prog->subprog[jmp_dst->subprog_idx].needs_reg_push) { 3572 err = nfp_fixup_immed_relo(nfp_prog, meta, 3573 jmp_dst, br_idx); 3574 if (err) 3575 return err; 3576 } 3577 3578 if (FIELD_GET(OP_RELO_TYPE, nfp_prog->prog[br_idx]) != 3579 RELO_BR_REL) 3580 continue; 3581 3582 for (idx = meta->off; idx <= br_idx; idx++) { 3583 if (!nfp_is_br(nfp_prog->prog[idx])) 3584 continue; 3585 br_set_offset(&nfp_prog->prog[idx], jmp_dst->off); 3586 } 3587 } 3588 3589 return 0; 3590 } 3591 3592 static void nfp_intro(struct nfp_prog *nfp_prog) 3593 { 3594 wrp_immed(nfp_prog, plen_reg(nfp_prog), GENMASK(13, 0)); 3595 emit_alu(nfp_prog, plen_reg(nfp_prog), 3596 plen_reg(nfp_prog), ALU_OP_AND, pv_len(nfp_prog)); 3597 } 3598 3599 static void 3600 nfp_subprog_prologue(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3601 { 3602 /* Save return address into the stack. */ 3603 wrp_mov(nfp_prog, reg_lm(0, 0), ret_reg(nfp_prog)); 3604 } 3605 3606 static void 3607 nfp_start_subprog(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta) 3608 { 3609 unsigned int depth = nfp_prog->subprog[meta->subprog_idx].stack_depth; 3610 3611 nfp_prog->stack_frame_depth = round_up(depth, 4); 3612 nfp_subprog_prologue(nfp_prog, meta); 3613 } 3614 3615 bool nfp_is_subprog_start(struct nfp_insn_meta *meta) 3616 { 3617 return meta->flags & FLAG_INSN_IS_SUBPROG_START; 3618 } 3619 3620 static void nfp_outro_tc_da(struct nfp_prog *nfp_prog) 3621 { 3622 /* TC direct-action mode: 3623 * 0,1 ok NOT SUPPORTED[1] 3624 * 2 drop 0x22 -> drop, count as stat1 3625 * 4,5 nuke 0x02 -> drop 3626 * 7 redir 0x44 -> redir, count as stat2 3627 * * unspec 0x11 -> pass, count as stat0 3628 * 3629 * [1] We can't support OK and RECLASSIFY because we can't tell TC 3630 * the exact decision made. We are forced to support UNSPEC 3631 * to handle aborts so that's the only one we handle for passing 3632 * packets up the stack. 3633 */ 3634 /* Target for aborts */ 3635 nfp_prog->tgt_abort = nfp_prog_current_offset(nfp_prog); 3636 3637 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 2, RELO_BR_NEXT_PKT); 3638 3639 wrp_mov(nfp_prog, reg_a(0), NFP_BPF_ABI_FLAGS); 3640 emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_imm(0x11), SHF_SC_L_SHF, 16); 3641 3642 /* Target for normal exits */ 3643 nfp_prog->tgt_out = nfp_prog_current_offset(nfp_prog); 3644 3645 /* if R0 > 7 jump to abort */ 3646 emit_alu(nfp_prog, reg_none(), reg_imm(7), ALU_OP_SUB, reg_b(0)); 3647 emit_br(nfp_prog, BR_BLO, nfp_prog->tgt_abort, 0); 3648 wrp_mov(nfp_prog, reg_a(0), NFP_BPF_ABI_FLAGS); 3649 3650 wrp_immed(nfp_prog, reg_b(2), 0x41221211); 3651 wrp_immed(nfp_prog, reg_b(3), 0x41001211); 3652 3653 emit_shf(nfp_prog, reg_a(1), 3654 reg_none(), SHF_OP_NONE, reg_b(0), SHF_SC_L_SHF, 2); 3655 3656 emit_alu(nfp_prog, reg_none(), reg_a(1), ALU_OP_OR, reg_imm(0)); 3657 emit_shf(nfp_prog, reg_a(2), 3658 reg_imm(0xf), SHF_OP_AND, reg_b(2), SHF_SC_R_SHF, 0); 3659 3660 emit_alu(nfp_prog, reg_none(), reg_a(1), ALU_OP_OR, reg_imm(0)); 3661 emit_shf(nfp_prog, reg_b(2), 3662 reg_imm(0xf), SHF_OP_AND, reg_b(3), SHF_SC_R_SHF, 0); 3663 3664 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 2, RELO_BR_NEXT_PKT); 3665 3666 emit_shf(nfp_prog, reg_b(2), 3667 reg_a(2), SHF_OP_OR, reg_b(2), SHF_SC_L_SHF, 4); 3668 emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_b(2), SHF_SC_L_SHF, 16); 3669 } 3670 3671 static void nfp_outro_xdp(struct nfp_prog *nfp_prog) 3672 { 3673 /* XDP return codes: 3674 * 0 aborted 0x82 -> drop, count as stat3 3675 * 1 drop 0x22 -> drop, count as stat1 3676 * 2 pass 0x11 -> pass, count as stat0 3677 * 3 tx 0x44 -> redir, count as stat2 3678 * * unknown 0x82 -> drop, count as stat3 3679 */ 3680 /* Target for aborts */ 3681 nfp_prog->tgt_abort = nfp_prog_current_offset(nfp_prog); 3682 3683 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 2, RELO_BR_NEXT_PKT); 3684 3685 wrp_mov(nfp_prog, reg_a(0), NFP_BPF_ABI_FLAGS); 3686 emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_imm(0x82), SHF_SC_L_SHF, 16); 3687 3688 /* Target for normal exits */ 3689 nfp_prog->tgt_out = nfp_prog_current_offset(nfp_prog); 3690 3691 /* if R0 > 3 jump to abort */ 3692 emit_alu(nfp_prog, reg_none(), reg_imm(3), ALU_OP_SUB, reg_b(0)); 3693 emit_br(nfp_prog, BR_BLO, nfp_prog->tgt_abort, 0); 3694 3695 wrp_immed(nfp_prog, reg_b(2), 0x44112282); 3696 3697 emit_shf(nfp_prog, reg_a(1), 3698 reg_none(), SHF_OP_NONE, reg_b(0), SHF_SC_L_SHF, 3); 3699 3700 emit_alu(nfp_prog, reg_none(), reg_a(1), ALU_OP_OR, reg_imm(0)); 3701 emit_shf(nfp_prog, reg_b(2), 3702 reg_imm(0xff), SHF_OP_AND, reg_b(2), SHF_SC_R_SHF, 0); 3703 3704 emit_br_relo(nfp_prog, BR_UNC, BR_OFF_RELO, 2, RELO_BR_NEXT_PKT); 3705 3706 wrp_mov(nfp_prog, reg_a(0), NFP_BPF_ABI_FLAGS); 3707 emit_ld_field(nfp_prog, reg_a(0), 0xc, reg_b(2), SHF_SC_L_SHF, 16); 3708 } 3709 3710 static bool nfp_prog_needs_callee_reg_save(struct nfp_prog *nfp_prog) 3711 { 3712 unsigned int idx; 3713 3714 for (idx = 1; idx < nfp_prog->subprog_cnt; idx++) 3715 if (nfp_prog->subprog[idx].needs_reg_push) 3716 return true; 3717 3718 return false; 3719 } 3720 3721 static void nfp_push_callee_registers(struct nfp_prog *nfp_prog) 3722 { 3723 u8 reg; 3724 3725 /* Subroutine: Save all callee saved registers (R6 ~ R9). 3726 * imm_b() holds the return address. 3727 */ 3728 nfp_prog->tgt_call_push_regs = nfp_prog_current_offset(nfp_prog); 3729 for (reg = BPF_REG_6; reg <= BPF_REG_9; reg++) { 3730 u8 adj = (reg - BPF_REG_0) * 2; 3731 u8 idx = (reg - BPF_REG_6) * 2; 3732 3733 /* The first slot in the stack frame is used to push the return 3734 * address in bpf_to_bpf_call(), start just after. 3735 */ 3736 wrp_mov(nfp_prog, reg_lm(0, 1 + idx), reg_b(adj)); 3737 3738 if (reg == BPF_REG_8) 3739 /* Prepare to jump back, last 3 insns use defer slots */ 3740 emit_rtn(nfp_prog, imm_b(nfp_prog), 3); 3741 3742 wrp_mov(nfp_prog, reg_lm(0, 1 + idx + 1), reg_b(adj + 1)); 3743 } 3744 } 3745 3746 static void nfp_pop_callee_registers(struct nfp_prog *nfp_prog) 3747 { 3748 u8 reg; 3749 3750 /* Subroutine: Restore all callee saved registers (R6 ~ R9). 3751 * ret_reg() holds the return address. 3752 */ 3753 nfp_prog->tgt_call_pop_regs = nfp_prog_current_offset(nfp_prog); 3754 for (reg = BPF_REG_6; reg <= BPF_REG_9; reg++) { 3755 u8 adj = (reg - BPF_REG_0) * 2; 3756 u8 idx = (reg - BPF_REG_6) * 2; 3757 3758 /* The first slot in the stack frame holds the return address, 3759 * start popping just after that. 3760 */ 3761 wrp_mov(nfp_prog, reg_both(adj), reg_lm(0, 1 + idx)); 3762 3763 if (reg == BPF_REG_8) 3764 /* Prepare to jump back, last 3 insns use defer slots */ 3765 emit_rtn(nfp_prog, ret_reg(nfp_prog), 3); 3766 3767 wrp_mov(nfp_prog, reg_both(adj + 1), reg_lm(0, 1 + idx + 1)); 3768 } 3769 } 3770 3771 static void nfp_outro(struct nfp_prog *nfp_prog) 3772 { 3773 switch (nfp_prog->type) { 3774 case BPF_PROG_TYPE_SCHED_CLS: 3775 nfp_outro_tc_da(nfp_prog); 3776 break; 3777 case BPF_PROG_TYPE_XDP: 3778 nfp_outro_xdp(nfp_prog); 3779 break; 3780 default: 3781 WARN_ON(1); 3782 } 3783 3784 if (!nfp_prog_needs_callee_reg_save(nfp_prog)) 3785 return; 3786 3787 nfp_push_callee_registers(nfp_prog); 3788 nfp_pop_callee_registers(nfp_prog); 3789 } 3790 3791 static int nfp_translate(struct nfp_prog *nfp_prog) 3792 { 3793 struct nfp_insn_meta *meta; 3794 unsigned int depth; 3795 int err; 3796 3797 depth = nfp_prog->subprog[0].stack_depth; 3798 nfp_prog->stack_frame_depth = round_up(depth, 4); 3799 3800 nfp_intro(nfp_prog); 3801 if (nfp_prog->error) 3802 return nfp_prog->error; 3803 3804 list_for_each_entry(meta, &nfp_prog->insns, l) { 3805 instr_cb_t cb = instr_cb[meta->insn.code]; 3806 3807 meta->off = nfp_prog_current_offset(nfp_prog); 3808 3809 if (nfp_is_subprog_start(meta)) { 3810 nfp_start_subprog(nfp_prog, meta); 3811 if (nfp_prog->error) 3812 return nfp_prog->error; 3813 } 3814 3815 if (meta->flags & FLAG_INSN_SKIP_MASK) { 3816 nfp_prog->n_translated++; 3817 continue; 3818 } 3819 3820 if (nfp_meta_has_prev(nfp_prog, meta) && 3821 nfp_meta_prev(meta)->double_cb) 3822 cb = nfp_meta_prev(meta)->double_cb; 3823 if (!cb) 3824 return -ENOENT; 3825 err = cb(nfp_prog, meta); 3826 if (err) 3827 return err; 3828 if (nfp_prog->error) 3829 return nfp_prog->error; 3830 3831 nfp_prog->n_translated++; 3832 } 3833 3834 nfp_prog->last_bpf_off = nfp_prog_current_offset(nfp_prog) - 1; 3835 3836 nfp_outro(nfp_prog); 3837 if (nfp_prog->error) 3838 return nfp_prog->error; 3839 3840 wrp_nops(nfp_prog, NFP_USTORE_PREFETCH_WINDOW); 3841 if (nfp_prog->error) 3842 return nfp_prog->error; 3843 3844 return nfp_fixup_branches(nfp_prog); 3845 } 3846 3847 /* --- Optimizations --- */ 3848 static void nfp_bpf_opt_reg_init(struct nfp_prog *nfp_prog) 3849 { 3850 struct nfp_insn_meta *meta; 3851 3852 list_for_each_entry(meta, &nfp_prog->insns, l) { 3853 struct bpf_insn insn = meta->insn; 3854 3855 /* Programs converted from cBPF start with register xoring */ 3856 if (insn.code == (BPF_ALU64 | BPF_XOR | BPF_X) && 3857 insn.src_reg == insn.dst_reg) 3858 continue; 3859 3860 /* Programs start with R6 = R1 but we ignore the skb pointer */ 3861 if (insn.code == (BPF_ALU64 | BPF_MOV | BPF_X) && 3862 insn.src_reg == 1 && insn.dst_reg == 6) 3863 meta->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 3864 3865 /* Return as soon as something doesn't match */ 3866 if (!(meta->flags & FLAG_INSN_SKIP_MASK)) 3867 return; 3868 } 3869 } 3870 3871 /* abs(insn.imm) will fit better into unrestricted reg immediate - 3872 * convert add/sub of a negative number into a sub/add of a positive one. 3873 */ 3874 static void nfp_bpf_opt_neg_add_sub(struct nfp_prog *nfp_prog) 3875 { 3876 struct nfp_insn_meta *meta; 3877 3878 list_for_each_entry(meta, &nfp_prog->insns, l) { 3879 struct bpf_insn insn = meta->insn; 3880 3881 if (meta->flags & FLAG_INSN_SKIP_MASK) 3882 continue; 3883 3884 if (!is_mbpf_alu(meta) && !is_mbpf_jmp(meta)) 3885 continue; 3886 if (BPF_SRC(insn.code) != BPF_K) 3887 continue; 3888 if (insn.imm >= 0) 3889 continue; 3890 3891 if (is_mbpf_jmp(meta)) { 3892 switch (BPF_OP(insn.code)) { 3893 case BPF_JGE: 3894 case BPF_JSGE: 3895 case BPF_JLT: 3896 case BPF_JSLT: 3897 meta->jump_neg_op = true; 3898 break; 3899 default: 3900 continue; 3901 } 3902 } else { 3903 if (BPF_OP(insn.code) == BPF_ADD) 3904 insn.code = BPF_CLASS(insn.code) | BPF_SUB; 3905 else if (BPF_OP(insn.code) == BPF_SUB) 3906 insn.code = BPF_CLASS(insn.code) | BPF_ADD; 3907 else 3908 continue; 3909 3910 meta->insn.code = insn.code | BPF_K; 3911 } 3912 3913 meta->insn.imm = -insn.imm; 3914 } 3915 } 3916 3917 /* Remove masking after load since our load guarantees this is not needed */ 3918 static void nfp_bpf_opt_ld_mask(struct nfp_prog *nfp_prog) 3919 { 3920 struct nfp_insn_meta *meta1, *meta2; 3921 const s32 exp_mask[] = { 3922 [BPF_B] = 0x000000ffU, 3923 [BPF_H] = 0x0000ffffU, 3924 [BPF_W] = 0xffffffffU, 3925 }; 3926 3927 nfp_for_each_insn_walk2(nfp_prog, meta1, meta2) { 3928 struct bpf_insn insn, next; 3929 3930 insn = meta1->insn; 3931 next = meta2->insn; 3932 3933 if (BPF_CLASS(insn.code) != BPF_LD) 3934 continue; 3935 if (BPF_MODE(insn.code) != BPF_ABS && 3936 BPF_MODE(insn.code) != BPF_IND) 3937 continue; 3938 3939 if (next.code != (BPF_ALU64 | BPF_AND | BPF_K)) 3940 continue; 3941 3942 if (!exp_mask[BPF_SIZE(insn.code)]) 3943 continue; 3944 if (exp_mask[BPF_SIZE(insn.code)] != next.imm) 3945 continue; 3946 3947 if (next.src_reg || next.dst_reg) 3948 continue; 3949 3950 if (meta2->flags & FLAG_INSN_IS_JUMP_DST) 3951 continue; 3952 3953 meta2->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 3954 } 3955 } 3956 3957 static void nfp_bpf_opt_ld_shift(struct nfp_prog *nfp_prog) 3958 { 3959 struct nfp_insn_meta *meta1, *meta2, *meta3; 3960 3961 nfp_for_each_insn_walk3(nfp_prog, meta1, meta2, meta3) { 3962 struct bpf_insn insn, next1, next2; 3963 3964 insn = meta1->insn; 3965 next1 = meta2->insn; 3966 next2 = meta3->insn; 3967 3968 if (BPF_CLASS(insn.code) != BPF_LD) 3969 continue; 3970 if (BPF_MODE(insn.code) != BPF_ABS && 3971 BPF_MODE(insn.code) != BPF_IND) 3972 continue; 3973 if (BPF_SIZE(insn.code) != BPF_W) 3974 continue; 3975 3976 if (!(next1.code == (BPF_LSH | BPF_K | BPF_ALU64) && 3977 next2.code == (BPF_RSH | BPF_K | BPF_ALU64)) && 3978 !(next1.code == (BPF_RSH | BPF_K | BPF_ALU64) && 3979 next2.code == (BPF_LSH | BPF_K | BPF_ALU64))) 3980 continue; 3981 3982 if (next1.src_reg || next1.dst_reg || 3983 next2.src_reg || next2.dst_reg) 3984 continue; 3985 3986 if (next1.imm != 0x20 || next2.imm != 0x20) 3987 continue; 3988 3989 if (meta2->flags & FLAG_INSN_IS_JUMP_DST || 3990 meta3->flags & FLAG_INSN_IS_JUMP_DST) 3991 continue; 3992 3993 meta2->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 3994 meta3->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 3995 } 3996 } 3997 3998 /* load/store pair that forms memory copy sould look like the following: 3999 * 4000 * ld_width R, [addr_src + offset_src] 4001 * st_width [addr_dest + offset_dest], R 4002 * 4003 * The destination register of load and source register of store should 4004 * be the same, load and store should also perform at the same width. 4005 * If either of addr_src or addr_dest is stack pointer, we don't do the 4006 * CPP optimization as stack is modelled by registers on NFP. 4007 */ 4008 static bool 4009 curr_pair_is_memcpy(struct nfp_insn_meta *ld_meta, 4010 struct nfp_insn_meta *st_meta) 4011 { 4012 struct bpf_insn *ld = &ld_meta->insn; 4013 struct bpf_insn *st = &st_meta->insn; 4014 4015 if (!is_mbpf_load(ld_meta) || !is_mbpf_store(st_meta)) 4016 return false; 4017 4018 if (ld_meta->ptr.type != PTR_TO_PACKET && 4019 ld_meta->ptr.type != PTR_TO_MAP_VALUE) 4020 return false; 4021 4022 if (st_meta->ptr.type != PTR_TO_PACKET) 4023 return false; 4024 4025 if (BPF_SIZE(ld->code) != BPF_SIZE(st->code)) 4026 return false; 4027 4028 if (ld->dst_reg != st->src_reg) 4029 return false; 4030 4031 /* There is jump to the store insn in this pair. */ 4032 if (st_meta->flags & FLAG_INSN_IS_JUMP_DST) 4033 return false; 4034 4035 return true; 4036 } 4037 4038 /* Currently, we only support chaining load/store pairs if: 4039 * 4040 * - Their address base registers are the same. 4041 * - Their address offsets are in the same order. 4042 * - They operate at the same memory width. 4043 * - There is no jump into the middle of them. 4044 */ 4045 static bool 4046 curr_pair_chain_with_previous(struct nfp_insn_meta *ld_meta, 4047 struct nfp_insn_meta *st_meta, 4048 struct bpf_insn *prev_ld, 4049 struct bpf_insn *prev_st) 4050 { 4051 u8 prev_size, curr_size, prev_ld_base, prev_st_base, prev_ld_dst; 4052 struct bpf_insn *ld = &ld_meta->insn; 4053 struct bpf_insn *st = &st_meta->insn; 4054 s16 prev_ld_off, prev_st_off; 4055 4056 /* This pair is the start pair. */ 4057 if (!prev_ld) 4058 return true; 4059 4060 prev_size = BPF_LDST_BYTES(prev_ld); 4061 curr_size = BPF_LDST_BYTES(ld); 4062 prev_ld_base = prev_ld->src_reg; 4063 prev_st_base = prev_st->dst_reg; 4064 prev_ld_dst = prev_ld->dst_reg; 4065 prev_ld_off = prev_ld->off; 4066 prev_st_off = prev_st->off; 4067 4068 if (ld->dst_reg != prev_ld_dst) 4069 return false; 4070 4071 if (ld->src_reg != prev_ld_base || st->dst_reg != prev_st_base) 4072 return false; 4073 4074 if (curr_size != prev_size) 4075 return false; 4076 4077 /* There is jump to the head of this pair. */ 4078 if (ld_meta->flags & FLAG_INSN_IS_JUMP_DST) 4079 return false; 4080 4081 /* Both in ascending order. */ 4082 if (prev_ld_off + prev_size == ld->off && 4083 prev_st_off + prev_size == st->off) 4084 return true; 4085 4086 /* Both in descending order. */ 4087 if (ld->off + curr_size == prev_ld_off && 4088 st->off + curr_size == prev_st_off) 4089 return true; 4090 4091 return false; 4092 } 4093 4094 /* Return TRUE if cross memory access happens. Cross memory access means 4095 * store area is overlapping with load area that a later load might load 4096 * the value from previous store, for this case we can't treat the sequence 4097 * as an memory copy. 4098 */ 4099 static bool 4100 cross_mem_access(struct bpf_insn *ld, struct nfp_insn_meta *head_ld_meta, 4101 struct nfp_insn_meta *head_st_meta) 4102 { 4103 s16 head_ld_off, head_st_off, ld_off; 4104 4105 /* Different pointer types does not overlap. */ 4106 if (head_ld_meta->ptr.type != head_st_meta->ptr.type) 4107 return false; 4108 4109 /* load and store are both PTR_TO_PACKET, check ID info. */ 4110 if (head_ld_meta->ptr.id != head_st_meta->ptr.id) 4111 return true; 4112 4113 /* Canonicalize the offsets. Turn all of them against the original 4114 * base register. 4115 */ 4116 head_ld_off = head_ld_meta->insn.off + head_ld_meta->ptr.off; 4117 head_st_off = head_st_meta->insn.off + head_st_meta->ptr.off; 4118 ld_off = ld->off + head_ld_meta->ptr.off; 4119 4120 /* Ascending order cross. */ 4121 if (ld_off > head_ld_off && 4122 head_ld_off < head_st_off && ld_off >= head_st_off) 4123 return true; 4124 4125 /* Descending order cross. */ 4126 if (ld_off < head_ld_off && 4127 head_ld_off > head_st_off && ld_off <= head_st_off) 4128 return true; 4129 4130 return false; 4131 } 4132 4133 /* This pass try to identify the following instructoin sequences. 4134 * 4135 * load R, [regA + offA] 4136 * store [regB + offB], R 4137 * load R, [regA + offA + const_imm_A] 4138 * store [regB + offB + const_imm_A], R 4139 * load R, [regA + offA + 2 * const_imm_A] 4140 * store [regB + offB + 2 * const_imm_A], R 4141 * ... 4142 * 4143 * Above sequence is typically generated by compiler when lowering 4144 * memcpy. NFP prefer using CPP instructions to accelerate it. 4145 */ 4146 static void nfp_bpf_opt_ldst_gather(struct nfp_prog *nfp_prog) 4147 { 4148 struct nfp_insn_meta *head_ld_meta = NULL; 4149 struct nfp_insn_meta *head_st_meta = NULL; 4150 struct nfp_insn_meta *meta1, *meta2; 4151 struct bpf_insn *prev_ld = NULL; 4152 struct bpf_insn *prev_st = NULL; 4153 u8 count = 0; 4154 4155 nfp_for_each_insn_walk2(nfp_prog, meta1, meta2) { 4156 struct bpf_insn *ld = &meta1->insn; 4157 struct bpf_insn *st = &meta2->insn; 4158 4159 /* Reset record status if any of the following if true: 4160 * - The current insn pair is not load/store. 4161 * - The load/store pair doesn't chain with previous one. 4162 * - The chained load/store pair crossed with previous pair. 4163 * - The chained load/store pair has a total size of memory 4164 * copy beyond 128 bytes which is the maximum length a 4165 * single NFP CPP command can transfer. 4166 */ 4167 if (!curr_pair_is_memcpy(meta1, meta2) || 4168 !curr_pair_chain_with_previous(meta1, meta2, prev_ld, 4169 prev_st) || 4170 (head_ld_meta && (cross_mem_access(ld, head_ld_meta, 4171 head_st_meta) || 4172 head_ld_meta->ldst_gather_len >= 128))) { 4173 if (!count) 4174 continue; 4175 4176 if (count > 1) { 4177 s16 prev_ld_off = prev_ld->off; 4178 s16 prev_st_off = prev_st->off; 4179 s16 head_ld_off = head_ld_meta->insn.off; 4180 4181 if (prev_ld_off < head_ld_off) { 4182 head_ld_meta->insn.off = prev_ld_off; 4183 head_st_meta->insn.off = prev_st_off; 4184 head_ld_meta->ldst_gather_len = 4185 -head_ld_meta->ldst_gather_len; 4186 } 4187 4188 head_ld_meta->paired_st = &head_st_meta->insn; 4189 head_st_meta->flags |= 4190 FLAG_INSN_SKIP_PREC_DEPENDENT; 4191 } else { 4192 head_ld_meta->ldst_gather_len = 0; 4193 } 4194 4195 /* If the chain is ended by an load/store pair then this 4196 * could serve as the new head of the the next chain. 4197 */ 4198 if (curr_pair_is_memcpy(meta1, meta2)) { 4199 head_ld_meta = meta1; 4200 head_st_meta = meta2; 4201 head_ld_meta->ldst_gather_len = 4202 BPF_LDST_BYTES(ld); 4203 meta1 = nfp_meta_next(meta1); 4204 meta2 = nfp_meta_next(meta2); 4205 prev_ld = ld; 4206 prev_st = st; 4207 count = 1; 4208 } else { 4209 head_ld_meta = NULL; 4210 head_st_meta = NULL; 4211 prev_ld = NULL; 4212 prev_st = NULL; 4213 count = 0; 4214 } 4215 4216 continue; 4217 } 4218 4219 if (!head_ld_meta) { 4220 head_ld_meta = meta1; 4221 head_st_meta = meta2; 4222 } else { 4223 meta1->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 4224 meta2->flags |= FLAG_INSN_SKIP_PREC_DEPENDENT; 4225 } 4226 4227 head_ld_meta->ldst_gather_len += BPF_LDST_BYTES(ld); 4228 meta1 = nfp_meta_next(meta1); 4229 meta2 = nfp_meta_next(meta2); 4230 prev_ld = ld; 4231 prev_st = st; 4232 count++; 4233 } 4234 } 4235 4236 static void nfp_bpf_opt_pkt_cache(struct nfp_prog *nfp_prog) 4237 { 4238 struct nfp_insn_meta *meta, *range_node = NULL; 4239 s16 range_start = 0, range_end = 0; 4240 bool cache_avail = false; 4241 struct bpf_insn *insn; 4242 s32 range_ptr_off = 0; 4243 u32 range_ptr_id = 0; 4244 4245 list_for_each_entry(meta, &nfp_prog->insns, l) { 4246 if (meta->flags & FLAG_INSN_IS_JUMP_DST) 4247 cache_avail = false; 4248 4249 if (meta->flags & FLAG_INSN_SKIP_MASK) 4250 continue; 4251 4252 insn = &meta->insn; 4253 4254 if (is_mbpf_store_pkt(meta) || 4255 insn->code == (BPF_JMP | BPF_CALL) || 4256 is_mbpf_classic_store_pkt(meta) || 4257 is_mbpf_classic_load(meta)) { 4258 cache_avail = false; 4259 continue; 4260 } 4261 4262 if (!is_mbpf_load(meta)) 4263 continue; 4264 4265 if (meta->ptr.type != PTR_TO_PACKET || meta->ldst_gather_len) { 4266 cache_avail = false; 4267 continue; 4268 } 4269 4270 if (!cache_avail) { 4271 cache_avail = true; 4272 if (range_node) 4273 goto end_current_then_start_new; 4274 goto start_new; 4275 } 4276 4277 /* Check ID to make sure two reads share the same 4278 * variable offset against PTR_TO_PACKET, and check OFF 4279 * to make sure they also share the same constant 4280 * offset. 4281 * 4282 * OFFs don't really need to be the same, because they 4283 * are the constant offsets against PTR_TO_PACKET, so 4284 * for different OFFs, we could canonicalize them to 4285 * offsets against original packet pointer. We don't 4286 * support this. 4287 */ 4288 if (meta->ptr.id == range_ptr_id && 4289 meta->ptr.off == range_ptr_off) { 4290 s16 new_start = range_start; 4291 s16 end, off = insn->off; 4292 s16 new_end = range_end; 4293 bool changed = false; 4294 4295 if (off < range_start) { 4296 new_start = off; 4297 changed = true; 4298 } 4299 4300 end = off + BPF_LDST_BYTES(insn); 4301 if (end > range_end) { 4302 new_end = end; 4303 changed = true; 4304 } 4305 4306 if (!changed) 4307 continue; 4308 4309 if (new_end - new_start <= 64) { 4310 /* Install new range. */ 4311 range_start = new_start; 4312 range_end = new_end; 4313 continue; 4314 } 4315 } 4316 4317 end_current_then_start_new: 4318 range_node->pkt_cache.range_start = range_start; 4319 range_node->pkt_cache.range_end = range_end; 4320 start_new: 4321 range_node = meta; 4322 range_node->pkt_cache.do_init = true; 4323 range_ptr_id = range_node->ptr.id; 4324 range_ptr_off = range_node->ptr.off; 4325 range_start = insn->off; 4326 range_end = insn->off + BPF_LDST_BYTES(insn); 4327 } 4328 4329 if (range_node) { 4330 range_node->pkt_cache.range_start = range_start; 4331 range_node->pkt_cache.range_end = range_end; 4332 } 4333 4334 list_for_each_entry(meta, &nfp_prog->insns, l) { 4335 if (meta->flags & FLAG_INSN_SKIP_MASK) 4336 continue; 4337 4338 if (is_mbpf_load_pkt(meta) && !meta->ldst_gather_len) { 4339 if (meta->pkt_cache.do_init) { 4340 range_start = meta->pkt_cache.range_start; 4341 range_end = meta->pkt_cache.range_end; 4342 } else { 4343 meta->pkt_cache.range_start = range_start; 4344 meta->pkt_cache.range_end = range_end; 4345 } 4346 } 4347 } 4348 } 4349 4350 static int nfp_bpf_optimize(struct nfp_prog *nfp_prog) 4351 { 4352 nfp_bpf_opt_reg_init(nfp_prog); 4353 4354 nfp_bpf_opt_neg_add_sub(nfp_prog); 4355 nfp_bpf_opt_ld_mask(nfp_prog); 4356 nfp_bpf_opt_ld_shift(nfp_prog); 4357 nfp_bpf_opt_ldst_gather(nfp_prog); 4358 nfp_bpf_opt_pkt_cache(nfp_prog); 4359 4360 return 0; 4361 } 4362 4363 static int nfp_bpf_replace_map_ptrs(struct nfp_prog *nfp_prog) 4364 { 4365 struct nfp_insn_meta *meta1, *meta2; 4366 struct nfp_bpf_map *nfp_map; 4367 struct bpf_map *map; 4368 u32 id; 4369 4370 nfp_for_each_insn_walk2(nfp_prog, meta1, meta2) { 4371 if (meta1->flags & FLAG_INSN_SKIP_MASK || 4372 meta2->flags & FLAG_INSN_SKIP_MASK) 4373 continue; 4374 4375 if (meta1->insn.code != (BPF_LD | BPF_IMM | BPF_DW) || 4376 meta1->insn.src_reg != BPF_PSEUDO_MAP_FD) 4377 continue; 4378 4379 map = (void *)(unsigned long)((u32)meta1->insn.imm | 4380 (u64)meta2->insn.imm << 32); 4381 if (bpf_map_offload_neutral(map)) { 4382 id = map->id; 4383 } else { 4384 nfp_map = map_to_offmap(map)->dev_priv; 4385 id = nfp_map->tid; 4386 } 4387 4388 meta1->insn.imm = id; 4389 meta2->insn.imm = 0; 4390 } 4391 4392 return 0; 4393 } 4394 4395 static int nfp_bpf_ustore_calc(u64 *prog, unsigned int len) 4396 { 4397 __le64 *ustore = (__force __le64 *)prog; 4398 int i; 4399 4400 for (i = 0; i < len; i++) { 4401 int err; 4402 4403 err = nfp_ustore_check_valid_no_ecc(prog[i]); 4404 if (err) 4405 return err; 4406 4407 ustore[i] = cpu_to_le64(nfp_ustore_calc_ecc_insn(prog[i])); 4408 } 4409 4410 return 0; 4411 } 4412 4413 static void nfp_bpf_prog_trim(struct nfp_prog *nfp_prog) 4414 { 4415 void *prog; 4416 4417 prog = kvmalloc_array(nfp_prog->prog_len, sizeof(u64), GFP_KERNEL); 4418 if (!prog) 4419 return; 4420 4421 nfp_prog->__prog_alloc_len = nfp_prog->prog_len * sizeof(u64); 4422 memcpy(prog, nfp_prog->prog, nfp_prog->__prog_alloc_len); 4423 kvfree(nfp_prog->prog); 4424 nfp_prog->prog = prog; 4425 } 4426 4427 int nfp_bpf_jit(struct nfp_prog *nfp_prog) 4428 { 4429 int ret; 4430 4431 ret = nfp_bpf_replace_map_ptrs(nfp_prog); 4432 if (ret) 4433 return ret; 4434 4435 ret = nfp_bpf_optimize(nfp_prog); 4436 if (ret) 4437 return ret; 4438 4439 ret = nfp_translate(nfp_prog); 4440 if (ret) { 4441 pr_err("Translation failed with error %d (translated: %u)\n", 4442 ret, nfp_prog->n_translated); 4443 return -EINVAL; 4444 } 4445 4446 nfp_bpf_prog_trim(nfp_prog); 4447 4448 return ret; 4449 } 4450 4451 void nfp_bpf_jit_prepare(struct nfp_prog *nfp_prog) 4452 { 4453 struct nfp_insn_meta *meta; 4454 4455 /* Another pass to record jump information. */ 4456 list_for_each_entry(meta, &nfp_prog->insns, l) { 4457 struct nfp_insn_meta *dst_meta; 4458 u64 code = meta->insn.code; 4459 unsigned int dst_idx; 4460 bool pseudo_call; 4461 4462 if (!is_mbpf_jmp(meta)) 4463 continue; 4464 if (BPF_OP(code) == BPF_EXIT) 4465 continue; 4466 if (is_mbpf_helper_call(meta)) 4467 continue; 4468 4469 /* If opcode is BPF_CALL at this point, this can only be a 4470 * BPF-to-BPF call (a.k.a pseudo call). 4471 */ 4472 pseudo_call = BPF_OP(code) == BPF_CALL; 4473 4474 if (pseudo_call) 4475 dst_idx = meta->n + 1 + meta->insn.imm; 4476 else 4477 dst_idx = meta->n + 1 + meta->insn.off; 4478 4479 dst_meta = nfp_bpf_goto_meta(nfp_prog, meta, dst_idx); 4480 4481 if (pseudo_call) 4482 dst_meta->flags |= FLAG_INSN_IS_SUBPROG_START; 4483 4484 dst_meta->flags |= FLAG_INSN_IS_JUMP_DST; 4485 meta->jmp_dst = dst_meta; 4486 } 4487 } 4488 4489 bool nfp_bpf_supported_opcode(u8 code) 4490 { 4491 return !!instr_cb[code]; 4492 } 4493 4494 void *nfp_bpf_relo_for_vnic(struct nfp_prog *nfp_prog, struct nfp_bpf_vnic *bv) 4495 { 4496 unsigned int i; 4497 u64 *prog; 4498 int err; 4499 4500 prog = kmemdup(nfp_prog->prog, nfp_prog->prog_len * sizeof(u64), 4501 GFP_KERNEL); 4502 if (!prog) 4503 return ERR_PTR(-ENOMEM); 4504 4505 for (i = 0; i < nfp_prog->prog_len; i++) { 4506 enum nfp_relo_type special; 4507 u32 val; 4508 u16 off; 4509 4510 special = FIELD_GET(OP_RELO_TYPE, prog[i]); 4511 switch (special) { 4512 case RELO_NONE: 4513 continue; 4514 case RELO_BR_REL: 4515 br_add_offset(&prog[i], bv->start_off); 4516 break; 4517 case RELO_BR_GO_OUT: 4518 br_set_offset(&prog[i], 4519 nfp_prog->tgt_out + bv->start_off); 4520 break; 4521 case RELO_BR_GO_ABORT: 4522 br_set_offset(&prog[i], 4523 nfp_prog->tgt_abort + bv->start_off); 4524 break; 4525 case RELO_BR_GO_CALL_PUSH_REGS: 4526 if (!nfp_prog->tgt_call_push_regs) { 4527 pr_err("BUG: failed to detect subprogram registers needs\n"); 4528 err = -EINVAL; 4529 goto err_free_prog; 4530 } 4531 off = nfp_prog->tgt_call_push_regs + bv->start_off; 4532 br_set_offset(&prog[i], off); 4533 break; 4534 case RELO_BR_GO_CALL_POP_REGS: 4535 if (!nfp_prog->tgt_call_pop_regs) { 4536 pr_err("BUG: failed to detect subprogram registers needs\n"); 4537 err = -EINVAL; 4538 goto err_free_prog; 4539 } 4540 off = nfp_prog->tgt_call_pop_regs + bv->start_off; 4541 br_set_offset(&prog[i], off); 4542 break; 4543 case RELO_BR_NEXT_PKT: 4544 br_set_offset(&prog[i], bv->tgt_done); 4545 break; 4546 case RELO_BR_HELPER: 4547 val = br_get_offset(prog[i]); 4548 val -= BR_OFF_RELO; 4549 switch (val) { 4550 case BPF_FUNC_map_lookup_elem: 4551 val = nfp_prog->bpf->helpers.map_lookup; 4552 break; 4553 case BPF_FUNC_map_update_elem: 4554 val = nfp_prog->bpf->helpers.map_update; 4555 break; 4556 case BPF_FUNC_map_delete_elem: 4557 val = nfp_prog->bpf->helpers.map_delete; 4558 break; 4559 case BPF_FUNC_perf_event_output: 4560 val = nfp_prog->bpf->helpers.perf_event_output; 4561 break; 4562 default: 4563 pr_err("relocation of unknown helper %d\n", 4564 val); 4565 err = -EINVAL; 4566 goto err_free_prog; 4567 } 4568 br_set_offset(&prog[i], val); 4569 break; 4570 case RELO_IMMED_REL: 4571 immed_add_value(&prog[i], bv->start_off); 4572 break; 4573 } 4574 4575 prog[i] &= ~OP_RELO_TYPE; 4576 } 4577 4578 err = nfp_bpf_ustore_calc(prog, nfp_prog->prog_len); 4579 if (err) 4580 goto err_free_prog; 4581 4582 return prog; 4583 4584 err_free_prog: 4585 kfree(prog); 4586 return ERR_PTR(err); 4587 } 4588