186387e1aSJeff Kirsher /************************************************************************ 286387e1aSJeff Kirsher * regs.h: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC 386387e1aSJeff Kirsher * Copyright(c) 2002-2010 Exar Corp. 486387e1aSJeff Kirsher 586387e1aSJeff Kirsher * This software may be used and distributed according to the terms of 686387e1aSJeff Kirsher * the GNU General Public License (GPL), incorporated herein by reference. 786387e1aSJeff Kirsher * Drivers based on or derived from this code fall under the GPL and must 886387e1aSJeff Kirsher * retain the authorship, copyright and license notice. This file is not 986387e1aSJeff Kirsher * a complete program and may only be used when the entire operating 1086387e1aSJeff Kirsher * system is licensed under the GPL. 1186387e1aSJeff Kirsher * See the file COPYING in this distribution for more information. 1286387e1aSJeff Kirsher ************************************************************************/ 1386387e1aSJeff Kirsher #ifndef _REGS_H 1486387e1aSJeff Kirsher #define _REGS_H 1586387e1aSJeff Kirsher 1686387e1aSJeff Kirsher #define TBD 0 1786387e1aSJeff Kirsher 1886387e1aSJeff Kirsher struct XENA_dev_config { 1986387e1aSJeff Kirsher /* Convention: mHAL_XXX is mask, vHAL_XXX is value */ 2086387e1aSJeff Kirsher 2186387e1aSJeff Kirsher /* General Control-Status Registers */ 2286387e1aSJeff Kirsher u64 general_int_status; 2386387e1aSJeff Kirsher #define GEN_INTR_TXPIC s2BIT(0) 2486387e1aSJeff Kirsher #define GEN_INTR_TXDMA s2BIT(1) 2586387e1aSJeff Kirsher #define GEN_INTR_TXMAC s2BIT(2) 2686387e1aSJeff Kirsher #define GEN_INTR_TXXGXS s2BIT(3) 2786387e1aSJeff Kirsher #define GEN_INTR_TXTRAFFIC s2BIT(8) 2886387e1aSJeff Kirsher #define GEN_INTR_RXPIC s2BIT(32) 2986387e1aSJeff Kirsher #define GEN_INTR_RXDMA s2BIT(33) 3086387e1aSJeff Kirsher #define GEN_INTR_RXMAC s2BIT(34) 3186387e1aSJeff Kirsher #define GEN_INTR_MC s2BIT(35) 3286387e1aSJeff Kirsher #define GEN_INTR_RXXGXS s2BIT(36) 3386387e1aSJeff Kirsher #define GEN_INTR_RXTRAFFIC s2BIT(40) 3486387e1aSJeff Kirsher #define GEN_ERROR_INTR GEN_INTR_TXPIC | GEN_INTR_RXPIC | \ 3586387e1aSJeff Kirsher GEN_INTR_TXDMA | GEN_INTR_RXDMA | \ 3686387e1aSJeff Kirsher GEN_INTR_TXMAC | GEN_INTR_RXMAC | \ 3786387e1aSJeff Kirsher GEN_INTR_TXXGXS| GEN_INTR_RXXGXS| \ 3886387e1aSJeff Kirsher GEN_INTR_MC 3986387e1aSJeff Kirsher 4086387e1aSJeff Kirsher u64 general_int_mask; 4186387e1aSJeff Kirsher 4286387e1aSJeff Kirsher u8 unused0[0x100 - 0x10]; 4386387e1aSJeff Kirsher 4486387e1aSJeff Kirsher u64 sw_reset; 4586387e1aSJeff Kirsher /* XGXS must be removed from reset only once. */ 4686387e1aSJeff Kirsher #define SW_RESET_XENA vBIT(0xA5,0,8) 4786387e1aSJeff Kirsher #define SW_RESET_FLASH vBIT(0xA5,8,8) 4886387e1aSJeff Kirsher #define SW_RESET_EOI vBIT(0xA5,16,8) 4986387e1aSJeff Kirsher #define SW_RESET_ALL (SW_RESET_XENA | \ 5086387e1aSJeff Kirsher SW_RESET_FLASH | \ 5186387e1aSJeff Kirsher SW_RESET_EOI) 5286387e1aSJeff Kirsher /* The SW_RESET register must read this value after a successful reset. */ 5386387e1aSJeff Kirsher #define SW_RESET_RAW_VAL 0xA5000000 5486387e1aSJeff Kirsher 5586387e1aSJeff Kirsher 5686387e1aSJeff Kirsher u64 adapter_status; 5786387e1aSJeff Kirsher #define ADAPTER_STATUS_TDMA_READY s2BIT(0) 5886387e1aSJeff Kirsher #define ADAPTER_STATUS_RDMA_READY s2BIT(1) 5986387e1aSJeff Kirsher #define ADAPTER_STATUS_PFC_READY s2BIT(2) 6086387e1aSJeff Kirsher #define ADAPTER_STATUS_TMAC_BUF_EMPTY s2BIT(3) 6186387e1aSJeff Kirsher #define ADAPTER_STATUS_PIC_QUIESCENT s2BIT(5) 6286387e1aSJeff Kirsher #define ADAPTER_STATUS_RMAC_REMOTE_FAULT s2BIT(6) 6386387e1aSJeff Kirsher #define ADAPTER_STATUS_RMAC_LOCAL_FAULT s2BIT(7) 6486387e1aSJeff Kirsher #define ADAPTER_STATUS_RMAC_PCC_IDLE vBIT(0xFF,8,8) 6586387e1aSJeff Kirsher #define ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE vBIT(0x0F,8,8) 6686387e1aSJeff Kirsher #define ADAPTER_STATUS_RC_PRC_QUIESCENT vBIT(0xFF,16,8) 6786387e1aSJeff Kirsher #define ADAPTER_STATUS_MC_DRAM_READY s2BIT(24) 6886387e1aSJeff Kirsher #define ADAPTER_STATUS_MC_QUEUES_READY s2BIT(25) 6986387e1aSJeff Kirsher #define ADAPTER_STATUS_RIC_RUNNING s2BIT(26) 7086387e1aSJeff Kirsher #define ADAPTER_STATUS_M_PLL_LOCK s2BIT(30) 7186387e1aSJeff Kirsher #define ADAPTER_STATUS_P_PLL_LOCK s2BIT(31) 7286387e1aSJeff Kirsher 7386387e1aSJeff Kirsher u64 adapter_control; 7486387e1aSJeff Kirsher #define ADAPTER_CNTL_EN s2BIT(7) 7586387e1aSJeff Kirsher #define ADAPTER_EOI_TX_ON s2BIT(15) 7686387e1aSJeff Kirsher #define ADAPTER_LED_ON s2BIT(23) 7786387e1aSJeff Kirsher #define ADAPTER_UDPI(val) vBIT(val,36,4) 7886387e1aSJeff Kirsher #define ADAPTER_WAIT_INT s2BIT(48) 7986387e1aSJeff Kirsher #define ADAPTER_ECC_EN s2BIT(55) 8086387e1aSJeff Kirsher 8186387e1aSJeff Kirsher u64 serr_source; 8286387e1aSJeff Kirsher #define SERR_SOURCE_PIC s2BIT(0) 8386387e1aSJeff Kirsher #define SERR_SOURCE_TXDMA s2BIT(1) 8486387e1aSJeff Kirsher #define SERR_SOURCE_RXDMA s2BIT(2) 8586387e1aSJeff Kirsher #define SERR_SOURCE_MAC s2BIT(3) 8686387e1aSJeff Kirsher #define SERR_SOURCE_MC s2BIT(4) 8786387e1aSJeff Kirsher #define SERR_SOURCE_XGXS s2BIT(5) 8886387e1aSJeff Kirsher #define SERR_SOURCE_ANY (SERR_SOURCE_PIC | \ 8986387e1aSJeff Kirsher SERR_SOURCE_TXDMA | \ 9086387e1aSJeff Kirsher SERR_SOURCE_RXDMA | \ 9186387e1aSJeff Kirsher SERR_SOURCE_MAC | \ 9286387e1aSJeff Kirsher SERR_SOURCE_MC | \ 9386387e1aSJeff Kirsher SERR_SOURCE_XGXS) 9486387e1aSJeff Kirsher 9586387e1aSJeff Kirsher u64 pci_mode; 9686387e1aSJeff Kirsher #define GET_PCI_MODE(val) ((val & vBIT(0xF, 0, 4)) >> 60) 9786387e1aSJeff Kirsher #define PCI_MODE_PCI_33 0 9886387e1aSJeff Kirsher #define PCI_MODE_PCI_66 0x1 9986387e1aSJeff Kirsher #define PCI_MODE_PCIX_M1_66 0x2 10086387e1aSJeff Kirsher #define PCI_MODE_PCIX_M1_100 0x3 10186387e1aSJeff Kirsher #define PCI_MODE_PCIX_M1_133 0x4 10286387e1aSJeff Kirsher #define PCI_MODE_PCIX_M2_66 0x5 10386387e1aSJeff Kirsher #define PCI_MODE_PCIX_M2_100 0x6 10486387e1aSJeff Kirsher #define PCI_MODE_PCIX_M2_133 0x7 10586387e1aSJeff Kirsher #define PCI_MODE_UNSUPPORTED s2BIT(0) 10686387e1aSJeff Kirsher #define PCI_MODE_32_BITS s2BIT(8) 10786387e1aSJeff Kirsher #define PCI_MODE_UNKNOWN_MODE s2BIT(9) 10886387e1aSJeff Kirsher 10986387e1aSJeff Kirsher u8 unused_0[0x800 - 0x128]; 11086387e1aSJeff Kirsher 11186387e1aSJeff Kirsher /* PCI-X Controller registers */ 11286387e1aSJeff Kirsher u64 pic_int_status; 11386387e1aSJeff Kirsher u64 pic_int_mask; 11486387e1aSJeff Kirsher #define PIC_INT_TX s2BIT(0) 11586387e1aSJeff Kirsher #define PIC_INT_FLSH s2BIT(1) 11686387e1aSJeff Kirsher #define PIC_INT_MDIO s2BIT(2) 11786387e1aSJeff Kirsher #define PIC_INT_IIC s2BIT(3) 11886387e1aSJeff Kirsher #define PIC_INT_GPIO s2BIT(4) 11986387e1aSJeff Kirsher #define PIC_INT_RX s2BIT(32) 12086387e1aSJeff Kirsher 12186387e1aSJeff Kirsher u64 txpic_int_reg; 12286387e1aSJeff Kirsher u64 txpic_int_mask; 12386387e1aSJeff Kirsher #define PCIX_INT_REG_ECC_SG_ERR s2BIT(0) 12486387e1aSJeff Kirsher #define PCIX_INT_REG_ECC_DB_ERR s2BIT(1) 12586387e1aSJeff Kirsher #define PCIX_INT_REG_FLASHR_R_FSM_ERR s2BIT(8) 12686387e1aSJeff Kirsher #define PCIX_INT_REG_FLASHR_W_FSM_ERR s2BIT(9) 12786387e1aSJeff Kirsher #define PCIX_INT_REG_INI_TX_FSM_SERR s2BIT(10) 12886387e1aSJeff Kirsher #define PCIX_INT_REG_INI_TXO_FSM_ERR s2BIT(11) 12986387e1aSJeff Kirsher #define PCIX_INT_REG_TRT_FSM_SERR s2BIT(13) 13086387e1aSJeff Kirsher #define PCIX_INT_REG_SRT_FSM_SERR s2BIT(14) 13186387e1aSJeff Kirsher #define PCIX_INT_REG_PIFR_FSM_SERR s2BIT(15) 13286387e1aSJeff Kirsher #define PCIX_INT_REG_WRC_TX_SEND_FSM_SERR s2BIT(21) 13386387e1aSJeff Kirsher #define PCIX_INT_REG_RRC_TX_REQ_FSM_SERR s2BIT(23) 13486387e1aSJeff Kirsher #define PCIX_INT_REG_INI_RX_FSM_SERR s2BIT(48) 13586387e1aSJeff Kirsher #define PCIX_INT_REG_RA_RX_FSM_SERR s2BIT(50) 13686387e1aSJeff Kirsher /* 13786387e1aSJeff Kirsher #define PCIX_INT_REG_WRC_RX_SEND_FSM_SERR s2BIT(52) 13886387e1aSJeff Kirsher #define PCIX_INT_REG_RRC_RX_REQ_FSM_SERR s2BIT(54) 13986387e1aSJeff Kirsher #define PCIX_INT_REG_RRC_RX_SPLIT_FSM_SERR s2BIT(58) 14086387e1aSJeff Kirsher */ 14186387e1aSJeff Kirsher u64 txpic_alarms; 14286387e1aSJeff Kirsher u64 rxpic_int_reg; 14386387e1aSJeff Kirsher u64 rxpic_int_mask; 14486387e1aSJeff Kirsher u64 rxpic_alarms; 14586387e1aSJeff Kirsher 14686387e1aSJeff Kirsher u64 flsh_int_reg; 14786387e1aSJeff Kirsher u64 flsh_int_mask; 14886387e1aSJeff Kirsher #define PIC_FLSH_INT_REG_CYCLE_FSM_ERR s2BIT(63) 14986387e1aSJeff Kirsher #define PIC_FLSH_INT_REG_ERR s2BIT(62) 15086387e1aSJeff Kirsher u64 flash_alarms; 15186387e1aSJeff Kirsher 15286387e1aSJeff Kirsher u64 mdio_int_reg; 15386387e1aSJeff Kirsher u64 mdio_int_mask; 15486387e1aSJeff Kirsher #define MDIO_INT_REG_MDIO_BUS_ERR s2BIT(0) 15586387e1aSJeff Kirsher #define MDIO_INT_REG_DTX_BUS_ERR s2BIT(8) 15686387e1aSJeff Kirsher #define MDIO_INT_REG_LASI s2BIT(39) 15786387e1aSJeff Kirsher u64 mdio_alarms; 15886387e1aSJeff Kirsher 15986387e1aSJeff Kirsher u64 iic_int_reg; 16086387e1aSJeff Kirsher u64 iic_int_mask; 16186387e1aSJeff Kirsher #define IIC_INT_REG_BUS_FSM_ERR s2BIT(4) 16286387e1aSJeff Kirsher #define IIC_INT_REG_BIT_FSM_ERR s2BIT(5) 16386387e1aSJeff Kirsher #define IIC_INT_REG_CYCLE_FSM_ERR s2BIT(6) 16486387e1aSJeff Kirsher #define IIC_INT_REG_REQ_FSM_ERR s2BIT(7) 16586387e1aSJeff Kirsher #define IIC_INT_REG_ACK_ERR s2BIT(8) 16686387e1aSJeff Kirsher u64 iic_alarms; 16786387e1aSJeff Kirsher 16886387e1aSJeff Kirsher u8 unused4[0x08]; 16986387e1aSJeff Kirsher 17086387e1aSJeff Kirsher u64 gpio_int_reg; 17186387e1aSJeff Kirsher #define GPIO_INT_REG_DP_ERR_INT s2BIT(0) 17286387e1aSJeff Kirsher #define GPIO_INT_REG_LINK_DOWN s2BIT(1) 17386387e1aSJeff Kirsher #define GPIO_INT_REG_LINK_UP s2BIT(2) 17486387e1aSJeff Kirsher u64 gpio_int_mask; 17586387e1aSJeff Kirsher #define GPIO_INT_MASK_LINK_DOWN s2BIT(1) 17686387e1aSJeff Kirsher #define GPIO_INT_MASK_LINK_UP s2BIT(2) 17786387e1aSJeff Kirsher u64 gpio_alarms; 17886387e1aSJeff Kirsher 17986387e1aSJeff Kirsher u8 unused5[0x38]; 18086387e1aSJeff Kirsher 18186387e1aSJeff Kirsher u64 tx_traffic_int; 18286387e1aSJeff Kirsher #define TX_TRAFFIC_INT_n(n) s2BIT(n) 18386387e1aSJeff Kirsher u64 tx_traffic_mask; 18486387e1aSJeff Kirsher 18586387e1aSJeff Kirsher u64 rx_traffic_int; 18686387e1aSJeff Kirsher #define RX_TRAFFIC_INT_n(n) s2BIT(n) 18786387e1aSJeff Kirsher u64 rx_traffic_mask; 18886387e1aSJeff Kirsher 18986387e1aSJeff Kirsher /* PIC Control registers */ 19086387e1aSJeff Kirsher u64 pic_control; 19186387e1aSJeff Kirsher #define PIC_CNTL_RX_ALARM_MAP_1 s2BIT(0) 19286387e1aSJeff Kirsher #define PIC_CNTL_SHARED_SPLITS(n) vBIT(n,11,5) 19386387e1aSJeff Kirsher 19486387e1aSJeff Kirsher u64 swapper_ctrl; 19586387e1aSJeff Kirsher #define SWAPPER_CTRL_PIF_R_FE s2BIT(0) 19686387e1aSJeff Kirsher #define SWAPPER_CTRL_PIF_R_SE s2BIT(1) 19786387e1aSJeff Kirsher #define SWAPPER_CTRL_PIF_W_FE s2BIT(8) 19886387e1aSJeff Kirsher #define SWAPPER_CTRL_PIF_W_SE s2BIT(9) 19986387e1aSJeff Kirsher #define SWAPPER_CTRL_TXP_FE s2BIT(16) 20086387e1aSJeff Kirsher #define SWAPPER_CTRL_TXP_SE s2BIT(17) 20186387e1aSJeff Kirsher #define SWAPPER_CTRL_TXD_R_FE s2BIT(18) 20286387e1aSJeff Kirsher #define SWAPPER_CTRL_TXD_R_SE s2BIT(19) 20386387e1aSJeff Kirsher #define SWAPPER_CTRL_TXD_W_FE s2BIT(20) 20486387e1aSJeff Kirsher #define SWAPPER_CTRL_TXD_W_SE s2BIT(21) 20586387e1aSJeff Kirsher #define SWAPPER_CTRL_TXF_R_FE s2BIT(22) 20686387e1aSJeff Kirsher #define SWAPPER_CTRL_TXF_R_SE s2BIT(23) 20786387e1aSJeff Kirsher #define SWAPPER_CTRL_RXD_R_FE s2BIT(32) 20886387e1aSJeff Kirsher #define SWAPPER_CTRL_RXD_R_SE s2BIT(33) 20986387e1aSJeff Kirsher #define SWAPPER_CTRL_RXD_W_FE s2BIT(34) 21086387e1aSJeff Kirsher #define SWAPPER_CTRL_RXD_W_SE s2BIT(35) 21186387e1aSJeff Kirsher #define SWAPPER_CTRL_RXF_W_FE s2BIT(36) 21286387e1aSJeff Kirsher #define SWAPPER_CTRL_RXF_W_SE s2BIT(37) 21386387e1aSJeff Kirsher #define SWAPPER_CTRL_XMSI_FE s2BIT(40) 21486387e1aSJeff Kirsher #define SWAPPER_CTRL_XMSI_SE s2BIT(41) 21586387e1aSJeff Kirsher #define SWAPPER_CTRL_STATS_FE s2BIT(48) 21686387e1aSJeff Kirsher #define SWAPPER_CTRL_STATS_SE s2BIT(49) 21786387e1aSJeff Kirsher 21886387e1aSJeff Kirsher u64 pif_rd_swapper_fb; 21986387e1aSJeff Kirsher #define IF_RD_SWAPPER_FB 0x0123456789ABCDEF 22086387e1aSJeff Kirsher 22186387e1aSJeff Kirsher u64 scheduled_int_ctrl; 22286387e1aSJeff Kirsher #define SCHED_INT_CTRL_TIMER_EN s2BIT(0) 22386387e1aSJeff Kirsher #define SCHED_INT_CTRL_ONE_SHOT s2BIT(1) 22486387e1aSJeff Kirsher #define SCHED_INT_CTRL_INT2MSI(val) vBIT(val,10,6) 22586387e1aSJeff Kirsher #define SCHED_INT_PERIOD TBD 22686387e1aSJeff Kirsher 22786387e1aSJeff Kirsher u64 txreqtimeout; 22886387e1aSJeff Kirsher #define TXREQTO_VAL(val) vBIT(val,0,32) 22986387e1aSJeff Kirsher #define TXREQTO_EN s2BIT(63) 23086387e1aSJeff Kirsher 23186387e1aSJeff Kirsher u64 statsreqtimeout; 23286387e1aSJeff Kirsher #define STATREQTO_VAL(n) TBD 23386387e1aSJeff Kirsher #define STATREQTO_EN s2BIT(63) 23486387e1aSJeff Kirsher 23586387e1aSJeff Kirsher u64 read_retry_delay; 23686387e1aSJeff Kirsher u64 read_retry_acceleration; 23786387e1aSJeff Kirsher u64 write_retry_delay; 23886387e1aSJeff Kirsher u64 write_retry_acceleration; 23986387e1aSJeff Kirsher 24086387e1aSJeff Kirsher u64 xmsi_control; 24186387e1aSJeff Kirsher u64 xmsi_access; 24286387e1aSJeff Kirsher u64 xmsi_address; 24386387e1aSJeff Kirsher u64 xmsi_data; 24486387e1aSJeff Kirsher 24586387e1aSJeff Kirsher u64 rx_mat; 24686387e1aSJeff Kirsher #define RX_MAT_SET(ring, msi) vBIT(msi, (8 * ring), 8) 24786387e1aSJeff Kirsher 24886387e1aSJeff Kirsher u8 unused6[0x8]; 24986387e1aSJeff Kirsher 25086387e1aSJeff Kirsher u64 tx_mat0_n[0x8]; 25186387e1aSJeff Kirsher #define TX_MAT_SET(fifo, msi) vBIT(msi, (8 * fifo), 8) 25286387e1aSJeff Kirsher 25386387e1aSJeff Kirsher u64 xmsi_mask_reg; 25486387e1aSJeff Kirsher u64 stat_byte_cnt; 25586387e1aSJeff Kirsher #define STAT_BC(n) vBIT(n,4,12) 25686387e1aSJeff Kirsher 25786387e1aSJeff Kirsher /* Automated statistics collection */ 25886387e1aSJeff Kirsher u64 stat_cfg; 25986387e1aSJeff Kirsher #define STAT_CFG_STAT_EN s2BIT(0) 26086387e1aSJeff Kirsher #define STAT_CFG_ONE_SHOT_EN s2BIT(1) 26186387e1aSJeff Kirsher #define STAT_CFG_STAT_NS_EN s2BIT(8) 26286387e1aSJeff Kirsher #define STAT_CFG_STAT_RO s2BIT(9) 26386387e1aSJeff Kirsher #define STAT_TRSF_PER(n) TBD 26486387e1aSJeff Kirsher #define PER_SEC 0x208d5 26586387e1aSJeff Kirsher #define SET_UPDT_PERIOD(n) vBIT((PER_SEC*n),32,32) 26686387e1aSJeff Kirsher #define SET_UPDT_CLICKS(val) vBIT(val, 32, 32) 26786387e1aSJeff Kirsher 26886387e1aSJeff Kirsher u64 stat_addr; 26986387e1aSJeff Kirsher 27086387e1aSJeff Kirsher /* General Configuration */ 27186387e1aSJeff Kirsher u64 mdio_control; 27286387e1aSJeff Kirsher #define MDIO_MMD_INDX_ADDR(val) vBIT(val, 0, 16) 27386387e1aSJeff Kirsher #define MDIO_MMD_DEV_ADDR(val) vBIT(val, 19, 5) 27486387e1aSJeff Kirsher #define MDIO_MMS_PRT_ADDR(val) vBIT(val, 27, 5) 27586387e1aSJeff Kirsher #define MDIO_CTRL_START_TRANS(val) vBIT(val, 56, 4) 27686387e1aSJeff Kirsher #define MDIO_OP(val) vBIT(val, 60, 2) 27786387e1aSJeff Kirsher #define MDIO_OP_ADDR_TRANS 0x0 27886387e1aSJeff Kirsher #define MDIO_OP_WRITE_TRANS 0x1 27986387e1aSJeff Kirsher #define MDIO_OP_READ_POST_INC_TRANS 0x2 28086387e1aSJeff Kirsher #define MDIO_OP_READ_TRANS 0x3 28186387e1aSJeff Kirsher #define MDIO_MDIO_DATA(val) vBIT(val, 32, 16) 28286387e1aSJeff Kirsher 28386387e1aSJeff Kirsher u64 dtx_control; 28486387e1aSJeff Kirsher 28586387e1aSJeff Kirsher u64 i2c_control; 28686387e1aSJeff Kirsher #define I2C_CONTROL_DEV_ID(id) vBIT(id,1,3) 28786387e1aSJeff Kirsher #define I2C_CONTROL_ADDR(addr) vBIT(addr,5,11) 28886387e1aSJeff Kirsher #define I2C_CONTROL_BYTE_CNT(cnt) vBIT(cnt,22,2) 28986387e1aSJeff Kirsher #define I2C_CONTROL_READ s2BIT(24) 29086387e1aSJeff Kirsher #define I2C_CONTROL_NACK s2BIT(25) 29186387e1aSJeff Kirsher #define I2C_CONTROL_CNTL_START vBIT(0xE,28,4) 29286387e1aSJeff Kirsher #define I2C_CONTROL_CNTL_END(val) (val & vBIT(0x1,28,4)) 29386387e1aSJeff Kirsher #define I2C_CONTROL_GET_DATA(val) (u32)(val & 0xFFFFFFFF) 29486387e1aSJeff Kirsher #define I2C_CONTROL_SET_DATA(val) vBIT(val,32,32) 29586387e1aSJeff Kirsher 29686387e1aSJeff Kirsher u64 gpio_control; 29786387e1aSJeff Kirsher #define GPIO_CTRL_GPIO_0 s2BIT(8) 29886387e1aSJeff Kirsher u64 misc_control; 29986387e1aSJeff Kirsher #define FAULT_BEHAVIOUR s2BIT(0) 30086387e1aSJeff Kirsher #define EXT_REQ_EN s2BIT(1) 30186387e1aSJeff Kirsher #define MISC_LINK_STABILITY_PRD(val) vBIT(val,29,3) 30286387e1aSJeff Kirsher 30386387e1aSJeff Kirsher u8 unused7_1[0x230 - 0x208]; 30486387e1aSJeff Kirsher 30586387e1aSJeff Kirsher u64 pic_control2; 30686387e1aSJeff Kirsher u64 ini_dperr_ctrl; 30786387e1aSJeff Kirsher 30886387e1aSJeff Kirsher u64 wreq_split_mask; 30986387e1aSJeff Kirsher #define WREQ_SPLIT_MASK_SET_MASK(val) vBIT(val, 52, 12) 31086387e1aSJeff Kirsher 31186387e1aSJeff Kirsher u8 unused7_2[0x800 - 0x248]; 31286387e1aSJeff Kirsher 31386387e1aSJeff Kirsher /* TxDMA registers */ 31486387e1aSJeff Kirsher u64 txdma_int_status; 31586387e1aSJeff Kirsher u64 txdma_int_mask; 31686387e1aSJeff Kirsher #define TXDMA_PFC_INT s2BIT(0) 31786387e1aSJeff Kirsher #define TXDMA_TDA_INT s2BIT(1) 31886387e1aSJeff Kirsher #define TXDMA_PCC_INT s2BIT(2) 31986387e1aSJeff Kirsher #define TXDMA_TTI_INT s2BIT(3) 32086387e1aSJeff Kirsher #define TXDMA_LSO_INT s2BIT(4) 32186387e1aSJeff Kirsher #define TXDMA_TPA_INT s2BIT(5) 32286387e1aSJeff Kirsher #define TXDMA_SM_INT s2BIT(6) 32386387e1aSJeff Kirsher u64 pfc_err_reg; 32486387e1aSJeff Kirsher #define PFC_ECC_SG_ERR s2BIT(7) 32586387e1aSJeff Kirsher #define PFC_ECC_DB_ERR s2BIT(15) 32686387e1aSJeff Kirsher #define PFC_SM_ERR_ALARM s2BIT(23) 32786387e1aSJeff Kirsher #define PFC_MISC_0_ERR s2BIT(31) 32886387e1aSJeff Kirsher #define PFC_MISC_1_ERR s2BIT(32) 32986387e1aSJeff Kirsher #define PFC_PCIX_ERR s2BIT(39) 33086387e1aSJeff Kirsher u64 pfc_err_mask; 33186387e1aSJeff Kirsher u64 pfc_err_alarm; 33286387e1aSJeff Kirsher 33386387e1aSJeff Kirsher u64 tda_err_reg; 33486387e1aSJeff Kirsher #define TDA_Fn_ECC_SG_ERR vBIT(0xff,0,8) 33586387e1aSJeff Kirsher #define TDA_Fn_ECC_DB_ERR vBIT(0xff,8,8) 33686387e1aSJeff Kirsher #define TDA_SM0_ERR_ALARM s2BIT(22) 33786387e1aSJeff Kirsher #define TDA_SM1_ERR_ALARM s2BIT(23) 33886387e1aSJeff Kirsher #define TDA_PCIX_ERR s2BIT(39) 33986387e1aSJeff Kirsher u64 tda_err_mask; 34086387e1aSJeff Kirsher u64 tda_err_alarm; 34186387e1aSJeff Kirsher 34286387e1aSJeff Kirsher u64 pcc_err_reg; 34386387e1aSJeff Kirsher #define PCC_FB_ECC_SG_ERR vBIT(0xFF,0,8) 34486387e1aSJeff Kirsher #define PCC_TXB_ECC_SG_ERR vBIT(0xFF,8,8) 34586387e1aSJeff Kirsher #define PCC_FB_ECC_DB_ERR vBIT(0xFF,16, 8) 34686387e1aSJeff Kirsher #define PCC_TXB_ECC_DB_ERR vBIT(0xff,24,8) 34786387e1aSJeff Kirsher #define PCC_SM_ERR_ALARM vBIT(0xff,32,8) 34886387e1aSJeff Kirsher #define PCC_WR_ERR_ALARM vBIT(0xff,40,8) 34986387e1aSJeff Kirsher #define PCC_N_SERR vBIT(0xff,48,8) 35086387e1aSJeff Kirsher #define PCC_6_COF_OV_ERR s2BIT(56) 35186387e1aSJeff Kirsher #define PCC_7_COF_OV_ERR s2BIT(57) 35286387e1aSJeff Kirsher #define PCC_6_LSO_OV_ERR s2BIT(58) 35386387e1aSJeff Kirsher #define PCC_7_LSO_OV_ERR s2BIT(59) 35486387e1aSJeff Kirsher #define PCC_ENABLE_FOUR vBIT(0x0F,0,8) 35586387e1aSJeff Kirsher u64 pcc_err_mask; 35686387e1aSJeff Kirsher u64 pcc_err_alarm; 35786387e1aSJeff Kirsher 35886387e1aSJeff Kirsher u64 tti_err_reg; 35986387e1aSJeff Kirsher #define TTI_ECC_SG_ERR s2BIT(7) 36086387e1aSJeff Kirsher #define TTI_ECC_DB_ERR s2BIT(15) 36186387e1aSJeff Kirsher #define TTI_SM_ERR_ALARM s2BIT(23) 36286387e1aSJeff Kirsher u64 tti_err_mask; 36386387e1aSJeff Kirsher u64 tti_err_alarm; 36486387e1aSJeff Kirsher 36586387e1aSJeff Kirsher u64 lso_err_reg; 36686387e1aSJeff Kirsher #define LSO6_SEND_OFLOW s2BIT(12) 36786387e1aSJeff Kirsher #define LSO7_SEND_OFLOW s2BIT(13) 36886387e1aSJeff Kirsher #define LSO6_ABORT s2BIT(14) 36986387e1aSJeff Kirsher #define LSO7_ABORT s2BIT(15) 37086387e1aSJeff Kirsher #define LSO6_SM_ERR_ALARM s2BIT(22) 37186387e1aSJeff Kirsher #define LSO7_SM_ERR_ALARM s2BIT(23) 37286387e1aSJeff Kirsher u64 lso_err_mask; 37386387e1aSJeff Kirsher u64 lso_err_alarm; 37486387e1aSJeff Kirsher 37586387e1aSJeff Kirsher u64 tpa_err_reg; 37686387e1aSJeff Kirsher #define TPA_TX_FRM_DROP s2BIT(7) 37786387e1aSJeff Kirsher #define TPA_SM_ERR_ALARM s2BIT(23) 37886387e1aSJeff Kirsher 37986387e1aSJeff Kirsher u64 tpa_err_mask; 38086387e1aSJeff Kirsher u64 tpa_err_alarm; 38186387e1aSJeff Kirsher 38286387e1aSJeff Kirsher u64 sm_err_reg; 38386387e1aSJeff Kirsher #define SM_SM_ERR_ALARM s2BIT(15) 38486387e1aSJeff Kirsher u64 sm_err_mask; 38586387e1aSJeff Kirsher u64 sm_err_alarm; 38686387e1aSJeff Kirsher 38786387e1aSJeff Kirsher u8 unused8[0x100 - 0xB8]; 38886387e1aSJeff Kirsher 38986387e1aSJeff Kirsher /* TxDMA arbiter */ 39086387e1aSJeff Kirsher u64 tx_dma_wrap_stat; 39186387e1aSJeff Kirsher 39286387e1aSJeff Kirsher /* Tx FIFO controller */ 39386387e1aSJeff Kirsher #define X_MAX_FIFOS 8 39486387e1aSJeff Kirsher #define X_FIFO_MAX_LEN 0x1FFF /*8191 */ 39586387e1aSJeff Kirsher u64 tx_fifo_partition_0; 39686387e1aSJeff Kirsher #define TX_FIFO_PARTITION_EN s2BIT(0) 39786387e1aSJeff Kirsher #define TX_FIFO_PARTITION_0_PRI(val) vBIT(val,5,3) 39886387e1aSJeff Kirsher #define TX_FIFO_PARTITION_0_LEN(val) vBIT(val,19,13) 39986387e1aSJeff Kirsher #define TX_FIFO_PARTITION_1_PRI(val) vBIT(val,37,3) 40086387e1aSJeff Kirsher #define TX_FIFO_PARTITION_1_LEN(val) vBIT(val,51,13 ) 40186387e1aSJeff Kirsher 40286387e1aSJeff Kirsher u64 tx_fifo_partition_1; 40386387e1aSJeff Kirsher #define TX_FIFO_PARTITION_2_PRI(val) vBIT(val,5,3) 40486387e1aSJeff Kirsher #define TX_FIFO_PARTITION_2_LEN(val) vBIT(val,19,13) 40586387e1aSJeff Kirsher #define TX_FIFO_PARTITION_3_PRI(val) vBIT(val,37,3) 40686387e1aSJeff Kirsher #define TX_FIFO_PARTITION_3_LEN(val) vBIT(val,51,13) 40786387e1aSJeff Kirsher 40886387e1aSJeff Kirsher u64 tx_fifo_partition_2; 40986387e1aSJeff Kirsher #define TX_FIFO_PARTITION_4_PRI(val) vBIT(val,5,3) 41086387e1aSJeff Kirsher #define TX_FIFO_PARTITION_4_LEN(val) vBIT(val,19,13) 41186387e1aSJeff Kirsher #define TX_FIFO_PARTITION_5_PRI(val) vBIT(val,37,3) 41286387e1aSJeff Kirsher #define TX_FIFO_PARTITION_5_LEN(val) vBIT(val,51,13) 41386387e1aSJeff Kirsher 41486387e1aSJeff Kirsher u64 tx_fifo_partition_3; 41586387e1aSJeff Kirsher #define TX_FIFO_PARTITION_6_PRI(val) vBIT(val,5,3) 41686387e1aSJeff Kirsher #define TX_FIFO_PARTITION_6_LEN(val) vBIT(val,19,13) 41786387e1aSJeff Kirsher #define TX_FIFO_PARTITION_7_PRI(val) vBIT(val,37,3) 41886387e1aSJeff Kirsher #define TX_FIFO_PARTITION_7_LEN(val) vBIT(val,51,13) 41986387e1aSJeff Kirsher 42086387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_0 0 /* highest */ 42186387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_1 1 42286387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_2 2 42386387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_3 3 42486387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_4 4 42586387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_5 5 42686387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_6 6 42786387e1aSJeff Kirsher #define TX_FIFO_PARTITION_PRI_7 7 /* lowest */ 42886387e1aSJeff Kirsher 42986387e1aSJeff Kirsher u64 tx_w_round_robin_0; 43086387e1aSJeff Kirsher u64 tx_w_round_robin_1; 43186387e1aSJeff Kirsher u64 tx_w_round_robin_2; 43286387e1aSJeff Kirsher u64 tx_w_round_robin_3; 43386387e1aSJeff Kirsher u64 tx_w_round_robin_4; 43486387e1aSJeff Kirsher 43586387e1aSJeff Kirsher u64 tti_command_mem; 43686387e1aSJeff Kirsher #define TTI_CMD_MEM_WE s2BIT(7) 43786387e1aSJeff Kirsher #define TTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) 43886387e1aSJeff Kirsher #define TTI_CMD_MEM_STROBE_BEING_EXECUTED s2BIT(15) 43986387e1aSJeff Kirsher #define TTI_CMD_MEM_OFFSET(n) vBIT(n,26,6) 44086387e1aSJeff Kirsher 44186387e1aSJeff Kirsher u64 tti_data1_mem; 44286387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_TIMER_VAL(n) vBIT(n,6,26) 44386387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_TIMER_AC_CI(n) vBIT(n,38,2) 44486387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_TIMER_AC_EN s2BIT(38) 44586387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_TIMER_CI_EN s2BIT(39) 44686387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_URNG_A(n) vBIT(n,41,7) 44786387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_URNG_B(n) vBIT(n,49,7) 44886387e1aSJeff Kirsher #define TTI_DATA1_MEM_TX_URNG_C(n) vBIT(n,57,7) 44986387e1aSJeff Kirsher 45086387e1aSJeff Kirsher u64 tti_data2_mem; 45186387e1aSJeff Kirsher #define TTI_DATA2_MEM_TX_UFC_A(n) vBIT(n,0,16) 45286387e1aSJeff Kirsher #define TTI_DATA2_MEM_TX_UFC_B(n) vBIT(n,16,16) 45386387e1aSJeff Kirsher #define TTI_DATA2_MEM_TX_UFC_C(n) vBIT(n,32,16) 45486387e1aSJeff Kirsher #define TTI_DATA2_MEM_TX_UFC_D(n) vBIT(n,48,16) 45586387e1aSJeff Kirsher 45686387e1aSJeff Kirsher /* Tx Protocol assist */ 45786387e1aSJeff Kirsher u64 tx_pa_cfg; 45886387e1aSJeff Kirsher #define TX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) 45986387e1aSJeff Kirsher #define TX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) 46086387e1aSJeff Kirsher #define TX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) 46186387e1aSJeff Kirsher #define TX_PA_CFG_IGNORE_L2_ERR s2BIT(6) 46286387e1aSJeff Kirsher #define RX_PA_CFG_STRIP_VLAN_TAG s2BIT(15) 46386387e1aSJeff Kirsher 46486387e1aSJeff Kirsher /* Recent add, used only debug purposes. */ 46586387e1aSJeff Kirsher u64 pcc_enable; 46686387e1aSJeff Kirsher 46786387e1aSJeff Kirsher u8 unused9[0x700 - 0x178]; 46886387e1aSJeff Kirsher 46986387e1aSJeff Kirsher u64 txdma_debug_ctrl; 47086387e1aSJeff Kirsher 47186387e1aSJeff Kirsher u8 unused10[0x1800 - 0x1708]; 47286387e1aSJeff Kirsher 47386387e1aSJeff Kirsher /* RxDMA Registers */ 47486387e1aSJeff Kirsher u64 rxdma_int_status; 47586387e1aSJeff Kirsher u64 rxdma_int_mask; 47686387e1aSJeff Kirsher #define RXDMA_INT_RC_INT_M s2BIT(0) 47786387e1aSJeff Kirsher #define RXDMA_INT_RPA_INT_M s2BIT(1) 47886387e1aSJeff Kirsher #define RXDMA_INT_RDA_INT_M s2BIT(2) 47986387e1aSJeff Kirsher #define RXDMA_INT_RTI_INT_M s2BIT(3) 48086387e1aSJeff Kirsher 48186387e1aSJeff Kirsher u64 rda_err_reg; 48286387e1aSJeff Kirsher #define RDA_RXDn_ECC_SG_ERR vBIT(0xFF,0,8) 48386387e1aSJeff Kirsher #define RDA_RXDn_ECC_DB_ERR vBIT(0xFF,8,8) 48486387e1aSJeff Kirsher #define RDA_FRM_ECC_SG_ERR s2BIT(23) 48586387e1aSJeff Kirsher #define RDA_FRM_ECC_DB_N_AERR s2BIT(31) 48686387e1aSJeff Kirsher #define RDA_SM1_ERR_ALARM s2BIT(38) 48786387e1aSJeff Kirsher #define RDA_SM0_ERR_ALARM s2BIT(39) 48886387e1aSJeff Kirsher #define RDA_MISC_ERR s2BIT(47) 48986387e1aSJeff Kirsher #define RDA_PCIX_ERR s2BIT(55) 49086387e1aSJeff Kirsher #define RDA_RXD_ECC_DB_SERR s2BIT(63) 49186387e1aSJeff Kirsher u64 rda_err_mask; 49286387e1aSJeff Kirsher u64 rda_err_alarm; 49386387e1aSJeff Kirsher 49486387e1aSJeff Kirsher u64 rc_err_reg; 49586387e1aSJeff Kirsher #define RC_PRCn_ECC_SG_ERR vBIT(0xFF,0,8) 49686387e1aSJeff Kirsher #define RC_PRCn_ECC_DB_ERR vBIT(0xFF,8,8) 49786387e1aSJeff Kirsher #define RC_FTC_ECC_SG_ERR s2BIT(23) 49886387e1aSJeff Kirsher #define RC_FTC_ECC_DB_ERR s2BIT(31) 49986387e1aSJeff Kirsher #define RC_PRCn_SM_ERR_ALARM vBIT(0xFF,32,8) 50086387e1aSJeff Kirsher #define RC_FTC_SM_ERR_ALARM s2BIT(47) 50186387e1aSJeff Kirsher #define RC_RDA_FAIL_WR_Rn vBIT(0xFF,48,8) 50286387e1aSJeff Kirsher u64 rc_err_mask; 50386387e1aSJeff Kirsher u64 rc_err_alarm; 50486387e1aSJeff Kirsher 50586387e1aSJeff Kirsher u64 prc_pcix_err_reg; 50686387e1aSJeff Kirsher #define PRC_PCI_AB_RD_Rn vBIT(0xFF,0,8) 50786387e1aSJeff Kirsher #define PRC_PCI_DP_RD_Rn vBIT(0xFF,8,8) 50886387e1aSJeff Kirsher #define PRC_PCI_AB_WR_Rn vBIT(0xFF,16,8) 50986387e1aSJeff Kirsher #define PRC_PCI_DP_WR_Rn vBIT(0xFF,24,8) 51086387e1aSJeff Kirsher #define PRC_PCI_AB_F_WR_Rn vBIT(0xFF,32,8) 51186387e1aSJeff Kirsher #define PRC_PCI_DP_F_WR_Rn vBIT(0xFF,40,8) 51286387e1aSJeff Kirsher u64 prc_pcix_err_mask; 51386387e1aSJeff Kirsher u64 prc_pcix_err_alarm; 51486387e1aSJeff Kirsher 51586387e1aSJeff Kirsher u64 rpa_err_reg; 51686387e1aSJeff Kirsher #define RPA_ECC_SG_ERR s2BIT(7) 51786387e1aSJeff Kirsher #define RPA_ECC_DB_ERR s2BIT(15) 51886387e1aSJeff Kirsher #define RPA_FLUSH_REQUEST s2BIT(22) 51986387e1aSJeff Kirsher #define RPA_SM_ERR_ALARM s2BIT(23) 52086387e1aSJeff Kirsher #define RPA_CREDIT_ERR s2BIT(31) 52186387e1aSJeff Kirsher u64 rpa_err_mask; 52286387e1aSJeff Kirsher u64 rpa_err_alarm; 52386387e1aSJeff Kirsher 52486387e1aSJeff Kirsher u64 rti_err_reg; 52586387e1aSJeff Kirsher #define RTI_ECC_SG_ERR s2BIT(7) 52686387e1aSJeff Kirsher #define RTI_ECC_DB_ERR s2BIT(15) 52786387e1aSJeff Kirsher #define RTI_SM_ERR_ALARM s2BIT(23) 52886387e1aSJeff Kirsher u64 rti_err_mask; 52986387e1aSJeff Kirsher u64 rti_err_alarm; 53086387e1aSJeff Kirsher 53186387e1aSJeff Kirsher u8 unused11[0x100 - 0x88]; 53286387e1aSJeff Kirsher 53386387e1aSJeff Kirsher /* DMA arbiter */ 53486387e1aSJeff Kirsher u64 rx_queue_priority; 53586387e1aSJeff Kirsher #define RX_QUEUE_0_PRIORITY(val) vBIT(val,5,3) 53686387e1aSJeff Kirsher #define RX_QUEUE_1_PRIORITY(val) vBIT(val,13,3) 53786387e1aSJeff Kirsher #define RX_QUEUE_2_PRIORITY(val) vBIT(val,21,3) 53886387e1aSJeff Kirsher #define RX_QUEUE_3_PRIORITY(val) vBIT(val,29,3) 53986387e1aSJeff Kirsher #define RX_QUEUE_4_PRIORITY(val) vBIT(val,37,3) 54086387e1aSJeff Kirsher #define RX_QUEUE_5_PRIORITY(val) vBIT(val,45,3) 54186387e1aSJeff Kirsher #define RX_QUEUE_6_PRIORITY(val) vBIT(val,53,3) 54286387e1aSJeff Kirsher #define RX_QUEUE_7_PRIORITY(val) vBIT(val,61,3) 54386387e1aSJeff Kirsher 54486387e1aSJeff Kirsher #define RX_QUEUE_PRI_0 0 /* highest */ 54586387e1aSJeff Kirsher #define RX_QUEUE_PRI_1 1 54686387e1aSJeff Kirsher #define RX_QUEUE_PRI_2 2 54786387e1aSJeff Kirsher #define RX_QUEUE_PRI_3 3 54886387e1aSJeff Kirsher #define RX_QUEUE_PRI_4 4 54986387e1aSJeff Kirsher #define RX_QUEUE_PRI_5 5 55086387e1aSJeff Kirsher #define RX_QUEUE_PRI_6 6 55186387e1aSJeff Kirsher #define RX_QUEUE_PRI_7 7 /* lowest */ 55286387e1aSJeff Kirsher 55386387e1aSJeff Kirsher u64 rx_w_round_robin_0; 55486387e1aSJeff Kirsher u64 rx_w_round_robin_1; 55586387e1aSJeff Kirsher u64 rx_w_round_robin_2; 55686387e1aSJeff Kirsher u64 rx_w_round_robin_3; 55786387e1aSJeff Kirsher u64 rx_w_round_robin_4; 55886387e1aSJeff Kirsher 55986387e1aSJeff Kirsher /* Per-ring controller regs */ 56086387e1aSJeff Kirsher #define RX_MAX_RINGS 8 56186387e1aSJeff Kirsher #if 0 56286387e1aSJeff Kirsher #define RX_MAX_RINGS_SZ 0xFFFF /* 65536 */ 56386387e1aSJeff Kirsher #define RX_MIN_RINGS_SZ 0x3F /* 63 */ 56486387e1aSJeff Kirsher #endif 56586387e1aSJeff Kirsher u64 prc_rxd0_n[RX_MAX_RINGS]; 56686387e1aSJeff Kirsher u64 prc_ctrl_n[RX_MAX_RINGS]; 56786387e1aSJeff Kirsher #define PRC_CTRL_RC_ENABLED s2BIT(7) 56886387e1aSJeff Kirsher #define PRC_CTRL_RING_MODE (s2BIT(14)|s2BIT(15)) 56986387e1aSJeff Kirsher #define PRC_CTRL_RING_MODE_1 vBIT(0,14,2) 57086387e1aSJeff Kirsher #define PRC_CTRL_RING_MODE_3 vBIT(1,14,2) 57186387e1aSJeff Kirsher #define PRC_CTRL_RING_MODE_5 vBIT(2,14,2) 57286387e1aSJeff Kirsher #define PRC_CTRL_RING_MODE_x vBIT(3,14,2) 57386387e1aSJeff Kirsher #define PRC_CTRL_NO_SNOOP (s2BIT(22)|s2BIT(23)) 57486387e1aSJeff Kirsher #define PRC_CTRL_NO_SNOOP_DESC s2BIT(22) 57586387e1aSJeff Kirsher #define PRC_CTRL_NO_SNOOP_BUFF s2BIT(23) 57686387e1aSJeff Kirsher #define PRC_CTRL_BIMODAL_INTERRUPT s2BIT(37) 57786387e1aSJeff Kirsher #define PRC_CTRL_GROUP_READS s2BIT(38) 57886387e1aSJeff Kirsher #define PRC_CTRL_RXD_BACKOFF_INTERVAL(val) vBIT(val,40,24) 57986387e1aSJeff Kirsher 58086387e1aSJeff Kirsher u64 prc_alarm_action; 58186387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R0_STOP s2BIT(3) 58286387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R0_STOP s2BIT(7) 58386387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R1_STOP s2BIT(11) 58486387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R1_STOP s2BIT(15) 58586387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R2_STOP s2BIT(19) 58686387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R2_STOP s2BIT(23) 58786387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R3_STOP s2BIT(27) 58886387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R3_STOP s2BIT(31) 58986387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R4_STOP s2BIT(35) 59086387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R4_STOP s2BIT(39) 59186387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R5_STOP s2BIT(43) 59286387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R5_STOP s2BIT(47) 59386387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R6_STOP s2BIT(51) 59486387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R6_STOP s2BIT(55) 59586387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RR_R7_STOP s2BIT(59) 59686387e1aSJeff Kirsher #define PRC_ALARM_ACTION_RW_R7_STOP s2BIT(63) 59786387e1aSJeff Kirsher 59886387e1aSJeff Kirsher /* Receive traffic interrupts */ 59986387e1aSJeff Kirsher u64 rti_command_mem; 60086387e1aSJeff Kirsher #define RTI_CMD_MEM_WE s2BIT(7) 60186387e1aSJeff Kirsher #define RTI_CMD_MEM_STROBE s2BIT(15) 60286387e1aSJeff Kirsher #define RTI_CMD_MEM_STROBE_NEW_CMD s2BIT(15) 60386387e1aSJeff Kirsher #define RTI_CMD_MEM_STROBE_CMD_BEING_EXECUTED s2BIT(15) 60486387e1aSJeff Kirsher #define RTI_CMD_MEM_OFFSET(n) vBIT(n,29,3) 60586387e1aSJeff Kirsher 60686387e1aSJeff Kirsher u64 rti_data1_mem; 60786387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_TIMER_VAL(n) vBIT(n,3,29) 60886387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_TIMER_AC_EN s2BIT(38) 60986387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_TIMER_CI_EN s2BIT(39) 61086387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_URNG_A(n) vBIT(n,41,7) 61186387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_URNG_B(n) vBIT(n,49,7) 61286387e1aSJeff Kirsher #define RTI_DATA1_MEM_RX_URNG_C(n) vBIT(n,57,7) 61386387e1aSJeff Kirsher 61486387e1aSJeff Kirsher u64 rti_data2_mem; 61586387e1aSJeff Kirsher #define RTI_DATA2_MEM_RX_UFC_A(n) vBIT(n,0,16) 61686387e1aSJeff Kirsher #define RTI_DATA2_MEM_RX_UFC_B(n) vBIT(n,16,16) 61786387e1aSJeff Kirsher #define RTI_DATA2_MEM_RX_UFC_C(n) vBIT(n,32,16) 61886387e1aSJeff Kirsher #define RTI_DATA2_MEM_RX_UFC_D(n) vBIT(n,48,16) 61986387e1aSJeff Kirsher 62086387e1aSJeff Kirsher u64 rx_pa_cfg; 62186387e1aSJeff Kirsher #define RX_PA_CFG_IGNORE_FRM_ERR s2BIT(1) 62286387e1aSJeff Kirsher #define RX_PA_CFG_IGNORE_SNAP_OUI s2BIT(2) 62386387e1aSJeff Kirsher #define RX_PA_CFG_IGNORE_LLC_CTRL s2BIT(3) 62486387e1aSJeff Kirsher #define RX_PA_CFG_IGNORE_L2_ERR s2BIT(6) 62586387e1aSJeff Kirsher 62686387e1aSJeff Kirsher u64 unused_11_1; 62786387e1aSJeff Kirsher 62886387e1aSJeff Kirsher u64 ring_bump_counter1; 62986387e1aSJeff Kirsher u64 ring_bump_counter2; 63086387e1aSJeff Kirsher 63186387e1aSJeff Kirsher u8 unused12[0x700 - 0x1F0]; 63286387e1aSJeff Kirsher 63386387e1aSJeff Kirsher u64 rxdma_debug_ctrl; 63486387e1aSJeff Kirsher 63586387e1aSJeff Kirsher u8 unused13[0x2000 - 0x1f08]; 63686387e1aSJeff Kirsher 63786387e1aSJeff Kirsher /* Media Access Controller Register */ 63886387e1aSJeff Kirsher u64 mac_int_status; 63986387e1aSJeff Kirsher u64 mac_int_mask; 64086387e1aSJeff Kirsher #define MAC_INT_STATUS_TMAC_INT s2BIT(0) 64186387e1aSJeff Kirsher #define MAC_INT_STATUS_RMAC_INT s2BIT(1) 64286387e1aSJeff Kirsher 64386387e1aSJeff Kirsher u64 mac_tmac_err_reg; 64486387e1aSJeff Kirsher #define TMAC_ECC_SG_ERR s2BIT(7) 64586387e1aSJeff Kirsher #define TMAC_ECC_DB_ERR s2BIT(15) 64686387e1aSJeff Kirsher #define TMAC_TX_BUF_OVRN s2BIT(23) 64786387e1aSJeff Kirsher #define TMAC_TX_CRI_ERR s2BIT(31) 64886387e1aSJeff Kirsher #define TMAC_TX_SM_ERR s2BIT(39) 64986387e1aSJeff Kirsher #define TMAC_DESC_ECC_SG_ERR s2BIT(47) 65086387e1aSJeff Kirsher #define TMAC_DESC_ECC_DB_ERR s2BIT(55) 65186387e1aSJeff Kirsher 65286387e1aSJeff Kirsher u64 mac_tmac_err_mask; 65386387e1aSJeff Kirsher u64 mac_tmac_err_alarm; 65486387e1aSJeff Kirsher 65586387e1aSJeff Kirsher u64 mac_rmac_err_reg; 65686387e1aSJeff Kirsher #define RMAC_RX_BUFF_OVRN s2BIT(0) 65786387e1aSJeff Kirsher #define RMAC_FRM_RCVD_INT s2BIT(1) 65886387e1aSJeff Kirsher #define RMAC_UNUSED_INT s2BIT(2) 65986387e1aSJeff Kirsher #define RMAC_RTS_PNUM_ECC_SG_ERR s2BIT(5) 66086387e1aSJeff Kirsher #define RMAC_RTS_DS_ECC_SG_ERR s2BIT(6) 66186387e1aSJeff Kirsher #define RMAC_RD_BUF_ECC_SG_ERR s2BIT(7) 66286387e1aSJeff Kirsher #define RMAC_RTH_MAP_ECC_SG_ERR s2BIT(8) 66386387e1aSJeff Kirsher #define RMAC_RTH_SPDM_ECC_SG_ERR s2BIT(9) 66486387e1aSJeff Kirsher #define RMAC_RTS_VID_ECC_SG_ERR s2BIT(10) 66586387e1aSJeff Kirsher #define RMAC_DA_SHADOW_ECC_SG_ERR s2BIT(11) 66686387e1aSJeff Kirsher #define RMAC_RTS_PNUM_ECC_DB_ERR s2BIT(13) 66786387e1aSJeff Kirsher #define RMAC_RTS_DS_ECC_DB_ERR s2BIT(14) 66886387e1aSJeff Kirsher #define RMAC_RD_BUF_ECC_DB_ERR s2BIT(15) 66986387e1aSJeff Kirsher #define RMAC_RTH_MAP_ECC_DB_ERR s2BIT(16) 67086387e1aSJeff Kirsher #define RMAC_RTH_SPDM_ECC_DB_ERR s2BIT(17) 67186387e1aSJeff Kirsher #define RMAC_RTS_VID_ECC_DB_ERR s2BIT(18) 67286387e1aSJeff Kirsher #define RMAC_DA_SHADOW_ECC_DB_ERR s2BIT(19) 67386387e1aSJeff Kirsher #define RMAC_LINK_STATE_CHANGE_INT s2BIT(31) 67486387e1aSJeff Kirsher #define RMAC_RX_SM_ERR s2BIT(39) 67586387e1aSJeff Kirsher #define RMAC_SINGLE_ECC_ERR (s2BIT(5) | s2BIT(6) | s2BIT(7) |\ 67686387e1aSJeff Kirsher s2BIT(8) | s2BIT(9) | s2BIT(10)|\ 67786387e1aSJeff Kirsher s2BIT(11)) 67886387e1aSJeff Kirsher #define RMAC_DOUBLE_ECC_ERR (s2BIT(13) | s2BIT(14) | s2BIT(15) |\ 67986387e1aSJeff Kirsher s2BIT(16) | s2BIT(17) | s2BIT(18)|\ 68086387e1aSJeff Kirsher s2BIT(19)) 68186387e1aSJeff Kirsher u64 mac_rmac_err_mask; 68286387e1aSJeff Kirsher u64 mac_rmac_err_alarm; 68386387e1aSJeff Kirsher 68486387e1aSJeff Kirsher u8 unused14[0x100 - 0x40]; 68586387e1aSJeff Kirsher 68686387e1aSJeff Kirsher u64 mac_cfg; 68786387e1aSJeff Kirsher #define MAC_CFG_TMAC_ENABLE s2BIT(0) 68886387e1aSJeff Kirsher #define MAC_CFG_RMAC_ENABLE s2BIT(1) 68986387e1aSJeff Kirsher #define MAC_CFG_LAN_NOT_WAN s2BIT(2) 69086387e1aSJeff Kirsher #define MAC_CFG_TMAC_LOOPBACK s2BIT(3) 69186387e1aSJeff Kirsher #define MAC_CFG_TMAC_APPEND_PAD s2BIT(4) 69286387e1aSJeff Kirsher #define MAC_CFG_RMAC_STRIP_FCS s2BIT(5) 69386387e1aSJeff Kirsher #define MAC_CFG_RMAC_STRIP_PAD s2BIT(6) 69486387e1aSJeff Kirsher #define MAC_CFG_RMAC_PROM_ENABLE s2BIT(7) 69586387e1aSJeff Kirsher #define MAC_RMAC_DISCARD_PFRM s2BIT(8) 69686387e1aSJeff Kirsher #define MAC_RMAC_BCAST_ENABLE s2BIT(9) 69786387e1aSJeff Kirsher #define MAC_RMAC_ALL_ADDR_ENABLE s2BIT(10) 69886387e1aSJeff Kirsher #define MAC_RMAC_INVLD_IPG_THR(val) vBIT(val,16,8) 69986387e1aSJeff Kirsher 70086387e1aSJeff Kirsher u64 tmac_avg_ipg; 70186387e1aSJeff Kirsher #define TMAC_AVG_IPG(val) vBIT(val,0,8) 70286387e1aSJeff Kirsher 70386387e1aSJeff Kirsher u64 rmac_max_pyld_len; 70486387e1aSJeff Kirsher #define RMAC_MAX_PYLD_LEN(val) vBIT(val,2,14) 70586387e1aSJeff Kirsher #define RMAC_MAX_PYLD_LEN_DEF vBIT(1500,2,14) 70686387e1aSJeff Kirsher #define RMAC_MAX_PYLD_LEN_JUMBO_DEF vBIT(9600,2,14) 70786387e1aSJeff Kirsher 70886387e1aSJeff Kirsher u64 rmac_err_cfg; 70986387e1aSJeff Kirsher #define RMAC_ERR_FCS s2BIT(0) 71086387e1aSJeff Kirsher #define RMAC_ERR_FCS_ACCEPT s2BIT(1) 71186387e1aSJeff Kirsher #define RMAC_ERR_TOO_LONG s2BIT(1) 71286387e1aSJeff Kirsher #define RMAC_ERR_TOO_LONG_ACCEPT s2BIT(1) 71386387e1aSJeff Kirsher #define RMAC_ERR_RUNT s2BIT(2) 71486387e1aSJeff Kirsher #define RMAC_ERR_RUNT_ACCEPT s2BIT(2) 71586387e1aSJeff Kirsher #define RMAC_ERR_LEN_MISMATCH s2BIT(3) 71686387e1aSJeff Kirsher #define RMAC_ERR_LEN_MISMATCH_ACCEPT s2BIT(3) 71786387e1aSJeff Kirsher 71886387e1aSJeff Kirsher u64 rmac_cfg_key; 71986387e1aSJeff Kirsher #define RMAC_CFG_KEY(val) vBIT(val,0,16) 72086387e1aSJeff Kirsher 72186387e1aSJeff Kirsher #define S2IO_MAC_ADDR_START_OFFSET 0 72286387e1aSJeff Kirsher 72386387e1aSJeff Kirsher #define S2IO_XENA_MAX_MC_ADDRESSES 64 /* multicast addresses */ 72486387e1aSJeff Kirsher #define S2IO_HERC_MAX_MC_ADDRESSES 256 72586387e1aSJeff Kirsher 72686387e1aSJeff Kirsher #define S2IO_XENA_MAX_MAC_ADDRESSES 16 72786387e1aSJeff Kirsher #define S2IO_HERC_MAX_MAC_ADDRESSES 64 72886387e1aSJeff Kirsher 72986387e1aSJeff Kirsher #define S2IO_XENA_MC_ADDR_START_OFFSET 16 73086387e1aSJeff Kirsher #define S2IO_HERC_MC_ADDR_START_OFFSET 64 73186387e1aSJeff Kirsher 73286387e1aSJeff Kirsher u64 rmac_addr_cmd_mem; 73386387e1aSJeff Kirsher #define RMAC_ADDR_CMD_MEM_WE s2BIT(7) 73486387e1aSJeff Kirsher #define RMAC_ADDR_CMD_MEM_RD 0 73586387e1aSJeff Kirsher #define RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD s2BIT(15) 73686387e1aSJeff Kirsher #define RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING s2BIT(15) 73786387e1aSJeff Kirsher #define RMAC_ADDR_CMD_MEM_OFFSET(n) vBIT(n,26,6) 73886387e1aSJeff Kirsher 73986387e1aSJeff Kirsher u64 rmac_addr_data0_mem; 74086387e1aSJeff Kirsher #define RMAC_ADDR_DATA0_MEM_ADDR(n) vBIT(n,0,48) 74186387e1aSJeff Kirsher #define RMAC_ADDR_DATA0_MEM_USER s2BIT(48) 74286387e1aSJeff Kirsher 74386387e1aSJeff Kirsher u64 rmac_addr_data1_mem; 74486387e1aSJeff Kirsher #define RMAC_ADDR_DATA1_MEM_MASK(n) vBIT(n,0,48) 74586387e1aSJeff Kirsher 74686387e1aSJeff Kirsher u8 unused15[0x8]; 74786387e1aSJeff Kirsher 74886387e1aSJeff Kirsher /* 74986387e1aSJeff Kirsher u64 rmac_addr_cfg; 75086387e1aSJeff Kirsher #define RMAC_ADDR_UCASTn_EN(n) mBIT(0)_n(n) 75186387e1aSJeff Kirsher #define RMAC_ADDR_MCASTn_EN(n) mBIT(0)_n(n) 75286387e1aSJeff Kirsher #define RMAC_ADDR_BCAST_EN vBIT(0)_48 75386387e1aSJeff Kirsher #define RMAC_ADDR_ALL_ADDR_EN vBIT(0)_49 75486387e1aSJeff Kirsher */ 75586387e1aSJeff Kirsher u64 tmac_ipg_cfg; 75686387e1aSJeff Kirsher 75786387e1aSJeff Kirsher u64 rmac_pause_cfg; 75886387e1aSJeff Kirsher #define RMAC_PAUSE_GEN s2BIT(0) 75986387e1aSJeff Kirsher #define RMAC_PAUSE_GEN_ENABLE s2BIT(0) 76086387e1aSJeff Kirsher #define RMAC_PAUSE_RX s2BIT(1) 76186387e1aSJeff Kirsher #define RMAC_PAUSE_RX_ENABLE s2BIT(1) 76286387e1aSJeff Kirsher #define RMAC_PAUSE_HG_PTIME_DEF vBIT(0xFFFF,16,16) 76386387e1aSJeff Kirsher #define RMAC_PAUSE_HG_PTIME(val) vBIT(val,16,16) 76486387e1aSJeff Kirsher 76586387e1aSJeff Kirsher u64 rmac_red_cfg; 76686387e1aSJeff Kirsher 76786387e1aSJeff Kirsher u64 rmac_red_rate_q0q3; 76886387e1aSJeff Kirsher u64 rmac_red_rate_q4q7; 76986387e1aSJeff Kirsher 77086387e1aSJeff Kirsher u64 mac_link_util; 77186387e1aSJeff Kirsher #define MAC_TX_LINK_UTIL vBIT(0xFE,1,7) 77286387e1aSJeff Kirsher #define MAC_TX_LINK_UTIL_DISABLE vBIT(0xF, 8,4) 77386387e1aSJeff Kirsher #define MAC_TX_LINK_UTIL_VAL( n ) vBIT(n,8,4) 77486387e1aSJeff Kirsher #define MAC_RX_LINK_UTIL vBIT(0xFE,33,7) 77586387e1aSJeff Kirsher #define MAC_RX_LINK_UTIL_DISABLE vBIT(0xF,40,4) 77686387e1aSJeff Kirsher #define MAC_RX_LINK_UTIL_VAL( n ) vBIT(n,40,4) 77786387e1aSJeff Kirsher 77886387e1aSJeff Kirsher #define MAC_LINK_UTIL_DISABLE MAC_TX_LINK_UTIL_DISABLE | \ 77986387e1aSJeff Kirsher MAC_RX_LINK_UTIL_DISABLE 78086387e1aSJeff Kirsher 78186387e1aSJeff Kirsher u64 rmac_invalid_ipg; 78286387e1aSJeff Kirsher 78386387e1aSJeff Kirsher /* rx traffic steering */ 78486387e1aSJeff Kirsher #define MAC_RTS_FRM_LEN_SET(len) vBIT(len,2,14) 78586387e1aSJeff Kirsher u64 rts_frm_len_n[8]; 78686387e1aSJeff Kirsher 78786387e1aSJeff Kirsher u64 rts_qos_steering; 78886387e1aSJeff Kirsher 78986387e1aSJeff Kirsher #define MAX_DIX_MAP 4 79086387e1aSJeff Kirsher u64 rts_dix_map_n[MAX_DIX_MAP]; 79186387e1aSJeff Kirsher #define RTS_DIX_MAP_ETYPE(val) vBIT(val,0,16) 79286387e1aSJeff Kirsher #define RTS_DIX_MAP_SCW(val) s2BIT(val,21) 79386387e1aSJeff Kirsher 79486387e1aSJeff Kirsher u64 rts_q_alternates; 79586387e1aSJeff Kirsher u64 rts_default_q; 79686387e1aSJeff Kirsher 79786387e1aSJeff Kirsher u64 rts_ctrl; 79886387e1aSJeff Kirsher #define RTS_CTRL_IGNORE_SNAP_OUI s2BIT(2) 79986387e1aSJeff Kirsher #define RTS_CTRL_IGNORE_LLC_CTRL s2BIT(3) 80086387e1aSJeff Kirsher 80186387e1aSJeff Kirsher u64 rts_pn_cam_ctrl; 80286387e1aSJeff Kirsher #define RTS_PN_CAM_CTRL_WE s2BIT(7) 80386387e1aSJeff Kirsher #define RTS_PN_CAM_CTRL_STROBE_NEW_CMD s2BIT(15) 80486387e1aSJeff Kirsher #define RTS_PN_CAM_CTRL_STROBE_BEING_EXECUTED s2BIT(15) 80586387e1aSJeff Kirsher #define RTS_PN_CAM_CTRL_OFFSET(n) vBIT(n,24,8) 80686387e1aSJeff Kirsher u64 rts_pn_cam_data; 80786387e1aSJeff Kirsher #define RTS_PN_CAM_DATA_TCP_SELECT s2BIT(7) 80886387e1aSJeff Kirsher #define RTS_PN_CAM_DATA_PORT(val) vBIT(val,8,16) 80986387e1aSJeff Kirsher #define RTS_PN_CAM_DATA_SCW(val) vBIT(val,24,8) 81086387e1aSJeff Kirsher 81186387e1aSJeff Kirsher u64 rts_ds_mem_ctrl; 81286387e1aSJeff Kirsher #define RTS_DS_MEM_CTRL_WE s2BIT(7) 81386387e1aSJeff Kirsher #define RTS_DS_MEM_CTRL_STROBE_NEW_CMD s2BIT(15) 81486387e1aSJeff Kirsher #define RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED s2BIT(15) 81586387e1aSJeff Kirsher #define RTS_DS_MEM_CTRL_OFFSET(n) vBIT(n,26,6) 81686387e1aSJeff Kirsher u64 rts_ds_mem_data; 81786387e1aSJeff Kirsher #define RTS_DS_MEM_DATA(n) vBIT(n,0,8) 81886387e1aSJeff Kirsher 81986387e1aSJeff Kirsher u8 unused16[0x700 - 0x220]; 82086387e1aSJeff Kirsher 82186387e1aSJeff Kirsher u64 mac_debug_ctrl; 82286387e1aSJeff Kirsher #define MAC_DBG_ACTIVITY_VALUE 0x411040400000000ULL 82386387e1aSJeff Kirsher 82486387e1aSJeff Kirsher u8 unused17[0x2800 - 0x2708]; 82586387e1aSJeff Kirsher 82686387e1aSJeff Kirsher /* memory controller registers */ 82786387e1aSJeff Kirsher u64 mc_int_status; 82886387e1aSJeff Kirsher #define MC_INT_STATUS_MC_INT s2BIT(0) 82986387e1aSJeff Kirsher u64 mc_int_mask; 83086387e1aSJeff Kirsher #define MC_INT_MASK_MC_INT s2BIT(0) 83186387e1aSJeff Kirsher 83286387e1aSJeff Kirsher u64 mc_err_reg; 83386387e1aSJeff Kirsher #define MC_ERR_REG_ECC_DB_ERR_L s2BIT(14) 83486387e1aSJeff Kirsher #define MC_ERR_REG_ECC_DB_ERR_U s2BIT(15) 83586387e1aSJeff Kirsher #define MC_ERR_REG_MIRI_ECC_DB_ERR_0 s2BIT(18) 83686387e1aSJeff Kirsher #define MC_ERR_REG_MIRI_ECC_DB_ERR_1 s2BIT(20) 83786387e1aSJeff Kirsher #define MC_ERR_REG_MIRI_CRI_ERR_0 s2BIT(22) 83886387e1aSJeff Kirsher #define MC_ERR_REG_MIRI_CRI_ERR_1 s2BIT(23) 83986387e1aSJeff Kirsher #define MC_ERR_REG_SM_ERR s2BIT(31) 84086387e1aSJeff Kirsher #define MC_ERR_REG_ECC_ALL_SNG (s2BIT(2) | s2BIT(3) | s2BIT(4) | s2BIT(5) |\ 84186387e1aSJeff Kirsher s2BIT(17) | s2BIT(19)) 84286387e1aSJeff Kirsher #define MC_ERR_REG_ECC_ALL_DBL (s2BIT(10) | s2BIT(11) | s2BIT(12) |\ 84386387e1aSJeff Kirsher s2BIT(13) | s2BIT(18) | s2BIT(20)) 84486387e1aSJeff Kirsher #define PLL_LOCK_N s2BIT(39) 84586387e1aSJeff Kirsher u64 mc_err_mask; 84686387e1aSJeff Kirsher u64 mc_err_alarm; 84786387e1aSJeff Kirsher 84886387e1aSJeff Kirsher u8 unused18[0x100 - 0x28]; 84986387e1aSJeff Kirsher 85086387e1aSJeff Kirsher /* MC configuration */ 85186387e1aSJeff Kirsher u64 rx_queue_cfg; 85286387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q0_SZ(n) vBIT(n,0,8) 85386387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q1_SZ(n) vBIT(n,8,8) 85486387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q2_SZ(n) vBIT(n,16,8) 85586387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q3_SZ(n) vBIT(n,24,8) 85686387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q4_SZ(n) vBIT(n,32,8) 85786387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q5_SZ(n) vBIT(n,40,8) 85886387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q6_SZ(n) vBIT(n,48,8) 85986387e1aSJeff Kirsher #define RX_QUEUE_CFG_Q7_SZ(n) vBIT(n,56,8) 86086387e1aSJeff Kirsher 86186387e1aSJeff Kirsher u64 mc_rldram_mrs; 86286387e1aSJeff Kirsher #define MC_RLDRAM_QUEUE_SIZE_ENABLE s2BIT(39) 86386387e1aSJeff Kirsher #define MC_RLDRAM_MRS_ENABLE s2BIT(47) 86486387e1aSJeff Kirsher 86586387e1aSJeff Kirsher u64 mc_rldram_interleave; 86686387e1aSJeff Kirsher 86786387e1aSJeff Kirsher u64 mc_pause_thresh_q0q3; 86886387e1aSJeff Kirsher u64 mc_pause_thresh_q4q7; 86986387e1aSJeff Kirsher 87086387e1aSJeff Kirsher u64 mc_red_thresh_q[8]; 87186387e1aSJeff Kirsher 87286387e1aSJeff Kirsher u8 unused19[0x200 - 0x168]; 87386387e1aSJeff Kirsher u64 mc_rldram_ref_per; 87486387e1aSJeff Kirsher u8 unused20[0x220 - 0x208]; 87586387e1aSJeff Kirsher u64 mc_rldram_test_ctrl; 87686387e1aSJeff Kirsher #define MC_RLDRAM_TEST_MODE s2BIT(47) 87786387e1aSJeff Kirsher #define MC_RLDRAM_TEST_WRITE s2BIT(7) 87886387e1aSJeff Kirsher #define MC_RLDRAM_TEST_GO s2BIT(15) 87986387e1aSJeff Kirsher #define MC_RLDRAM_TEST_DONE s2BIT(23) 88086387e1aSJeff Kirsher #define MC_RLDRAM_TEST_PASS s2BIT(31) 88186387e1aSJeff Kirsher 88286387e1aSJeff Kirsher u8 unused21[0x240 - 0x228]; 88386387e1aSJeff Kirsher u64 mc_rldram_test_add; 88486387e1aSJeff Kirsher u8 unused22[0x260 - 0x248]; 88586387e1aSJeff Kirsher u64 mc_rldram_test_d0; 88686387e1aSJeff Kirsher u8 unused23[0x280 - 0x268]; 88786387e1aSJeff Kirsher u64 mc_rldram_test_d1; 88886387e1aSJeff Kirsher u8 unused24[0x300 - 0x288]; 88986387e1aSJeff Kirsher u64 mc_rldram_test_d2; 89086387e1aSJeff Kirsher 89186387e1aSJeff Kirsher u8 unused24_1[0x360 - 0x308]; 89286387e1aSJeff Kirsher u64 mc_rldram_ctrl; 89386387e1aSJeff Kirsher #define MC_RLDRAM_ENABLE_ODT s2BIT(7) 89486387e1aSJeff Kirsher 89586387e1aSJeff Kirsher u8 unused24_2[0x640 - 0x368]; 89686387e1aSJeff Kirsher u64 mc_rldram_ref_per_herc; 89786387e1aSJeff Kirsher #define MC_RLDRAM_SET_REF_PERIOD(val) vBIT(val, 0, 16) 89886387e1aSJeff Kirsher 89986387e1aSJeff Kirsher u8 unused24_3[0x660 - 0x648]; 90086387e1aSJeff Kirsher u64 mc_rldram_mrs_herc; 90186387e1aSJeff Kirsher 90286387e1aSJeff Kirsher u8 unused25[0x700 - 0x668]; 90386387e1aSJeff Kirsher u64 mc_debug_ctrl; 90486387e1aSJeff Kirsher 90586387e1aSJeff Kirsher u8 unused26[0x3000 - 0x2f08]; 90686387e1aSJeff Kirsher 90786387e1aSJeff Kirsher /* XGXG */ 90886387e1aSJeff Kirsher /* XGXS control registers */ 90986387e1aSJeff Kirsher 91086387e1aSJeff Kirsher u64 xgxs_int_status; 91186387e1aSJeff Kirsher #define XGXS_INT_STATUS_TXGXS s2BIT(0) 91286387e1aSJeff Kirsher #define XGXS_INT_STATUS_RXGXS s2BIT(1) 91386387e1aSJeff Kirsher u64 xgxs_int_mask; 91486387e1aSJeff Kirsher #define XGXS_INT_MASK_TXGXS s2BIT(0) 91586387e1aSJeff Kirsher #define XGXS_INT_MASK_RXGXS s2BIT(1) 91686387e1aSJeff Kirsher 91786387e1aSJeff Kirsher u64 xgxs_txgxs_err_reg; 91886387e1aSJeff Kirsher #define TXGXS_ECC_SG_ERR s2BIT(7) 91986387e1aSJeff Kirsher #define TXGXS_ECC_DB_ERR s2BIT(15) 92086387e1aSJeff Kirsher #define TXGXS_ESTORE_UFLOW s2BIT(31) 92186387e1aSJeff Kirsher #define TXGXS_TX_SM_ERR s2BIT(39) 92286387e1aSJeff Kirsher 92386387e1aSJeff Kirsher u64 xgxs_txgxs_err_mask; 92486387e1aSJeff Kirsher u64 xgxs_txgxs_err_alarm; 92586387e1aSJeff Kirsher 92686387e1aSJeff Kirsher u64 xgxs_rxgxs_err_reg; 92786387e1aSJeff Kirsher #define RXGXS_ESTORE_OFLOW s2BIT(7) 92886387e1aSJeff Kirsher #define RXGXS_RX_SM_ERR s2BIT(39) 92986387e1aSJeff Kirsher u64 xgxs_rxgxs_err_mask; 93086387e1aSJeff Kirsher u64 xgxs_rxgxs_err_alarm; 93186387e1aSJeff Kirsher 93286387e1aSJeff Kirsher u8 unused27[0x100 - 0x40]; 93386387e1aSJeff Kirsher 93486387e1aSJeff Kirsher u64 xgxs_cfg; 93586387e1aSJeff Kirsher u64 xgxs_status; 93686387e1aSJeff Kirsher 93786387e1aSJeff Kirsher u64 xgxs_cfg_key; 93886387e1aSJeff Kirsher u64 xgxs_efifo_cfg; /* CHANGED */ 93986387e1aSJeff Kirsher u64 rxgxs_ber_0; /* CHANGED */ 94086387e1aSJeff Kirsher u64 rxgxs_ber_1; /* CHANGED */ 94186387e1aSJeff Kirsher 94286387e1aSJeff Kirsher u64 spi_control; 94386387e1aSJeff Kirsher #define SPI_CONTROL_KEY(key) vBIT(key,0,4) 94486387e1aSJeff Kirsher #define SPI_CONTROL_BYTECNT(cnt) vBIT(cnt,29,3) 94586387e1aSJeff Kirsher #define SPI_CONTROL_CMD(cmd) vBIT(cmd,32,8) 94686387e1aSJeff Kirsher #define SPI_CONTROL_ADDR(addr) vBIT(addr,40,24) 94786387e1aSJeff Kirsher #define SPI_CONTROL_SEL1 s2BIT(4) 94886387e1aSJeff Kirsher #define SPI_CONTROL_REQ s2BIT(7) 94986387e1aSJeff Kirsher #define SPI_CONTROL_NACK s2BIT(5) 95086387e1aSJeff Kirsher #define SPI_CONTROL_DONE s2BIT(6) 95186387e1aSJeff Kirsher u64 spi_data; 95286387e1aSJeff Kirsher #define SPI_DATA_WRITE(data,len) vBIT(data,0,len) 95386387e1aSJeff Kirsher }; 95486387e1aSJeff Kirsher 95586387e1aSJeff Kirsher #define XENA_REG_SPACE sizeof(struct XENA_dev_config) 95686387e1aSJeff Kirsher #define XENA_EEPROM_SPACE (0x01 << 11) 95786387e1aSJeff Kirsher 95886387e1aSJeff Kirsher #endif /* _REGS_H */ 959