1 #define VERSION "0.23" 2 /* ns83820.c by Benjamin LaHaise with contributions. 3 * 4 * Questions/comments/discussion to linux-ns83820@kvack.org. 5 * 6 * $Revision: 1.34.2.23 $ 7 * 8 * Copyright 2001 Benjamin LaHaise. 9 * Copyright 2001, 2002 Red Hat. 10 * 11 * Mmmm, chocolate vanilla mocha... 12 * 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License as published by 16 * the Free Software Foundation; either version 2 of the License, or 17 * (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 27 * 28 * 29 * ChangeLog 30 * ========= 31 * 20010414 0.1 - created 32 * 20010622 0.2 - basic rx and tx. 33 * 20010711 0.3 - added duplex and link state detection support. 34 * 20010713 0.4 - zero copy, no hangs. 35 * 0.5 - 64 bit dma support (davem will hate me for this) 36 * - disable jumbo frames to avoid tx hangs 37 * - work around tx deadlocks on my 1.02 card via 38 * fiddling with TXCFG 39 * 20010810 0.6 - use pci dma api for ringbuffers, work on ia64 40 * 20010816 0.7 - misc cleanups 41 * 20010826 0.8 - fix critical zero copy bugs 42 * 0.9 - internal experiment 43 * 20010827 0.10 - fix ia64 unaligned access. 44 * 20010906 0.11 - accept all packets with checksum errors as 45 * otherwise fragments get lost 46 * - fix >> 32 bugs 47 * 0.12 - add statistics counters 48 * - add allmulti/promisc support 49 * 20011009 0.13 - hotplug support, other smaller pci api cleanups 50 * 20011204 0.13a - optical transceiver support added 51 * by Michael Clark <michael@metaparadigm.com> 52 * 20011205 0.13b - call register_netdev earlier in initialization 53 * suppress duplicate link status messages 54 * 20011117 0.14 - ethtool GDRVINFO, GLINK support from jgarzik 55 * 20011204 0.15 get ppc (big endian) working 56 * 20011218 0.16 various cleanups 57 * 20020310 0.17 speedups 58 * 20020610 0.18 - actually use the pci dma api for highmem 59 * - remove pci latency register fiddling 60 * 0.19 - better bist support 61 * - add ihr and reset_phy parameters 62 * - gmii bus probing 63 * - fix missed txok introduced during performance 64 * tuning 65 * 0.20 - fix stupid RFEN thinko. i am such a smurf. 66 * 20040828 0.21 - add hardware vlan accleration 67 * by Neil Horman <nhorman@redhat.com> 68 * 20050406 0.22 - improved DAC ifdefs from Andi Kleen 69 * - removal of dead code from Adrian Bunk 70 * - fix half duplex collision behaviour 71 * Driver Overview 72 * =============== 73 * 74 * This driver was originally written for the National Semiconductor 75 * 83820 chip, a 10/100/1000 Mbps 64 bit PCI ethernet NIC. Hopefully 76 * this code will turn out to be a) clean, b) correct, and c) fast. 77 * With that in mind, I'm aiming to split the code up as much as 78 * reasonably possible. At present there are X major sections that 79 * break down into a) packet receive, b) packet transmit, c) link 80 * management, d) initialization and configuration. Where possible, 81 * these code paths are designed to run in parallel. 82 * 83 * This driver has been tested and found to work with the following 84 * cards (in no particular order): 85 * 86 * Cameo SOHO-GA2000T SOHO-GA2500T 87 * D-Link DGE-500T 88 * PureData PDP8023Z-TG 89 * SMC SMC9452TX SMC9462TX 90 * Netgear GA621 91 * 92 * Special thanks to SMC for providing hardware to test this driver on. 93 * 94 * Reports of success or failure would be greatly appreciated. 95 */ 96 //#define dprintk printk 97 #define dprintk(x...) do { } while (0) 98 99 #include <linux/module.h> 100 #include <linux/moduleparam.h> 101 #include <linux/types.h> 102 #include <linux/pci.h> 103 #include <linux/dma-mapping.h> 104 #include <linux/netdevice.h> 105 #include <linux/etherdevice.h> 106 #include <linux/delay.h> 107 #include <linux/workqueue.h> 108 #include <linux/init.h> 109 #include <linux/interrupt.h> 110 #include <linux/ip.h> /* for iph */ 111 #include <linux/in.h> /* for IPPROTO_... */ 112 #include <linux/compiler.h> 113 #include <linux/prefetch.h> 114 #include <linux/ethtool.h> 115 #include <linux/sched.h> 116 #include <linux/timer.h> 117 #include <linux/if_vlan.h> 118 #include <linux/rtnetlink.h> 119 #include <linux/jiffies.h> 120 #include <linux/slab.h> 121 122 #include <asm/io.h> 123 #include <asm/uaccess.h> 124 #include <asm/system.h> 125 126 #define DRV_NAME "ns83820" 127 128 /* Global parameters. See module_param near the bottom. */ 129 static int ihr = 2; 130 static int reset_phy = 0; 131 static int lnksts = 0; /* CFG_LNKSTS bit polarity */ 132 133 /* Dprintk is used for more interesting debug events */ 134 #undef Dprintk 135 #define Dprintk dprintk 136 137 /* tunables */ 138 #define RX_BUF_SIZE 1500 /* 8192 */ 139 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 140 #define NS83820_VLAN_ACCEL_SUPPORT 141 #endif 142 143 /* Must not exceed ~65000. */ 144 #define NR_RX_DESC 64 145 #define NR_TX_DESC 128 146 147 /* not tunable */ 148 #define REAL_RX_BUF_SIZE (RX_BUF_SIZE + 14) /* rx/tx mac addr + type */ 149 150 #define MIN_TX_DESC_FREE 8 151 152 /* register defines */ 153 #define CFGCS 0x04 154 155 #define CR_TXE 0x00000001 156 #define CR_TXD 0x00000002 157 /* Ramit : Here's a tip, don't do a RXD immediately followed by an RXE 158 * The Receive engine skips one descriptor and moves 159 * onto the next one!! */ 160 #define CR_RXE 0x00000004 161 #define CR_RXD 0x00000008 162 #define CR_TXR 0x00000010 163 #define CR_RXR 0x00000020 164 #define CR_SWI 0x00000080 165 #define CR_RST 0x00000100 166 167 #define PTSCR_EEBIST_FAIL 0x00000001 168 #define PTSCR_EEBIST_EN 0x00000002 169 #define PTSCR_EELOAD_EN 0x00000004 170 #define PTSCR_RBIST_FAIL 0x000001b8 171 #define PTSCR_RBIST_DONE 0x00000200 172 #define PTSCR_RBIST_EN 0x00000400 173 #define PTSCR_RBIST_RST 0x00002000 174 175 #define MEAR_EEDI 0x00000001 176 #define MEAR_EEDO 0x00000002 177 #define MEAR_EECLK 0x00000004 178 #define MEAR_EESEL 0x00000008 179 #define MEAR_MDIO 0x00000010 180 #define MEAR_MDDIR 0x00000020 181 #define MEAR_MDC 0x00000040 182 183 #define ISR_TXDESC3 0x40000000 184 #define ISR_TXDESC2 0x20000000 185 #define ISR_TXDESC1 0x10000000 186 #define ISR_TXDESC0 0x08000000 187 #define ISR_RXDESC3 0x04000000 188 #define ISR_RXDESC2 0x02000000 189 #define ISR_RXDESC1 0x01000000 190 #define ISR_RXDESC0 0x00800000 191 #define ISR_TXRCMP 0x00400000 192 #define ISR_RXRCMP 0x00200000 193 #define ISR_DPERR 0x00100000 194 #define ISR_SSERR 0x00080000 195 #define ISR_RMABT 0x00040000 196 #define ISR_RTABT 0x00020000 197 #define ISR_RXSOVR 0x00010000 198 #define ISR_HIBINT 0x00008000 199 #define ISR_PHY 0x00004000 200 #define ISR_PME 0x00002000 201 #define ISR_SWI 0x00001000 202 #define ISR_MIB 0x00000800 203 #define ISR_TXURN 0x00000400 204 #define ISR_TXIDLE 0x00000200 205 #define ISR_TXERR 0x00000100 206 #define ISR_TXDESC 0x00000080 207 #define ISR_TXOK 0x00000040 208 #define ISR_RXORN 0x00000020 209 #define ISR_RXIDLE 0x00000010 210 #define ISR_RXEARLY 0x00000008 211 #define ISR_RXERR 0x00000004 212 #define ISR_RXDESC 0x00000002 213 #define ISR_RXOK 0x00000001 214 215 #define TXCFG_CSI 0x80000000 216 #define TXCFG_HBI 0x40000000 217 #define TXCFG_MLB 0x20000000 218 #define TXCFG_ATP 0x10000000 219 #define TXCFG_ECRETRY 0x00800000 220 #define TXCFG_BRST_DIS 0x00080000 221 #define TXCFG_MXDMA1024 0x00000000 222 #define TXCFG_MXDMA512 0x00700000 223 #define TXCFG_MXDMA256 0x00600000 224 #define TXCFG_MXDMA128 0x00500000 225 #define TXCFG_MXDMA64 0x00400000 226 #define TXCFG_MXDMA32 0x00300000 227 #define TXCFG_MXDMA16 0x00200000 228 #define TXCFG_MXDMA8 0x00100000 229 230 #define CFG_LNKSTS 0x80000000 231 #define CFG_SPDSTS 0x60000000 232 #define CFG_SPDSTS1 0x40000000 233 #define CFG_SPDSTS0 0x20000000 234 #define CFG_DUPSTS 0x10000000 235 #define CFG_TBI_EN 0x01000000 236 #define CFG_MODE_1000 0x00400000 237 /* Ramit : Dont' ever use AUTO_1000, it never works and is buggy. 238 * Read the Phy response and then configure the MAC accordingly */ 239 #define CFG_AUTO_1000 0x00200000 240 #define CFG_PINT_CTL 0x001c0000 241 #define CFG_PINT_DUPSTS 0x00100000 242 #define CFG_PINT_LNKSTS 0x00080000 243 #define CFG_PINT_SPDSTS 0x00040000 244 #define CFG_TMRTEST 0x00020000 245 #define CFG_MRM_DIS 0x00010000 246 #define CFG_MWI_DIS 0x00008000 247 #define CFG_T64ADDR 0x00004000 248 #define CFG_PCI64_DET 0x00002000 249 #define CFG_DATA64_EN 0x00001000 250 #define CFG_M64ADDR 0x00000800 251 #define CFG_PHY_RST 0x00000400 252 #define CFG_PHY_DIS 0x00000200 253 #define CFG_EXTSTS_EN 0x00000100 254 #define CFG_REQALG 0x00000080 255 #define CFG_SB 0x00000040 256 #define CFG_POW 0x00000020 257 #define CFG_EXD 0x00000010 258 #define CFG_PESEL 0x00000008 259 #define CFG_BROM_DIS 0x00000004 260 #define CFG_EXT_125 0x00000002 261 #define CFG_BEM 0x00000001 262 263 #define EXTSTS_UDPPKT 0x00200000 264 #define EXTSTS_TCPPKT 0x00080000 265 #define EXTSTS_IPPKT 0x00020000 266 #define EXTSTS_VPKT 0x00010000 267 #define EXTSTS_VTG_MASK 0x0000ffff 268 269 #define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0)) 270 271 #define MIBC_MIBS 0x00000008 272 #define MIBC_ACLR 0x00000004 273 #define MIBC_FRZ 0x00000002 274 #define MIBC_WRN 0x00000001 275 276 #define PCR_PSEN (1 << 31) 277 #define PCR_PS_MCAST (1 << 30) 278 #define PCR_PS_DA (1 << 29) 279 #define PCR_STHI_8 (3 << 23) 280 #define PCR_STLO_4 (1 << 23) 281 #define PCR_FFHI_8K (3 << 21) 282 #define PCR_FFLO_4K (1 << 21) 283 #define PCR_PAUSE_CNT 0xFFFE 284 285 #define RXCFG_AEP 0x80000000 286 #define RXCFG_ARP 0x40000000 287 #define RXCFG_STRIPCRC 0x20000000 288 #define RXCFG_RX_FD 0x10000000 289 #define RXCFG_ALP 0x08000000 290 #define RXCFG_AIRL 0x04000000 291 #define RXCFG_MXDMA512 0x00700000 292 #define RXCFG_DRTH 0x0000003e 293 #define RXCFG_DRTH0 0x00000002 294 295 #define RFCR_RFEN 0x80000000 296 #define RFCR_AAB 0x40000000 297 #define RFCR_AAM 0x20000000 298 #define RFCR_AAU 0x10000000 299 #define RFCR_APM 0x08000000 300 #define RFCR_APAT 0x07800000 301 #define RFCR_APAT3 0x04000000 302 #define RFCR_APAT2 0x02000000 303 #define RFCR_APAT1 0x01000000 304 #define RFCR_APAT0 0x00800000 305 #define RFCR_AARP 0x00400000 306 #define RFCR_MHEN 0x00200000 307 #define RFCR_UHEN 0x00100000 308 #define RFCR_ULM 0x00080000 309 310 #define VRCR_RUDPE 0x00000080 311 #define VRCR_RTCPE 0x00000040 312 #define VRCR_RIPE 0x00000020 313 #define VRCR_IPEN 0x00000010 314 #define VRCR_DUTF 0x00000008 315 #define VRCR_DVTF 0x00000004 316 #define VRCR_VTREN 0x00000002 317 #define VRCR_VTDEN 0x00000001 318 319 #define VTCR_PPCHK 0x00000008 320 #define VTCR_GCHK 0x00000004 321 #define VTCR_VPPTI 0x00000002 322 #define VTCR_VGTI 0x00000001 323 324 #define CR 0x00 325 #define CFG 0x04 326 #define MEAR 0x08 327 #define PTSCR 0x0c 328 #define ISR 0x10 329 #define IMR 0x14 330 #define IER 0x18 331 #define IHR 0x1c 332 #define TXDP 0x20 333 #define TXDP_HI 0x24 334 #define TXCFG 0x28 335 #define GPIOR 0x2c 336 #define RXDP 0x30 337 #define RXDP_HI 0x34 338 #define RXCFG 0x38 339 #define PQCR 0x3c 340 #define WCSR 0x40 341 #define PCR 0x44 342 #define RFCR 0x48 343 #define RFDR 0x4c 344 345 #define SRR 0x58 346 347 #define VRCR 0xbc 348 #define VTCR 0xc0 349 #define VDR 0xc4 350 #define CCSR 0xcc 351 352 #define TBICR 0xe0 353 #define TBISR 0xe4 354 #define TANAR 0xe8 355 #define TANLPAR 0xec 356 #define TANER 0xf0 357 #define TESR 0xf4 358 359 #define TBICR_MR_AN_ENABLE 0x00001000 360 #define TBICR_MR_RESTART_AN 0x00000200 361 362 #define TBISR_MR_LINK_STATUS 0x00000020 363 #define TBISR_MR_AN_COMPLETE 0x00000004 364 365 #define TANAR_PS2 0x00000100 366 #define TANAR_PS1 0x00000080 367 #define TANAR_HALF_DUP 0x00000040 368 #define TANAR_FULL_DUP 0x00000020 369 370 #define GPIOR_GP5_OE 0x00000200 371 #define GPIOR_GP4_OE 0x00000100 372 #define GPIOR_GP3_OE 0x00000080 373 #define GPIOR_GP2_OE 0x00000040 374 #define GPIOR_GP1_OE 0x00000020 375 #define GPIOR_GP3_OUT 0x00000004 376 #define GPIOR_GP1_OUT 0x00000001 377 378 #define LINK_AUTONEGOTIATE 0x01 379 #define LINK_DOWN 0x02 380 #define LINK_UP 0x04 381 382 #define HW_ADDR_LEN sizeof(dma_addr_t) 383 #define desc_addr_set(desc, addr) \ 384 do { \ 385 ((desc)[0] = cpu_to_le32(addr)); \ 386 if (HW_ADDR_LEN == 8) \ 387 (desc)[1] = cpu_to_le32(((u64)addr) >> 32); \ 388 } while(0) 389 #define desc_addr_get(desc) \ 390 (le32_to_cpu((desc)[0]) | \ 391 (HW_ADDR_LEN == 8 ? ((dma_addr_t)le32_to_cpu((desc)[1]))<<32 : 0)) 392 393 #define DESC_LINK 0 394 #define DESC_BUFPTR (DESC_LINK + HW_ADDR_LEN/4) 395 #define DESC_CMDSTS (DESC_BUFPTR + HW_ADDR_LEN/4) 396 #define DESC_EXTSTS (DESC_CMDSTS + 4/4) 397 398 #define CMDSTS_OWN 0x80000000 399 #define CMDSTS_MORE 0x40000000 400 #define CMDSTS_INTR 0x20000000 401 #define CMDSTS_ERR 0x10000000 402 #define CMDSTS_OK 0x08000000 403 #define CMDSTS_RUNT 0x00200000 404 #define CMDSTS_LEN_MASK 0x0000ffff 405 406 #define CMDSTS_DEST_MASK 0x01800000 407 #define CMDSTS_DEST_SELF 0x00800000 408 #define CMDSTS_DEST_MULTI 0x01000000 409 410 #define DESC_SIZE 8 /* Should be cache line sized */ 411 412 struct rx_info { 413 spinlock_t lock; 414 int up; 415 unsigned long idle; 416 417 struct sk_buff *skbs[NR_RX_DESC]; 418 419 __le32 *next_rx_desc; 420 u16 next_rx, next_empty; 421 422 __le32 *descs; 423 dma_addr_t phy_descs; 424 }; 425 426 427 struct ns83820 { 428 u8 __iomem *base; 429 430 struct pci_dev *pci_dev; 431 struct net_device *ndev; 432 433 struct rx_info rx_info; 434 struct tasklet_struct rx_tasklet; 435 436 unsigned ihr; 437 struct work_struct tq_refill; 438 439 /* protects everything below. irqsave when using. */ 440 spinlock_t misc_lock; 441 442 u32 CFG_cache; 443 444 u32 MEAR_cache; 445 u32 IMR_cache; 446 447 unsigned linkstate; 448 449 spinlock_t tx_lock; 450 451 u16 tx_done_idx; 452 u16 tx_idx; 453 volatile u16 tx_free_idx; /* idx of free desc chain */ 454 u16 tx_intr_idx; 455 456 atomic_t nr_tx_skbs; 457 struct sk_buff *tx_skbs[NR_TX_DESC]; 458 459 char pad[16] __attribute__((aligned(16))); 460 __le32 *tx_descs; 461 dma_addr_t tx_phy_descs; 462 463 struct timer_list tx_watchdog; 464 }; 465 466 static inline struct ns83820 *PRIV(struct net_device *dev) 467 { 468 return netdev_priv(dev); 469 } 470 471 #define __kick_rx(dev) writel(CR_RXE, dev->base + CR) 472 473 static inline void kick_rx(struct net_device *ndev) 474 { 475 struct ns83820 *dev = PRIV(ndev); 476 dprintk("kick_rx: maybe kicking\n"); 477 if (test_and_clear_bit(0, &dev->rx_info.idle)) { 478 dprintk("actually kicking\n"); 479 writel(dev->rx_info.phy_descs + 480 (4 * DESC_SIZE * dev->rx_info.next_rx), 481 dev->base + RXDP); 482 if (dev->rx_info.next_rx == dev->rx_info.next_empty) 483 printk(KERN_DEBUG "%s: uh-oh: next_rx == next_empty???\n", 484 ndev->name); 485 __kick_rx(dev); 486 } 487 } 488 489 //free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC 490 #define start_tx_okay(dev) \ 491 (((NR_TX_DESC-2 + dev->tx_done_idx - dev->tx_free_idx) % NR_TX_DESC) > MIN_TX_DESC_FREE) 492 493 /* Packet Receiver 494 * 495 * The hardware supports linked lists of receive descriptors for 496 * which ownership is transferred back and forth by means of an 497 * ownership bit. While the hardware does support the use of a 498 * ring for receive descriptors, we only make use of a chain in 499 * an attempt to reduce bus traffic under heavy load scenarios. 500 * This will also make bugs a bit more obvious. The current code 501 * only makes use of a single rx chain; I hope to implement 502 * priority based rx for version 1.0. Goal: even under overload 503 * conditions, still route realtime traffic with as low jitter as 504 * possible. 505 */ 506 static inline void build_rx_desc(struct ns83820 *dev, __le32 *desc, dma_addr_t link, dma_addr_t buf, u32 cmdsts, u32 extsts) 507 { 508 desc_addr_set(desc + DESC_LINK, link); 509 desc_addr_set(desc + DESC_BUFPTR, buf); 510 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 511 mb(); 512 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 513 } 514 515 #define nr_rx_empty(dev) ((NR_RX_DESC-2 + dev->rx_info.next_rx - dev->rx_info.next_empty) % NR_RX_DESC) 516 static inline int ns83820_add_rx_skb(struct ns83820 *dev, struct sk_buff *skb) 517 { 518 unsigned next_empty; 519 u32 cmdsts; 520 __le32 *sg; 521 dma_addr_t buf; 522 523 next_empty = dev->rx_info.next_empty; 524 525 /* don't overrun last rx marker */ 526 if (unlikely(nr_rx_empty(dev) <= 2)) { 527 kfree_skb(skb); 528 return 1; 529 } 530 531 #if 0 532 dprintk("next_empty[%d] nr_used[%d] next_rx[%d]\n", 533 dev->rx_info.next_empty, 534 dev->rx_info.nr_used, 535 dev->rx_info.next_rx 536 ); 537 #endif 538 539 sg = dev->rx_info.descs + (next_empty * DESC_SIZE); 540 BUG_ON(NULL != dev->rx_info.skbs[next_empty]); 541 dev->rx_info.skbs[next_empty] = skb; 542 543 dev->rx_info.next_empty = (next_empty + 1) % NR_RX_DESC; 544 cmdsts = REAL_RX_BUF_SIZE | CMDSTS_INTR; 545 buf = pci_map_single(dev->pci_dev, skb->data, 546 REAL_RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 547 build_rx_desc(dev, sg, 0, buf, cmdsts, 0); 548 /* update link of previous rx */ 549 if (likely(next_empty != dev->rx_info.next_rx)) 550 dev->rx_info.descs[((NR_RX_DESC + next_empty - 1) % NR_RX_DESC) * DESC_SIZE] = cpu_to_le32(dev->rx_info.phy_descs + (next_empty * DESC_SIZE * 4)); 551 552 return 0; 553 } 554 555 static inline int rx_refill(struct net_device *ndev, gfp_t gfp) 556 { 557 struct ns83820 *dev = PRIV(ndev); 558 unsigned i; 559 unsigned long flags = 0; 560 561 if (unlikely(nr_rx_empty(dev) <= 2)) 562 return 0; 563 564 dprintk("rx_refill(%p)\n", ndev); 565 if (gfp == GFP_ATOMIC) 566 spin_lock_irqsave(&dev->rx_info.lock, flags); 567 for (i=0; i<NR_RX_DESC; i++) { 568 struct sk_buff *skb; 569 long res; 570 571 /* extra 16 bytes for alignment */ 572 skb = __netdev_alloc_skb(ndev, REAL_RX_BUF_SIZE+16, gfp); 573 if (unlikely(!skb)) 574 break; 575 576 skb_reserve(skb, skb->data - PTR_ALIGN(skb->data, 16)); 577 if (gfp != GFP_ATOMIC) 578 spin_lock_irqsave(&dev->rx_info.lock, flags); 579 res = ns83820_add_rx_skb(dev, skb); 580 if (gfp != GFP_ATOMIC) 581 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 582 if (res) { 583 i = 1; 584 break; 585 } 586 } 587 if (gfp == GFP_ATOMIC) 588 spin_unlock_irqrestore(&dev->rx_info.lock, flags); 589 590 return i ? 0 : -ENOMEM; 591 } 592 593 static void rx_refill_atomic(struct net_device *ndev) 594 { 595 rx_refill(ndev, GFP_ATOMIC); 596 } 597 598 /* REFILL */ 599 static inline void queue_refill(struct work_struct *work) 600 { 601 struct ns83820 *dev = container_of(work, struct ns83820, tq_refill); 602 struct net_device *ndev = dev->ndev; 603 604 rx_refill(ndev, GFP_KERNEL); 605 if (dev->rx_info.up) 606 kick_rx(ndev); 607 } 608 609 static inline void clear_rx_desc(struct ns83820 *dev, unsigned i) 610 { 611 build_rx_desc(dev, dev->rx_info.descs + (DESC_SIZE * i), 0, 0, CMDSTS_OWN, 0); 612 } 613 614 static void phy_intr(struct net_device *ndev) 615 { 616 struct ns83820 *dev = PRIV(ndev); 617 static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" }; 618 u32 cfg, new_cfg; 619 u32 tbisr, tanar, tanlpar; 620 int speed, fullduplex, newlinkstate; 621 622 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 623 624 if (dev->CFG_cache & CFG_TBI_EN) { 625 /* we have an optical transceiver */ 626 tbisr = readl(dev->base + TBISR); 627 tanar = readl(dev->base + TANAR); 628 tanlpar = readl(dev->base + TANLPAR); 629 dprintk("phy_intr: tbisr=%08x, tanar=%08x, tanlpar=%08x\n", 630 tbisr, tanar, tanlpar); 631 632 if ( (fullduplex = (tanlpar & TANAR_FULL_DUP) && 633 (tanar & TANAR_FULL_DUP)) ) { 634 635 /* both of us are full duplex */ 636 writel(readl(dev->base + TXCFG) 637 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 638 dev->base + TXCFG); 639 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 640 dev->base + RXCFG); 641 /* Light up full duplex LED */ 642 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, 643 dev->base + GPIOR); 644 645 } else if (((tanlpar & TANAR_HALF_DUP) && 646 (tanar & TANAR_HALF_DUP)) || 647 ((tanlpar & TANAR_FULL_DUP) && 648 (tanar & TANAR_HALF_DUP)) || 649 ((tanlpar & TANAR_HALF_DUP) && 650 (tanar & TANAR_FULL_DUP))) { 651 652 /* one or both of us are half duplex */ 653 writel((readl(dev->base + TXCFG) 654 & ~(TXCFG_CSI | TXCFG_HBI)) | TXCFG_ATP, 655 dev->base + TXCFG); 656 writel(readl(dev->base + RXCFG) & ~RXCFG_RX_FD, 657 dev->base + RXCFG); 658 /* Turn off full duplex LED */ 659 writel(readl(dev->base + GPIOR) & ~GPIOR_GP1_OUT, 660 dev->base + GPIOR); 661 } 662 663 speed = 4; /* 1000F */ 664 665 } else { 666 /* we have a copper transceiver */ 667 new_cfg = dev->CFG_cache & ~(CFG_SB | CFG_MODE_1000 | CFG_SPDSTS); 668 669 if (cfg & CFG_SPDSTS1) 670 new_cfg |= CFG_MODE_1000; 671 else 672 new_cfg &= ~CFG_MODE_1000; 673 674 speed = ((cfg / CFG_SPDSTS0) & 3); 675 fullduplex = (cfg & CFG_DUPSTS); 676 677 if (fullduplex) { 678 new_cfg |= CFG_SB; 679 writel(readl(dev->base + TXCFG) 680 | TXCFG_CSI | TXCFG_HBI, 681 dev->base + TXCFG); 682 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 683 dev->base + RXCFG); 684 } else { 685 writel(readl(dev->base + TXCFG) 686 & ~(TXCFG_CSI | TXCFG_HBI), 687 dev->base + TXCFG); 688 writel(readl(dev->base + RXCFG) & ~(RXCFG_RX_FD), 689 dev->base + RXCFG); 690 } 691 692 if ((cfg & CFG_LNKSTS) && 693 ((new_cfg ^ dev->CFG_cache) != 0)) { 694 writel(new_cfg, dev->base + CFG); 695 dev->CFG_cache = new_cfg; 696 } 697 698 dev->CFG_cache &= ~CFG_SPDSTS; 699 dev->CFG_cache |= cfg & CFG_SPDSTS; 700 } 701 702 newlinkstate = (cfg & CFG_LNKSTS) ? LINK_UP : LINK_DOWN; 703 704 if (newlinkstate & LINK_UP && 705 dev->linkstate != newlinkstate) { 706 netif_start_queue(ndev); 707 netif_wake_queue(ndev); 708 printk(KERN_INFO "%s: link now %s mbps, %s duplex and up.\n", 709 ndev->name, 710 speeds[speed], 711 fullduplex ? "full" : "half"); 712 } else if (newlinkstate & LINK_DOWN && 713 dev->linkstate != newlinkstate) { 714 netif_stop_queue(ndev); 715 printk(KERN_INFO "%s: link now down.\n", ndev->name); 716 } 717 718 dev->linkstate = newlinkstate; 719 } 720 721 static int ns83820_setup_rx(struct net_device *ndev) 722 { 723 struct ns83820 *dev = PRIV(ndev); 724 unsigned i; 725 int ret; 726 727 dprintk("ns83820_setup_rx(%p)\n", ndev); 728 729 dev->rx_info.idle = 1; 730 dev->rx_info.next_rx = 0; 731 dev->rx_info.next_rx_desc = dev->rx_info.descs; 732 dev->rx_info.next_empty = 0; 733 734 for (i=0; i<NR_RX_DESC; i++) 735 clear_rx_desc(dev, i); 736 737 writel(0, dev->base + RXDP_HI); 738 writel(dev->rx_info.phy_descs, dev->base + RXDP); 739 740 ret = rx_refill(ndev, GFP_KERNEL); 741 if (!ret) { 742 dprintk("starting receiver\n"); 743 /* prevent the interrupt handler from stomping on us */ 744 spin_lock_irq(&dev->rx_info.lock); 745 746 writel(0x0001, dev->base + CCSR); 747 writel(0, dev->base + RFCR); 748 writel(0x7fc00000, dev->base + RFCR); 749 writel(0xffc00000, dev->base + RFCR); 750 751 dev->rx_info.up = 1; 752 753 phy_intr(ndev); 754 755 /* Okay, let it rip */ 756 spin_lock(&dev->misc_lock); 757 dev->IMR_cache |= ISR_PHY; 758 dev->IMR_cache |= ISR_RXRCMP; 759 //dev->IMR_cache |= ISR_RXERR; 760 //dev->IMR_cache |= ISR_RXOK; 761 dev->IMR_cache |= ISR_RXORN; 762 dev->IMR_cache |= ISR_RXSOVR; 763 dev->IMR_cache |= ISR_RXDESC; 764 dev->IMR_cache |= ISR_RXIDLE; 765 dev->IMR_cache |= ISR_TXDESC; 766 dev->IMR_cache |= ISR_TXIDLE; 767 768 writel(dev->IMR_cache, dev->base + IMR); 769 writel(1, dev->base + IER); 770 spin_unlock(&dev->misc_lock); 771 772 kick_rx(ndev); 773 774 spin_unlock_irq(&dev->rx_info.lock); 775 } 776 return ret; 777 } 778 779 static void ns83820_cleanup_rx(struct ns83820 *dev) 780 { 781 unsigned i; 782 unsigned long flags; 783 784 dprintk("ns83820_cleanup_rx(%p)\n", dev); 785 786 /* disable receive interrupts */ 787 spin_lock_irqsave(&dev->misc_lock, flags); 788 dev->IMR_cache &= ~(ISR_RXOK | ISR_RXDESC | ISR_RXERR | ISR_RXEARLY | ISR_RXIDLE); 789 writel(dev->IMR_cache, dev->base + IMR); 790 spin_unlock_irqrestore(&dev->misc_lock, flags); 791 792 /* synchronize with the interrupt handler and kill it */ 793 dev->rx_info.up = 0; 794 synchronize_irq(dev->pci_dev->irq); 795 796 /* touch the pci bus... */ 797 readl(dev->base + IMR); 798 799 /* assumes the transmitter is already disabled and reset */ 800 writel(0, dev->base + RXDP_HI); 801 writel(0, dev->base + RXDP); 802 803 for (i=0; i<NR_RX_DESC; i++) { 804 struct sk_buff *skb = dev->rx_info.skbs[i]; 805 dev->rx_info.skbs[i] = NULL; 806 clear_rx_desc(dev, i); 807 kfree_skb(skb); 808 } 809 } 810 811 static void ns83820_rx_kick(struct net_device *ndev) 812 { 813 struct ns83820 *dev = PRIV(ndev); 814 /*if (nr_rx_empty(dev) >= NR_RX_DESC/4)*/ { 815 if (dev->rx_info.up) { 816 rx_refill_atomic(ndev); 817 kick_rx(ndev); 818 } 819 } 820 821 if (dev->rx_info.up && nr_rx_empty(dev) > NR_RX_DESC*3/4) 822 schedule_work(&dev->tq_refill); 823 else 824 kick_rx(ndev); 825 if (dev->rx_info.idle) 826 printk(KERN_DEBUG "%s: BAD\n", ndev->name); 827 } 828 829 /* rx_irq 830 * 831 */ 832 static void rx_irq(struct net_device *ndev) 833 { 834 struct ns83820 *dev = PRIV(ndev); 835 struct rx_info *info = &dev->rx_info; 836 unsigned next_rx; 837 int rx_rc, len; 838 u32 cmdsts; 839 __le32 *desc; 840 unsigned long flags; 841 int nr = 0; 842 843 dprintk("rx_irq(%p)\n", ndev); 844 dprintk("rxdp: %08x, descs: %08lx next_rx[%d]: %p next_empty[%d]: %p\n", 845 readl(dev->base + RXDP), 846 (long)(dev->rx_info.phy_descs), 847 (int)dev->rx_info.next_rx, 848 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_rx)), 849 (int)dev->rx_info.next_empty, 850 (dev->rx_info.descs + (DESC_SIZE * dev->rx_info.next_empty)) 851 ); 852 853 spin_lock_irqsave(&info->lock, flags); 854 if (!info->up) 855 goto out; 856 857 dprintk("walking descs\n"); 858 next_rx = info->next_rx; 859 desc = info->next_rx_desc; 860 while ((CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) && 861 (cmdsts != CMDSTS_OWN)) { 862 struct sk_buff *skb; 863 u32 extsts = le32_to_cpu(desc[DESC_EXTSTS]); 864 dma_addr_t bufptr = desc_addr_get(desc + DESC_BUFPTR); 865 866 dprintk("cmdsts: %08x\n", cmdsts); 867 dprintk("link: %08x\n", cpu_to_le32(desc[DESC_LINK])); 868 dprintk("extsts: %08x\n", extsts); 869 870 skb = info->skbs[next_rx]; 871 info->skbs[next_rx] = NULL; 872 info->next_rx = (next_rx + 1) % NR_RX_DESC; 873 874 mb(); 875 clear_rx_desc(dev, next_rx); 876 877 pci_unmap_single(dev->pci_dev, bufptr, 878 RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 879 len = cmdsts & CMDSTS_LEN_MASK; 880 #ifdef NS83820_VLAN_ACCEL_SUPPORT 881 /* NH: As was mentioned below, this chip is kinda 882 * brain dead about vlan tag stripping. Frames 883 * that are 64 bytes with a vlan header appended 884 * like arp frames, or pings, are flagged as Runts 885 * when the tag is stripped and hardware. This 886 * also means that the OK bit in the descriptor 887 * is cleared when the frame comes in so we have 888 * to do a specific length check here to make sure 889 * the frame would have been ok, had we not stripped 890 * the tag. 891 */ 892 if (likely((CMDSTS_OK & cmdsts) || 893 ((cmdsts & CMDSTS_RUNT) && len >= 56))) { 894 #else 895 if (likely(CMDSTS_OK & cmdsts)) { 896 #endif 897 skb_put(skb, len); 898 if (unlikely(!skb)) 899 goto netdev_mangle_me_harder_failed; 900 if (cmdsts & CMDSTS_DEST_MULTI) 901 ndev->stats.multicast++; 902 ndev->stats.rx_packets++; 903 ndev->stats.rx_bytes += len; 904 if ((extsts & 0x002a0000) && !(extsts & 0x00540000)) { 905 skb->ip_summed = CHECKSUM_UNNECESSARY; 906 } else { 907 skb_checksum_none_assert(skb); 908 } 909 skb->protocol = eth_type_trans(skb, ndev); 910 #ifdef NS83820_VLAN_ACCEL_SUPPORT 911 if(extsts & EXTSTS_VPKT) { 912 unsigned short tag; 913 914 tag = ntohs(extsts & EXTSTS_VTG_MASK); 915 __vlan_hwaccel_put_tag(skb, tag); 916 } 917 #endif 918 rx_rc = netif_rx(skb); 919 if (NET_RX_DROP == rx_rc) { 920 netdev_mangle_me_harder_failed: 921 ndev->stats.rx_dropped++; 922 } 923 } else { 924 kfree_skb(skb); 925 } 926 927 nr++; 928 next_rx = info->next_rx; 929 desc = info->descs + (DESC_SIZE * next_rx); 930 } 931 info->next_rx = next_rx; 932 info->next_rx_desc = info->descs + (DESC_SIZE * next_rx); 933 934 out: 935 if (0 && !nr) { 936 Dprintk("dazed: cmdsts_f: %08x\n", cmdsts); 937 } 938 939 spin_unlock_irqrestore(&info->lock, flags); 940 } 941 942 static void rx_action(unsigned long _dev) 943 { 944 struct net_device *ndev = (void *)_dev; 945 struct ns83820 *dev = PRIV(ndev); 946 rx_irq(ndev); 947 writel(ihr, dev->base + IHR); 948 949 spin_lock_irq(&dev->misc_lock); 950 dev->IMR_cache |= ISR_RXDESC; 951 writel(dev->IMR_cache, dev->base + IMR); 952 spin_unlock_irq(&dev->misc_lock); 953 954 rx_irq(ndev); 955 ns83820_rx_kick(ndev); 956 } 957 958 /* Packet Transmit code 959 */ 960 static inline void kick_tx(struct ns83820 *dev) 961 { 962 dprintk("kick_tx(%p): tx_idx=%d free_idx=%d\n", 963 dev, dev->tx_idx, dev->tx_free_idx); 964 writel(CR_TXE, dev->base + CR); 965 } 966 967 /* No spinlock needed on the transmit irq path as the interrupt handler is 968 * serialized. 969 */ 970 static void do_tx_done(struct net_device *ndev) 971 { 972 struct ns83820 *dev = PRIV(ndev); 973 u32 cmdsts, tx_done_idx; 974 __le32 *desc; 975 976 dprintk("do_tx_done(%p)\n", ndev); 977 tx_done_idx = dev->tx_done_idx; 978 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 979 980 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 981 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 982 while ((tx_done_idx != dev->tx_free_idx) && 983 !(CMDSTS_OWN & (cmdsts = le32_to_cpu(desc[DESC_CMDSTS]))) ) { 984 struct sk_buff *skb; 985 unsigned len; 986 dma_addr_t addr; 987 988 if (cmdsts & CMDSTS_ERR) 989 ndev->stats.tx_errors++; 990 if (cmdsts & CMDSTS_OK) 991 ndev->stats.tx_packets++; 992 if (cmdsts & CMDSTS_OK) 993 ndev->stats.tx_bytes += cmdsts & 0xffff; 994 995 dprintk("tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 996 tx_done_idx, dev->tx_free_idx, cmdsts); 997 skb = dev->tx_skbs[tx_done_idx]; 998 dev->tx_skbs[tx_done_idx] = NULL; 999 dprintk("done(%p)\n", skb); 1000 1001 len = cmdsts & CMDSTS_LEN_MASK; 1002 addr = desc_addr_get(desc + DESC_BUFPTR); 1003 if (skb) { 1004 pci_unmap_single(dev->pci_dev, 1005 addr, 1006 len, 1007 PCI_DMA_TODEVICE); 1008 dev_kfree_skb_irq(skb); 1009 atomic_dec(&dev->nr_tx_skbs); 1010 } else 1011 pci_unmap_page(dev->pci_dev, 1012 addr, 1013 len, 1014 PCI_DMA_TODEVICE); 1015 1016 tx_done_idx = (tx_done_idx + 1) % NR_TX_DESC; 1017 dev->tx_done_idx = tx_done_idx; 1018 desc[DESC_CMDSTS] = cpu_to_le32(0); 1019 mb(); 1020 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1021 } 1022 1023 /* Allow network stack to resume queueing packets after we've 1024 * finished transmitting at least 1/4 of the packets in the queue. 1025 */ 1026 if (netif_queue_stopped(ndev) && start_tx_okay(dev)) { 1027 dprintk("start_queue(%p)\n", ndev); 1028 netif_start_queue(ndev); 1029 netif_wake_queue(ndev); 1030 } 1031 } 1032 1033 static void ns83820_cleanup_tx(struct ns83820 *dev) 1034 { 1035 unsigned i; 1036 1037 for (i=0; i<NR_TX_DESC; i++) { 1038 struct sk_buff *skb = dev->tx_skbs[i]; 1039 dev->tx_skbs[i] = NULL; 1040 if (skb) { 1041 __le32 *desc = dev->tx_descs + (i * DESC_SIZE); 1042 pci_unmap_single(dev->pci_dev, 1043 desc_addr_get(desc + DESC_BUFPTR), 1044 le32_to_cpu(desc[DESC_CMDSTS]) & CMDSTS_LEN_MASK, 1045 PCI_DMA_TODEVICE); 1046 dev_kfree_skb_irq(skb); 1047 atomic_dec(&dev->nr_tx_skbs); 1048 } 1049 } 1050 1051 memset(dev->tx_descs, 0, NR_TX_DESC * DESC_SIZE * 4); 1052 } 1053 1054 /* transmit routine. This code relies on the network layer serializing 1055 * its calls in, but will run happily in parallel with the interrupt 1056 * handler. This code currently has provisions for fragmenting tx buffers 1057 * while trying to track down a bug in either the zero copy code or 1058 * the tx fifo (hence the MAX_FRAG_LEN). 1059 */ 1060 static netdev_tx_t ns83820_hard_start_xmit(struct sk_buff *skb, 1061 struct net_device *ndev) 1062 { 1063 struct ns83820 *dev = PRIV(ndev); 1064 u32 free_idx, cmdsts, extsts; 1065 int nr_free, nr_frags; 1066 unsigned tx_done_idx, last_idx; 1067 dma_addr_t buf; 1068 unsigned len; 1069 skb_frag_t *frag; 1070 int stopped = 0; 1071 int do_intr = 0; 1072 volatile __le32 *first_desc; 1073 1074 dprintk("ns83820_hard_start_xmit\n"); 1075 1076 nr_frags = skb_shinfo(skb)->nr_frags; 1077 again: 1078 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) { 1079 netif_stop_queue(ndev); 1080 if (unlikely(dev->CFG_cache & CFG_LNKSTS)) 1081 return NETDEV_TX_BUSY; 1082 netif_start_queue(ndev); 1083 } 1084 1085 last_idx = free_idx = dev->tx_free_idx; 1086 tx_done_idx = dev->tx_done_idx; 1087 nr_free = (tx_done_idx + NR_TX_DESC-2 - free_idx) % NR_TX_DESC; 1088 nr_free -= 1; 1089 if (nr_free <= nr_frags) { 1090 dprintk("stop_queue - not enough(%p)\n", ndev); 1091 netif_stop_queue(ndev); 1092 1093 /* Check again: we may have raced with a tx done irq */ 1094 if (dev->tx_done_idx != tx_done_idx) { 1095 dprintk("restart queue(%p)\n", ndev); 1096 netif_start_queue(ndev); 1097 goto again; 1098 } 1099 return NETDEV_TX_BUSY; 1100 } 1101 1102 if (free_idx == dev->tx_intr_idx) { 1103 do_intr = 1; 1104 dev->tx_intr_idx = (dev->tx_intr_idx + NR_TX_DESC/4) % NR_TX_DESC; 1105 } 1106 1107 nr_free -= nr_frags; 1108 if (nr_free < MIN_TX_DESC_FREE) { 1109 dprintk("stop_queue - last entry(%p)\n", ndev); 1110 netif_stop_queue(ndev); 1111 stopped = 1; 1112 } 1113 1114 frag = skb_shinfo(skb)->frags; 1115 if (!nr_frags) 1116 frag = NULL; 1117 extsts = 0; 1118 if (skb->ip_summed == CHECKSUM_PARTIAL) { 1119 extsts |= EXTSTS_IPPKT; 1120 if (IPPROTO_TCP == ip_hdr(skb)->protocol) 1121 extsts |= EXTSTS_TCPPKT; 1122 else if (IPPROTO_UDP == ip_hdr(skb)->protocol) 1123 extsts |= EXTSTS_UDPPKT; 1124 } 1125 1126 #ifdef NS83820_VLAN_ACCEL_SUPPORT 1127 if(vlan_tx_tag_present(skb)) { 1128 /* fetch the vlan tag info out of the 1129 * ancillary data if the vlan code 1130 * is using hw vlan acceleration 1131 */ 1132 short tag = vlan_tx_tag_get(skb); 1133 extsts |= (EXTSTS_VPKT | htons(tag)); 1134 } 1135 #endif 1136 1137 len = skb->len; 1138 if (nr_frags) 1139 len -= skb->data_len; 1140 buf = pci_map_single(dev->pci_dev, skb->data, len, PCI_DMA_TODEVICE); 1141 1142 first_desc = dev->tx_descs + (free_idx * DESC_SIZE); 1143 1144 for (;;) { 1145 volatile __le32 *desc = dev->tx_descs + (free_idx * DESC_SIZE); 1146 1147 dprintk("frag[%3u]: %4u @ 0x%08Lx\n", free_idx, len, 1148 (unsigned long long)buf); 1149 last_idx = free_idx; 1150 free_idx = (free_idx + 1) % NR_TX_DESC; 1151 desc[DESC_LINK] = cpu_to_le32(dev->tx_phy_descs + (free_idx * DESC_SIZE * 4)); 1152 desc_addr_set(desc + DESC_BUFPTR, buf); 1153 desc[DESC_EXTSTS] = cpu_to_le32(extsts); 1154 1155 cmdsts = ((nr_frags) ? CMDSTS_MORE : do_intr ? CMDSTS_INTR : 0); 1156 cmdsts |= (desc == first_desc) ? 0 : CMDSTS_OWN; 1157 cmdsts |= len; 1158 desc[DESC_CMDSTS] = cpu_to_le32(cmdsts); 1159 1160 if (!nr_frags) 1161 break; 1162 1163 buf = skb_frag_dma_map(&dev->pci_dev->dev, frag, 0, 1164 skb_frag_size(frag), DMA_TO_DEVICE); 1165 dprintk("frag: buf=%08Lx page=%08lx offset=%08lx\n", 1166 (long long)buf, (long) page_to_pfn(frag->page), 1167 frag->page_offset); 1168 len = skb_frag_size(frag); 1169 frag++; 1170 nr_frags--; 1171 } 1172 dprintk("done pkt\n"); 1173 1174 spin_lock_irq(&dev->tx_lock); 1175 dev->tx_skbs[last_idx] = skb; 1176 first_desc[DESC_CMDSTS] |= cpu_to_le32(CMDSTS_OWN); 1177 dev->tx_free_idx = free_idx; 1178 atomic_inc(&dev->nr_tx_skbs); 1179 spin_unlock_irq(&dev->tx_lock); 1180 1181 kick_tx(dev); 1182 1183 /* Check again: we may have raced with a tx done irq */ 1184 if (stopped && (dev->tx_done_idx != tx_done_idx) && start_tx_okay(dev)) 1185 netif_start_queue(ndev); 1186 1187 return NETDEV_TX_OK; 1188 } 1189 1190 static void ns83820_update_stats(struct ns83820 *dev) 1191 { 1192 struct net_device *ndev = dev->ndev; 1193 u8 __iomem *base = dev->base; 1194 1195 /* the DP83820 will freeze counters, so we need to read all of them */ 1196 ndev->stats.rx_errors += readl(base + 0x60) & 0xffff; 1197 ndev->stats.rx_crc_errors += readl(base + 0x64) & 0xffff; 1198 ndev->stats.rx_missed_errors += readl(base + 0x68) & 0xffff; 1199 ndev->stats.rx_frame_errors += readl(base + 0x6c) & 0xffff; 1200 /*ndev->stats.rx_symbol_errors +=*/ readl(base + 0x70); 1201 ndev->stats.rx_length_errors += readl(base + 0x74) & 0xffff; 1202 ndev->stats.rx_length_errors += readl(base + 0x78) & 0xffff; 1203 /*ndev->stats.rx_badopcode_errors += */ readl(base + 0x7c); 1204 /*ndev->stats.rx_pause_count += */ readl(base + 0x80); 1205 /*ndev->stats.tx_pause_count += */ readl(base + 0x84); 1206 ndev->stats.tx_carrier_errors += readl(base + 0x88) & 0xff; 1207 } 1208 1209 static struct net_device_stats *ns83820_get_stats(struct net_device *ndev) 1210 { 1211 struct ns83820 *dev = PRIV(ndev); 1212 1213 /* somewhat overkill */ 1214 spin_lock_irq(&dev->misc_lock); 1215 ns83820_update_stats(dev); 1216 spin_unlock_irq(&dev->misc_lock); 1217 1218 return &ndev->stats; 1219 } 1220 1221 /* Let ethtool retrieve info */ 1222 static int ns83820_get_settings(struct net_device *ndev, 1223 struct ethtool_cmd *cmd) 1224 { 1225 struct ns83820 *dev = PRIV(ndev); 1226 u32 cfg, tanar, tbicr; 1227 int fullduplex = 0; 1228 1229 /* 1230 * Here's the list of available ethtool commands from other drivers: 1231 * cmd->advertising = 1232 * ethtool_cmd_speed_set(cmd, ...) 1233 * cmd->duplex = 1234 * cmd->port = 0; 1235 * cmd->phy_address = 1236 * cmd->transceiver = 0; 1237 * cmd->autoneg = 1238 * cmd->maxtxpkt = 0; 1239 * cmd->maxrxpkt = 0; 1240 */ 1241 1242 /* read current configuration */ 1243 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1244 tanar = readl(dev->base + TANAR); 1245 tbicr = readl(dev->base + TBICR); 1246 1247 fullduplex = (cfg & CFG_DUPSTS) ? 1 : 0; 1248 1249 cmd->supported = SUPPORTED_Autoneg; 1250 1251 if (dev->CFG_cache & CFG_TBI_EN) { 1252 /* we have optical interface */ 1253 cmd->supported |= SUPPORTED_1000baseT_Half | 1254 SUPPORTED_1000baseT_Full | 1255 SUPPORTED_FIBRE; 1256 cmd->port = PORT_FIBRE; 1257 } else { 1258 /* we have copper */ 1259 cmd->supported |= SUPPORTED_10baseT_Half | 1260 SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Half | 1261 SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Half | 1262 SUPPORTED_1000baseT_Full | 1263 SUPPORTED_MII; 1264 cmd->port = PORT_MII; 1265 } 1266 1267 cmd->duplex = fullduplex ? DUPLEX_FULL : DUPLEX_HALF; 1268 switch (cfg / CFG_SPDSTS0 & 3) { 1269 case 2: 1270 ethtool_cmd_speed_set(cmd, SPEED_1000); 1271 break; 1272 case 1: 1273 ethtool_cmd_speed_set(cmd, SPEED_100); 1274 break; 1275 default: 1276 ethtool_cmd_speed_set(cmd, SPEED_10); 1277 break; 1278 } 1279 cmd->autoneg = (tbicr & TBICR_MR_AN_ENABLE) 1280 ? AUTONEG_ENABLE : AUTONEG_DISABLE; 1281 return 0; 1282 } 1283 1284 /* Let ethool change settings*/ 1285 static int ns83820_set_settings(struct net_device *ndev, 1286 struct ethtool_cmd *cmd) 1287 { 1288 struct ns83820 *dev = PRIV(ndev); 1289 u32 cfg, tanar; 1290 int have_optical = 0; 1291 int fullduplex = 0; 1292 1293 /* read current configuration */ 1294 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1295 tanar = readl(dev->base + TANAR); 1296 1297 if (dev->CFG_cache & CFG_TBI_EN) { 1298 /* we have optical */ 1299 have_optical = 1; 1300 fullduplex = (tanar & TANAR_FULL_DUP); 1301 1302 } else { 1303 /* we have copper */ 1304 fullduplex = cfg & CFG_DUPSTS; 1305 } 1306 1307 spin_lock_irq(&dev->misc_lock); 1308 spin_lock(&dev->tx_lock); 1309 1310 /* Set duplex */ 1311 if (cmd->duplex != fullduplex) { 1312 if (have_optical) { 1313 /*set full duplex*/ 1314 if (cmd->duplex == DUPLEX_FULL) { 1315 /* force full duplex */ 1316 writel(readl(dev->base + TXCFG) 1317 | TXCFG_CSI | TXCFG_HBI | TXCFG_ATP, 1318 dev->base + TXCFG); 1319 writel(readl(dev->base + RXCFG) | RXCFG_RX_FD, 1320 dev->base + RXCFG); 1321 /* Light up full duplex LED */ 1322 writel(readl(dev->base + GPIOR) | GPIOR_GP1_OUT, 1323 dev->base + GPIOR); 1324 } else { 1325 /*TODO: set half duplex */ 1326 } 1327 1328 } else { 1329 /*we have copper*/ 1330 /* TODO: Set duplex for copper cards */ 1331 } 1332 printk(KERN_INFO "%s: Duplex set via ethtool\n", 1333 ndev->name); 1334 } 1335 1336 /* Set autonegotiation */ 1337 if (1) { 1338 if (cmd->autoneg == AUTONEG_ENABLE) { 1339 /* restart auto negotiation */ 1340 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 1341 dev->base + TBICR); 1342 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); 1343 dev->linkstate = LINK_AUTONEGOTIATE; 1344 1345 printk(KERN_INFO "%s: autoneg enabled via ethtool\n", 1346 ndev->name); 1347 } else { 1348 /* disable auto negotiation */ 1349 writel(0x00000000, dev->base + TBICR); 1350 } 1351 1352 printk(KERN_INFO "%s: autoneg %s via ethtool\n", ndev->name, 1353 cmd->autoneg ? "ENABLED" : "DISABLED"); 1354 } 1355 1356 phy_intr(ndev); 1357 spin_unlock(&dev->tx_lock); 1358 spin_unlock_irq(&dev->misc_lock); 1359 1360 return 0; 1361 } 1362 /* end ethtool get/set support -df */ 1363 1364 static void ns83820_get_drvinfo(struct net_device *ndev, struct ethtool_drvinfo *info) 1365 { 1366 struct ns83820 *dev = PRIV(ndev); 1367 strcpy(info->driver, "ns83820"); 1368 strcpy(info->version, VERSION); 1369 strcpy(info->bus_info, pci_name(dev->pci_dev)); 1370 } 1371 1372 static u32 ns83820_get_link(struct net_device *ndev) 1373 { 1374 struct ns83820 *dev = PRIV(ndev); 1375 u32 cfg = readl(dev->base + CFG) ^ SPDSTS_POLARITY; 1376 return cfg & CFG_LNKSTS ? 1 : 0; 1377 } 1378 1379 static const struct ethtool_ops ops = { 1380 .get_settings = ns83820_get_settings, 1381 .set_settings = ns83820_set_settings, 1382 .get_drvinfo = ns83820_get_drvinfo, 1383 .get_link = ns83820_get_link 1384 }; 1385 1386 static inline void ns83820_disable_interrupts(struct ns83820 *dev) 1387 { 1388 writel(0, dev->base + IMR); 1389 writel(0, dev->base + IER); 1390 readl(dev->base + IER); 1391 } 1392 1393 /* this function is called in irq context from the ISR */ 1394 static void ns83820_mib_isr(struct ns83820 *dev) 1395 { 1396 unsigned long flags; 1397 spin_lock_irqsave(&dev->misc_lock, flags); 1398 ns83820_update_stats(dev); 1399 spin_unlock_irqrestore(&dev->misc_lock, flags); 1400 } 1401 1402 static void ns83820_do_isr(struct net_device *ndev, u32 isr); 1403 static irqreturn_t ns83820_irq(int foo, void *data) 1404 { 1405 struct net_device *ndev = data; 1406 struct ns83820 *dev = PRIV(ndev); 1407 u32 isr; 1408 dprintk("ns83820_irq(%p)\n", ndev); 1409 1410 dev->ihr = 0; 1411 1412 isr = readl(dev->base + ISR); 1413 dprintk("irq: %08x\n", isr); 1414 ns83820_do_isr(ndev, isr); 1415 return IRQ_HANDLED; 1416 } 1417 1418 static void ns83820_do_isr(struct net_device *ndev, u32 isr) 1419 { 1420 struct ns83820 *dev = PRIV(ndev); 1421 unsigned long flags; 1422 1423 #ifdef DEBUG 1424 if (isr & ~(ISR_PHY | ISR_RXDESC | ISR_RXEARLY | ISR_RXOK | ISR_RXERR | ISR_TXIDLE | ISR_TXOK | ISR_TXDESC)) 1425 Dprintk("odd isr? 0x%08x\n", isr); 1426 #endif 1427 1428 if (ISR_RXIDLE & isr) { 1429 dev->rx_info.idle = 1; 1430 Dprintk("oh dear, we are idle\n"); 1431 ns83820_rx_kick(ndev); 1432 } 1433 1434 if ((ISR_RXDESC | ISR_RXOK) & isr) { 1435 prefetch(dev->rx_info.next_rx_desc); 1436 1437 spin_lock_irqsave(&dev->misc_lock, flags); 1438 dev->IMR_cache &= ~(ISR_RXDESC | ISR_RXOK); 1439 writel(dev->IMR_cache, dev->base + IMR); 1440 spin_unlock_irqrestore(&dev->misc_lock, flags); 1441 1442 tasklet_schedule(&dev->rx_tasklet); 1443 //rx_irq(ndev); 1444 //writel(4, dev->base + IHR); 1445 } 1446 1447 if ((ISR_RXIDLE | ISR_RXORN | ISR_RXDESC | ISR_RXOK | ISR_RXERR) & isr) 1448 ns83820_rx_kick(ndev); 1449 1450 if (unlikely(ISR_RXSOVR & isr)) { 1451 //printk("overrun: rxsovr\n"); 1452 ndev->stats.rx_fifo_errors++; 1453 } 1454 1455 if (unlikely(ISR_RXORN & isr)) { 1456 //printk("overrun: rxorn\n"); 1457 ndev->stats.rx_fifo_errors++; 1458 } 1459 1460 if ((ISR_RXRCMP & isr) && dev->rx_info.up) 1461 writel(CR_RXE, dev->base + CR); 1462 1463 if (ISR_TXIDLE & isr) { 1464 u32 txdp; 1465 txdp = readl(dev->base + TXDP); 1466 dprintk("txdp: %08x\n", txdp); 1467 txdp -= dev->tx_phy_descs; 1468 dev->tx_idx = txdp / (DESC_SIZE * 4); 1469 if (dev->tx_idx >= NR_TX_DESC) { 1470 printk(KERN_ALERT "%s: BUG -- txdp out of range\n", ndev->name); 1471 dev->tx_idx = 0; 1472 } 1473 /* The may have been a race between a pci originated read 1474 * and the descriptor update from the cpu. Just in case, 1475 * kick the transmitter if the hardware thinks it is on a 1476 * different descriptor than we are. 1477 */ 1478 if (dev->tx_idx != dev->tx_free_idx) 1479 kick_tx(dev); 1480 } 1481 1482 /* Defer tx ring processing until more than a minimum amount of 1483 * work has accumulated 1484 */ 1485 if ((ISR_TXDESC | ISR_TXIDLE | ISR_TXOK | ISR_TXERR) & isr) { 1486 spin_lock_irqsave(&dev->tx_lock, flags); 1487 do_tx_done(ndev); 1488 spin_unlock_irqrestore(&dev->tx_lock, flags); 1489 1490 /* Disable TxOk if there are no outstanding tx packets. 1491 */ 1492 if ((dev->tx_done_idx == dev->tx_free_idx) && 1493 (dev->IMR_cache & ISR_TXOK)) { 1494 spin_lock_irqsave(&dev->misc_lock, flags); 1495 dev->IMR_cache &= ~ISR_TXOK; 1496 writel(dev->IMR_cache, dev->base + IMR); 1497 spin_unlock_irqrestore(&dev->misc_lock, flags); 1498 } 1499 } 1500 1501 /* The TxIdle interrupt can come in before the transmit has 1502 * completed. Normally we reap packets off of the combination 1503 * of TxDesc and TxIdle and leave TxOk disabled (since it 1504 * occurs on every packet), but when no further irqs of this 1505 * nature are expected, we must enable TxOk. 1506 */ 1507 if ((ISR_TXIDLE & isr) && (dev->tx_done_idx != dev->tx_free_idx)) { 1508 spin_lock_irqsave(&dev->misc_lock, flags); 1509 dev->IMR_cache |= ISR_TXOK; 1510 writel(dev->IMR_cache, dev->base + IMR); 1511 spin_unlock_irqrestore(&dev->misc_lock, flags); 1512 } 1513 1514 /* MIB interrupt: one of the statistics counters is about to overflow */ 1515 if (unlikely(ISR_MIB & isr)) 1516 ns83820_mib_isr(dev); 1517 1518 /* PHY: Link up/down/negotiation state change */ 1519 if (unlikely(ISR_PHY & isr)) 1520 phy_intr(ndev); 1521 1522 #if 0 /* Still working on the interrupt mitigation strategy */ 1523 if (dev->ihr) 1524 writel(dev->ihr, dev->base + IHR); 1525 #endif 1526 } 1527 1528 static void ns83820_do_reset(struct ns83820 *dev, u32 which) 1529 { 1530 Dprintk("resetting chip...\n"); 1531 writel(which, dev->base + CR); 1532 do { 1533 schedule(); 1534 } while (readl(dev->base + CR) & which); 1535 Dprintk("okay!\n"); 1536 } 1537 1538 static int ns83820_stop(struct net_device *ndev) 1539 { 1540 struct ns83820 *dev = PRIV(ndev); 1541 1542 /* FIXME: protect against interrupt handler? */ 1543 del_timer_sync(&dev->tx_watchdog); 1544 1545 ns83820_disable_interrupts(dev); 1546 1547 dev->rx_info.up = 0; 1548 synchronize_irq(dev->pci_dev->irq); 1549 1550 ns83820_do_reset(dev, CR_RST); 1551 1552 synchronize_irq(dev->pci_dev->irq); 1553 1554 spin_lock_irq(&dev->misc_lock); 1555 dev->IMR_cache &= ~(ISR_TXURN | ISR_TXIDLE | ISR_TXERR | ISR_TXDESC | ISR_TXOK); 1556 spin_unlock_irq(&dev->misc_lock); 1557 1558 ns83820_cleanup_rx(dev); 1559 ns83820_cleanup_tx(dev); 1560 1561 return 0; 1562 } 1563 1564 static void ns83820_tx_timeout(struct net_device *ndev) 1565 { 1566 struct ns83820 *dev = PRIV(ndev); 1567 u32 tx_done_idx; 1568 __le32 *desc; 1569 unsigned long flags; 1570 1571 spin_lock_irqsave(&dev->tx_lock, flags); 1572 1573 tx_done_idx = dev->tx_done_idx; 1574 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1575 1576 printk(KERN_INFO "%s: tx_timeout: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1577 ndev->name, 1578 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1579 1580 #if defined(DEBUG) 1581 { 1582 u32 isr; 1583 isr = readl(dev->base + ISR); 1584 printk("irq: %08x imr: %08x\n", isr, dev->IMR_cache); 1585 ns83820_do_isr(ndev, isr); 1586 } 1587 #endif 1588 1589 do_tx_done(ndev); 1590 1591 tx_done_idx = dev->tx_done_idx; 1592 desc = dev->tx_descs + (tx_done_idx * DESC_SIZE); 1593 1594 printk(KERN_INFO "%s: after: tx_done_idx=%d free_idx=%d cmdsts=%08x\n", 1595 ndev->name, 1596 tx_done_idx, dev->tx_free_idx, le32_to_cpu(desc[DESC_CMDSTS])); 1597 1598 spin_unlock_irqrestore(&dev->tx_lock, flags); 1599 } 1600 1601 static void ns83820_tx_watch(unsigned long data) 1602 { 1603 struct net_device *ndev = (void *)data; 1604 struct ns83820 *dev = PRIV(ndev); 1605 1606 #if defined(DEBUG) 1607 printk("ns83820_tx_watch: %u %u %d\n", 1608 dev->tx_done_idx, dev->tx_free_idx, atomic_read(&dev->nr_tx_skbs) 1609 ); 1610 #endif 1611 1612 if (time_after(jiffies, dev_trans_start(ndev) + 1*HZ) && 1613 dev->tx_done_idx != dev->tx_free_idx) { 1614 printk(KERN_DEBUG "%s: ns83820_tx_watch: %u %u %d\n", 1615 ndev->name, 1616 dev->tx_done_idx, dev->tx_free_idx, 1617 atomic_read(&dev->nr_tx_skbs)); 1618 ns83820_tx_timeout(ndev); 1619 } 1620 1621 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1622 } 1623 1624 static int ns83820_open(struct net_device *ndev) 1625 { 1626 struct ns83820 *dev = PRIV(ndev); 1627 unsigned i; 1628 u32 desc; 1629 int ret; 1630 1631 dprintk("ns83820_open\n"); 1632 1633 writel(0, dev->base + PQCR); 1634 1635 ret = ns83820_setup_rx(ndev); 1636 if (ret) 1637 goto failed; 1638 1639 memset(dev->tx_descs, 0, 4 * NR_TX_DESC * DESC_SIZE); 1640 for (i=0; i<NR_TX_DESC; i++) { 1641 dev->tx_descs[(i * DESC_SIZE) + DESC_LINK] 1642 = cpu_to_le32( 1643 dev->tx_phy_descs 1644 + ((i+1) % NR_TX_DESC) * DESC_SIZE * 4); 1645 } 1646 1647 dev->tx_idx = 0; 1648 dev->tx_done_idx = 0; 1649 desc = dev->tx_phy_descs; 1650 writel(0, dev->base + TXDP_HI); 1651 writel(desc, dev->base + TXDP); 1652 1653 init_timer(&dev->tx_watchdog); 1654 dev->tx_watchdog.data = (unsigned long)ndev; 1655 dev->tx_watchdog.function = ns83820_tx_watch; 1656 mod_timer(&dev->tx_watchdog, jiffies + 2*HZ); 1657 1658 netif_start_queue(ndev); /* FIXME: wait for phy to come up */ 1659 1660 return 0; 1661 1662 failed: 1663 ns83820_stop(ndev); 1664 return ret; 1665 } 1666 1667 static void ns83820_getmac(struct ns83820 *dev, u8 *mac) 1668 { 1669 unsigned i; 1670 for (i=0; i<3; i++) { 1671 u32 data; 1672 1673 /* Read from the perfect match memory: this is loaded by 1674 * the chip from the EEPROM via the EELOAD self test. 1675 */ 1676 writel(i*2, dev->base + RFCR); 1677 data = readl(dev->base + RFDR); 1678 1679 *mac++ = data; 1680 *mac++ = data >> 8; 1681 } 1682 } 1683 1684 static int ns83820_change_mtu(struct net_device *ndev, int new_mtu) 1685 { 1686 if (new_mtu > RX_BUF_SIZE) 1687 return -EINVAL; 1688 ndev->mtu = new_mtu; 1689 return 0; 1690 } 1691 1692 static void ns83820_set_multicast(struct net_device *ndev) 1693 { 1694 struct ns83820 *dev = PRIV(ndev); 1695 u8 __iomem *rfcr = dev->base + RFCR; 1696 u32 and_mask = 0xffffffff; 1697 u32 or_mask = 0; 1698 u32 val; 1699 1700 if (ndev->flags & IFF_PROMISC) 1701 or_mask |= RFCR_AAU | RFCR_AAM; 1702 else 1703 and_mask &= ~(RFCR_AAU | RFCR_AAM); 1704 1705 if (ndev->flags & IFF_ALLMULTI || netdev_mc_count(ndev)) 1706 or_mask |= RFCR_AAM; 1707 else 1708 and_mask &= ~RFCR_AAM; 1709 1710 spin_lock_irq(&dev->misc_lock); 1711 val = (readl(rfcr) & and_mask) | or_mask; 1712 /* Ramit : RFCR Write Fix doc says RFEN must be 0 modify other bits */ 1713 writel(val & ~RFCR_RFEN, rfcr); 1714 writel(val, rfcr); 1715 spin_unlock_irq(&dev->misc_lock); 1716 } 1717 1718 static void ns83820_run_bist(struct net_device *ndev, const char *name, u32 enable, u32 done, u32 fail) 1719 { 1720 struct ns83820 *dev = PRIV(ndev); 1721 int timed_out = 0; 1722 unsigned long start; 1723 u32 status; 1724 int loops = 0; 1725 1726 dprintk("%s: start %s\n", ndev->name, name); 1727 1728 start = jiffies; 1729 1730 writel(enable, dev->base + PTSCR); 1731 for (;;) { 1732 loops++; 1733 status = readl(dev->base + PTSCR); 1734 if (!(status & enable)) 1735 break; 1736 if (status & done) 1737 break; 1738 if (status & fail) 1739 break; 1740 if (time_after_eq(jiffies, start + HZ)) { 1741 timed_out = 1; 1742 break; 1743 } 1744 schedule_timeout_uninterruptible(1); 1745 } 1746 1747 if (status & fail) 1748 printk(KERN_INFO "%s: %s failed! (0x%08x & 0x%08x)\n", 1749 ndev->name, name, status, fail); 1750 else if (timed_out) 1751 printk(KERN_INFO "%s: run_bist %s timed out! (%08x)\n", 1752 ndev->name, name, status); 1753 1754 dprintk("%s: done %s in %d loops\n", ndev->name, name, loops); 1755 } 1756 1757 #ifdef PHY_CODE_IS_FINISHED 1758 static void ns83820_mii_write_bit(struct ns83820 *dev, int bit) 1759 { 1760 /* drive MDC low */ 1761 dev->MEAR_cache &= ~MEAR_MDC; 1762 writel(dev->MEAR_cache, dev->base + MEAR); 1763 readl(dev->base + MEAR); 1764 1765 /* enable output, set bit */ 1766 dev->MEAR_cache |= MEAR_MDDIR; 1767 if (bit) 1768 dev->MEAR_cache |= MEAR_MDIO; 1769 else 1770 dev->MEAR_cache &= ~MEAR_MDIO; 1771 1772 /* set the output bit */ 1773 writel(dev->MEAR_cache, dev->base + MEAR); 1774 readl(dev->base + MEAR); 1775 1776 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1777 udelay(1); 1778 1779 /* drive MDC high causing the data bit to be latched */ 1780 dev->MEAR_cache |= MEAR_MDC; 1781 writel(dev->MEAR_cache, dev->base + MEAR); 1782 readl(dev->base + MEAR); 1783 1784 /* Wait again... */ 1785 udelay(1); 1786 } 1787 1788 static int ns83820_mii_read_bit(struct ns83820 *dev) 1789 { 1790 int bit; 1791 1792 /* drive MDC low, disable output */ 1793 dev->MEAR_cache &= ~MEAR_MDC; 1794 dev->MEAR_cache &= ~MEAR_MDDIR; 1795 writel(dev->MEAR_cache, dev->base + MEAR); 1796 readl(dev->base + MEAR); 1797 1798 /* Wait. Max clock rate is 2.5MHz, this way we come in under 1MHz */ 1799 udelay(1); 1800 1801 /* drive MDC high causing the data bit to be latched */ 1802 bit = (readl(dev->base + MEAR) & MEAR_MDIO) ? 1 : 0; 1803 dev->MEAR_cache |= MEAR_MDC; 1804 writel(dev->MEAR_cache, dev->base + MEAR); 1805 1806 /* Wait again... */ 1807 udelay(1); 1808 1809 return bit; 1810 } 1811 1812 static unsigned ns83820_mii_read_reg(struct ns83820 *dev, unsigned phy, unsigned reg) 1813 { 1814 unsigned data = 0; 1815 int i; 1816 1817 /* read some garbage so that we eventually sync up */ 1818 for (i=0; i<64; i++) 1819 ns83820_mii_read_bit(dev); 1820 1821 ns83820_mii_write_bit(dev, 0); /* start */ 1822 ns83820_mii_write_bit(dev, 1); 1823 ns83820_mii_write_bit(dev, 1); /* opcode read */ 1824 ns83820_mii_write_bit(dev, 0); 1825 1826 /* write out the phy address: 5 bits, msb first */ 1827 for (i=0; i<5; i++) 1828 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1829 1830 /* write out the register address, 5 bits, msb first */ 1831 for (i=0; i<5; i++) 1832 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1833 1834 ns83820_mii_read_bit(dev); /* turn around cycles */ 1835 ns83820_mii_read_bit(dev); 1836 1837 /* read in the register data, 16 bits msb first */ 1838 for (i=0; i<16; i++) { 1839 data <<= 1; 1840 data |= ns83820_mii_read_bit(dev); 1841 } 1842 1843 return data; 1844 } 1845 1846 static unsigned ns83820_mii_write_reg(struct ns83820 *dev, unsigned phy, unsigned reg, unsigned data) 1847 { 1848 int i; 1849 1850 /* read some garbage so that we eventually sync up */ 1851 for (i=0; i<64; i++) 1852 ns83820_mii_read_bit(dev); 1853 1854 ns83820_mii_write_bit(dev, 0); /* start */ 1855 ns83820_mii_write_bit(dev, 1); 1856 ns83820_mii_write_bit(dev, 0); /* opcode read */ 1857 ns83820_mii_write_bit(dev, 1); 1858 1859 /* write out the phy address: 5 bits, msb first */ 1860 for (i=0; i<5; i++) 1861 ns83820_mii_write_bit(dev, phy & (0x10 >> i)); 1862 1863 /* write out the register address, 5 bits, msb first */ 1864 for (i=0; i<5; i++) 1865 ns83820_mii_write_bit(dev, reg & (0x10 >> i)); 1866 1867 ns83820_mii_read_bit(dev); /* turn around cycles */ 1868 ns83820_mii_read_bit(dev); 1869 1870 /* read in the register data, 16 bits msb first */ 1871 for (i=0; i<16; i++) 1872 ns83820_mii_write_bit(dev, (data >> (15 - i)) & 1); 1873 1874 return data; 1875 } 1876 1877 static void ns83820_probe_phy(struct net_device *ndev) 1878 { 1879 struct ns83820 *dev = PRIV(ndev); 1880 static int first; 1881 int i; 1882 #define MII_PHYIDR1 0x02 1883 #define MII_PHYIDR2 0x03 1884 1885 #if 0 1886 if (!first) { 1887 unsigned tmp; 1888 ns83820_mii_read_reg(dev, 1, 0x09); 1889 ns83820_mii_write_reg(dev, 1, 0x10, 0x0d3e); 1890 1891 tmp = ns83820_mii_read_reg(dev, 1, 0x00); 1892 ns83820_mii_write_reg(dev, 1, 0x00, tmp | 0x8000); 1893 udelay(1300); 1894 ns83820_mii_read_reg(dev, 1, 0x09); 1895 } 1896 #endif 1897 first = 1; 1898 1899 for (i=1; i<2; i++) { 1900 int j; 1901 unsigned a, b; 1902 a = ns83820_mii_read_reg(dev, i, MII_PHYIDR1); 1903 b = ns83820_mii_read_reg(dev, i, MII_PHYIDR2); 1904 1905 //printk("%s: phy %d: 0x%04x 0x%04x\n", 1906 // ndev->name, i, a, b); 1907 1908 for (j=0; j<0x16; j+=4) { 1909 dprintk("%s: [0x%02x] %04x %04x %04x %04x\n", 1910 ndev->name, j, 1911 ns83820_mii_read_reg(dev, i, 0 + j), 1912 ns83820_mii_read_reg(dev, i, 1 + j), 1913 ns83820_mii_read_reg(dev, i, 2 + j), 1914 ns83820_mii_read_reg(dev, i, 3 + j) 1915 ); 1916 } 1917 } 1918 { 1919 unsigned a, b; 1920 /* read firmware version: memory addr is 0x8402 and 0x8403 */ 1921 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1922 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1923 a = ns83820_mii_read_reg(dev, 1, 0x1d); 1924 1925 ns83820_mii_write_reg(dev, 1, 0x16, 0x000d); 1926 ns83820_mii_write_reg(dev, 1, 0x1e, 0x810e); 1927 b = ns83820_mii_read_reg(dev, 1, 0x1d); 1928 dprintk("version: 0x%04x 0x%04x\n", a, b); 1929 } 1930 } 1931 #endif 1932 1933 static const struct net_device_ops netdev_ops = { 1934 .ndo_open = ns83820_open, 1935 .ndo_stop = ns83820_stop, 1936 .ndo_start_xmit = ns83820_hard_start_xmit, 1937 .ndo_get_stats = ns83820_get_stats, 1938 .ndo_change_mtu = ns83820_change_mtu, 1939 .ndo_set_rx_mode = ns83820_set_multicast, 1940 .ndo_validate_addr = eth_validate_addr, 1941 .ndo_set_mac_address = eth_mac_addr, 1942 .ndo_tx_timeout = ns83820_tx_timeout, 1943 }; 1944 1945 static int __devinit ns83820_init_one(struct pci_dev *pci_dev, 1946 const struct pci_device_id *id) 1947 { 1948 struct net_device *ndev; 1949 struct ns83820 *dev; 1950 long addr; 1951 int err; 1952 int using_dac = 0; 1953 1954 /* See if we can set the dma mask early on; failure is fatal. */ 1955 if (sizeof(dma_addr_t) == 8 && 1956 !pci_set_dma_mask(pci_dev, DMA_BIT_MASK(64))) { 1957 using_dac = 1; 1958 } else if (!pci_set_dma_mask(pci_dev, DMA_BIT_MASK(32))) { 1959 using_dac = 0; 1960 } else { 1961 dev_warn(&pci_dev->dev, "pci_set_dma_mask failed!\n"); 1962 return -ENODEV; 1963 } 1964 1965 ndev = alloc_etherdev(sizeof(struct ns83820)); 1966 err = -ENOMEM; 1967 if (!ndev) 1968 goto out; 1969 1970 dev = PRIV(ndev); 1971 dev->ndev = ndev; 1972 1973 spin_lock_init(&dev->rx_info.lock); 1974 spin_lock_init(&dev->tx_lock); 1975 spin_lock_init(&dev->misc_lock); 1976 dev->pci_dev = pci_dev; 1977 1978 SET_NETDEV_DEV(ndev, &pci_dev->dev); 1979 1980 INIT_WORK(&dev->tq_refill, queue_refill); 1981 tasklet_init(&dev->rx_tasklet, rx_action, (unsigned long)ndev); 1982 1983 err = pci_enable_device(pci_dev); 1984 if (err) { 1985 dev_info(&pci_dev->dev, "pci_enable_dev failed: %d\n", err); 1986 goto out_free; 1987 } 1988 1989 pci_set_master(pci_dev); 1990 addr = pci_resource_start(pci_dev, 1); 1991 dev->base = ioremap_nocache(addr, PAGE_SIZE); 1992 dev->tx_descs = pci_alloc_consistent(pci_dev, 1993 4 * DESC_SIZE * NR_TX_DESC, &dev->tx_phy_descs); 1994 dev->rx_info.descs = pci_alloc_consistent(pci_dev, 1995 4 * DESC_SIZE * NR_RX_DESC, &dev->rx_info.phy_descs); 1996 err = -ENOMEM; 1997 if (!dev->base || !dev->tx_descs || !dev->rx_info.descs) 1998 goto out_disable; 1999 2000 dprintk("%p: %08lx %p: %08lx\n", 2001 dev->tx_descs, (long)dev->tx_phy_descs, 2002 dev->rx_info.descs, (long)dev->rx_info.phy_descs); 2003 2004 ns83820_disable_interrupts(dev); 2005 2006 dev->IMR_cache = 0; 2007 2008 err = request_irq(pci_dev->irq, ns83820_irq, IRQF_SHARED, 2009 DRV_NAME, ndev); 2010 if (err) { 2011 dev_info(&pci_dev->dev, "unable to register irq %d, err %d\n", 2012 pci_dev->irq, err); 2013 goto out_disable; 2014 } 2015 2016 /* 2017 * FIXME: we are holding rtnl_lock() over obscenely long area only 2018 * because some of the setup code uses dev->name. It's Wrong(tm) - 2019 * we should be using driver-specific names for all that stuff. 2020 * For now that will do, but we really need to come back and kill 2021 * most of the dev_alloc_name() users later. 2022 */ 2023 rtnl_lock(); 2024 err = dev_alloc_name(ndev, ndev->name); 2025 if (err < 0) { 2026 dev_info(&pci_dev->dev, "unable to get netdev name: %d\n", err); 2027 goto out_free_irq; 2028 } 2029 2030 printk("%s: ns83820.c: 0x22c: %08x, subsystem: %04x:%04x\n", 2031 ndev->name, le32_to_cpu(readl(dev->base + 0x22c)), 2032 pci_dev->subsystem_vendor, pci_dev->subsystem_device); 2033 2034 ndev->netdev_ops = &netdev_ops; 2035 SET_ETHTOOL_OPS(ndev, &ops); 2036 ndev->watchdog_timeo = 5 * HZ; 2037 pci_set_drvdata(pci_dev, ndev); 2038 2039 ns83820_do_reset(dev, CR_RST); 2040 2041 /* Must reset the ram bist before running it */ 2042 writel(PTSCR_RBIST_RST, dev->base + PTSCR); 2043 ns83820_run_bist(ndev, "sram bist", PTSCR_RBIST_EN, 2044 PTSCR_RBIST_DONE, PTSCR_RBIST_FAIL); 2045 ns83820_run_bist(ndev, "eeprom bist", PTSCR_EEBIST_EN, 0, 2046 PTSCR_EEBIST_FAIL); 2047 ns83820_run_bist(ndev, "eeprom load", PTSCR_EELOAD_EN, 0, 0); 2048 2049 /* I love config registers */ 2050 dev->CFG_cache = readl(dev->base + CFG); 2051 2052 if ((dev->CFG_cache & CFG_PCI64_DET)) { 2053 printk(KERN_INFO "%s: detected 64 bit PCI data bus.\n", 2054 ndev->name); 2055 /*dev->CFG_cache |= CFG_DATA64_EN;*/ 2056 if (!(dev->CFG_cache & CFG_DATA64_EN)) 2057 printk(KERN_INFO "%s: EEPROM did not enable 64 bit bus. Disabled.\n", 2058 ndev->name); 2059 } else 2060 dev->CFG_cache &= ~(CFG_DATA64_EN); 2061 2062 dev->CFG_cache &= (CFG_TBI_EN | CFG_MRM_DIS | CFG_MWI_DIS | 2063 CFG_T64ADDR | CFG_DATA64_EN | CFG_EXT_125 | 2064 CFG_M64ADDR); 2065 dev->CFG_cache |= CFG_PINT_DUPSTS | CFG_PINT_LNKSTS | CFG_PINT_SPDSTS | 2066 CFG_EXTSTS_EN | CFG_EXD | CFG_PESEL; 2067 dev->CFG_cache |= CFG_REQALG; 2068 dev->CFG_cache |= CFG_POW; 2069 dev->CFG_cache |= CFG_TMRTEST; 2070 2071 /* When compiled with 64 bit addressing, we must always enable 2072 * the 64 bit descriptor format. 2073 */ 2074 if (sizeof(dma_addr_t) == 8) 2075 dev->CFG_cache |= CFG_M64ADDR; 2076 if (using_dac) 2077 dev->CFG_cache |= CFG_T64ADDR; 2078 2079 /* Big endian mode does not seem to do what the docs suggest */ 2080 dev->CFG_cache &= ~CFG_BEM; 2081 2082 /* setup optical transceiver if we have one */ 2083 if (dev->CFG_cache & CFG_TBI_EN) { 2084 printk(KERN_INFO "%s: enabling optical transceiver\n", 2085 ndev->name); 2086 writel(readl(dev->base + GPIOR) | 0x3e8, dev->base + GPIOR); 2087 2088 /* setup auto negotiation feature advertisement */ 2089 writel(readl(dev->base + TANAR) 2090 | TANAR_HALF_DUP | TANAR_FULL_DUP, 2091 dev->base + TANAR); 2092 2093 /* start auto negotiation */ 2094 writel(TBICR_MR_AN_ENABLE | TBICR_MR_RESTART_AN, 2095 dev->base + TBICR); 2096 writel(TBICR_MR_AN_ENABLE, dev->base + TBICR); 2097 dev->linkstate = LINK_AUTONEGOTIATE; 2098 2099 dev->CFG_cache |= CFG_MODE_1000; 2100 } 2101 2102 writel(dev->CFG_cache, dev->base + CFG); 2103 dprintk("CFG: %08x\n", dev->CFG_cache); 2104 2105 if (reset_phy) { 2106 printk(KERN_INFO "%s: resetting phy\n", ndev->name); 2107 writel(dev->CFG_cache | CFG_PHY_RST, dev->base + CFG); 2108 msleep(10); 2109 writel(dev->CFG_cache, dev->base + CFG); 2110 } 2111 2112 #if 0 /* Huh? This sets the PCI latency register. Should be done via 2113 * the PCI layer. FIXME. 2114 */ 2115 if (readl(dev->base + SRR)) 2116 writel(readl(dev->base+0x20c) | 0xfe00, dev->base + 0x20c); 2117 #endif 2118 2119 /* Note! The DMA burst size interacts with packet 2120 * transmission, such that the largest packet that 2121 * can be transmitted is 8192 - FLTH - burst size. 2122 * If only the transmit fifo was larger... 2123 */ 2124 /* Ramit : 1024 DMA is not a good idea, it ends up banging 2125 * some DELL and COMPAQ SMP systems */ 2126 writel(TXCFG_CSI | TXCFG_HBI | TXCFG_ATP | TXCFG_MXDMA512 2127 | ((1600 / 32) * 0x100), 2128 dev->base + TXCFG); 2129 2130 /* Flush the interrupt holdoff timer */ 2131 writel(0x000, dev->base + IHR); 2132 writel(0x100, dev->base + IHR); 2133 writel(0x000, dev->base + IHR); 2134 2135 /* Set Rx to full duplex, don't accept runt, errored, long or length 2136 * range errored packets. Use 512 byte DMA. 2137 */ 2138 /* Ramit : 1024 DMA is not a good idea, it ends up banging 2139 * some DELL and COMPAQ SMP systems 2140 * Turn on ALP, only we are accpeting Jumbo Packets */ 2141 writel(RXCFG_AEP | RXCFG_ARP | RXCFG_AIRL | RXCFG_RX_FD 2142 | RXCFG_STRIPCRC 2143 //| RXCFG_ALP 2144 | (RXCFG_MXDMA512) | 0, dev->base + RXCFG); 2145 2146 /* Disable priority queueing */ 2147 writel(0, dev->base + PQCR); 2148 2149 /* Enable IP checksum validation and detetion of VLAN headers. 2150 * Note: do not set the reject options as at least the 0x102 2151 * revision of the chip does not properly accept IP fragments 2152 * at least for UDP. 2153 */ 2154 /* Ramit : Be sure to turn on RXCFG_ARP if VLAN's are enabled, since 2155 * the MAC it calculates the packetsize AFTER stripping the VLAN 2156 * header, and if a VLAN Tagged packet of 64 bytes is received (like 2157 * a ping with a VLAN header) then the card, strips the 4 byte VLAN 2158 * tag and then checks the packet size, so if RXCFG_ARP is not enabled, 2159 * it discrards it!. These guys...... 2160 * also turn on tag stripping if hardware acceleration is enabled 2161 */ 2162 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2163 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN|VRCR_VTREN) 2164 #else 2165 #define VRCR_INIT_VALUE (VRCR_IPEN|VRCR_VTDEN) 2166 #endif 2167 writel(VRCR_INIT_VALUE, dev->base + VRCR); 2168 2169 /* Enable per-packet TCP/UDP/IP checksumming 2170 * and per packet vlan tag insertion if 2171 * vlan hardware acceleration is enabled 2172 */ 2173 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2174 #define VTCR_INIT_VALUE (VTCR_PPCHK|VTCR_VPPTI) 2175 #else 2176 #define VTCR_INIT_VALUE VTCR_PPCHK 2177 #endif 2178 writel(VTCR_INIT_VALUE, dev->base + VTCR); 2179 2180 /* Ramit : Enable async and sync pause frames */ 2181 /* writel(0, dev->base + PCR); */ 2182 writel((PCR_PS_MCAST | PCR_PS_DA | PCR_PSEN | PCR_FFLO_4K | 2183 PCR_FFHI_8K | PCR_STLO_4 | PCR_STHI_8 | PCR_PAUSE_CNT), 2184 dev->base + PCR); 2185 2186 /* Disable Wake On Lan */ 2187 writel(0, dev->base + WCSR); 2188 2189 ns83820_getmac(dev, ndev->dev_addr); 2190 2191 /* Yes, we support dumb IP checksum on transmit */ 2192 ndev->features |= NETIF_F_SG; 2193 ndev->features |= NETIF_F_IP_CSUM; 2194 2195 #ifdef NS83820_VLAN_ACCEL_SUPPORT 2196 /* We also support hardware vlan acceleration */ 2197 ndev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX; 2198 #endif 2199 2200 if (using_dac) { 2201 printk(KERN_INFO "%s: using 64 bit addressing.\n", 2202 ndev->name); 2203 ndev->features |= NETIF_F_HIGHDMA; 2204 } 2205 2206 printk(KERN_INFO "%s: ns83820 v" VERSION ": DP83820 v%u.%u: %pM io=0x%08lx irq=%d f=%s\n", 2207 ndev->name, 2208 (unsigned)readl(dev->base + SRR) >> 8, 2209 (unsigned)readl(dev->base + SRR) & 0xff, 2210 ndev->dev_addr, addr, pci_dev->irq, 2211 (ndev->features & NETIF_F_HIGHDMA) ? "h,sg" : "sg" 2212 ); 2213 2214 #ifdef PHY_CODE_IS_FINISHED 2215 ns83820_probe_phy(ndev); 2216 #endif 2217 2218 err = register_netdevice(ndev); 2219 if (err) { 2220 printk(KERN_INFO "ns83820: unable to register netdev: %d\n", err); 2221 goto out_cleanup; 2222 } 2223 rtnl_unlock(); 2224 2225 return 0; 2226 2227 out_cleanup: 2228 ns83820_disable_interrupts(dev); /* paranoia */ 2229 out_free_irq: 2230 rtnl_unlock(); 2231 free_irq(pci_dev->irq, ndev); 2232 out_disable: 2233 if (dev->base) 2234 iounmap(dev->base); 2235 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_TX_DESC, dev->tx_descs, dev->tx_phy_descs); 2236 pci_free_consistent(pci_dev, 4 * DESC_SIZE * NR_RX_DESC, dev->rx_info.descs, dev->rx_info.phy_descs); 2237 pci_disable_device(pci_dev); 2238 out_free: 2239 free_netdev(ndev); 2240 pci_set_drvdata(pci_dev, NULL); 2241 out: 2242 return err; 2243 } 2244 2245 static void __devexit ns83820_remove_one(struct pci_dev *pci_dev) 2246 { 2247 struct net_device *ndev = pci_get_drvdata(pci_dev); 2248 struct ns83820 *dev = PRIV(ndev); /* ok even if NULL */ 2249 2250 if (!ndev) /* paranoia */ 2251 return; 2252 2253 ns83820_disable_interrupts(dev); /* paranoia */ 2254 2255 unregister_netdev(ndev); 2256 free_irq(dev->pci_dev->irq, ndev); 2257 iounmap(dev->base); 2258 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_TX_DESC, 2259 dev->tx_descs, dev->tx_phy_descs); 2260 pci_free_consistent(dev->pci_dev, 4 * DESC_SIZE * NR_RX_DESC, 2261 dev->rx_info.descs, dev->rx_info.phy_descs); 2262 pci_disable_device(dev->pci_dev); 2263 free_netdev(ndev); 2264 pci_set_drvdata(pci_dev, NULL); 2265 } 2266 2267 static DEFINE_PCI_DEVICE_TABLE(ns83820_pci_tbl) = { 2268 { 0x100b, 0x0022, PCI_ANY_ID, PCI_ANY_ID, 0, .driver_data = 0, }, 2269 { 0, }, 2270 }; 2271 2272 static struct pci_driver driver = { 2273 .name = "ns83820", 2274 .id_table = ns83820_pci_tbl, 2275 .probe = ns83820_init_one, 2276 .remove = __devexit_p(ns83820_remove_one), 2277 #if 0 /* FIXME: implement */ 2278 .suspend = , 2279 .resume = , 2280 #endif 2281 }; 2282 2283 2284 static int __init ns83820_init(void) 2285 { 2286 printk(KERN_INFO "ns83820.c: National Semiconductor DP83820 10/100/1000 driver.\n"); 2287 return pci_register_driver(&driver); 2288 } 2289 2290 static void __exit ns83820_exit(void) 2291 { 2292 pci_unregister_driver(&driver); 2293 } 2294 2295 MODULE_AUTHOR("Benjamin LaHaise <bcrl@kvack.org>"); 2296 MODULE_DESCRIPTION("National Semiconductor DP83820 10/100/1000 driver"); 2297 MODULE_LICENSE("GPL"); 2298 2299 MODULE_DEVICE_TABLE(pci, ns83820_pci_tbl); 2300 2301 module_param(lnksts, int, 0); 2302 MODULE_PARM_DESC(lnksts, "Polarity of LNKSTS bit"); 2303 2304 module_param(ihr, int, 0); 2305 MODULE_PARM_DESC(ihr, "Time in 100 us increments to delay interrupts (range 0-127)"); 2306 2307 module_param(reset_phy, int, 0); 2308 MODULE_PARM_DESC(reset_phy, "Set to 1 to reset the PHY on startup"); 2309 2310 module_init(ns83820_init); 2311 module_exit(ns83820_exit); 2312