1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */ 2 /* 3 Written/copyright 1999-2001 by Donald Becker. 4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com) 5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com) 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org> 7 8 This software may be used and distributed according to the terms of 9 the GNU General Public License (GPL), incorporated herein by reference. 10 Drivers based on or derived from this code fall under the GPL and must 11 retain the authorship, copyright and license notice. This file is not 12 a complete program and may only be used when the entire operating 13 system is licensed under the GPL. License for under other terms may be 14 available. Contact the original author for details. 15 16 The original author may be reached as becker@scyld.com, or at 17 Scyld Computing Corporation 18 410 Severn Ave., Suite 210 19 Annapolis MD 21403 20 21 Support information and updates available at 22 http://www.scyld.com/network/netsemi.html 23 [link no longer provides useful info -jgarzik] 24 25 26 TODO: 27 * big endian support with CFG:BEM instead of cpu_to_le32 28 */ 29 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/string.h> 33 #include <linux/timer.h> 34 #include <linux/errno.h> 35 #include <linux/ioport.h> 36 #include <linux/slab.h> 37 #include <linux/interrupt.h> 38 #include <linux/pci.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 #include <linux/skbuff.h> 42 #include <linux/init.h> 43 #include <linux/spinlock.h> 44 #include <linux/ethtool.h> 45 #include <linux/delay.h> 46 #include <linux/rtnetlink.h> 47 #include <linux/mii.h> 48 #include <linux/crc32.h> 49 #include <linux/bitops.h> 50 #include <linux/prefetch.h> 51 #include <asm/processor.h> /* Processor type for cache alignment. */ 52 #include <asm/io.h> 53 #include <asm/irq.h> 54 #include <asm/uaccess.h> 55 56 #define DRV_NAME "natsemi" 57 #define DRV_VERSION "2.1" 58 #define DRV_RELDATE "Sept 11, 2006" 59 60 #define RX_OFFSET 2 61 62 /* Updated to recommendations in pci-skeleton v2.03. */ 63 64 /* The user-configurable values. 65 These may be modified when a driver module is loaded.*/ 66 67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \ 68 NETIF_MSG_LINK | \ 69 NETIF_MSG_WOL | \ 70 NETIF_MSG_RX_ERR | \ 71 NETIF_MSG_TX_ERR) 72 static int debug = -1; 73 74 static int mtu; 75 76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 77 This chip uses a 512 element hash table based on the Ethernet CRC. */ 78 static const int multicast_filter_limit = 100; 79 80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. 81 Setting to > 1518 effectively disables this feature. */ 82 static int rx_copybreak; 83 84 static int dspcfg_workaround = 1; 85 86 /* Used to pass the media type, etc. 87 Both 'options[]' and 'full_duplex[]' should exist for driver 88 interoperability. 89 The media type is usually passed in 'options[]'. 90 */ 91 #define MAX_UNITS 8 /* More are supported, limit only on options */ 92 static int options[MAX_UNITS]; 93 static int full_duplex[MAX_UNITS]; 94 95 /* Operational parameters that are set at compile time. */ 96 97 /* Keep the ring sizes a power of two for compile efficiency. 98 The compiler will convert <unsigned>'%'<2^N> into a bit mask. 99 Making the Tx ring too large decreases the effectiveness of channel 100 bonding and packet priority. 101 There are no ill effects from too-large receive rings. */ 102 #define TX_RING_SIZE 16 103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */ 104 #define RX_RING_SIZE 32 105 106 /* Operational parameters that usually are not changed. */ 107 /* Time in jiffies before concluding the transmitter is hung. */ 108 #define TX_TIMEOUT (2*HZ) 109 110 #define NATSEMI_HW_TIMEOUT 400 111 #define NATSEMI_TIMER_FREQ 5*HZ 112 #define NATSEMI_PG0_NREGS 64 113 #define NATSEMI_RFDR_NREGS 8 114 #define NATSEMI_PG1_NREGS 4 115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \ 116 NATSEMI_PG1_NREGS) 117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */ 118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) 119 120 /* Buffer sizes: 121 * The nic writes 32-bit values, even if the upper bytes of 122 * a 32-bit value are beyond the end of the buffer. 123 */ 124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */ 125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */ 126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */ 127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ 128 129 /* These identify the driver base version and may not be removed. */ 130 static const char version[] = 131 KERN_INFO DRV_NAME " dp8381x driver, version " 132 DRV_VERSION ", " DRV_RELDATE "\n" 133 " originally by Donald Becker <becker@scyld.com>\n" 134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n"; 135 136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver"); 138 MODULE_LICENSE("GPL"); 139 140 module_param(mtu, int, 0); 141 module_param(debug, int, 0); 142 module_param(rx_copybreak, int, 0); 143 module_param(dspcfg_workaround, int, 0); 144 module_param_array(options, int, NULL, 0); 145 module_param_array(full_duplex, int, NULL, 0); 146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)"); 147 MODULE_PARM_DESC(debug, "DP8381x default debug level"); 148 MODULE_PARM_DESC(rx_copybreak, 149 "DP8381x copy breakpoint for copy-only-tiny-frames"); 150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround"); 151 MODULE_PARM_DESC(options, 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex"); 153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)"); 154 155 /* 156 Theory of Operation 157 158 I. Board Compatibility 159 160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC. 161 It also works with other chips in in the DP83810 series. 162 163 II. Board-specific settings 164 165 This driver requires the PCI interrupt line to be valid. 166 It honors the EEPROM-set values. 167 168 III. Driver operation 169 170 IIIa. Ring buffers 171 172 This driver uses two statically allocated fixed-size descriptor lists 173 formed into rings by a branch from the final descriptor to the beginning of 174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 175 The NatSemi design uses a 'next descriptor' pointer that the driver forms 176 into a list. 177 178 IIIb/c. Transmit/Receive Structure 179 180 This driver uses a zero-copy receive and transmit scheme. 181 The driver allocates full frame size skbuffs for the Rx ring buffers at 182 open() time and passes the skb->data field to the chip as receive data 183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 184 a fresh skbuff is allocated and the frame is copied to the new skbuff. 185 When the incoming frame is larger, the skbuff is passed directly up the 186 protocol stack. Buffers consumed this way are replaced by newly allocated 187 skbuffs in a later phase of receives. 188 189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by 190 using a full-sized skbuff for small frames vs. the copying costs of larger 191 frames. New boards are typically used in generously configured machines 192 and the underfilled buffers have negligible impact compared to the benefit of 193 a single allocation size, so the default value of zero results in never 194 copying packets. When copying is done, the cost is usually mitigated by using 195 a combined copy/checksum routine. Copying also preloads the cache, which is 196 most useful with small frames. 197 198 A subtle aspect of the operation is that unaligned buffers are not permitted 199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't 200 longword aligned for further processing. On copies frames are put into the 201 skbuff at an offset of "+2", 16-byte aligning the IP header. 202 203 IIId. Synchronization 204 205 Most operations are synchronized on the np->lock irq spinlock, except the 206 receive and transmit paths which are synchronised using a combination of 207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. 208 209 IVb. References 210 211 http://www.scyld.com/expert/100mbps.html 212 http://www.scyld.com/expert/NWay.html 213 Datasheet is available from: 214 http://www.national.com/pf/DP/DP83815.html 215 216 IVc. Errata 217 218 None characterised. 219 */ 220 221 222 223 /* 224 * Support for fibre connections on Am79C874: 225 * This phy needs a special setup when connected to a fibre cable. 226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf 227 */ 228 #define PHYID_AM79C874 0x0022561b 229 230 enum { 231 MII_MCTRL = 0x15, /* mode control register */ 232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */ 233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */ 234 }; 235 236 enum { 237 NATSEMI_FLAG_IGNORE_PHY = 0x1, 238 }; 239 240 /* array of board data directly indexed by pci_tbl[x].driver_data */ 241 static struct { 242 const char *name; 243 unsigned long flags; 244 unsigned int eeprom_size; 245 } natsemi_pci_info[] = { 246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 }, 247 { "NatSemi DP8381[56]", 0, 24 }, 248 }; 249 250 static DEFINE_PCI_DEVICE_TABLE(natsemi_pci_tbl) = { 251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 }, 252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, 253 { } /* terminate list */ 254 }; 255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl); 256 257 /* Offsets to the device registers. 258 Unlike software-only systems, device drivers interact with complex hardware. 259 It's not useful to define symbolic names for every register bit in the 260 device. 261 */ 262 enum register_offsets { 263 ChipCmd = 0x00, 264 ChipConfig = 0x04, 265 EECtrl = 0x08, 266 PCIBusCfg = 0x0C, 267 IntrStatus = 0x10, 268 IntrMask = 0x14, 269 IntrEnable = 0x18, 270 IntrHoldoff = 0x1C, /* DP83816 only */ 271 TxRingPtr = 0x20, 272 TxConfig = 0x24, 273 RxRingPtr = 0x30, 274 RxConfig = 0x34, 275 ClkRun = 0x3C, 276 WOLCmd = 0x40, 277 PauseCmd = 0x44, 278 RxFilterAddr = 0x48, 279 RxFilterData = 0x4C, 280 BootRomAddr = 0x50, 281 BootRomData = 0x54, 282 SiliconRev = 0x58, 283 StatsCtrl = 0x5C, 284 StatsData = 0x60, 285 RxPktErrs = 0x60, 286 RxMissed = 0x68, 287 RxCRCErrs = 0x64, 288 BasicControl = 0x80, 289 BasicStatus = 0x84, 290 AnegAdv = 0x90, 291 AnegPeer = 0x94, 292 PhyStatus = 0xC0, 293 MIntrCtrl = 0xC4, 294 MIntrStatus = 0xC8, 295 PhyCtrl = 0xE4, 296 297 /* These are from the spec, around page 78... on a separate table. 298 * The meaning of these registers depend on the value of PGSEL. */ 299 PGSEL = 0xCC, 300 PMDCSR = 0xE4, 301 TSTDAT = 0xFC, 302 DSPCFG = 0xF4, 303 SDCFG = 0xF8 304 }; 305 /* the values for the 'magic' registers above (PGSEL=1) */ 306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ 307 #define TSTDAT_VAL 0x0 308 #define DSPCFG_VAL 0x5040 309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ 310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ 311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ 312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ 313 314 /* misc PCI space registers */ 315 enum pci_register_offsets { 316 PCIPM = 0x44, 317 }; 318 319 enum ChipCmd_bits { 320 ChipReset = 0x100, 321 RxReset = 0x20, 322 TxReset = 0x10, 323 RxOff = 0x08, 324 RxOn = 0x04, 325 TxOff = 0x02, 326 TxOn = 0x01, 327 }; 328 329 enum ChipConfig_bits { 330 CfgPhyDis = 0x200, 331 CfgPhyRst = 0x400, 332 CfgExtPhy = 0x1000, 333 CfgAnegEnable = 0x2000, 334 CfgAneg100 = 0x4000, 335 CfgAnegFull = 0x8000, 336 CfgAnegDone = 0x8000000, 337 CfgFullDuplex = 0x20000000, 338 CfgSpeed100 = 0x40000000, 339 CfgLink = 0x80000000, 340 }; 341 342 enum EECtrl_bits { 343 EE_ShiftClk = 0x04, 344 EE_DataIn = 0x01, 345 EE_ChipSelect = 0x08, 346 EE_DataOut = 0x02, 347 MII_Data = 0x10, 348 MII_Write = 0x20, 349 MII_ShiftClk = 0x40, 350 }; 351 352 enum PCIBusCfg_bits { 353 EepromReload = 0x4, 354 }; 355 356 /* Bits in the interrupt status/mask registers. */ 357 enum IntrStatus_bits { 358 IntrRxDone = 0x0001, 359 IntrRxIntr = 0x0002, 360 IntrRxErr = 0x0004, 361 IntrRxEarly = 0x0008, 362 IntrRxIdle = 0x0010, 363 IntrRxOverrun = 0x0020, 364 IntrTxDone = 0x0040, 365 IntrTxIntr = 0x0080, 366 IntrTxErr = 0x0100, 367 IntrTxIdle = 0x0200, 368 IntrTxUnderrun = 0x0400, 369 StatsMax = 0x0800, 370 SWInt = 0x1000, 371 WOLPkt = 0x2000, 372 LinkChange = 0x4000, 373 IntrHighBits = 0x8000, 374 RxStatusFIFOOver = 0x10000, 375 IntrPCIErr = 0xf00000, 376 RxResetDone = 0x1000000, 377 TxResetDone = 0x2000000, 378 IntrAbnormalSummary = 0xCD20, 379 }; 380 381 /* 382 * Default Interrupts: 383 * Rx OK, Rx Packet Error, Rx Overrun, 384 * Tx OK, Tx Packet Error, Tx Underrun, 385 * MIB Service, Phy Interrupt, High Bits, 386 * Rx Status FIFO overrun, 387 * Received Target Abort, Received Master Abort, 388 * Signalled System Error, Received Parity Error 389 */ 390 #define DEFAULT_INTR 0x00f1cd65 391 392 enum TxConfig_bits { 393 TxDrthMask = 0x3f, 394 TxFlthMask = 0x3f00, 395 TxMxdmaMask = 0x700000, 396 TxMxdma_512 = 0x0, 397 TxMxdma_4 = 0x100000, 398 TxMxdma_8 = 0x200000, 399 TxMxdma_16 = 0x300000, 400 TxMxdma_32 = 0x400000, 401 TxMxdma_64 = 0x500000, 402 TxMxdma_128 = 0x600000, 403 TxMxdma_256 = 0x700000, 404 TxCollRetry = 0x800000, 405 TxAutoPad = 0x10000000, 406 TxMacLoop = 0x20000000, 407 TxHeartIgn = 0x40000000, 408 TxCarrierIgn = 0x80000000 409 }; 410 411 /* 412 * Tx Configuration: 413 * - 256 byte DMA burst length 414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free) 415 * - 64 bytes initial drain threshold (i.e. begin actual transmission 416 * when 64 byte are in the fifo) 417 * - on tx underruns, increase drain threshold by 64. 418 * - at most use a drain threshold of 1472 bytes: The sum of the fill 419 * threshold and the drain threshold must be less than 2016 bytes. 420 * 421 */ 422 #define TX_FLTH_VAL ((512/32) << 8) 423 #define TX_DRTH_VAL_START (64/32) 424 #define TX_DRTH_VAL_INC 2 425 #define TX_DRTH_VAL_LIMIT (1472/32) 426 427 enum RxConfig_bits { 428 RxDrthMask = 0x3e, 429 RxMxdmaMask = 0x700000, 430 RxMxdma_512 = 0x0, 431 RxMxdma_4 = 0x100000, 432 RxMxdma_8 = 0x200000, 433 RxMxdma_16 = 0x300000, 434 RxMxdma_32 = 0x400000, 435 RxMxdma_64 = 0x500000, 436 RxMxdma_128 = 0x600000, 437 RxMxdma_256 = 0x700000, 438 RxAcceptLong = 0x8000000, 439 RxAcceptTx = 0x10000000, 440 RxAcceptRunt = 0x40000000, 441 RxAcceptErr = 0x80000000 442 }; 443 #define RX_DRTH_VAL (128/8) 444 445 enum ClkRun_bits { 446 PMEEnable = 0x100, 447 PMEStatus = 0x8000, 448 }; 449 450 enum WolCmd_bits { 451 WakePhy = 0x1, 452 WakeUnicast = 0x2, 453 WakeMulticast = 0x4, 454 WakeBroadcast = 0x8, 455 WakeArp = 0x10, 456 WakePMatch0 = 0x20, 457 WakePMatch1 = 0x40, 458 WakePMatch2 = 0x80, 459 WakePMatch3 = 0x100, 460 WakeMagic = 0x200, 461 WakeMagicSecure = 0x400, 462 SecureHack = 0x100000, 463 WokePhy = 0x400000, 464 WokeUnicast = 0x800000, 465 WokeMulticast = 0x1000000, 466 WokeBroadcast = 0x2000000, 467 WokeArp = 0x4000000, 468 WokePMatch0 = 0x8000000, 469 WokePMatch1 = 0x10000000, 470 WokePMatch2 = 0x20000000, 471 WokePMatch3 = 0x40000000, 472 WokeMagic = 0x80000000, 473 WakeOptsSummary = 0x7ff 474 }; 475 476 enum RxFilterAddr_bits { 477 RFCRAddressMask = 0x3ff, 478 AcceptMulticast = 0x00200000, 479 AcceptMyPhys = 0x08000000, 480 AcceptAllPhys = 0x10000000, 481 AcceptAllMulticast = 0x20000000, 482 AcceptBroadcast = 0x40000000, 483 RxFilterEnable = 0x80000000 484 }; 485 486 enum StatsCtrl_bits { 487 StatsWarn = 0x1, 488 StatsFreeze = 0x2, 489 StatsClear = 0x4, 490 StatsStrobe = 0x8, 491 }; 492 493 enum MIntrCtrl_bits { 494 MICRIntEn = 0x2, 495 }; 496 497 enum PhyCtrl_bits { 498 PhyAddrMask = 0x1f, 499 }; 500 501 #define PHY_ADDR_NONE 32 502 #define PHY_ADDR_INTERNAL 1 503 504 /* values we might find in the silicon revision register */ 505 #define SRR_DP83815_C 0x0302 506 #define SRR_DP83815_D 0x0403 507 #define SRR_DP83816_A4 0x0504 508 #define SRR_DP83816_A5 0x0505 509 510 /* The Rx and Tx buffer descriptors. */ 511 /* Note that using only 32 bit fields simplifies conversion to big-endian 512 architectures. */ 513 struct netdev_desc { 514 __le32 next_desc; 515 __le32 cmd_status; 516 __le32 addr; 517 __le32 software_use; 518 }; 519 520 /* Bits in network_desc.status */ 521 enum desc_status_bits { 522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000, 523 DescNoCRC=0x10000000, DescPktOK=0x08000000, 524 DescSizeMask=0xfff, 525 526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000, 527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000, 528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000, 529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000, 530 531 DescRxAbort=0x04000000, DescRxOver=0x02000000, 532 DescRxDest=0x01800000, DescRxLong=0x00400000, 533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000, 534 DescRxCRC=0x00080000, DescRxAlign=0x00040000, 535 DescRxLoop=0x00020000, DesRxColl=0x00010000, 536 }; 537 538 struct netdev_private { 539 /* Descriptor rings first for alignment */ 540 dma_addr_t ring_dma; 541 struct netdev_desc *rx_ring; 542 struct netdev_desc *tx_ring; 543 /* The addresses of receive-in-place skbuffs */ 544 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 545 dma_addr_t rx_dma[RX_RING_SIZE]; 546 /* address of a sent-in-place packet/buffer, for later free() */ 547 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 548 dma_addr_t tx_dma[TX_RING_SIZE]; 549 struct net_device *dev; 550 void __iomem *ioaddr; 551 struct napi_struct napi; 552 /* Media monitoring timer */ 553 struct timer_list timer; 554 /* Frequently used values: keep some adjacent for cache effect */ 555 struct pci_dev *pci_dev; 556 struct netdev_desc *rx_head_desc; 557 /* Producer/consumer ring indices */ 558 unsigned int cur_rx, dirty_rx; 559 unsigned int cur_tx, dirty_tx; 560 /* Based on MTU+slack. */ 561 unsigned int rx_buf_sz; 562 int oom; 563 /* Interrupt status */ 564 u32 intr_status; 565 /* Do not touch the nic registers */ 566 int hands_off; 567 /* Don't pay attention to the reported link state. */ 568 int ignore_phy; 569 /* external phy that is used: only valid if dev->if_port != PORT_TP */ 570 int mii; 571 int phy_addr_external; 572 unsigned int full_duplex; 573 /* Rx filter */ 574 u32 cur_rx_mode; 575 u32 rx_filter[16]; 576 /* FIFO and PCI burst thresholds */ 577 u32 tx_config, rx_config; 578 /* original contents of ClkRun register */ 579 u32 SavedClkRun; 580 /* silicon revision */ 581 u32 srr; 582 /* expected DSPCFG value */ 583 u16 dspcfg; 584 int dspcfg_workaround; 585 /* parms saved in ethtool format */ 586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 587 u8 duplex; /* Duplex, half or full */ 588 u8 autoneg; /* Autonegotiation enabled */ 589 /* MII transceiver section */ 590 u16 advertising; 591 unsigned int iosize; 592 spinlock_t lock; 593 u32 msg_enable; 594 /* EEPROM data */ 595 int eeprom_size; 596 }; 597 598 static void move_int_phy(struct net_device *dev, int addr); 599 static int eeprom_read(void __iomem *ioaddr, int location); 600 static int mdio_read(struct net_device *dev, int reg); 601 static void mdio_write(struct net_device *dev, int reg, u16 data); 602 static void init_phy_fixup(struct net_device *dev); 603 static int miiport_read(struct net_device *dev, int phy_id, int reg); 604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); 605 static int find_mii(struct net_device *dev); 606 static void natsemi_reset(struct net_device *dev); 607 static void natsemi_reload_eeprom(struct net_device *dev); 608 static void natsemi_stop_rxtx(struct net_device *dev); 609 static int netdev_open(struct net_device *dev); 610 static void do_cable_magic(struct net_device *dev); 611 static void undo_cable_magic(struct net_device *dev); 612 static void check_link(struct net_device *dev); 613 static void netdev_timer(unsigned long data); 614 static void dump_ring(struct net_device *dev); 615 static void ns_tx_timeout(struct net_device *dev); 616 static int alloc_ring(struct net_device *dev); 617 static void refill_rx(struct net_device *dev); 618 static void init_ring(struct net_device *dev); 619 static void drain_tx(struct net_device *dev); 620 static void drain_ring(struct net_device *dev); 621 static void free_ring(struct net_device *dev); 622 static void reinit_ring(struct net_device *dev); 623 static void init_registers(struct net_device *dev); 624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 625 static irqreturn_t intr_handler(int irq, void *dev_instance); 626 static void netdev_error(struct net_device *dev, int intr_status); 627 static int natsemi_poll(struct napi_struct *napi, int budget); 628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do); 629 static void netdev_tx_done(struct net_device *dev); 630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu); 631 #ifdef CONFIG_NET_POLL_CONTROLLER 632 static void natsemi_poll_controller(struct net_device *dev); 633 #endif 634 static void __set_rx_mode(struct net_device *dev); 635 static void set_rx_mode(struct net_device *dev); 636 static void __get_stats(struct net_device *dev); 637 static struct net_device_stats *get_stats(struct net_device *dev); 638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 639 static int netdev_set_wol(struct net_device *dev, u32 newval); 640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur); 641 static int netdev_set_sopass(struct net_device *dev, u8 *newval); 642 static int netdev_get_sopass(struct net_device *dev, u8 *data); 643 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); 644 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd); 645 static void enable_wol_mode(struct net_device *dev, int enable_intr); 646 static int netdev_close(struct net_device *dev); 647 static int netdev_get_regs(struct net_device *dev, u8 *buf); 648 static int netdev_get_eeprom(struct net_device *dev, u8 *buf); 649 static const struct ethtool_ops ethtool_ops; 650 651 #define NATSEMI_ATTR(_name) \ 652 static ssize_t natsemi_show_##_name(struct device *dev, \ 653 struct device_attribute *attr, char *buf); \ 654 static ssize_t natsemi_set_##_name(struct device *dev, \ 655 struct device_attribute *attr, \ 656 const char *buf, size_t count); \ 657 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name) 658 659 #define NATSEMI_CREATE_FILE(_dev, _name) \ 660 device_create_file(&_dev->dev, &dev_attr_##_name) 661 #define NATSEMI_REMOVE_FILE(_dev, _name) \ 662 device_remove_file(&_dev->dev, &dev_attr_##_name) 663 664 NATSEMI_ATTR(dspcfg_workaround); 665 666 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, 667 struct device_attribute *attr, 668 char *buf) 669 { 670 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 671 672 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off"); 673 } 674 675 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev, 676 struct device_attribute *attr, 677 const char *buf, size_t count) 678 { 679 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 680 int new_setting; 681 unsigned long flags; 682 683 /* Find out the new setting */ 684 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1)) 685 new_setting = 1; 686 else if (!strncmp("off", buf, count - 1) || 687 !strncmp("0", buf, count - 1)) 688 new_setting = 0; 689 else 690 return count; 691 692 spin_lock_irqsave(&np->lock, flags); 693 694 np->dspcfg_workaround = new_setting; 695 696 spin_unlock_irqrestore(&np->lock, flags); 697 698 return count; 699 } 700 701 static inline void __iomem *ns_ioaddr(struct net_device *dev) 702 { 703 struct netdev_private *np = netdev_priv(dev); 704 705 return np->ioaddr; 706 } 707 708 static inline void natsemi_irq_enable(struct net_device *dev) 709 { 710 writel(1, ns_ioaddr(dev) + IntrEnable); 711 readl(ns_ioaddr(dev) + IntrEnable); 712 } 713 714 static inline void natsemi_irq_disable(struct net_device *dev) 715 { 716 writel(0, ns_ioaddr(dev) + IntrEnable); 717 readl(ns_ioaddr(dev) + IntrEnable); 718 } 719 720 static void move_int_phy(struct net_device *dev, int addr) 721 { 722 struct netdev_private *np = netdev_priv(dev); 723 void __iomem *ioaddr = ns_ioaddr(dev); 724 int target = 31; 725 726 /* 727 * The internal phy is visible on the external mii bus. Therefore we must 728 * move it away before we can send commands to an external phy. 729 * There are two addresses we must avoid: 730 * - the address on the external phy that is used for transmission. 731 * - the address that we want to access. User space can access phys 732 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the 733 * phy that is used for transmission. 734 */ 735 736 if (target == addr) 737 target--; 738 if (target == np->phy_addr_external) 739 target--; 740 writew(target, ioaddr + PhyCtrl); 741 readw(ioaddr + PhyCtrl); 742 udelay(1); 743 } 744 745 static void natsemi_init_media(struct net_device *dev) 746 { 747 struct netdev_private *np = netdev_priv(dev); 748 u32 tmp; 749 750 if (np->ignore_phy) 751 netif_carrier_on(dev); 752 else 753 netif_carrier_off(dev); 754 755 /* get the initial settings from hardware */ 756 tmp = mdio_read(dev, MII_BMCR); 757 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10; 758 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF; 759 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE; 760 np->advertising= mdio_read(dev, MII_ADVERTISE); 761 762 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL && 763 netif_msg_probe(np)) { 764 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s " 765 "10%s %s duplex.\n", 766 pci_name(np->pci_dev), 767 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)? 768 "enabled, advertise" : "disabled, force", 769 (np->advertising & 770 (ADVERTISE_100FULL|ADVERTISE_100HALF))? 771 "0" : "", 772 (np->advertising & 773 (ADVERTISE_100FULL|ADVERTISE_10FULL))? 774 "full" : "half"); 775 } 776 if (netif_msg_probe(np)) 777 printk(KERN_INFO 778 "natsemi %s: Transceiver status %#04x advertising %#04x.\n", 779 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR), 780 np->advertising); 781 782 } 783 784 static const struct net_device_ops natsemi_netdev_ops = { 785 .ndo_open = netdev_open, 786 .ndo_stop = netdev_close, 787 .ndo_start_xmit = start_tx, 788 .ndo_get_stats = get_stats, 789 .ndo_set_rx_mode = set_rx_mode, 790 .ndo_change_mtu = natsemi_change_mtu, 791 .ndo_do_ioctl = netdev_ioctl, 792 .ndo_tx_timeout = ns_tx_timeout, 793 .ndo_set_mac_address = eth_mac_addr, 794 .ndo_validate_addr = eth_validate_addr, 795 #ifdef CONFIG_NET_POLL_CONTROLLER 796 .ndo_poll_controller = natsemi_poll_controller, 797 #endif 798 }; 799 800 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent) 801 { 802 struct net_device *dev; 803 struct netdev_private *np; 804 int i, option, irq, chip_idx = ent->driver_data; 805 static int find_cnt = -1; 806 resource_size_t iostart; 807 unsigned long iosize; 808 void __iomem *ioaddr; 809 const int pcibar = 1; /* PCI base address register */ 810 int prev_eedata; 811 u32 tmp; 812 813 /* when built into the kernel, we only print version if device is found */ 814 #ifndef MODULE 815 static int printed_version; 816 if (!printed_version++) 817 printk(version); 818 #endif 819 820 i = pci_enable_device(pdev); 821 if (i) return i; 822 823 /* natsemi has a non-standard PM control register 824 * in PCI config space. Some boards apparently need 825 * to be brought to D0 in this manner. 826 */ 827 pci_read_config_dword(pdev, PCIPM, &tmp); 828 if (tmp & PCI_PM_CTRL_STATE_MASK) { 829 /* D0 state, disable PME assertion */ 830 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK; 831 pci_write_config_dword(pdev, PCIPM, newtmp); 832 } 833 834 find_cnt++; 835 iostart = pci_resource_start(pdev, pcibar); 836 iosize = pci_resource_len(pdev, pcibar); 837 irq = pdev->irq; 838 839 pci_set_master(pdev); 840 841 dev = alloc_etherdev(sizeof (struct netdev_private)); 842 if (!dev) 843 return -ENOMEM; 844 SET_NETDEV_DEV(dev, &pdev->dev); 845 846 i = pci_request_regions(pdev, DRV_NAME); 847 if (i) 848 goto err_pci_request_regions; 849 850 ioaddr = ioremap(iostart, iosize); 851 if (!ioaddr) { 852 i = -ENOMEM; 853 goto err_ioremap; 854 } 855 856 /* Work around the dropped serial bit. */ 857 prev_eedata = eeprom_read(ioaddr, 6); 858 for (i = 0; i < 3; i++) { 859 int eedata = eeprom_read(ioaddr, i + 7); 860 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15); 861 dev->dev_addr[i*2+1] = eedata >> 7; 862 prev_eedata = eedata; 863 } 864 865 np = netdev_priv(dev); 866 np->ioaddr = ioaddr; 867 868 netif_napi_add(dev, &np->napi, natsemi_poll, 64); 869 np->dev = dev; 870 871 np->pci_dev = pdev; 872 pci_set_drvdata(pdev, dev); 873 np->iosize = iosize; 874 spin_lock_init(&np->lock); 875 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG; 876 np->hands_off = 0; 877 np->intr_status = 0; 878 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size; 879 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY) 880 np->ignore_phy = 1; 881 else 882 np->ignore_phy = 0; 883 np->dspcfg_workaround = dspcfg_workaround; 884 885 /* Initial port: 886 * - If configured to ignore the PHY set up for external. 887 * - If the nic was configured to use an external phy and if find_mii 888 * finds a phy: use external port, first phy that replies. 889 * - Otherwise: internal port. 890 * Note that the phy address for the internal phy doesn't matter: 891 * The address would be used to access a phy over the mii bus, but 892 * the internal phy is accessed through mapped registers. 893 */ 894 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy) 895 dev->if_port = PORT_MII; 896 else 897 dev->if_port = PORT_TP; 898 /* Reset the chip to erase previous misconfiguration. */ 899 natsemi_reload_eeprom(dev); 900 natsemi_reset(dev); 901 902 if (dev->if_port != PORT_TP) { 903 np->phy_addr_external = find_mii(dev); 904 /* If we're ignoring the PHY it doesn't matter if we can't 905 * find one. */ 906 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) { 907 dev->if_port = PORT_TP; 908 np->phy_addr_external = PHY_ADDR_INTERNAL; 909 } 910 } else { 911 np->phy_addr_external = PHY_ADDR_INTERNAL; 912 } 913 914 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; 915 /* The lower four bits are the media type. */ 916 if (option) { 917 if (option & 0x200) 918 np->full_duplex = 1; 919 if (option & 15) 920 printk(KERN_INFO 921 "natsemi %s: ignoring user supplied media type %d", 922 pci_name(np->pci_dev), option & 15); 923 } 924 if (find_cnt < MAX_UNITS && full_duplex[find_cnt]) 925 np->full_duplex = 1; 926 927 dev->netdev_ops = &natsemi_netdev_ops; 928 dev->watchdog_timeo = TX_TIMEOUT; 929 930 SET_ETHTOOL_OPS(dev, ðtool_ops); 931 932 if (mtu) 933 dev->mtu = mtu; 934 935 natsemi_init_media(dev); 936 937 /* save the silicon revision for later querying */ 938 np->srr = readl(ioaddr + SiliconRev); 939 if (netif_msg_hw(np)) 940 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n", 941 pci_name(np->pci_dev), np->srr); 942 943 i = register_netdev(dev); 944 if (i) 945 goto err_register_netdev; 946 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround); 947 if (i) 948 goto err_create_file; 949 950 if (netif_msg_drv(np)) { 951 printk(KERN_INFO "natsemi %s: %s at %#08llx " 952 "(%s), %pM, IRQ %d", 953 dev->name, natsemi_pci_info[chip_idx].name, 954 (unsigned long long)iostart, pci_name(np->pci_dev), 955 dev->dev_addr, irq); 956 if (dev->if_port == PORT_TP) 957 printk(", port TP.\n"); 958 else if (np->ignore_phy) 959 printk(", port MII, ignoring PHY\n"); 960 else 961 printk(", port MII, phy ad %d.\n", np->phy_addr_external); 962 } 963 return 0; 964 965 err_create_file: 966 unregister_netdev(dev); 967 968 err_register_netdev: 969 iounmap(ioaddr); 970 971 err_ioremap: 972 pci_release_regions(pdev); 973 pci_set_drvdata(pdev, NULL); 974 975 err_pci_request_regions: 976 free_netdev(dev); 977 return i; 978 } 979 980 981 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. 982 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */ 983 984 /* Delay between EEPROM clock transitions. 985 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need 986 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that 987 made udelay() unreliable. 988 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is 989 deprecated. 990 */ 991 #define eeprom_delay(ee_addr) readl(ee_addr) 992 993 #define EE_Write0 (EE_ChipSelect) 994 #define EE_Write1 (EE_ChipSelect | EE_DataIn) 995 996 /* The EEPROM commands include the alway-set leading bit. */ 997 enum EEPROM_Cmds { 998 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), 999 }; 1000 1001 static int eeprom_read(void __iomem *addr, int location) 1002 { 1003 int i; 1004 int retval = 0; 1005 void __iomem *ee_addr = addr + EECtrl; 1006 int read_cmd = location | EE_ReadCmd; 1007 1008 writel(EE_Write0, ee_addr); 1009 1010 /* Shift the read command bits out. */ 1011 for (i = 10; i >= 0; i--) { 1012 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; 1013 writel(dataval, ee_addr); 1014 eeprom_delay(ee_addr); 1015 writel(dataval | EE_ShiftClk, ee_addr); 1016 eeprom_delay(ee_addr); 1017 } 1018 writel(EE_ChipSelect, ee_addr); 1019 eeprom_delay(ee_addr); 1020 1021 for (i = 0; i < 16; i++) { 1022 writel(EE_ChipSelect | EE_ShiftClk, ee_addr); 1023 eeprom_delay(ee_addr); 1024 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0; 1025 writel(EE_ChipSelect, ee_addr); 1026 eeprom_delay(ee_addr); 1027 } 1028 1029 /* Terminate the EEPROM access. */ 1030 writel(EE_Write0, ee_addr); 1031 writel(0, ee_addr); 1032 return retval; 1033 } 1034 1035 /* MII transceiver control section. 1036 * The 83815 series has an internal transceiver, and we present the 1037 * internal management registers as if they were MII connected. 1038 * External Phy registers are referenced through the MII interface. 1039 */ 1040 1041 /* clock transitions >= 20ns (25MHz) 1042 * One readl should be good to PCI @ 100MHz 1043 */ 1044 #define mii_delay(ioaddr) readl(ioaddr + EECtrl) 1045 1046 static int mii_getbit (struct net_device *dev) 1047 { 1048 int data; 1049 void __iomem *ioaddr = ns_ioaddr(dev); 1050 1051 writel(MII_ShiftClk, ioaddr + EECtrl); 1052 data = readl(ioaddr + EECtrl); 1053 writel(0, ioaddr + EECtrl); 1054 mii_delay(ioaddr); 1055 return (data & MII_Data)? 1 : 0; 1056 } 1057 1058 static void mii_send_bits (struct net_device *dev, u32 data, int len) 1059 { 1060 u32 i; 1061 void __iomem *ioaddr = ns_ioaddr(dev); 1062 1063 for (i = (1 << (len-1)); i; i >>= 1) 1064 { 1065 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0); 1066 writel(mdio_val, ioaddr + EECtrl); 1067 mii_delay(ioaddr); 1068 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl); 1069 mii_delay(ioaddr); 1070 } 1071 writel(0, ioaddr + EECtrl); 1072 mii_delay(ioaddr); 1073 } 1074 1075 static int miiport_read(struct net_device *dev, int phy_id, int reg) 1076 { 1077 u32 cmd; 1078 int i; 1079 u32 retval = 0; 1080 1081 /* Ensure sync */ 1082 mii_send_bits (dev, 0xffffffff, 32); 1083 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1084 /* ST,OP = 0110'b for read operation */ 1085 cmd = (0x06 << 10) | (phy_id << 5) | reg; 1086 mii_send_bits (dev, cmd, 14); 1087 /* Turnaround */ 1088 if (mii_getbit (dev)) 1089 return 0; 1090 /* Read data */ 1091 for (i = 0; i < 16; i++) { 1092 retval <<= 1; 1093 retval |= mii_getbit (dev); 1094 } 1095 /* End cycle */ 1096 mii_getbit (dev); 1097 return retval; 1098 } 1099 1100 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) 1101 { 1102 u32 cmd; 1103 1104 /* Ensure sync */ 1105 mii_send_bits (dev, 0xffffffff, 32); 1106 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1107 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1108 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data; 1109 mii_send_bits (dev, cmd, 32); 1110 /* End cycle */ 1111 mii_getbit (dev); 1112 } 1113 1114 static int mdio_read(struct net_device *dev, int reg) 1115 { 1116 struct netdev_private *np = netdev_priv(dev); 1117 void __iomem *ioaddr = ns_ioaddr(dev); 1118 1119 /* The 83815 series has two ports: 1120 * - an internal transceiver 1121 * - an external mii bus 1122 */ 1123 if (dev->if_port == PORT_TP) 1124 return readw(ioaddr+BasicControl+(reg<<2)); 1125 else 1126 return miiport_read(dev, np->phy_addr_external, reg); 1127 } 1128 1129 static void mdio_write(struct net_device *dev, int reg, u16 data) 1130 { 1131 struct netdev_private *np = netdev_priv(dev); 1132 void __iomem *ioaddr = ns_ioaddr(dev); 1133 1134 /* The 83815 series has an internal transceiver; handle separately */ 1135 if (dev->if_port == PORT_TP) 1136 writew(data, ioaddr+BasicControl+(reg<<2)); 1137 else 1138 miiport_write(dev, np->phy_addr_external, reg, data); 1139 } 1140 1141 static void init_phy_fixup(struct net_device *dev) 1142 { 1143 struct netdev_private *np = netdev_priv(dev); 1144 void __iomem *ioaddr = ns_ioaddr(dev); 1145 int i; 1146 u32 cfg; 1147 u16 tmp; 1148 1149 /* restore stuff lost when power was out */ 1150 tmp = mdio_read(dev, MII_BMCR); 1151 if (np->autoneg == AUTONEG_ENABLE) { 1152 /* renegotiate if something changed */ 1153 if ((tmp & BMCR_ANENABLE) == 0 || 1154 np->advertising != mdio_read(dev, MII_ADVERTISE)) 1155 { 1156 /* turn on autonegotiation and force negotiation */ 1157 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART); 1158 mdio_write(dev, MII_ADVERTISE, np->advertising); 1159 } 1160 } else { 1161 /* turn off auto negotiation, set speed and duplexity */ 1162 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); 1163 if (np->speed == SPEED_100) 1164 tmp |= BMCR_SPEED100; 1165 if (np->duplex == DUPLEX_FULL) 1166 tmp |= BMCR_FULLDPLX; 1167 /* 1168 * Note: there is no good way to inform the link partner 1169 * that our capabilities changed. The user has to unplug 1170 * and replug the network cable after some changes, e.g. 1171 * after switching from 10HD, autoneg off to 100 HD, 1172 * autoneg off. 1173 */ 1174 } 1175 mdio_write(dev, MII_BMCR, tmp); 1176 readl(ioaddr + ChipConfig); 1177 udelay(1); 1178 1179 /* find out what phy this is */ 1180 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1181 + mdio_read(dev, MII_PHYSID2); 1182 1183 /* handle external phys here */ 1184 switch (np->mii) { 1185 case PHYID_AM79C874: 1186 /* phy specific configuration for fibre/tp operation */ 1187 tmp = mdio_read(dev, MII_MCTRL); 1188 tmp &= ~(MII_FX_SEL | MII_EN_SCRM); 1189 if (dev->if_port == PORT_FIBRE) 1190 tmp |= MII_FX_SEL; 1191 else 1192 tmp |= MII_EN_SCRM; 1193 mdio_write(dev, MII_MCTRL, tmp); 1194 break; 1195 default: 1196 break; 1197 } 1198 cfg = readl(ioaddr + ChipConfig); 1199 if (cfg & CfgExtPhy) 1200 return; 1201 1202 /* On page 78 of the spec, they recommend some settings for "optimum 1203 performance" to be done in sequence. These settings optimize some 1204 of the 100Mbit autodetection circuitry. They say we only want to 1205 do this for rev C of the chip, but engineers at NSC (Bradley 1206 Kennedy) recommends always setting them. If you don't, you get 1207 errors on some autonegotiations that make the device unusable. 1208 1209 It seems that the DSP needs a few usec to reinitialize after 1210 the start of the phy. Just retry writing these values until they 1211 stick. 1212 */ 1213 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1214 1215 int dspcfg; 1216 writew(1, ioaddr + PGSEL); 1217 writew(PMDCSR_VAL, ioaddr + PMDCSR); 1218 writew(TSTDAT_VAL, ioaddr + TSTDAT); 1219 np->dspcfg = (np->srr <= SRR_DP83815_C)? 1220 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG)); 1221 writew(np->dspcfg, ioaddr + DSPCFG); 1222 writew(SDCFG_VAL, ioaddr + SDCFG); 1223 writew(0, ioaddr + PGSEL); 1224 readl(ioaddr + ChipConfig); 1225 udelay(10); 1226 1227 writew(1, ioaddr + PGSEL); 1228 dspcfg = readw(ioaddr + DSPCFG); 1229 writew(0, ioaddr + PGSEL); 1230 if (np->dspcfg == dspcfg) 1231 break; 1232 } 1233 1234 if (netif_msg_link(np)) { 1235 if (i==NATSEMI_HW_TIMEOUT) { 1236 printk(KERN_INFO 1237 "%s: DSPCFG mismatch after retrying for %d usec.\n", 1238 dev->name, i*10); 1239 } else { 1240 printk(KERN_INFO 1241 "%s: DSPCFG accepted after %d usec.\n", 1242 dev->name, i*10); 1243 } 1244 } 1245 /* 1246 * Enable PHY Specific event based interrupts. Link state change 1247 * and Auto-Negotiation Completion are among the affected. 1248 * Read the intr status to clear it (needed for wake events). 1249 */ 1250 readw(ioaddr + MIntrStatus); 1251 writew(MICRIntEn, ioaddr + MIntrCtrl); 1252 } 1253 1254 static int switch_port_external(struct net_device *dev) 1255 { 1256 struct netdev_private *np = netdev_priv(dev); 1257 void __iomem *ioaddr = ns_ioaddr(dev); 1258 u32 cfg; 1259 1260 cfg = readl(ioaddr + ChipConfig); 1261 if (cfg & CfgExtPhy) 1262 return 0; 1263 1264 if (netif_msg_link(np)) { 1265 printk(KERN_INFO "%s: switching to external transceiver.\n", 1266 dev->name); 1267 } 1268 1269 /* 1) switch back to external phy */ 1270 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig); 1271 readl(ioaddr + ChipConfig); 1272 udelay(1); 1273 1274 /* 2) reset the external phy: */ 1275 /* resetting the external PHY has been known to cause a hub supplying 1276 * power over Ethernet to kill the power. We don't want to kill 1277 * power to this computer, so we avoid resetting the phy. 1278 */ 1279 1280 /* 3) reinit the phy fixup, it got lost during power down. */ 1281 move_int_phy(dev, np->phy_addr_external); 1282 init_phy_fixup(dev); 1283 1284 return 1; 1285 } 1286 1287 static int switch_port_internal(struct net_device *dev) 1288 { 1289 struct netdev_private *np = netdev_priv(dev); 1290 void __iomem *ioaddr = ns_ioaddr(dev); 1291 int i; 1292 u32 cfg; 1293 u16 bmcr; 1294 1295 cfg = readl(ioaddr + ChipConfig); 1296 if (!(cfg &CfgExtPhy)) 1297 return 0; 1298 1299 if (netif_msg_link(np)) { 1300 printk(KERN_INFO "%s: switching to internal transceiver.\n", 1301 dev->name); 1302 } 1303 /* 1) switch back to internal phy: */ 1304 cfg = cfg & ~(CfgExtPhy | CfgPhyDis); 1305 writel(cfg, ioaddr + ChipConfig); 1306 readl(ioaddr + ChipConfig); 1307 udelay(1); 1308 1309 /* 2) reset the internal phy: */ 1310 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1311 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2)); 1312 readl(ioaddr + ChipConfig); 1313 udelay(10); 1314 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1315 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1316 if (!(bmcr & BMCR_RESET)) 1317 break; 1318 udelay(10); 1319 } 1320 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) { 1321 printk(KERN_INFO 1322 "%s: phy reset did not complete in %d usec.\n", 1323 dev->name, i*10); 1324 } 1325 /* 3) reinit the phy fixup, it got lost during power down. */ 1326 init_phy_fixup(dev); 1327 1328 return 1; 1329 } 1330 1331 /* Scan for a PHY on the external mii bus. 1332 * There are two tricky points: 1333 * - Do not scan while the internal phy is enabled. The internal phy will 1334 * crash: e.g. reads from the DSPCFG register will return odd values and 1335 * the nasty random phy reset code will reset the nic every few seconds. 1336 * - The internal phy must be moved around, an external phy could 1337 * have the same address as the internal phy. 1338 */ 1339 static int find_mii(struct net_device *dev) 1340 { 1341 struct netdev_private *np = netdev_priv(dev); 1342 int tmp; 1343 int i; 1344 int did_switch; 1345 1346 /* Switch to external phy */ 1347 did_switch = switch_port_external(dev); 1348 1349 /* Scan the possible phy addresses: 1350 * 1351 * PHY address 0 means that the phy is in isolate mode. Not yet 1352 * supported due to lack of test hardware. User space should 1353 * handle it through ethtool. 1354 */ 1355 for (i = 1; i <= 31; i++) { 1356 move_int_phy(dev, i); 1357 tmp = miiport_read(dev, i, MII_BMSR); 1358 if (tmp != 0xffff && tmp != 0x0000) { 1359 /* found something! */ 1360 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1361 + mdio_read(dev, MII_PHYSID2); 1362 if (netif_msg_probe(np)) { 1363 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n", 1364 pci_name(np->pci_dev), np->mii, i); 1365 } 1366 break; 1367 } 1368 } 1369 /* And switch back to internal phy: */ 1370 if (did_switch) 1371 switch_port_internal(dev); 1372 return i; 1373 } 1374 1375 /* CFG bits [13:16] [18:23] */ 1376 #define CFG_RESET_SAVE 0xfde000 1377 /* WCSR bits [0:4] [9:10] */ 1378 #define WCSR_RESET_SAVE 0x61f 1379 /* RFCR bits [20] [22] [27:31] */ 1380 #define RFCR_RESET_SAVE 0xf8500000 1381 1382 static void natsemi_reset(struct net_device *dev) 1383 { 1384 int i; 1385 u32 cfg; 1386 u32 wcsr; 1387 u32 rfcr; 1388 u16 pmatch[3]; 1389 u16 sopass[3]; 1390 struct netdev_private *np = netdev_priv(dev); 1391 void __iomem *ioaddr = ns_ioaddr(dev); 1392 1393 /* 1394 * Resetting the chip causes some registers to be lost. 1395 * Natsemi suggests NOT reloading the EEPROM while live, so instead 1396 * we save the state that would have been loaded from EEPROM 1397 * on a normal power-up (see the spec EEPROM map). This assumes 1398 * whoever calls this will follow up with init_registers() eventually. 1399 */ 1400 1401 /* CFG */ 1402 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE; 1403 /* WCSR */ 1404 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE; 1405 /* RFCR */ 1406 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE; 1407 /* PMATCH */ 1408 for (i = 0; i < 3; i++) { 1409 writel(i*2, ioaddr + RxFilterAddr); 1410 pmatch[i] = readw(ioaddr + RxFilterData); 1411 } 1412 /* SOPAS */ 1413 for (i = 0; i < 3; i++) { 1414 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1415 sopass[i] = readw(ioaddr + RxFilterData); 1416 } 1417 1418 /* now whack the chip */ 1419 writel(ChipReset, ioaddr + ChipCmd); 1420 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1421 if (!(readl(ioaddr + ChipCmd) & ChipReset)) 1422 break; 1423 udelay(5); 1424 } 1425 if (i==NATSEMI_HW_TIMEOUT) { 1426 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n", 1427 dev->name, i*5); 1428 } else if (netif_msg_hw(np)) { 1429 printk(KERN_DEBUG "%s: reset completed in %d usec.\n", 1430 dev->name, i*5); 1431 } 1432 1433 /* restore CFG */ 1434 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE; 1435 /* turn on external phy if it was selected */ 1436 if (dev->if_port == PORT_TP) 1437 cfg &= ~(CfgExtPhy | CfgPhyDis); 1438 else 1439 cfg |= (CfgExtPhy | CfgPhyDis); 1440 writel(cfg, ioaddr + ChipConfig); 1441 /* restore WCSR */ 1442 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE; 1443 writel(wcsr, ioaddr + WOLCmd); 1444 /* read RFCR */ 1445 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE; 1446 /* restore PMATCH */ 1447 for (i = 0; i < 3; i++) { 1448 writel(i*2, ioaddr + RxFilterAddr); 1449 writew(pmatch[i], ioaddr + RxFilterData); 1450 } 1451 for (i = 0; i < 3; i++) { 1452 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1453 writew(sopass[i], ioaddr + RxFilterData); 1454 } 1455 /* restore RFCR */ 1456 writel(rfcr, ioaddr + RxFilterAddr); 1457 } 1458 1459 static void reset_rx(struct net_device *dev) 1460 { 1461 int i; 1462 struct netdev_private *np = netdev_priv(dev); 1463 void __iomem *ioaddr = ns_ioaddr(dev); 1464 1465 np->intr_status &= ~RxResetDone; 1466 1467 writel(RxReset, ioaddr + ChipCmd); 1468 1469 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1470 np->intr_status |= readl(ioaddr + IntrStatus); 1471 if (np->intr_status & RxResetDone) 1472 break; 1473 udelay(15); 1474 } 1475 if (i==NATSEMI_HW_TIMEOUT) { 1476 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n", 1477 dev->name, i*15); 1478 } else if (netif_msg_hw(np)) { 1479 printk(KERN_WARNING "%s: RX reset took %d usec.\n", 1480 dev->name, i*15); 1481 } 1482 } 1483 1484 static void natsemi_reload_eeprom(struct net_device *dev) 1485 { 1486 struct netdev_private *np = netdev_priv(dev); 1487 void __iomem *ioaddr = ns_ioaddr(dev); 1488 int i; 1489 1490 writel(EepromReload, ioaddr + PCIBusCfg); 1491 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1492 udelay(50); 1493 if (!(readl(ioaddr + PCIBusCfg) & EepromReload)) 1494 break; 1495 } 1496 if (i==NATSEMI_HW_TIMEOUT) { 1497 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n", 1498 pci_name(np->pci_dev), i*50); 1499 } else if (netif_msg_hw(np)) { 1500 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n", 1501 pci_name(np->pci_dev), i*50); 1502 } 1503 } 1504 1505 static void natsemi_stop_rxtx(struct net_device *dev) 1506 { 1507 void __iomem * ioaddr = ns_ioaddr(dev); 1508 struct netdev_private *np = netdev_priv(dev); 1509 int i; 1510 1511 writel(RxOff | TxOff, ioaddr + ChipCmd); 1512 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) { 1513 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0) 1514 break; 1515 udelay(5); 1516 } 1517 if (i==NATSEMI_HW_TIMEOUT) { 1518 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n", 1519 dev->name, i*5); 1520 } else if (netif_msg_hw(np)) { 1521 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n", 1522 dev->name, i*5); 1523 } 1524 } 1525 1526 static int netdev_open(struct net_device *dev) 1527 { 1528 struct netdev_private *np = netdev_priv(dev); 1529 void __iomem * ioaddr = ns_ioaddr(dev); 1530 const int irq = np->pci_dev->irq; 1531 int i; 1532 1533 /* Reset the chip, just in case. */ 1534 natsemi_reset(dev); 1535 1536 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 1537 if (i) return i; 1538 1539 if (netif_msg_ifup(np)) 1540 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", 1541 dev->name, irq); 1542 i = alloc_ring(dev); 1543 if (i < 0) { 1544 free_irq(irq, dev); 1545 return i; 1546 } 1547 napi_enable(&np->napi); 1548 1549 init_ring(dev); 1550 spin_lock_irq(&np->lock); 1551 init_registers(dev); 1552 /* now set the MAC address according to dev->dev_addr */ 1553 for (i = 0; i < 3; i++) { 1554 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i]; 1555 1556 writel(i*2, ioaddr + RxFilterAddr); 1557 writew(mac, ioaddr + RxFilterData); 1558 } 1559 writel(np->cur_rx_mode, ioaddr + RxFilterAddr); 1560 spin_unlock_irq(&np->lock); 1561 1562 netif_start_queue(dev); 1563 1564 if (netif_msg_ifup(np)) 1565 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n", 1566 dev->name, (int)readl(ioaddr + ChipCmd)); 1567 1568 /* Set the timer to check for link beat. */ 1569 init_timer(&np->timer); 1570 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ); 1571 np->timer.data = (unsigned long)dev; 1572 np->timer.function = netdev_timer; /* timer handler */ 1573 add_timer(&np->timer); 1574 1575 return 0; 1576 } 1577 1578 static void do_cable_magic(struct net_device *dev) 1579 { 1580 struct netdev_private *np = netdev_priv(dev); 1581 void __iomem *ioaddr = ns_ioaddr(dev); 1582 1583 if (dev->if_port != PORT_TP) 1584 return; 1585 1586 if (np->srr >= SRR_DP83816_A5) 1587 return; 1588 1589 /* 1590 * 100 MBit links with short cables can trip an issue with the chip. 1591 * The problem manifests as lots of CRC errors and/or flickering 1592 * activity LED while idle. This process is based on instructions 1593 * from engineers at National. 1594 */ 1595 if (readl(ioaddr + ChipConfig) & CfgSpeed100) { 1596 u16 data; 1597 1598 writew(1, ioaddr + PGSEL); 1599 /* 1600 * coefficient visibility should already be enabled via 1601 * DSPCFG | 0x1000 1602 */ 1603 data = readw(ioaddr + TSTDAT) & 0xff; 1604 /* 1605 * the value must be negative, and within certain values 1606 * (these values all come from National) 1607 */ 1608 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) { 1609 np = netdev_priv(dev); 1610 1611 /* the bug has been triggered - fix the coefficient */ 1612 writew(TSTDAT_FIXED, ioaddr + TSTDAT); 1613 /* lock the value */ 1614 data = readw(ioaddr + DSPCFG); 1615 np->dspcfg = data | DSPCFG_LOCK; 1616 writew(np->dspcfg, ioaddr + DSPCFG); 1617 } 1618 writew(0, ioaddr + PGSEL); 1619 } 1620 } 1621 1622 static void undo_cable_magic(struct net_device *dev) 1623 { 1624 u16 data; 1625 struct netdev_private *np = netdev_priv(dev); 1626 void __iomem * ioaddr = ns_ioaddr(dev); 1627 1628 if (dev->if_port != PORT_TP) 1629 return; 1630 1631 if (np->srr >= SRR_DP83816_A5) 1632 return; 1633 1634 writew(1, ioaddr + PGSEL); 1635 /* make sure the lock bit is clear */ 1636 data = readw(ioaddr + DSPCFG); 1637 np->dspcfg = data & ~DSPCFG_LOCK; 1638 writew(np->dspcfg, ioaddr + DSPCFG); 1639 writew(0, ioaddr + PGSEL); 1640 } 1641 1642 static void check_link(struct net_device *dev) 1643 { 1644 struct netdev_private *np = netdev_priv(dev); 1645 void __iomem * ioaddr = ns_ioaddr(dev); 1646 int duplex = np->duplex; 1647 u16 bmsr; 1648 1649 /* If we are ignoring the PHY then don't try reading it. */ 1650 if (np->ignore_phy) 1651 goto propagate_state; 1652 1653 /* The link status field is latched: it remains low after a temporary 1654 * link failure until it's read. We need the current link status, 1655 * thus read twice. 1656 */ 1657 mdio_read(dev, MII_BMSR); 1658 bmsr = mdio_read(dev, MII_BMSR); 1659 1660 if (!(bmsr & BMSR_LSTATUS)) { 1661 if (netif_carrier_ok(dev)) { 1662 if (netif_msg_link(np)) 1663 printk(KERN_NOTICE "%s: link down.\n", 1664 dev->name); 1665 netif_carrier_off(dev); 1666 undo_cable_magic(dev); 1667 } 1668 return; 1669 } 1670 if (!netif_carrier_ok(dev)) { 1671 if (netif_msg_link(np)) 1672 printk(KERN_NOTICE "%s: link up.\n", dev->name); 1673 netif_carrier_on(dev); 1674 do_cable_magic(dev); 1675 } 1676 1677 duplex = np->full_duplex; 1678 if (!duplex) { 1679 if (bmsr & BMSR_ANEGCOMPLETE) { 1680 int tmp = mii_nway_result( 1681 np->advertising & mdio_read(dev, MII_LPA)); 1682 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 1683 duplex = 1; 1684 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX) 1685 duplex = 1; 1686 } 1687 1688 propagate_state: 1689 /* if duplex is set then bit 28 must be set, too */ 1690 if (duplex ^ !!(np->rx_config & RxAcceptTx)) { 1691 if (netif_msg_link(np)) 1692 printk(KERN_INFO 1693 "%s: Setting %s-duplex based on negotiated " 1694 "link capability.\n", dev->name, 1695 duplex ? "full" : "half"); 1696 if (duplex) { 1697 np->rx_config |= RxAcceptTx; 1698 np->tx_config |= TxCarrierIgn | TxHeartIgn; 1699 } else { 1700 np->rx_config &= ~RxAcceptTx; 1701 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn); 1702 } 1703 writel(np->tx_config, ioaddr + TxConfig); 1704 writel(np->rx_config, ioaddr + RxConfig); 1705 } 1706 } 1707 1708 static void init_registers(struct net_device *dev) 1709 { 1710 struct netdev_private *np = netdev_priv(dev); 1711 void __iomem * ioaddr = ns_ioaddr(dev); 1712 1713 init_phy_fixup(dev); 1714 1715 /* clear any interrupts that are pending, such as wake events */ 1716 readl(ioaddr + IntrStatus); 1717 1718 writel(np->ring_dma, ioaddr + RxRingPtr); 1719 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), 1720 ioaddr + TxRingPtr); 1721 1722 /* Initialize other registers. 1723 * Configure the PCI bus bursts and FIFO thresholds. 1724 * Configure for standard, in-spec Ethernet. 1725 * Start with half-duplex. check_link will update 1726 * to the correct settings. 1727 */ 1728 1729 /* DRTH: 2: start tx if 64 bytes are in the fifo 1730 * FLTH: 0x10: refill with next packet if 512 bytes are free 1731 * MXDMA: 0: up to 256 byte bursts. 1732 * MXDMA must be <= FLTH 1733 * ECRETRY=1 1734 * ATP=1 1735 */ 1736 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | 1737 TX_FLTH_VAL | TX_DRTH_VAL_START; 1738 writel(np->tx_config, ioaddr + TxConfig); 1739 1740 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo 1741 * MXDMA 0: up to 256 byte bursts 1742 */ 1743 np->rx_config = RxMxdma_256 | RX_DRTH_VAL; 1744 /* if receive ring now has bigger buffers than normal, enable jumbo */ 1745 if (np->rx_buf_sz > NATSEMI_LONGPKT) 1746 np->rx_config |= RxAcceptLong; 1747 1748 writel(np->rx_config, ioaddr + RxConfig); 1749 1750 /* Disable PME: 1751 * The PME bit is initialized from the EEPROM contents. 1752 * PCI cards probably have PME disabled, but motherboard 1753 * implementations may have PME set to enable WakeOnLan. 1754 * With PME set the chip will scan incoming packets but 1755 * nothing will be written to memory. */ 1756 np->SavedClkRun = readl(ioaddr + ClkRun); 1757 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun); 1758 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) { 1759 printk(KERN_NOTICE "%s: Wake-up event %#08x\n", 1760 dev->name, readl(ioaddr + WOLCmd)); 1761 } 1762 1763 check_link(dev); 1764 __set_rx_mode(dev); 1765 1766 /* Enable interrupts by setting the interrupt mask. */ 1767 writel(DEFAULT_INTR, ioaddr + IntrMask); 1768 natsemi_irq_enable(dev); 1769 1770 writel(RxOn | TxOn, ioaddr + ChipCmd); 1771 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */ 1772 } 1773 1774 /* 1775 * netdev_timer: 1776 * Purpose: 1777 * 1) check for link changes. Usually they are handled by the MII interrupt 1778 * but it doesn't hurt to check twice. 1779 * 2) check for sudden death of the NIC: 1780 * It seems that a reference set for this chip went out with incorrect info, 1781 * and there exist boards that aren't quite right. An unexpected voltage 1782 * drop can cause the PHY to get itself in a weird state (basically reset). 1783 * NOTE: this only seems to affect revC chips. The user can disable 1784 * this check via dspcfg_workaround sysfs option. 1785 * 3) check of death of the RX path due to OOM 1786 */ 1787 static void netdev_timer(unsigned long data) 1788 { 1789 struct net_device *dev = (struct net_device *)data; 1790 struct netdev_private *np = netdev_priv(dev); 1791 void __iomem * ioaddr = ns_ioaddr(dev); 1792 int next_tick = NATSEMI_TIMER_FREQ; 1793 const int irq = np->pci_dev->irq; 1794 1795 if (netif_msg_timer(np)) { 1796 /* DO NOT read the IntrStatus register, 1797 * a read clears any pending interrupts. 1798 */ 1799 printk(KERN_DEBUG "%s: Media selection timer tick.\n", 1800 dev->name); 1801 } 1802 1803 if (dev->if_port == PORT_TP) { 1804 u16 dspcfg; 1805 1806 spin_lock_irq(&np->lock); 1807 /* check for a nasty random phy-reset - use dspcfg as a flag */ 1808 writew(1, ioaddr+PGSEL); 1809 dspcfg = readw(ioaddr+DSPCFG); 1810 writew(0, ioaddr+PGSEL); 1811 if (np->dspcfg_workaround && dspcfg != np->dspcfg) { 1812 if (!netif_queue_stopped(dev)) { 1813 spin_unlock_irq(&np->lock); 1814 if (netif_msg_drv(np)) 1815 printk(KERN_NOTICE "%s: possible phy reset: " 1816 "re-initializing\n", dev->name); 1817 disable_irq(irq); 1818 spin_lock_irq(&np->lock); 1819 natsemi_stop_rxtx(dev); 1820 dump_ring(dev); 1821 reinit_ring(dev); 1822 init_registers(dev); 1823 spin_unlock_irq(&np->lock); 1824 enable_irq(irq); 1825 } else { 1826 /* hurry back */ 1827 next_tick = HZ; 1828 spin_unlock_irq(&np->lock); 1829 } 1830 } else { 1831 /* init_registers() calls check_link() for the above case */ 1832 check_link(dev); 1833 spin_unlock_irq(&np->lock); 1834 } 1835 } else { 1836 spin_lock_irq(&np->lock); 1837 check_link(dev); 1838 spin_unlock_irq(&np->lock); 1839 } 1840 if (np->oom) { 1841 disable_irq(irq); 1842 np->oom = 0; 1843 refill_rx(dev); 1844 enable_irq(irq); 1845 if (!np->oom) { 1846 writel(RxOn, ioaddr + ChipCmd); 1847 } else { 1848 next_tick = 1; 1849 } 1850 } 1851 1852 if (next_tick > 1) 1853 mod_timer(&np->timer, round_jiffies(jiffies + next_tick)); 1854 else 1855 mod_timer(&np->timer, jiffies + next_tick); 1856 } 1857 1858 static void dump_ring(struct net_device *dev) 1859 { 1860 struct netdev_private *np = netdev_priv(dev); 1861 1862 if (netif_msg_pktdata(np)) { 1863 int i; 1864 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring); 1865 for (i = 0; i < TX_RING_SIZE; i++) { 1866 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1867 i, np->tx_ring[i].next_desc, 1868 np->tx_ring[i].cmd_status, 1869 np->tx_ring[i].addr); 1870 } 1871 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring); 1872 for (i = 0; i < RX_RING_SIZE; i++) { 1873 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1874 i, np->rx_ring[i].next_desc, 1875 np->rx_ring[i].cmd_status, 1876 np->rx_ring[i].addr); 1877 } 1878 } 1879 } 1880 1881 static void ns_tx_timeout(struct net_device *dev) 1882 { 1883 struct netdev_private *np = netdev_priv(dev); 1884 void __iomem * ioaddr = ns_ioaddr(dev); 1885 const int irq = np->pci_dev->irq; 1886 1887 disable_irq(irq); 1888 spin_lock_irq(&np->lock); 1889 if (!np->hands_off) { 1890 if (netif_msg_tx_err(np)) 1891 printk(KERN_WARNING 1892 "%s: Transmit timed out, status %#08x," 1893 " resetting...\n", 1894 dev->name, readl(ioaddr + IntrStatus)); 1895 dump_ring(dev); 1896 1897 natsemi_reset(dev); 1898 reinit_ring(dev); 1899 init_registers(dev); 1900 } else { 1901 printk(KERN_WARNING 1902 "%s: tx_timeout while in hands_off state?\n", 1903 dev->name); 1904 } 1905 spin_unlock_irq(&np->lock); 1906 enable_irq(irq); 1907 1908 dev->trans_start = jiffies; /* prevent tx timeout */ 1909 dev->stats.tx_errors++; 1910 netif_wake_queue(dev); 1911 } 1912 1913 static int alloc_ring(struct net_device *dev) 1914 { 1915 struct netdev_private *np = netdev_priv(dev); 1916 np->rx_ring = pci_alloc_consistent(np->pci_dev, 1917 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 1918 &np->ring_dma); 1919 if (!np->rx_ring) 1920 return -ENOMEM; 1921 np->tx_ring = &np->rx_ring[RX_RING_SIZE]; 1922 return 0; 1923 } 1924 1925 static void refill_rx(struct net_device *dev) 1926 { 1927 struct netdev_private *np = netdev_priv(dev); 1928 1929 /* Refill the Rx ring buffers. */ 1930 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { 1931 struct sk_buff *skb; 1932 int entry = np->dirty_rx % RX_RING_SIZE; 1933 if (np->rx_skbuff[entry] == NULL) { 1934 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING; 1935 skb = netdev_alloc_skb(dev, buflen); 1936 np->rx_skbuff[entry] = skb; 1937 if (skb == NULL) 1938 break; /* Better luck next round. */ 1939 np->rx_dma[entry] = pci_map_single(np->pci_dev, 1940 skb->data, buflen, PCI_DMA_FROMDEVICE); 1941 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]); 1942 } 1943 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz); 1944 } 1945 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) { 1946 if (netif_msg_rx_err(np)) 1947 printk(KERN_WARNING "%s: going OOM.\n", dev->name); 1948 np->oom = 1; 1949 } 1950 } 1951 1952 static void set_bufsize(struct net_device *dev) 1953 { 1954 struct netdev_private *np = netdev_priv(dev); 1955 if (dev->mtu <= ETH_DATA_LEN) 1956 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS; 1957 else 1958 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS; 1959 } 1960 1961 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1962 static void init_ring(struct net_device *dev) 1963 { 1964 struct netdev_private *np = netdev_priv(dev); 1965 int i; 1966 1967 /* 1) TX ring */ 1968 np->dirty_tx = np->cur_tx = 0; 1969 for (i = 0; i < TX_RING_SIZE; i++) { 1970 np->tx_skbuff[i] = NULL; 1971 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma 1972 +sizeof(struct netdev_desc) 1973 *((i+1)%TX_RING_SIZE+RX_RING_SIZE)); 1974 np->tx_ring[i].cmd_status = 0; 1975 } 1976 1977 /* 2) RX ring */ 1978 np->dirty_rx = 0; 1979 np->cur_rx = RX_RING_SIZE; 1980 np->oom = 0; 1981 set_bufsize(dev); 1982 1983 np->rx_head_desc = &np->rx_ring[0]; 1984 1985 /* Please be careful before changing this loop - at least gcc-2.95.1 1986 * miscompiles it otherwise. 1987 */ 1988 /* Initialize all Rx descriptors. */ 1989 for (i = 0; i < RX_RING_SIZE; i++) { 1990 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma 1991 +sizeof(struct netdev_desc) 1992 *((i+1)%RX_RING_SIZE)); 1993 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 1994 np->rx_skbuff[i] = NULL; 1995 } 1996 refill_rx(dev); 1997 dump_ring(dev); 1998 } 1999 2000 static void drain_tx(struct net_device *dev) 2001 { 2002 struct netdev_private *np = netdev_priv(dev); 2003 int i; 2004 2005 for (i = 0; i < TX_RING_SIZE; i++) { 2006 if (np->tx_skbuff[i]) { 2007 pci_unmap_single(np->pci_dev, 2008 np->tx_dma[i], np->tx_skbuff[i]->len, 2009 PCI_DMA_TODEVICE); 2010 dev_kfree_skb(np->tx_skbuff[i]); 2011 dev->stats.tx_dropped++; 2012 } 2013 np->tx_skbuff[i] = NULL; 2014 } 2015 } 2016 2017 static void drain_rx(struct net_device *dev) 2018 { 2019 struct netdev_private *np = netdev_priv(dev); 2020 unsigned int buflen = np->rx_buf_sz; 2021 int i; 2022 2023 /* Free all the skbuffs in the Rx queue. */ 2024 for (i = 0; i < RX_RING_SIZE; i++) { 2025 np->rx_ring[i].cmd_status = 0; 2026 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 2027 if (np->rx_skbuff[i]) { 2028 pci_unmap_single(np->pci_dev, np->rx_dma[i], 2029 buflen + NATSEMI_PADDING, 2030 PCI_DMA_FROMDEVICE); 2031 dev_kfree_skb(np->rx_skbuff[i]); 2032 } 2033 np->rx_skbuff[i] = NULL; 2034 } 2035 } 2036 2037 static void drain_ring(struct net_device *dev) 2038 { 2039 drain_rx(dev); 2040 drain_tx(dev); 2041 } 2042 2043 static void free_ring(struct net_device *dev) 2044 { 2045 struct netdev_private *np = netdev_priv(dev); 2046 pci_free_consistent(np->pci_dev, 2047 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 2048 np->rx_ring, np->ring_dma); 2049 } 2050 2051 static void reinit_rx(struct net_device *dev) 2052 { 2053 struct netdev_private *np = netdev_priv(dev); 2054 int i; 2055 2056 /* RX Ring */ 2057 np->dirty_rx = 0; 2058 np->cur_rx = RX_RING_SIZE; 2059 np->rx_head_desc = &np->rx_ring[0]; 2060 /* Initialize all Rx descriptors. */ 2061 for (i = 0; i < RX_RING_SIZE; i++) 2062 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 2063 2064 refill_rx(dev); 2065 } 2066 2067 static void reinit_ring(struct net_device *dev) 2068 { 2069 struct netdev_private *np = netdev_priv(dev); 2070 int i; 2071 2072 /* drain TX ring */ 2073 drain_tx(dev); 2074 np->dirty_tx = np->cur_tx = 0; 2075 for (i=0;i<TX_RING_SIZE;i++) 2076 np->tx_ring[i].cmd_status = 0; 2077 2078 reinit_rx(dev); 2079 } 2080 2081 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) 2082 { 2083 struct netdev_private *np = netdev_priv(dev); 2084 void __iomem * ioaddr = ns_ioaddr(dev); 2085 unsigned entry; 2086 unsigned long flags; 2087 2088 /* Note: Ordering is important here, set the field with the 2089 "ownership" bit last, and only then increment cur_tx. */ 2090 2091 /* Calculate the next Tx descriptor entry. */ 2092 entry = np->cur_tx % TX_RING_SIZE; 2093 2094 np->tx_skbuff[entry] = skb; 2095 np->tx_dma[entry] = pci_map_single(np->pci_dev, 2096 skb->data,skb->len, PCI_DMA_TODEVICE); 2097 2098 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]); 2099 2100 spin_lock_irqsave(&np->lock, flags); 2101 2102 if (!np->hands_off) { 2103 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len); 2104 /* StrongARM: Explicitly cache flush np->tx_ring and 2105 * skb->data,skb->len. */ 2106 wmb(); 2107 np->cur_tx++; 2108 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) { 2109 netdev_tx_done(dev); 2110 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) 2111 netif_stop_queue(dev); 2112 } 2113 /* Wake the potentially-idle transmit channel. */ 2114 writel(TxOn, ioaddr + ChipCmd); 2115 } else { 2116 dev_kfree_skb_irq(skb); 2117 dev->stats.tx_dropped++; 2118 } 2119 spin_unlock_irqrestore(&np->lock, flags); 2120 2121 if (netif_msg_tx_queued(np)) { 2122 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", 2123 dev->name, np->cur_tx, entry); 2124 } 2125 return NETDEV_TX_OK; 2126 } 2127 2128 static void netdev_tx_done(struct net_device *dev) 2129 { 2130 struct netdev_private *np = netdev_priv(dev); 2131 2132 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { 2133 int entry = np->dirty_tx % TX_RING_SIZE; 2134 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn)) 2135 break; 2136 if (netif_msg_tx_done(np)) 2137 printk(KERN_DEBUG 2138 "%s: tx frame #%d finished, status %#08x.\n", 2139 dev->name, np->dirty_tx, 2140 le32_to_cpu(np->tx_ring[entry].cmd_status)); 2141 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) { 2142 dev->stats.tx_packets++; 2143 dev->stats.tx_bytes += np->tx_skbuff[entry]->len; 2144 } else { /* Various Tx errors */ 2145 int tx_status = 2146 le32_to_cpu(np->tx_ring[entry].cmd_status); 2147 if (tx_status & (DescTxAbort|DescTxExcColl)) 2148 dev->stats.tx_aborted_errors++; 2149 if (tx_status & DescTxFIFO) 2150 dev->stats.tx_fifo_errors++; 2151 if (tx_status & DescTxCarrier) 2152 dev->stats.tx_carrier_errors++; 2153 if (tx_status & DescTxOOWCol) 2154 dev->stats.tx_window_errors++; 2155 dev->stats.tx_errors++; 2156 } 2157 pci_unmap_single(np->pci_dev,np->tx_dma[entry], 2158 np->tx_skbuff[entry]->len, 2159 PCI_DMA_TODEVICE); 2160 /* Free the original skb. */ 2161 dev_kfree_skb_irq(np->tx_skbuff[entry]); 2162 np->tx_skbuff[entry] = NULL; 2163 } 2164 if (netif_queue_stopped(dev) && 2165 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { 2166 /* The ring is no longer full, wake queue. */ 2167 netif_wake_queue(dev); 2168 } 2169 } 2170 2171 /* The interrupt handler doesn't actually handle interrupts itself, it 2172 * schedules a NAPI poll if there is anything to do. */ 2173 static irqreturn_t intr_handler(int irq, void *dev_instance) 2174 { 2175 struct net_device *dev = dev_instance; 2176 struct netdev_private *np = netdev_priv(dev); 2177 void __iomem * ioaddr = ns_ioaddr(dev); 2178 2179 /* Reading IntrStatus automatically acknowledges so don't do 2180 * that while interrupts are disabled, (for example, while a 2181 * poll is scheduled). */ 2182 if (np->hands_off || !readl(ioaddr + IntrEnable)) 2183 return IRQ_NONE; 2184 2185 np->intr_status = readl(ioaddr + IntrStatus); 2186 2187 if (!np->intr_status) 2188 return IRQ_NONE; 2189 2190 if (netif_msg_intr(np)) 2191 printk(KERN_DEBUG 2192 "%s: Interrupt, status %#08x, mask %#08x.\n", 2193 dev->name, np->intr_status, 2194 readl(ioaddr + IntrMask)); 2195 2196 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]); 2197 2198 if (napi_schedule_prep(&np->napi)) { 2199 /* Disable interrupts and register for poll */ 2200 natsemi_irq_disable(dev); 2201 __napi_schedule(&np->napi); 2202 } else 2203 printk(KERN_WARNING 2204 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n", 2205 dev->name, np->intr_status, 2206 readl(ioaddr + IntrMask)); 2207 2208 return IRQ_HANDLED; 2209 } 2210 2211 /* This is the NAPI poll routine. As well as the standard RX handling 2212 * it also handles all other interrupts that the chip might raise. 2213 */ 2214 static int natsemi_poll(struct napi_struct *napi, int budget) 2215 { 2216 struct netdev_private *np = container_of(napi, struct netdev_private, napi); 2217 struct net_device *dev = np->dev; 2218 void __iomem * ioaddr = ns_ioaddr(dev); 2219 int work_done = 0; 2220 2221 do { 2222 if (netif_msg_intr(np)) 2223 printk(KERN_DEBUG 2224 "%s: Poll, status %#08x, mask %#08x.\n", 2225 dev->name, np->intr_status, 2226 readl(ioaddr + IntrMask)); 2227 2228 /* netdev_rx() may read IntrStatus again if the RX state 2229 * machine falls over so do it first. */ 2230 if (np->intr_status & 2231 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver | 2232 IntrRxErr | IntrRxOverrun)) { 2233 netdev_rx(dev, &work_done, budget); 2234 } 2235 2236 if (np->intr_status & 2237 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) { 2238 spin_lock(&np->lock); 2239 netdev_tx_done(dev); 2240 spin_unlock(&np->lock); 2241 } 2242 2243 /* Abnormal error summary/uncommon events handlers. */ 2244 if (np->intr_status & IntrAbnormalSummary) 2245 netdev_error(dev, np->intr_status); 2246 2247 if (work_done >= budget) 2248 return work_done; 2249 2250 np->intr_status = readl(ioaddr + IntrStatus); 2251 } while (np->intr_status); 2252 2253 napi_complete(napi); 2254 2255 /* Reenable interrupts providing nothing is trying to shut 2256 * the chip down. */ 2257 spin_lock(&np->lock); 2258 if (!np->hands_off) 2259 natsemi_irq_enable(dev); 2260 spin_unlock(&np->lock); 2261 2262 return work_done; 2263 } 2264 2265 /* This routine is logically part of the interrupt handler, but separated 2266 for clarity and better register allocation. */ 2267 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do) 2268 { 2269 struct netdev_private *np = netdev_priv(dev); 2270 int entry = np->cur_rx % RX_RING_SIZE; 2271 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx; 2272 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2273 unsigned int buflen = np->rx_buf_sz; 2274 void __iomem * ioaddr = ns_ioaddr(dev); 2275 2276 /* If the driver owns the next entry it's a new packet. Send it up. */ 2277 while (desc_status < 0) { /* e.g. & DescOwn */ 2278 int pkt_len; 2279 if (netif_msg_rx_status(np)) 2280 printk(KERN_DEBUG 2281 " netdev_rx() entry %d status was %#08x.\n", 2282 entry, desc_status); 2283 if (--boguscnt < 0) 2284 break; 2285 2286 if (*work_done >= work_to_do) 2287 break; 2288 2289 (*work_done)++; 2290 2291 pkt_len = (desc_status & DescSizeMask) - 4; 2292 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){ 2293 if (desc_status & DescMore) { 2294 unsigned long flags; 2295 2296 if (netif_msg_rx_err(np)) 2297 printk(KERN_WARNING 2298 "%s: Oversized(?) Ethernet " 2299 "frame spanned multiple " 2300 "buffers, entry %#08x " 2301 "status %#08x.\n", dev->name, 2302 np->cur_rx, desc_status); 2303 dev->stats.rx_length_errors++; 2304 2305 /* The RX state machine has probably 2306 * locked up beneath us. Follow the 2307 * reset procedure documented in 2308 * AN-1287. */ 2309 2310 spin_lock_irqsave(&np->lock, flags); 2311 reset_rx(dev); 2312 reinit_rx(dev); 2313 writel(np->ring_dma, ioaddr + RxRingPtr); 2314 check_link(dev); 2315 spin_unlock_irqrestore(&np->lock, flags); 2316 2317 /* We'll enable RX on exit from this 2318 * function. */ 2319 break; 2320 2321 } else { 2322 /* There was an error. */ 2323 dev->stats.rx_errors++; 2324 if (desc_status & (DescRxAbort|DescRxOver)) 2325 dev->stats.rx_over_errors++; 2326 if (desc_status & (DescRxLong|DescRxRunt)) 2327 dev->stats.rx_length_errors++; 2328 if (desc_status & (DescRxInvalid|DescRxAlign)) 2329 dev->stats.rx_frame_errors++; 2330 if (desc_status & DescRxCRC) 2331 dev->stats.rx_crc_errors++; 2332 } 2333 } else if (pkt_len > np->rx_buf_sz) { 2334 /* if this is the tail of a double buffer 2335 * packet, we've already counted the error 2336 * on the first part. Ignore the second half. 2337 */ 2338 } else { 2339 struct sk_buff *skb; 2340 /* Omit CRC size. */ 2341 /* Check if the packet is long enough to accept 2342 * without copying to a minimally-sized skbuff. */ 2343 if (pkt_len < rx_copybreak && 2344 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) { 2345 /* 16 byte align the IP header */ 2346 skb_reserve(skb, RX_OFFSET); 2347 pci_dma_sync_single_for_cpu(np->pci_dev, 2348 np->rx_dma[entry], 2349 buflen, 2350 PCI_DMA_FROMDEVICE); 2351 skb_copy_to_linear_data(skb, 2352 np->rx_skbuff[entry]->data, pkt_len); 2353 skb_put(skb, pkt_len); 2354 pci_dma_sync_single_for_device(np->pci_dev, 2355 np->rx_dma[entry], 2356 buflen, 2357 PCI_DMA_FROMDEVICE); 2358 } else { 2359 pci_unmap_single(np->pci_dev, np->rx_dma[entry], 2360 buflen + NATSEMI_PADDING, 2361 PCI_DMA_FROMDEVICE); 2362 skb_put(skb = np->rx_skbuff[entry], pkt_len); 2363 np->rx_skbuff[entry] = NULL; 2364 } 2365 skb->protocol = eth_type_trans(skb, dev); 2366 netif_receive_skb(skb); 2367 dev->stats.rx_packets++; 2368 dev->stats.rx_bytes += pkt_len; 2369 } 2370 entry = (++np->cur_rx) % RX_RING_SIZE; 2371 np->rx_head_desc = &np->rx_ring[entry]; 2372 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2373 } 2374 refill_rx(dev); 2375 2376 /* Restart Rx engine if stopped. */ 2377 if (np->oom) 2378 mod_timer(&np->timer, jiffies + 1); 2379 else 2380 writel(RxOn, ioaddr + ChipCmd); 2381 } 2382 2383 static void netdev_error(struct net_device *dev, int intr_status) 2384 { 2385 struct netdev_private *np = netdev_priv(dev); 2386 void __iomem * ioaddr = ns_ioaddr(dev); 2387 2388 spin_lock(&np->lock); 2389 if (intr_status & LinkChange) { 2390 u16 lpa = mdio_read(dev, MII_LPA); 2391 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE && 2392 netif_msg_link(np)) { 2393 printk(KERN_INFO 2394 "%s: Autonegotiation advertising" 2395 " %#04x partner %#04x.\n", dev->name, 2396 np->advertising, lpa); 2397 } 2398 2399 /* read MII int status to clear the flag */ 2400 readw(ioaddr + MIntrStatus); 2401 check_link(dev); 2402 } 2403 if (intr_status & StatsMax) { 2404 __get_stats(dev); 2405 } 2406 if (intr_status & IntrTxUnderrun) { 2407 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) { 2408 np->tx_config += TX_DRTH_VAL_INC; 2409 if (netif_msg_tx_err(np)) 2410 printk(KERN_NOTICE 2411 "%s: increased tx threshold, txcfg %#08x.\n", 2412 dev->name, np->tx_config); 2413 } else { 2414 if (netif_msg_tx_err(np)) 2415 printk(KERN_NOTICE 2416 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n", 2417 dev->name, np->tx_config); 2418 } 2419 writel(np->tx_config, ioaddr + TxConfig); 2420 } 2421 if (intr_status & WOLPkt && netif_msg_wol(np)) { 2422 int wol_status = readl(ioaddr + WOLCmd); 2423 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n", 2424 dev->name, wol_status); 2425 } 2426 if (intr_status & RxStatusFIFOOver) { 2427 if (netif_msg_rx_err(np) && netif_msg_intr(np)) { 2428 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n", 2429 dev->name); 2430 } 2431 dev->stats.rx_fifo_errors++; 2432 dev->stats.rx_errors++; 2433 } 2434 /* Hmmmmm, it's not clear how to recover from PCI faults. */ 2435 if (intr_status & IntrPCIErr) { 2436 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name, 2437 intr_status & IntrPCIErr); 2438 dev->stats.tx_fifo_errors++; 2439 dev->stats.tx_errors++; 2440 dev->stats.rx_fifo_errors++; 2441 dev->stats.rx_errors++; 2442 } 2443 spin_unlock(&np->lock); 2444 } 2445 2446 static void __get_stats(struct net_device *dev) 2447 { 2448 void __iomem * ioaddr = ns_ioaddr(dev); 2449 2450 /* The chip only need report frame silently dropped. */ 2451 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs); 2452 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed); 2453 } 2454 2455 static struct net_device_stats *get_stats(struct net_device *dev) 2456 { 2457 struct netdev_private *np = netdev_priv(dev); 2458 2459 /* The chip only need report frame silently dropped. */ 2460 spin_lock_irq(&np->lock); 2461 if (netif_running(dev) && !np->hands_off) 2462 __get_stats(dev); 2463 spin_unlock_irq(&np->lock); 2464 2465 return &dev->stats; 2466 } 2467 2468 #ifdef CONFIG_NET_POLL_CONTROLLER 2469 static void natsemi_poll_controller(struct net_device *dev) 2470 { 2471 struct netdev_private *np = netdev_priv(dev); 2472 const int irq = np->pci_dev->irq; 2473 2474 disable_irq(irq); 2475 intr_handler(irq, dev); 2476 enable_irq(irq); 2477 } 2478 #endif 2479 2480 #define HASH_TABLE 0x200 2481 static void __set_rx_mode(struct net_device *dev) 2482 { 2483 void __iomem * ioaddr = ns_ioaddr(dev); 2484 struct netdev_private *np = netdev_priv(dev); 2485 u8 mc_filter[64]; /* Multicast hash filter */ 2486 u32 rx_mode; 2487 2488 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 2489 rx_mode = RxFilterEnable | AcceptBroadcast 2490 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys; 2491 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2492 (dev->flags & IFF_ALLMULTI)) { 2493 rx_mode = RxFilterEnable | AcceptBroadcast 2494 | AcceptAllMulticast | AcceptMyPhys; 2495 } else { 2496 struct netdev_hw_addr *ha; 2497 int i; 2498 2499 memset(mc_filter, 0, sizeof(mc_filter)); 2500 netdev_for_each_mc_addr(ha, dev) { 2501 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff; 2502 mc_filter[b/8] |= (1 << (b & 0x07)); 2503 } 2504 rx_mode = RxFilterEnable | AcceptBroadcast 2505 | AcceptMulticast | AcceptMyPhys; 2506 for (i = 0; i < 64; i += 2) { 2507 writel(HASH_TABLE + i, ioaddr + RxFilterAddr); 2508 writel((mc_filter[i + 1] << 8) + mc_filter[i], 2509 ioaddr + RxFilterData); 2510 } 2511 } 2512 writel(rx_mode, ioaddr + RxFilterAddr); 2513 np->cur_rx_mode = rx_mode; 2514 } 2515 2516 static int natsemi_change_mtu(struct net_device *dev, int new_mtu) 2517 { 2518 if (new_mtu < 64 || new_mtu > NATSEMI_RX_LIMIT-NATSEMI_HEADERS) 2519 return -EINVAL; 2520 2521 dev->mtu = new_mtu; 2522 2523 /* synchronized against open : rtnl_lock() held by caller */ 2524 if (netif_running(dev)) { 2525 struct netdev_private *np = netdev_priv(dev); 2526 void __iomem * ioaddr = ns_ioaddr(dev); 2527 const int irq = np->pci_dev->irq; 2528 2529 disable_irq(irq); 2530 spin_lock(&np->lock); 2531 /* stop engines */ 2532 natsemi_stop_rxtx(dev); 2533 /* drain rx queue */ 2534 drain_rx(dev); 2535 /* change buffers */ 2536 set_bufsize(dev); 2537 reinit_rx(dev); 2538 writel(np->ring_dma, ioaddr + RxRingPtr); 2539 /* restart engines */ 2540 writel(RxOn | TxOn, ioaddr + ChipCmd); 2541 spin_unlock(&np->lock); 2542 enable_irq(irq); 2543 } 2544 return 0; 2545 } 2546 2547 static void set_rx_mode(struct net_device *dev) 2548 { 2549 struct netdev_private *np = netdev_priv(dev); 2550 spin_lock_irq(&np->lock); 2551 if (!np->hands_off) 2552 __set_rx_mode(dev); 2553 spin_unlock_irq(&np->lock); 2554 } 2555 2556 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2557 { 2558 struct netdev_private *np = netdev_priv(dev); 2559 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2560 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2561 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 2562 } 2563 2564 static int get_regs_len(struct net_device *dev) 2565 { 2566 return NATSEMI_REGS_SIZE; 2567 } 2568 2569 static int get_eeprom_len(struct net_device *dev) 2570 { 2571 struct netdev_private *np = netdev_priv(dev); 2572 return np->eeprom_size; 2573 } 2574 2575 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2576 { 2577 struct netdev_private *np = netdev_priv(dev); 2578 spin_lock_irq(&np->lock); 2579 netdev_get_ecmd(dev, ecmd); 2580 spin_unlock_irq(&np->lock); 2581 return 0; 2582 } 2583 2584 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd) 2585 { 2586 struct netdev_private *np = netdev_priv(dev); 2587 int res; 2588 spin_lock_irq(&np->lock); 2589 res = netdev_set_ecmd(dev, ecmd); 2590 spin_unlock_irq(&np->lock); 2591 return res; 2592 } 2593 2594 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2595 { 2596 struct netdev_private *np = netdev_priv(dev); 2597 spin_lock_irq(&np->lock); 2598 netdev_get_wol(dev, &wol->supported, &wol->wolopts); 2599 netdev_get_sopass(dev, wol->sopass); 2600 spin_unlock_irq(&np->lock); 2601 } 2602 2603 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2604 { 2605 struct netdev_private *np = netdev_priv(dev); 2606 int res; 2607 spin_lock_irq(&np->lock); 2608 netdev_set_wol(dev, wol->wolopts); 2609 res = netdev_set_sopass(dev, wol->sopass); 2610 spin_unlock_irq(&np->lock); 2611 return res; 2612 } 2613 2614 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) 2615 { 2616 struct netdev_private *np = netdev_priv(dev); 2617 regs->version = NATSEMI_REGS_VER; 2618 spin_lock_irq(&np->lock); 2619 netdev_get_regs(dev, buf); 2620 spin_unlock_irq(&np->lock); 2621 } 2622 2623 static u32 get_msglevel(struct net_device *dev) 2624 { 2625 struct netdev_private *np = netdev_priv(dev); 2626 return np->msg_enable; 2627 } 2628 2629 static void set_msglevel(struct net_device *dev, u32 val) 2630 { 2631 struct netdev_private *np = netdev_priv(dev); 2632 np->msg_enable = val; 2633 } 2634 2635 static int nway_reset(struct net_device *dev) 2636 { 2637 int tmp; 2638 int r = -EINVAL; 2639 /* if autoneg is off, it's an error */ 2640 tmp = mdio_read(dev, MII_BMCR); 2641 if (tmp & BMCR_ANENABLE) { 2642 tmp |= (BMCR_ANRESTART); 2643 mdio_write(dev, MII_BMCR, tmp); 2644 r = 0; 2645 } 2646 return r; 2647 } 2648 2649 static u32 get_link(struct net_device *dev) 2650 { 2651 /* LSTATUS is latched low until a read - so read twice */ 2652 mdio_read(dev, MII_BMSR); 2653 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0; 2654 } 2655 2656 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) 2657 { 2658 struct netdev_private *np = netdev_priv(dev); 2659 u8 *eebuf; 2660 int res; 2661 2662 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL); 2663 if (!eebuf) 2664 return -ENOMEM; 2665 2666 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16); 2667 spin_lock_irq(&np->lock); 2668 res = netdev_get_eeprom(dev, eebuf); 2669 spin_unlock_irq(&np->lock); 2670 if (!res) 2671 memcpy(data, eebuf+eeprom->offset, eeprom->len); 2672 kfree(eebuf); 2673 return res; 2674 } 2675 2676 static const struct ethtool_ops ethtool_ops = { 2677 .get_drvinfo = get_drvinfo, 2678 .get_regs_len = get_regs_len, 2679 .get_eeprom_len = get_eeprom_len, 2680 .get_settings = get_settings, 2681 .set_settings = set_settings, 2682 .get_wol = get_wol, 2683 .set_wol = set_wol, 2684 .get_regs = get_regs, 2685 .get_msglevel = get_msglevel, 2686 .set_msglevel = set_msglevel, 2687 .nway_reset = nway_reset, 2688 .get_link = get_link, 2689 .get_eeprom = get_eeprom, 2690 }; 2691 2692 static int netdev_set_wol(struct net_device *dev, u32 newval) 2693 { 2694 struct netdev_private *np = netdev_priv(dev); 2695 void __iomem * ioaddr = ns_ioaddr(dev); 2696 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary; 2697 2698 /* translate to bitmasks this chip understands */ 2699 if (newval & WAKE_PHY) 2700 data |= WakePhy; 2701 if (newval & WAKE_UCAST) 2702 data |= WakeUnicast; 2703 if (newval & WAKE_MCAST) 2704 data |= WakeMulticast; 2705 if (newval & WAKE_BCAST) 2706 data |= WakeBroadcast; 2707 if (newval & WAKE_ARP) 2708 data |= WakeArp; 2709 if (newval & WAKE_MAGIC) 2710 data |= WakeMagic; 2711 if (np->srr >= SRR_DP83815_D) { 2712 if (newval & WAKE_MAGICSECURE) { 2713 data |= WakeMagicSecure; 2714 } 2715 } 2716 2717 writel(data, ioaddr + WOLCmd); 2718 2719 return 0; 2720 } 2721 2722 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur) 2723 { 2724 struct netdev_private *np = netdev_priv(dev); 2725 void __iomem * ioaddr = ns_ioaddr(dev); 2726 u32 regval = readl(ioaddr + WOLCmd); 2727 2728 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST 2729 | WAKE_ARP | WAKE_MAGIC); 2730 2731 if (np->srr >= SRR_DP83815_D) { 2732 /* SOPASS works on revD and higher */ 2733 *supported |= WAKE_MAGICSECURE; 2734 } 2735 *cur = 0; 2736 2737 /* translate from chip bitmasks */ 2738 if (regval & WakePhy) 2739 *cur |= WAKE_PHY; 2740 if (regval & WakeUnicast) 2741 *cur |= WAKE_UCAST; 2742 if (regval & WakeMulticast) 2743 *cur |= WAKE_MCAST; 2744 if (regval & WakeBroadcast) 2745 *cur |= WAKE_BCAST; 2746 if (regval & WakeArp) 2747 *cur |= WAKE_ARP; 2748 if (regval & WakeMagic) 2749 *cur |= WAKE_MAGIC; 2750 if (regval & WakeMagicSecure) { 2751 /* this can be on in revC, but it's broken */ 2752 *cur |= WAKE_MAGICSECURE; 2753 } 2754 2755 return 0; 2756 } 2757 2758 static int netdev_set_sopass(struct net_device *dev, u8 *newval) 2759 { 2760 struct netdev_private *np = netdev_priv(dev); 2761 void __iomem * ioaddr = ns_ioaddr(dev); 2762 u16 *sval = (u16 *)newval; 2763 u32 addr; 2764 2765 if (np->srr < SRR_DP83815_D) { 2766 return 0; 2767 } 2768 2769 /* enable writing to these registers by disabling the RX filter */ 2770 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2771 addr &= ~RxFilterEnable; 2772 writel(addr, ioaddr + RxFilterAddr); 2773 2774 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2775 writel(addr | 0xa, ioaddr + RxFilterAddr); 2776 writew(sval[0], ioaddr + RxFilterData); 2777 2778 writel(addr | 0xc, ioaddr + RxFilterAddr); 2779 writew(sval[1], ioaddr + RxFilterData); 2780 2781 writel(addr | 0xe, ioaddr + RxFilterAddr); 2782 writew(sval[2], ioaddr + RxFilterData); 2783 2784 /* re-enable the RX filter */ 2785 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr); 2786 2787 return 0; 2788 } 2789 2790 static int netdev_get_sopass(struct net_device *dev, u8 *data) 2791 { 2792 struct netdev_private *np = netdev_priv(dev); 2793 void __iomem * ioaddr = ns_ioaddr(dev); 2794 u16 *sval = (u16 *)data; 2795 u32 addr; 2796 2797 if (np->srr < SRR_DP83815_D) { 2798 sval[0] = sval[1] = sval[2] = 0; 2799 return 0; 2800 } 2801 2802 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2803 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2804 2805 writel(addr | 0xa, ioaddr + RxFilterAddr); 2806 sval[0] = readw(ioaddr + RxFilterData); 2807 2808 writel(addr | 0xc, ioaddr + RxFilterAddr); 2809 sval[1] = readw(ioaddr + RxFilterData); 2810 2811 writel(addr | 0xe, ioaddr + RxFilterAddr); 2812 sval[2] = readw(ioaddr + RxFilterData); 2813 2814 writel(addr, ioaddr + RxFilterAddr); 2815 2816 return 0; 2817 } 2818 2819 static int netdev_get_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) 2820 { 2821 struct netdev_private *np = netdev_priv(dev); 2822 u32 tmp; 2823 2824 ecmd->port = dev->if_port; 2825 ethtool_cmd_speed_set(ecmd, np->speed); 2826 ecmd->duplex = np->duplex; 2827 ecmd->autoneg = np->autoneg; 2828 ecmd->advertising = 0; 2829 if (np->advertising & ADVERTISE_10HALF) 2830 ecmd->advertising |= ADVERTISED_10baseT_Half; 2831 if (np->advertising & ADVERTISE_10FULL) 2832 ecmd->advertising |= ADVERTISED_10baseT_Full; 2833 if (np->advertising & ADVERTISE_100HALF) 2834 ecmd->advertising |= ADVERTISED_100baseT_Half; 2835 if (np->advertising & ADVERTISE_100FULL) 2836 ecmd->advertising |= ADVERTISED_100baseT_Full; 2837 ecmd->supported = (SUPPORTED_Autoneg | 2838 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2839 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2840 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE); 2841 ecmd->phy_address = np->phy_addr_external; 2842 /* 2843 * We intentionally report the phy address of the external 2844 * phy, even if the internal phy is used. This is necessary 2845 * to work around a deficiency of the ethtool interface: 2846 * It's only possible to query the settings of the active 2847 * port. Therefore 2848 * # ethtool -s ethX port mii 2849 * actually sends an ioctl to switch to port mii with the 2850 * settings that are used for the current active port. 2851 * If we would report a different phy address in this 2852 * command, then 2853 * # ethtool -s ethX port tp;ethtool -s ethX port mii 2854 * would unintentionally change the phy address. 2855 * 2856 * Fortunately the phy address doesn't matter with the 2857 * internal phy... 2858 */ 2859 2860 /* set information based on active port type */ 2861 switch (ecmd->port) { 2862 default: 2863 case PORT_TP: 2864 ecmd->advertising |= ADVERTISED_TP; 2865 ecmd->transceiver = XCVR_INTERNAL; 2866 break; 2867 case PORT_MII: 2868 ecmd->advertising |= ADVERTISED_MII; 2869 ecmd->transceiver = XCVR_EXTERNAL; 2870 break; 2871 case PORT_FIBRE: 2872 ecmd->advertising |= ADVERTISED_FIBRE; 2873 ecmd->transceiver = XCVR_EXTERNAL; 2874 break; 2875 } 2876 2877 /* if autonegotiation is on, try to return the active speed/duplex */ 2878 if (ecmd->autoneg == AUTONEG_ENABLE) { 2879 ecmd->advertising |= ADVERTISED_Autoneg; 2880 tmp = mii_nway_result( 2881 np->advertising & mdio_read(dev, MII_LPA)); 2882 if (tmp == LPA_100FULL || tmp == LPA_100HALF) 2883 ethtool_cmd_speed_set(ecmd, SPEED_100); 2884 else 2885 ethtool_cmd_speed_set(ecmd, SPEED_10); 2886 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 2887 ecmd->duplex = DUPLEX_FULL; 2888 else 2889 ecmd->duplex = DUPLEX_HALF; 2890 } 2891 2892 /* ignore maxtxpkt, maxrxpkt for now */ 2893 2894 return 0; 2895 } 2896 2897 static int netdev_set_ecmd(struct net_device *dev, struct ethtool_cmd *ecmd) 2898 { 2899 struct netdev_private *np = netdev_priv(dev); 2900 2901 if (ecmd->port != PORT_TP && ecmd->port != PORT_MII && ecmd->port != PORT_FIBRE) 2902 return -EINVAL; 2903 if (ecmd->transceiver != XCVR_INTERNAL && ecmd->transceiver != XCVR_EXTERNAL) 2904 return -EINVAL; 2905 if (ecmd->autoneg == AUTONEG_ENABLE) { 2906 if ((ecmd->advertising & (ADVERTISED_10baseT_Half | 2907 ADVERTISED_10baseT_Full | 2908 ADVERTISED_100baseT_Half | 2909 ADVERTISED_100baseT_Full)) == 0) { 2910 return -EINVAL; 2911 } 2912 } else if (ecmd->autoneg == AUTONEG_DISABLE) { 2913 u32 speed = ethtool_cmd_speed(ecmd); 2914 if (speed != SPEED_10 && speed != SPEED_100) 2915 return -EINVAL; 2916 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL) 2917 return -EINVAL; 2918 } else { 2919 return -EINVAL; 2920 } 2921 2922 /* 2923 * If we're ignoring the PHY then autoneg and the internal 2924 * transceiver are really not going to work so don't let the 2925 * user select them. 2926 */ 2927 if (np->ignore_phy && (ecmd->autoneg == AUTONEG_ENABLE || 2928 ecmd->port == PORT_TP)) 2929 return -EINVAL; 2930 2931 /* 2932 * maxtxpkt, maxrxpkt: ignored for now. 2933 * 2934 * transceiver: 2935 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always 2936 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and 2937 * selects based on ecmd->port. 2938 * 2939 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre 2940 * phys that are connected to the mii bus. It's used to apply fibre 2941 * specific updates. 2942 */ 2943 2944 /* WHEW! now lets bang some bits */ 2945 2946 /* save the parms */ 2947 dev->if_port = ecmd->port; 2948 np->autoneg = ecmd->autoneg; 2949 np->phy_addr_external = ecmd->phy_address & PhyAddrMask; 2950 if (np->autoneg == AUTONEG_ENABLE) { 2951 /* advertise only what has been requested */ 2952 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 2953 if (ecmd->advertising & ADVERTISED_10baseT_Half) 2954 np->advertising |= ADVERTISE_10HALF; 2955 if (ecmd->advertising & ADVERTISED_10baseT_Full) 2956 np->advertising |= ADVERTISE_10FULL; 2957 if (ecmd->advertising & ADVERTISED_100baseT_Half) 2958 np->advertising |= ADVERTISE_100HALF; 2959 if (ecmd->advertising & ADVERTISED_100baseT_Full) 2960 np->advertising |= ADVERTISE_100FULL; 2961 } else { 2962 np->speed = ethtool_cmd_speed(ecmd); 2963 np->duplex = ecmd->duplex; 2964 /* user overriding the initial full duplex parm? */ 2965 if (np->duplex == DUPLEX_HALF) 2966 np->full_duplex = 0; 2967 } 2968 2969 /* get the right phy enabled */ 2970 if (ecmd->port == PORT_TP) 2971 switch_port_internal(dev); 2972 else 2973 switch_port_external(dev); 2974 2975 /* set parms and see how this affected our link status */ 2976 init_phy_fixup(dev); 2977 check_link(dev); 2978 return 0; 2979 } 2980 2981 static int netdev_get_regs(struct net_device *dev, u8 *buf) 2982 { 2983 int i; 2984 int j; 2985 u32 rfcr; 2986 u32 *rbuf = (u32 *)buf; 2987 void __iomem * ioaddr = ns_ioaddr(dev); 2988 2989 /* read non-mii page 0 of registers */ 2990 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) { 2991 rbuf[i] = readl(ioaddr + i*4); 2992 } 2993 2994 /* read current mii registers */ 2995 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++) 2996 rbuf[i] = mdio_read(dev, i & 0x1f); 2997 2998 /* read only the 'magic' registers from page 1 */ 2999 writew(1, ioaddr + PGSEL); 3000 rbuf[i++] = readw(ioaddr + PMDCSR); 3001 rbuf[i++] = readw(ioaddr + TSTDAT); 3002 rbuf[i++] = readw(ioaddr + DSPCFG); 3003 rbuf[i++] = readw(ioaddr + SDCFG); 3004 writew(0, ioaddr + PGSEL); 3005 3006 /* read RFCR indexed registers */ 3007 rfcr = readl(ioaddr + RxFilterAddr); 3008 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) { 3009 writel(j*2, ioaddr + RxFilterAddr); 3010 rbuf[i++] = readw(ioaddr + RxFilterData); 3011 } 3012 writel(rfcr, ioaddr + RxFilterAddr); 3013 3014 /* the interrupt status is clear-on-read - see if we missed any */ 3015 if (rbuf[4] & rbuf[5]) { 3016 printk(KERN_WARNING 3017 "%s: shoot, we dropped an interrupt (%#08x)\n", 3018 dev->name, rbuf[4] & rbuf[5]); 3019 } 3020 3021 return 0; 3022 } 3023 3024 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \ 3025 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \ 3026 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \ 3027 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \ 3028 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \ 3029 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \ 3030 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \ 3031 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) ) 3032 3033 static int netdev_get_eeprom(struct net_device *dev, u8 *buf) 3034 { 3035 int i; 3036 u16 *ebuf = (u16 *)buf; 3037 void __iomem * ioaddr = ns_ioaddr(dev); 3038 struct netdev_private *np = netdev_priv(dev); 3039 3040 /* eeprom_read reads 16 bits, and indexes by 16 bits */ 3041 for (i = 0; i < np->eeprom_size/2; i++) { 3042 ebuf[i] = eeprom_read(ioaddr, i); 3043 /* The EEPROM itself stores data bit-swapped, but eeprom_read 3044 * reads it back "sanely". So we swap it back here in order to 3045 * present it to userland as it is stored. */ 3046 ebuf[i] = SWAP_BITS(ebuf[i]); 3047 } 3048 return 0; 3049 } 3050 3051 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3052 { 3053 struct mii_ioctl_data *data = if_mii(rq); 3054 struct netdev_private *np = netdev_priv(dev); 3055 3056 switch(cmd) { 3057 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 3058 data->phy_id = np->phy_addr_external; 3059 /* Fall Through */ 3060 3061 case SIOCGMIIREG: /* Read MII PHY register. */ 3062 /* The phy_id is not enough to uniquely identify 3063 * the intended target. Therefore the command is sent to 3064 * the given mii on the current port. 3065 */ 3066 if (dev->if_port == PORT_TP) { 3067 if ((data->phy_id & 0x1f) == np->phy_addr_external) 3068 data->val_out = mdio_read(dev, 3069 data->reg_num & 0x1f); 3070 else 3071 data->val_out = 0; 3072 } else { 3073 move_int_phy(dev, data->phy_id & 0x1f); 3074 data->val_out = miiport_read(dev, data->phy_id & 0x1f, 3075 data->reg_num & 0x1f); 3076 } 3077 return 0; 3078 3079 case SIOCSMIIREG: /* Write MII PHY register. */ 3080 if (dev->if_port == PORT_TP) { 3081 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3082 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3083 np->advertising = data->val_in; 3084 mdio_write(dev, data->reg_num & 0x1f, 3085 data->val_in); 3086 } 3087 } else { 3088 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3089 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3090 np->advertising = data->val_in; 3091 } 3092 move_int_phy(dev, data->phy_id & 0x1f); 3093 miiport_write(dev, data->phy_id & 0x1f, 3094 data->reg_num & 0x1f, 3095 data->val_in); 3096 } 3097 return 0; 3098 default: 3099 return -EOPNOTSUPP; 3100 } 3101 } 3102 3103 static void enable_wol_mode(struct net_device *dev, int enable_intr) 3104 { 3105 void __iomem * ioaddr = ns_ioaddr(dev); 3106 struct netdev_private *np = netdev_priv(dev); 3107 3108 if (netif_msg_wol(np)) 3109 printk(KERN_INFO "%s: remaining active for wake-on-lan\n", 3110 dev->name); 3111 3112 /* For WOL we must restart the rx process in silent mode. 3113 * Write NULL to the RxRingPtr. Only possible if 3114 * rx process is stopped 3115 */ 3116 writel(0, ioaddr + RxRingPtr); 3117 3118 /* read WoL status to clear */ 3119 readl(ioaddr + WOLCmd); 3120 3121 /* PME on, clear status */ 3122 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun); 3123 3124 /* and restart the rx process */ 3125 writel(RxOn, ioaddr + ChipCmd); 3126 3127 if (enable_intr) { 3128 /* enable the WOL interrupt. 3129 * Could be used to send a netlink message. 3130 */ 3131 writel(WOLPkt | LinkChange, ioaddr + IntrMask); 3132 natsemi_irq_enable(dev); 3133 } 3134 } 3135 3136 static int netdev_close(struct net_device *dev) 3137 { 3138 void __iomem * ioaddr = ns_ioaddr(dev); 3139 struct netdev_private *np = netdev_priv(dev); 3140 const int irq = np->pci_dev->irq; 3141 3142 if (netif_msg_ifdown(np)) 3143 printk(KERN_DEBUG 3144 "%s: Shutting down ethercard, status was %#04x.\n", 3145 dev->name, (int)readl(ioaddr + ChipCmd)); 3146 if (netif_msg_pktdata(np)) 3147 printk(KERN_DEBUG 3148 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 3149 dev->name, np->cur_tx, np->dirty_tx, 3150 np->cur_rx, np->dirty_rx); 3151 3152 napi_disable(&np->napi); 3153 3154 /* 3155 * FIXME: what if someone tries to close a device 3156 * that is suspended? 3157 * Should we reenable the nic to switch to 3158 * the final WOL settings? 3159 */ 3160 3161 del_timer_sync(&np->timer); 3162 disable_irq(irq); 3163 spin_lock_irq(&np->lock); 3164 natsemi_irq_disable(dev); 3165 np->hands_off = 1; 3166 spin_unlock_irq(&np->lock); 3167 enable_irq(irq); 3168 3169 free_irq(irq, dev); 3170 3171 /* Interrupt disabled, interrupt handler released, 3172 * queue stopped, timer deleted, rtnl_lock held 3173 * All async codepaths that access the driver are disabled. 3174 */ 3175 spin_lock_irq(&np->lock); 3176 np->hands_off = 0; 3177 readl(ioaddr + IntrMask); 3178 readw(ioaddr + MIntrStatus); 3179 3180 /* Freeze Stats */ 3181 writel(StatsFreeze, ioaddr + StatsCtrl); 3182 3183 /* Stop the chip's Tx and Rx processes. */ 3184 natsemi_stop_rxtx(dev); 3185 3186 __get_stats(dev); 3187 spin_unlock_irq(&np->lock); 3188 3189 /* clear the carrier last - an interrupt could reenable it otherwise */ 3190 netif_carrier_off(dev); 3191 netif_stop_queue(dev); 3192 3193 dump_ring(dev); 3194 drain_ring(dev); 3195 free_ring(dev); 3196 3197 { 3198 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3199 if (wol) { 3200 /* restart the NIC in WOL mode. 3201 * The nic must be stopped for this. 3202 */ 3203 enable_wol_mode(dev, 0); 3204 } else { 3205 /* Restore PME enable bit unmolested */ 3206 writel(np->SavedClkRun, ioaddr + ClkRun); 3207 } 3208 } 3209 return 0; 3210 } 3211 3212 3213 static void natsemi_remove1(struct pci_dev *pdev) 3214 { 3215 struct net_device *dev = pci_get_drvdata(pdev); 3216 void __iomem * ioaddr = ns_ioaddr(dev); 3217 3218 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround); 3219 unregister_netdev (dev); 3220 pci_release_regions (pdev); 3221 iounmap(ioaddr); 3222 free_netdev (dev); 3223 pci_set_drvdata(pdev, NULL); 3224 } 3225 3226 #ifdef CONFIG_PM 3227 3228 /* 3229 * The ns83815 chip doesn't have explicit RxStop bits. 3230 * Kicking the Rx or Tx process for a new packet reenables the Rx process 3231 * of the nic, thus this function must be very careful: 3232 * 3233 * suspend/resume synchronization: 3234 * entry points: 3235 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler, 3236 * start_tx, ns_tx_timeout 3237 * 3238 * No function accesses the hardware without checking np->hands_off. 3239 * the check occurs under spin_lock_irq(&np->lock); 3240 * exceptions: 3241 * * netdev_ioctl: noncritical access. 3242 * * netdev_open: cannot happen due to the device_detach 3243 * * netdev_close: doesn't hurt. 3244 * * netdev_timer: timer stopped by natsemi_suspend. 3245 * * intr_handler: doesn't acquire the spinlock. suspend calls 3246 * disable_irq() to enforce synchronization. 3247 * * natsemi_poll: checks before reenabling interrupts. suspend 3248 * sets hands_off, disables interrupts and then waits with 3249 * napi_disable(). 3250 * 3251 * Interrupts must be disabled, otherwise hands_off can cause irq storms. 3252 */ 3253 3254 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state) 3255 { 3256 struct net_device *dev = pci_get_drvdata (pdev); 3257 struct netdev_private *np = netdev_priv(dev); 3258 void __iomem * ioaddr = ns_ioaddr(dev); 3259 3260 rtnl_lock(); 3261 if (netif_running (dev)) { 3262 const int irq = np->pci_dev->irq; 3263 3264 del_timer_sync(&np->timer); 3265 3266 disable_irq(irq); 3267 spin_lock_irq(&np->lock); 3268 3269 natsemi_irq_disable(dev); 3270 np->hands_off = 1; 3271 natsemi_stop_rxtx(dev); 3272 netif_stop_queue(dev); 3273 3274 spin_unlock_irq(&np->lock); 3275 enable_irq(irq); 3276 3277 napi_disable(&np->napi); 3278 3279 /* Update the error counts. */ 3280 __get_stats(dev); 3281 3282 /* pci_power_off(pdev, -1); */ 3283 drain_ring(dev); 3284 { 3285 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3286 /* Restore PME enable bit */ 3287 if (wol) { 3288 /* restart the NIC in WOL mode. 3289 * The nic must be stopped for this. 3290 * FIXME: use the WOL interrupt 3291 */ 3292 enable_wol_mode(dev, 0); 3293 } else { 3294 /* Restore PME enable bit unmolested */ 3295 writel(np->SavedClkRun, ioaddr + ClkRun); 3296 } 3297 } 3298 } 3299 netif_device_detach(dev); 3300 rtnl_unlock(); 3301 return 0; 3302 } 3303 3304 3305 static int natsemi_resume (struct pci_dev *pdev) 3306 { 3307 struct net_device *dev = pci_get_drvdata (pdev); 3308 struct netdev_private *np = netdev_priv(dev); 3309 int ret = 0; 3310 3311 rtnl_lock(); 3312 if (netif_device_present(dev)) 3313 goto out; 3314 if (netif_running(dev)) { 3315 const int irq = np->pci_dev->irq; 3316 3317 BUG_ON(!np->hands_off); 3318 ret = pci_enable_device(pdev); 3319 if (ret < 0) { 3320 dev_err(&pdev->dev, 3321 "pci_enable_device() failed: %d\n", ret); 3322 goto out; 3323 } 3324 /* pci_power_on(pdev); */ 3325 3326 napi_enable(&np->napi); 3327 3328 natsemi_reset(dev); 3329 init_ring(dev); 3330 disable_irq(irq); 3331 spin_lock_irq(&np->lock); 3332 np->hands_off = 0; 3333 init_registers(dev); 3334 netif_device_attach(dev); 3335 spin_unlock_irq(&np->lock); 3336 enable_irq(irq); 3337 3338 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ)); 3339 } 3340 netif_device_attach(dev); 3341 out: 3342 rtnl_unlock(); 3343 return ret; 3344 } 3345 3346 #endif /* CONFIG_PM */ 3347 3348 static struct pci_driver natsemi_driver = { 3349 .name = DRV_NAME, 3350 .id_table = natsemi_pci_tbl, 3351 .probe = natsemi_probe1, 3352 .remove = natsemi_remove1, 3353 #ifdef CONFIG_PM 3354 .suspend = natsemi_suspend, 3355 .resume = natsemi_resume, 3356 #endif 3357 }; 3358 3359 static int __init natsemi_init_mod (void) 3360 { 3361 /* when a module, this is printed whether or not devices are found in probe */ 3362 #ifdef MODULE 3363 printk(version); 3364 #endif 3365 3366 return pci_register_driver(&natsemi_driver); 3367 } 3368 3369 static void __exit natsemi_exit_mod (void) 3370 { 3371 pci_unregister_driver (&natsemi_driver); 3372 } 3373 3374 module_init(natsemi_init_mod); 3375 module_exit(natsemi_exit_mod); 3376 3377