1 /* natsemi.c: A Linux PCI Ethernet driver for the NatSemi DP8381x series. */ 2 /* 3 Written/copyright 1999-2001 by Donald Becker. 4 Portions copyright (c) 2001,2002 Sun Microsystems (thockin@sun.com) 5 Portions copyright 2001,2002 Manfred Spraul (manfred@colorfullife.com) 6 Portions copyright 2004 Harald Welte <laforge@gnumonks.org> 7 8 This software may be used and distributed according to the terms of 9 the GNU General Public License (GPL), incorporated herein by reference. 10 Drivers based on or derived from this code fall under the GPL and must 11 retain the authorship, copyright and license notice. This file is not 12 a complete program and may only be used when the entire operating 13 system is licensed under the GPL. License for under other terms may be 14 available. Contact the original author for details. 15 16 The original author may be reached as becker@scyld.com, or at 17 Scyld Computing Corporation 18 410 Severn Ave., Suite 210 19 Annapolis MD 21403 20 21 Support information and updates available at 22 http://www.scyld.com/network/netsemi.html 23 [link no longer provides useful info -jgarzik] 24 25 26 TODO: 27 * big endian support with CFG:BEM instead of cpu_to_le32 28 */ 29 30 #include <linux/module.h> 31 #include <linux/kernel.h> 32 #include <linux/string.h> 33 #include <linux/timer.h> 34 #include <linux/errno.h> 35 #include <linux/ioport.h> 36 #include <linux/slab.h> 37 #include <linux/interrupt.h> 38 #include <linux/pci.h> 39 #include <linux/netdevice.h> 40 #include <linux/etherdevice.h> 41 #include <linux/skbuff.h> 42 #include <linux/init.h> 43 #include <linux/spinlock.h> 44 #include <linux/ethtool.h> 45 #include <linux/delay.h> 46 #include <linux/rtnetlink.h> 47 #include <linux/mii.h> 48 #include <linux/crc32.h> 49 #include <linux/bitops.h> 50 #include <linux/prefetch.h> 51 #include <asm/processor.h> /* Processor type for cache alignment. */ 52 #include <asm/io.h> 53 #include <asm/irq.h> 54 #include <linux/uaccess.h> 55 56 #define DRV_NAME "natsemi" 57 #define DRV_VERSION "2.1" 58 #define DRV_RELDATE "Sept 11, 2006" 59 60 #define RX_OFFSET 2 61 62 /* Updated to recommendations in pci-skeleton v2.03. */ 63 64 /* The user-configurable values. 65 These may be modified when a driver module is loaded.*/ 66 67 #define NATSEMI_DEF_MSG (NETIF_MSG_DRV | \ 68 NETIF_MSG_LINK | \ 69 NETIF_MSG_WOL | \ 70 NETIF_MSG_RX_ERR | \ 71 NETIF_MSG_TX_ERR) 72 static int debug = -1; 73 74 static int mtu; 75 76 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 77 This chip uses a 512 element hash table based on the Ethernet CRC. */ 78 static const int multicast_filter_limit = 100; 79 80 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. 81 Setting to > 1518 effectively disables this feature. */ 82 static int rx_copybreak; 83 84 static int dspcfg_workaround = 1; 85 86 /* Used to pass the media type, etc. 87 Both 'options[]' and 'full_duplex[]' should exist for driver 88 interoperability. 89 The media type is usually passed in 'options[]'. 90 */ 91 #define MAX_UNITS 8 /* More are supported, limit only on options */ 92 static int options[MAX_UNITS]; 93 static int full_duplex[MAX_UNITS]; 94 95 /* Operational parameters that are set at compile time. */ 96 97 /* Keep the ring sizes a power of two for compile efficiency. 98 The compiler will convert <unsigned>'%'<2^N> into a bit mask. 99 Making the Tx ring too large decreases the effectiveness of channel 100 bonding and packet priority. 101 There are no ill effects from too-large receive rings. */ 102 #define TX_RING_SIZE 16 103 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used, min 4. */ 104 #define RX_RING_SIZE 32 105 106 /* Operational parameters that usually are not changed. */ 107 /* Time in jiffies before concluding the transmitter is hung. */ 108 #define TX_TIMEOUT (2*HZ) 109 110 #define NATSEMI_HW_TIMEOUT 400 111 #define NATSEMI_TIMER_FREQ 5*HZ 112 #define NATSEMI_PG0_NREGS 64 113 #define NATSEMI_RFDR_NREGS 8 114 #define NATSEMI_PG1_NREGS 4 115 #define NATSEMI_NREGS (NATSEMI_PG0_NREGS + NATSEMI_RFDR_NREGS + \ 116 NATSEMI_PG1_NREGS) 117 #define NATSEMI_REGS_VER 1 /* v1 added RFDR registers */ 118 #define NATSEMI_REGS_SIZE (NATSEMI_NREGS * sizeof(u32)) 119 120 /* Buffer sizes: 121 * The nic writes 32-bit values, even if the upper bytes of 122 * a 32-bit value are beyond the end of the buffer. 123 */ 124 #define NATSEMI_HEADERS 22 /* 2*mac,type,vlan,crc */ 125 #define NATSEMI_PADDING 16 /* 2 bytes should be sufficient */ 126 #define NATSEMI_LONGPKT 1518 /* limit for normal packets */ 127 #define NATSEMI_RX_LIMIT 2046 /* maximum supported by hardware */ 128 129 /* These identify the driver base version and may not be removed. */ 130 static const char version[] = 131 KERN_INFO DRV_NAME " dp8381x driver, version " 132 DRV_VERSION ", " DRV_RELDATE "\n" 133 " originally by Donald Becker <becker@scyld.com>\n" 134 " 2.4.x kernel port by Jeff Garzik, Tjeerd Mulder\n"; 135 136 MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 137 MODULE_DESCRIPTION("National Semiconductor DP8381x series PCI Ethernet driver"); 138 MODULE_LICENSE("GPL"); 139 140 module_param(mtu, int, 0); 141 module_param(debug, int, 0); 142 module_param(rx_copybreak, int, 0); 143 module_param(dspcfg_workaround, int, 0); 144 module_param_array(options, int, NULL, 0); 145 module_param_array(full_duplex, int, NULL, 0); 146 MODULE_PARM_DESC(mtu, "DP8381x MTU (all boards)"); 147 MODULE_PARM_DESC(debug, "DP8381x default debug level"); 148 MODULE_PARM_DESC(rx_copybreak, 149 "DP8381x copy breakpoint for copy-only-tiny-frames"); 150 MODULE_PARM_DESC(dspcfg_workaround, "DP8381x: control DspCfg workaround"); 151 MODULE_PARM_DESC(options, 152 "DP8381x: Bits 0-3: media type, bit 17: full duplex"); 153 MODULE_PARM_DESC(full_duplex, "DP8381x full duplex setting(s) (1)"); 154 155 /* 156 Theory of Operation 157 158 I. Board Compatibility 159 160 This driver is designed for National Semiconductor DP83815 PCI Ethernet NIC. 161 It also works with other chips in in the DP83810 series. 162 163 II. Board-specific settings 164 165 This driver requires the PCI interrupt line to be valid. 166 It honors the EEPROM-set values. 167 168 III. Driver operation 169 170 IIIa. Ring buffers 171 172 This driver uses two statically allocated fixed-size descriptor lists 173 formed into rings by a branch from the final descriptor to the beginning of 174 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 175 The NatSemi design uses a 'next descriptor' pointer that the driver forms 176 into a list. 177 178 IIIb/c. Transmit/Receive Structure 179 180 This driver uses a zero-copy receive and transmit scheme. 181 The driver allocates full frame size skbuffs for the Rx ring buffers at 182 open() time and passes the skb->data field to the chip as receive data 183 buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 184 a fresh skbuff is allocated and the frame is copied to the new skbuff. 185 When the incoming frame is larger, the skbuff is passed directly up the 186 protocol stack. Buffers consumed this way are replaced by newly allocated 187 skbuffs in a later phase of receives. 188 189 The RX_COPYBREAK value is chosen to trade-off the memory wasted by 190 using a full-sized skbuff for small frames vs. the copying costs of larger 191 frames. New boards are typically used in generously configured machines 192 and the underfilled buffers have negligible impact compared to the benefit of 193 a single allocation size, so the default value of zero results in never 194 copying packets. When copying is done, the cost is usually mitigated by using 195 a combined copy/checksum routine. Copying also preloads the cache, which is 196 most useful with small frames. 197 198 A subtle aspect of the operation is that unaligned buffers are not permitted 199 by the hardware. Thus the IP header at offset 14 in an ethernet frame isn't 200 longword aligned for further processing. On copies frames are put into the 201 skbuff at an offset of "+2", 16-byte aligning the IP header. 202 203 IIId. Synchronization 204 205 Most operations are synchronized on the np->lock irq spinlock, except the 206 receive and transmit paths which are synchronised using a combination of 207 hardware descriptor ownership, disabling interrupts and NAPI poll scheduling. 208 209 IVb. References 210 211 http://www.scyld.com/expert/100mbps.html 212 http://www.scyld.com/expert/NWay.html 213 Datasheet is available from: 214 http://www.national.com/pf/DP/DP83815.html 215 216 IVc. Errata 217 218 None characterised. 219 */ 220 221 222 223 /* 224 * Support for fibre connections on Am79C874: 225 * This phy needs a special setup when connected to a fibre cable. 226 * http://www.amd.com/files/connectivitysolutions/networking/archivednetworking/22235.pdf 227 */ 228 #define PHYID_AM79C874 0x0022561b 229 230 enum { 231 MII_MCTRL = 0x15, /* mode control register */ 232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */ 233 MII_EN_SCRM = 0x0004, /* enable scrambler (tp) */ 234 }; 235 236 enum { 237 NATSEMI_FLAG_IGNORE_PHY = 0x1, 238 }; 239 240 /* array of board data directly indexed by pci_tbl[x].driver_data */ 241 static struct { 242 const char *name; 243 unsigned long flags; 244 unsigned int eeprom_size; 245 } natsemi_pci_info[] = { 246 { "Aculab E1/T1 PMXc cPCI carrier card", NATSEMI_FLAG_IGNORE_PHY, 128 }, 247 { "NatSemi DP8381[56]", 0, 24 }, 248 }; 249 250 static const struct pci_device_id natsemi_pci_tbl[] = { 251 { PCI_VENDOR_ID_NS, 0x0020, 0x12d9, 0x000c, 0, 0, 0 }, 252 { PCI_VENDOR_ID_NS, 0x0020, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 }, 253 { } /* terminate list */ 254 }; 255 MODULE_DEVICE_TABLE(pci, natsemi_pci_tbl); 256 257 /* Offsets to the device registers. 258 Unlike software-only systems, device drivers interact with complex hardware. 259 It's not useful to define symbolic names for every register bit in the 260 device. 261 */ 262 enum register_offsets { 263 ChipCmd = 0x00, 264 ChipConfig = 0x04, 265 EECtrl = 0x08, 266 PCIBusCfg = 0x0C, 267 IntrStatus = 0x10, 268 IntrMask = 0x14, 269 IntrEnable = 0x18, 270 IntrHoldoff = 0x1C, /* DP83816 only */ 271 TxRingPtr = 0x20, 272 TxConfig = 0x24, 273 RxRingPtr = 0x30, 274 RxConfig = 0x34, 275 ClkRun = 0x3C, 276 WOLCmd = 0x40, 277 PauseCmd = 0x44, 278 RxFilterAddr = 0x48, 279 RxFilterData = 0x4C, 280 BootRomAddr = 0x50, 281 BootRomData = 0x54, 282 SiliconRev = 0x58, 283 StatsCtrl = 0x5C, 284 StatsData = 0x60, 285 RxPktErrs = 0x60, 286 RxMissed = 0x68, 287 RxCRCErrs = 0x64, 288 BasicControl = 0x80, 289 BasicStatus = 0x84, 290 AnegAdv = 0x90, 291 AnegPeer = 0x94, 292 PhyStatus = 0xC0, 293 MIntrCtrl = 0xC4, 294 MIntrStatus = 0xC8, 295 PhyCtrl = 0xE4, 296 297 /* These are from the spec, around page 78... on a separate table. 298 * The meaning of these registers depend on the value of PGSEL. */ 299 PGSEL = 0xCC, 300 PMDCSR = 0xE4, 301 TSTDAT = 0xFC, 302 DSPCFG = 0xF4, 303 SDCFG = 0xF8 304 }; 305 /* the values for the 'magic' registers above (PGSEL=1) */ 306 #define PMDCSR_VAL 0x189c /* enable preferred adaptation circuitry */ 307 #define TSTDAT_VAL 0x0 308 #define DSPCFG_VAL 0x5040 309 #define SDCFG_VAL 0x008c /* set voltage thresholds for Signal Detect */ 310 #define DSPCFG_LOCK 0x20 /* coefficient lock bit in DSPCFG */ 311 #define DSPCFG_COEF 0x1000 /* see coefficient (in TSTDAT) bit in DSPCFG */ 312 #define TSTDAT_FIXED 0xe8 /* magic number for bad coefficients */ 313 314 /* misc PCI space registers */ 315 enum pci_register_offsets { 316 PCIPM = 0x44, 317 }; 318 319 enum ChipCmd_bits { 320 ChipReset = 0x100, 321 RxReset = 0x20, 322 TxReset = 0x10, 323 RxOff = 0x08, 324 RxOn = 0x04, 325 TxOff = 0x02, 326 TxOn = 0x01, 327 }; 328 329 enum ChipConfig_bits { 330 CfgPhyDis = 0x200, 331 CfgPhyRst = 0x400, 332 CfgExtPhy = 0x1000, 333 CfgAnegEnable = 0x2000, 334 CfgAneg100 = 0x4000, 335 CfgAnegFull = 0x8000, 336 CfgAnegDone = 0x8000000, 337 CfgFullDuplex = 0x20000000, 338 CfgSpeed100 = 0x40000000, 339 CfgLink = 0x80000000, 340 }; 341 342 enum EECtrl_bits { 343 EE_ShiftClk = 0x04, 344 EE_DataIn = 0x01, 345 EE_ChipSelect = 0x08, 346 EE_DataOut = 0x02, 347 MII_Data = 0x10, 348 MII_Write = 0x20, 349 MII_ShiftClk = 0x40, 350 }; 351 352 enum PCIBusCfg_bits { 353 EepromReload = 0x4, 354 }; 355 356 /* Bits in the interrupt status/mask registers. */ 357 enum IntrStatus_bits { 358 IntrRxDone = 0x0001, 359 IntrRxIntr = 0x0002, 360 IntrRxErr = 0x0004, 361 IntrRxEarly = 0x0008, 362 IntrRxIdle = 0x0010, 363 IntrRxOverrun = 0x0020, 364 IntrTxDone = 0x0040, 365 IntrTxIntr = 0x0080, 366 IntrTxErr = 0x0100, 367 IntrTxIdle = 0x0200, 368 IntrTxUnderrun = 0x0400, 369 StatsMax = 0x0800, 370 SWInt = 0x1000, 371 WOLPkt = 0x2000, 372 LinkChange = 0x4000, 373 IntrHighBits = 0x8000, 374 RxStatusFIFOOver = 0x10000, 375 IntrPCIErr = 0xf00000, 376 RxResetDone = 0x1000000, 377 TxResetDone = 0x2000000, 378 IntrAbnormalSummary = 0xCD20, 379 }; 380 381 /* 382 * Default Interrupts: 383 * Rx OK, Rx Packet Error, Rx Overrun, 384 * Tx OK, Tx Packet Error, Tx Underrun, 385 * MIB Service, Phy Interrupt, High Bits, 386 * Rx Status FIFO overrun, 387 * Received Target Abort, Received Master Abort, 388 * Signalled System Error, Received Parity Error 389 */ 390 #define DEFAULT_INTR 0x00f1cd65 391 392 enum TxConfig_bits { 393 TxDrthMask = 0x3f, 394 TxFlthMask = 0x3f00, 395 TxMxdmaMask = 0x700000, 396 TxMxdma_512 = 0x0, 397 TxMxdma_4 = 0x100000, 398 TxMxdma_8 = 0x200000, 399 TxMxdma_16 = 0x300000, 400 TxMxdma_32 = 0x400000, 401 TxMxdma_64 = 0x500000, 402 TxMxdma_128 = 0x600000, 403 TxMxdma_256 = 0x700000, 404 TxCollRetry = 0x800000, 405 TxAutoPad = 0x10000000, 406 TxMacLoop = 0x20000000, 407 TxHeartIgn = 0x40000000, 408 TxCarrierIgn = 0x80000000 409 }; 410 411 /* 412 * Tx Configuration: 413 * - 256 byte DMA burst length 414 * - fill threshold 512 bytes (i.e. restart DMA when 512 bytes are free) 415 * - 64 bytes initial drain threshold (i.e. begin actual transmission 416 * when 64 byte are in the fifo) 417 * - on tx underruns, increase drain threshold by 64. 418 * - at most use a drain threshold of 1472 bytes: The sum of the fill 419 * threshold and the drain threshold must be less than 2016 bytes. 420 * 421 */ 422 #define TX_FLTH_VAL ((512/32) << 8) 423 #define TX_DRTH_VAL_START (64/32) 424 #define TX_DRTH_VAL_INC 2 425 #define TX_DRTH_VAL_LIMIT (1472/32) 426 427 enum RxConfig_bits { 428 RxDrthMask = 0x3e, 429 RxMxdmaMask = 0x700000, 430 RxMxdma_512 = 0x0, 431 RxMxdma_4 = 0x100000, 432 RxMxdma_8 = 0x200000, 433 RxMxdma_16 = 0x300000, 434 RxMxdma_32 = 0x400000, 435 RxMxdma_64 = 0x500000, 436 RxMxdma_128 = 0x600000, 437 RxMxdma_256 = 0x700000, 438 RxAcceptLong = 0x8000000, 439 RxAcceptTx = 0x10000000, 440 RxAcceptRunt = 0x40000000, 441 RxAcceptErr = 0x80000000 442 }; 443 #define RX_DRTH_VAL (128/8) 444 445 enum ClkRun_bits { 446 PMEEnable = 0x100, 447 PMEStatus = 0x8000, 448 }; 449 450 enum WolCmd_bits { 451 WakePhy = 0x1, 452 WakeUnicast = 0x2, 453 WakeMulticast = 0x4, 454 WakeBroadcast = 0x8, 455 WakeArp = 0x10, 456 WakePMatch0 = 0x20, 457 WakePMatch1 = 0x40, 458 WakePMatch2 = 0x80, 459 WakePMatch3 = 0x100, 460 WakeMagic = 0x200, 461 WakeMagicSecure = 0x400, 462 SecureHack = 0x100000, 463 WokePhy = 0x400000, 464 WokeUnicast = 0x800000, 465 WokeMulticast = 0x1000000, 466 WokeBroadcast = 0x2000000, 467 WokeArp = 0x4000000, 468 WokePMatch0 = 0x8000000, 469 WokePMatch1 = 0x10000000, 470 WokePMatch2 = 0x20000000, 471 WokePMatch3 = 0x40000000, 472 WokeMagic = 0x80000000, 473 WakeOptsSummary = 0x7ff 474 }; 475 476 enum RxFilterAddr_bits { 477 RFCRAddressMask = 0x3ff, 478 AcceptMulticast = 0x00200000, 479 AcceptMyPhys = 0x08000000, 480 AcceptAllPhys = 0x10000000, 481 AcceptAllMulticast = 0x20000000, 482 AcceptBroadcast = 0x40000000, 483 RxFilterEnable = 0x80000000 484 }; 485 486 enum StatsCtrl_bits { 487 StatsWarn = 0x1, 488 StatsFreeze = 0x2, 489 StatsClear = 0x4, 490 StatsStrobe = 0x8, 491 }; 492 493 enum MIntrCtrl_bits { 494 MICRIntEn = 0x2, 495 }; 496 497 enum PhyCtrl_bits { 498 PhyAddrMask = 0x1f, 499 }; 500 501 #define PHY_ADDR_NONE 32 502 #define PHY_ADDR_INTERNAL 1 503 504 /* values we might find in the silicon revision register */ 505 #define SRR_DP83815_C 0x0302 506 #define SRR_DP83815_D 0x0403 507 #define SRR_DP83816_A4 0x0504 508 #define SRR_DP83816_A5 0x0505 509 510 /* The Rx and Tx buffer descriptors. */ 511 /* Note that using only 32 bit fields simplifies conversion to big-endian 512 architectures. */ 513 struct netdev_desc { 514 __le32 next_desc; 515 __le32 cmd_status; 516 __le32 addr; 517 __le32 software_use; 518 }; 519 520 /* Bits in network_desc.status */ 521 enum desc_status_bits { 522 DescOwn=0x80000000, DescMore=0x40000000, DescIntr=0x20000000, 523 DescNoCRC=0x10000000, DescPktOK=0x08000000, 524 DescSizeMask=0xfff, 525 526 DescTxAbort=0x04000000, DescTxFIFO=0x02000000, 527 DescTxCarrier=0x01000000, DescTxDefer=0x00800000, 528 DescTxExcDefer=0x00400000, DescTxOOWCol=0x00200000, 529 DescTxExcColl=0x00100000, DescTxCollCount=0x000f0000, 530 531 DescRxAbort=0x04000000, DescRxOver=0x02000000, 532 DescRxDest=0x01800000, DescRxLong=0x00400000, 533 DescRxRunt=0x00200000, DescRxInvalid=0x00100000, 534 DescRxCRC=0x00080000, DescRxAlign=0x00040000, 535 DescRxLoop=0x00020000, DesRxColl=0x00010000, 536 }; 537 538 struct netdev_private { 539 /* Descriptor rings first for alignment */ 540 dma_addr_t ring_dma; 541 struct netdev_desc *rx_ring; 542 struct netdev_desc *tx_ring; 543 /* The addresses of receive-in-place skbuffs */ 544 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 545 dma_addr_t rx_dma[RX_RING_SIZE]; 546 /* address of a sent-in-place packet/buffer, for later free() */ 547 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 548 dma_addr_t tx_dma[TX_RING_SIZE]; 549 struct net_device *dev; 550 void __iomem *ioaddr; 551 struct napi_struct napi; 552 /* Media monitoring timer */ 553 struct timer_list timer; 554 /* Frequently used values: keep some adjacent for cache effect */ 555 struct pci_dev *pci_dev; 556 struct netdev_desc *rx_head_desc; 557 /* Producer/consumer ring indices */ 558 unsigned int cur_rx, dirty_rx; 559 unsigned int cur_tx, dirty_tx; 560 /* Based on MTU+slack. */ 561 unsigned int rx_buf_sz; 562 int oom; 563 /* Interrupt status */ 564 u32 intr_status; 565 /* Do not touch the nic registers */ 566 int hands_off; 567 /* Don't pay attention to the reported link state. */ 568 int ignore_phy; 569 /* external phy that is used: only valid if dev->if_port != PORT_TP */ 570 int mii; 571 int phy_addr_external; 572 unsigned int full_duplex; 573 /* Rx filter */ 574 u32 cur_rx_mode; 575 u32 rx_filter[16]; 576 /* FIFO and PCI burst thresholds */ 577 u32 tx_config, rx_config; 578 /* original contents of ClkRun register */ 579 u32 SavedClkRun; 580 /* silicon revision */ 581 u32 srr; 582 /* expected DSPCFG value */ 583 u16 dspcfg; 584 int dspcfg_workaround; 585 /* parms saved in ethtool format */ 586 u16 speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 587 u8 duplex; /* Duplex, half or full */ 588 u8 autoneg; /* Autonegotiation enabled */ 589 /* MII transceiver section */ 590 u16 advertising; 591 unsigned int iosize; 592 spinlock_t lock; 593 u32 msg_enable; 594 /* EEPROM data */ 595 int eeprom_size; 596 }; 597 598 static void move_int_phy(struct net_device *dev, int addr); 599 static int eeprom_read(void __iomem *ioaddr, int location); 600 static int mdio_read(struct net_device *dev, int reg); 601 static void mdio_write(struct net_device *dev, int reg, u16 data); 602 static void init_phy_fixup(struct net_device *dev); 603 static int miiport_read(struct net_device *dev, int phy_id, int reg); 604 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data); 605 static int find_mii(struct net_device *dev); 606 static void natsemi_reset(struct net_device *dev); 607 static void natsemi_reload_eeprom(struct net_device *dev); 608 static void natsemi_stop_rxtx(struct net_device *dev); 609 static int netdev_open(struct net_device *dev); 610 static void do_cable_magic(struct net_device *dev); 611 static void undo_cable_magic(struct net_device *dev); 612 static void check_link(struct net_device *dev); 613 static void netdev_timer(unsigned long data); 614 static void dump_ring(struct net_device *dev); 615 static void ns_tx_timeout(struct net_device *dev); 616 static int alloc_ring(struct net_device *dev); 617 static void refill_rx(struct net_device *dev); 618 static void init_ring(struct net_device *dev); 619 static void drain_tx(struct net_device *dev); 620 static void drain_ring(struct net_device *dev); 621 static void free_ring(struct net_device *dev); 622 static void reinit_ring(struct net_device *dev); 623 static void init_registers(struct net_device *dev); 624 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev); 625 static irqreturn_t intr_handler(int irq, void *dev_instance); 626 static void netdev_error(struct net_device *dev, int intr_status); 627 static int natsemi_poll(struct napi_struct *napi, int budget); 628 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do); 629 static void netdev_tx_done(struct net_device *dev); 630 static int natsemi_change_mtu(struct net_device *dev, int new_mtu); 631 #ifdef CONFIG_NET_POLL_CONTROLLER 632 static void natsemi_poll_controller(struct net_device *dev); 633 #endif 634 static void __set_rx_mode(struct net_device *dev); 635 static void set_rx_mode(struct net_device *dev); 636 static void __get_stats(struct net_device *dev); 637 static struct net_device_stats *get_stats(struct net_device *dev); 638 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 639 static int netdev_set_wol(struct net_device *dev, u32 newval); 640 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur); 641 static int netdev_set_sopass(struct net_device *dev, u8 *newval); 642 static int netdev_get_sopass(struct net_device *dev, u8 *data); 643 static int netdev_get_ecmd(struct net_device *dev, 644 struct ethtool_link_ksettings *ecmd); 645 static int netdev_set_ecmd(struct net_device *dev, 646 const struct ethtool_link_ksettings *ecmd); 647 static void enable_wol_mode(struct net_device *dev, int enable_intr); 648 static int netdev_close(struct net_device *dev); 649 static int netdev_get_regs(struct net_device *dev, u8 *buf); 650 static int netdev_get_eeprom(struct net_device *dev, u8 *buf); 651 static const struct ethtool_ops ethtool_ops; 652 653 #define NATSEMI_ATTR(_name) \ 654 static ssize_t natsemi_show_##_name(struct device *dev, \ 655 struct device_attribute *attr, char *buf); \ 656 static ssize_t natsemi_set_##_name(struct device *dev, \ 657 struct device_attribute *attr, \ 658 const char *buf, size_t count); \ 659 static DEVICE_ATTR(_name, 0644, natsemi_show_##_name, natsemi_set_##_name) 660 661 #define NATSEMI_CREATE_FILE(_dev, _name) \ 662 device_create_file(&_dev->dev, &dev_attr_##_name) 663 #define NATSEMI_REMOVE_FILE(_dev, _name) \ 664 device_remove_file(&_dev->dev, &dev_attr_##_name) 665 666 NATSEMI_ATTR(dspcfg_workaround); 667 668 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev, 669 struct device_attribute *attr, 670 char *buf) 671 { 672 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 673 674 return sprintf(buf, "%s\n", np->dspcfg_workaround ? "on" : "off"); 675 } 676 677 static ssize_t natsemi_set_dspcfg_workaround(struct device *dev, 678 struct device_attribute *attr, 679 const char *buf, size_t count) 680 { 681 struct netdev_private *np = netdev_priv(to_net_dev(dev)); 682 int new_setting; 683 unsigned long flags; 684 685 /* Find out the new setting */ 686 if (!strncmp("on", buf, count - 1) || !strncmp("1", buf, count - 1)) 687 new_setting = 1; 688 else if (!strncmp("off", buf, count - 1) || 689 !strncmp("0", buf, count - 1)) 690 new_setting = 0; 691 else 692 return count; 693 694 spin_lock_irqsave(&np->lock, flags); 695 696 np->dspcfg_workaround = new_setting; 697 698 spin_unlock_irqrestore(&np->lock, flags); 699 700 return count; 701 } 702 703 static inline void __iomem *ns_ioaddr(struct net_device *dev) 704 { 705 struct netdev_private *np = netdev_priv(dev); 706 707 return np->ioaddr; 708 } 709 710 static inline void natsemi_irq_enable(struct net_device *dev) 711 { 712 writel(1, ns_ioaddr(dev) + IntrEnable); 713 readl(ns_ioaddr(dev) + IntrEnable); 714 } 715 716 static inline void natsemi_irq_disable(struct net_device *dev) 717 { 718 writel(0, ns_ioaddr(dev) + IntrEnable); 719 readl(ns_ioaddr(dev) + IntrEnable); 720 } 721 722 static void move_int_phy(struct net_device *dev, int addr) 723 { 724 struct netdev_private *np = netdev_priv(dev); 725 void __iomem *ioaddr = ns_ioaddr(dev); 726 int target = 31; 727 728 /* 729 * The internal phy is visible on the external mii bus. Therefore we must 730 * move it away before we can send commands to an external phy. 731 * There are two addresses we must avoid: 732 * - the address on the external phy that is used for transmission. 733 * - the address that we want to access. User space can access phys 734 * on the mii bus with SIOCGMIIREG/SIOCSMIIREG, independent from the 735 * phy that is used for transmission. 736 */ 737 738 if (target == addr) 739 target--; 740 if (target == np->phy_addr_external) 741 target--; 742 writew(target, ioaddr + PhyCtrl); 743 readw(ioaddr + PhyCtrl); 744 udelay(1); 745 } 746 747 static void natsemi_init_media(struct net_device *dev) 748 { 749 struct netdev_private *np = netdev_priv(dev); 750 u32 tmp; 751 752 if (np->ignore_phy) 753 netif_carrier_on(dev); 754 else 755 netif_carrier_off(dev); 756 757 /* get the initial settings from hardware */ 758 tmp = mdio_read(dev, MII_BMCR); 759 np->speed = (tmp & BMCR_SPEED100)? SPEED_100 : SPEED_10; 760 np->duplex = (tmp & BMCR_FULLDPLX)? DUPLEX_FULL : DUPLEX_HALF; 761 np->autoneg = (tmp & BMCR_ANENABLE)? AUTONEG_ENABLE: AUTONEG_DISABLE; 762 np->advertising= mdio_read(dev, MII_ADVERTISE); 763 764 if ((np->advertising & ADVERTISE_ALL) != ADVERTISE_ALL && 765 netif_msg_probe(np)) { 766 printk(KERN_INFO "natsemi %s: Transceiver default autonegotiation %s " 767 "10%s %s duplex.\n", 768 pci_name(np->pci_dev), 769 (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE)? 770 "enabled, advertise" : "disabled, force", 771 (np->advertising & 772 (ADVERTISE_100FULL|ADVERTISE_100HALF))? 773 "0" : "", 774 (np->advertising & 775 (ADVERTISE_100FULL|ADVERTISE_10FULL))? 776 "full" : "half"); 777 } 778 if (netif_msg_probe(np)) 779 printk(KERN_INFO 780 "natsemi %s: Transceiver status %#04x advertising %#04x.\n", 781 pci_name(np->pci_dev), mdio_read(dev, MII_BMSR), 782 np->advertising); 783 784 } 785 786 static const struct net_device_ops natsemi_netdev_ops = { 787 .ndo_open = netdev_open, 788 .ndo_stop = netdev_close, 789 .ndo_start_xmit = start_tx, 790 .ndo_get_stats = get_stats, 791 .ndo_set_rx_mode = set_rx_mode, 792 .ndo_change_mtu = natsemi_change_mtu, 793 .ndo_do_ioctl = netdev_ioctl, 794 .ndo_tx_timeout = ns_tx_timeout, 795 .ndo_set_mac_address = eth_mac_addr, 796 .ndo_validate_addr = eth_validate_addr, 797 #ifdef CONFIG_NET_POLL_CONTROLLER 798 .ndo_poll_controller = natsemi_poll_controller, 799 #endif 800 }; 801 802 static int natsemi_probe1(struct pci_dev *pdev, const struct pci_device_id *ent) 803 { 804 struct net_device *dev; 805 struct netdev_private *np; 806 int i, option, irq, chip_idx = ent->driver_data; 807 static int find_cnt = -1; 808 resource_size_t iostart; 809 unsigned long iosize; 810 void __iomem *ioaddr; 811 const int pcibar = 1; /* PCI base address register */ 812 int prev_eedata; 813 u32 tmp; 814 815 /* when built into the kernel, we only print version if device is found */ 816 #ifndef MODULE 817 static int printed_version; 818 if (!printed_version++) 819 printk(version); 820 #endif 821 822 i = pci_enable_device(pdev); 823 if (i) return i; 824 825 /* natsemi has a non-standard PM control register 826 * in PCI config space. Some boards apparently need 827 * to be brought to D0 in this manner. 828 */ 829 pci_read_config_dword(pdev, PCIPM, &tmp); 830 if (tmp & PCI_PM_CTRL_STATE_MASK) { 831 /* D0 state, disable PME assertion */ 832 u32 newtmp = tmp & ~PCI_PM_CTRL_STATE_MASK; 833 pci_write_config_dword(pdev, PCIPM, newtmp); 834 } 835 836 find_cnt++; 837 iostart = pci_resource_start(pdev, pcibar); 838 iosize = pci_resource_len(pdev, pcibar); 839 irq = pdev->irq; 840 841 pci_set_master(pdev); 842 843 dev = alloc_etherdev(sizeof (struct netdev_private)); 844 if (!dev) 845 return -ENOMEM; 846 SET_NETDEV_DEV(dev, &pdev->dev); 847 848 i = pci_request_regions(pdev, DRV_NAME); 849 if (i) 850 goto err_pci_request_regions; 851 852 ioaddr = ioremap(iostart, iosize); 853 if (!ioaddr) { 854 i = -ENOMEM; 855 goto err_ioremap; 856 } 857 858 /* Work around the dropped serial bit. */ 859 prev_eedata = eeprom_read(ioaddr, 6); 860 for (i = 0; i < 3; i++) { 861 int eedata = eeprom_read(ioaddr, i + 7); 862 dev->dev_addr[i*2] = (eedata << 1) + (prev_eedata >> 15); 863 dev->dev_addr[i*2+1] = eedata >> 7; 864 prev_eedata = eedata; 865 } 866 867 np = netdev_priv(dev); 868 np->ioaddr = ioaddr; 869 870 netif_napi_add(dev, &np->napi, natsemi_poll, 64); 871 np->dev = dev; 872 873 np->pci_dev = pdev; 874 pci_set_drvdata(pdev, dev); 875 np->iosize = iosize; 876 spin_lock_init(&np->lock); 877 np->msg_enable = (debug >= 0) ? (1<<debug)-1 : NATSEMI_DEF_MSG; 878 np->hands_off = 0; 879 np->intr_status = 0; 880 np->eeprom_size = natsemi_pci_info[chip_idx].eeprom_size; 881 if (natsemi_pci_info[chip_idx].flags & NATSEMI_FLAG_IGNORE_PHY) 882 np->ignore_phy = 1; 883 else 884 np->ignore_phy = 0; 885 np->dspcfg_workaround = dspcfg_workaround; 886 887 /* Initial port: 888 * - If configured to ignore the PHY set up for external. 889 * - If the nic was configured to use an external phy and if find_mii 890 * finds a phy: use external port, first phy that replies. 891 * - Otherwise: internal port. 892 * Note that the phy address for the internal phy doesn't matter: 893 * The address would be used to access a phy over the mii bus, but 894 * the internal phy is accessed through mapped registers. 895 */ 896 if (np->ignore_phy || readl(ioaddr + ChipConfig) & CfgExtPhy) 897 dev->if_port = PORT_MII; 898 else 899 dev->if_port = PORT_TP; 900 /* Reset the chip to erase previous misconfiguration. */ 901 natsemi_reload_eeprom(dev); 902 natsemi_reset(dev); 903 904 if (dev->if_port != PORT_TP) { 905 np->phy_addr_external = find_mii(dev); 906 /* If we're ignoring the PHY it doesn't matter if we can't 907 * find one. */ 908 if (!np->ignore_phy && np->phy_addr_external == PHY_ADDR_NONE) { 909 dev->if_port = PORT_TP; 910 np->phy_addr_external = PHY_ADDR_INTERNAL; 911 } 912 } else { 913 np->phy_addr_external = PHY_ADDR_INTERNAL; 914 } 915 916 option = find_cnt < MAX_UNITS ? options[find_cnt] : 0; 917 /* The lower four bits are the media type. */ 918 if (option) { 919 if (option & 0x200) 920 np->full_duplex = 1; 921 if (option & 15) 922 printk(KERN_INFO 923 "natsemi %s: ignoring user supplied media type %d", 924 pci_name(np->pci_dev), option & 15); 925 } 926 if (find_cnt < MAX_UNITS && full_duplex[find_cnt]) 927 np->full_duplex = 1; 928 929 dev->netdev_ops = &natsemi_netdev_ops; 930 dev->watchdog_timeo = TX_TIMEOUT; 931 932 dev->ethtool_ops = ðtool_ops; 933 934 /* MTU range: 64 - 2024 */ 935 dev->min_mtu = ETH_ZLEN + ETH_FCS_LEN; 936 dev->max_mtu = NATSEMI_RX_LIMIT - NATSEMI_HEADERS; 937 938 if (mtu) 939 dev->mtu = mtu; 940 941 natsemi_init_media(dev); 942 943 /* save the silicon revision for later querying */ 944 np->srr = readl(ioaddr + SiliconRev); 945 if (netif_msg_hw(np)) 946 printk(KERN_INFO "natsemi %s: silicon revision %#04x.\n", 947 pci_name(np->pci_dev), np->srr); 948 949 i = register_netdev(dev); 950 if (i) 951 goto err_register_netdev; 952 i = NATSEMI_CREATE_FILE(pdev, dspcfg_workaround); 953 if (i) 954 goto err_create_file; 955 956 if (netif_msg_drv(np)) { 957 printk(KERN_INFO "natsemi %s: %s at %#08llx " 958 "(%s), %pM, IRQ %d", 959 dev->name, natsemi_pci_info[chip_idx].name, 960 (unsigned long long)iostart, pci_name(np->pci_dev), 961 dev->dev_addr, irq); 962 if (dev->if_port == PORT_TP) 963 printk(", port TP.\n"); 964 else if (np->ignore_phy) 965 printk(", port MII, ignoring PHY\n"); 966 else 967 printk(", port MII, phy ad %d.\n", np->phy_addr_external); 968 } 969 return 0; 970 971 err_create_file: 972 unregister_netdev(dev); 973 974 err_register_netdev: 975 iounmap(ioaddr); 976 977 err_ioremap: 978 pci_release_regions(pdev); 979 980 err_pci_request_regions: 981 free_netdev(dev); 982 return i; 983 } 984 985 986 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. 987 The EEPROM code is for the common 93c06/46 EEPROMs with 6 bit addresses. */ 988 989 /* Delay between EEPROM clock transitions. 990 No extra delay is needed with 33Mhz PCI, but future 66Mhz access may need 991 a delay. Note that pre-2.0.34 kernels had a cache-alignment bug that 992 made udelay() unreliable. 993 The old method of using an ISA access as a delay, __SLOW_DOWN_IO__, is 994 deprecated. 995 */ 996 #define eeprom_delay(ee_addr) readl(ee_addr) 997 998 #define EE_Write0 (EE_ChipSelect) 999 #define EE_Write1 (EE_ChipSelect | EE_DataIn) 1000 1001 /* The EEPROM commands include the alway-set leading bit. */ 1002 enum EEPROM_Cmds { 1003 EE_WriteCmd=(5 << 6), EE_ReadCmd=(6 << 6), EE_EraseCmd=(7 << 6), 1004 }; 1005 1006 static int eeprom_read(void __iomem *addr, int location) 1007 { 1008 int i; 1009 int retval = 0; 1010 void __iomem *ee_addr = addr + EECtrl; 1011 int read_cmd = location | EE_ReadCmd; 1012 1013 writel(EE_Write0, ee_addr); 1014 1015 /* Shift the read command bits out. */ 1016 for (i = 10; i >= 0; i--) { 1017 short dataval = (read_cmd & (1 << i)) ? EE_Write1 : EE_Write0; 1018 writel(dataval, ee_addr); 1019 eeprom_delay(ee_addr); 1020 writel(dataval | EE_ShiftClk, ee_addr); 1021 eeprom_delay(ee_addr); 1022 } 1023 writel(EE_ChipSelect, ee_addr); 1024 eeprom_delay(ee_addr); 1025 1026 for (i = 0; i < 16; i++) { 1027 writel(EE_ChipSelect | EE_ShiftClk, ee_addr); 1028 eeprom_delay(ee_addr); 1029 retval |= (readl(ee_addr) & EE_DataOut) ? 1 << i : 0; 1030 writel(EE_ChipSelect, ee_addr); 1031 eeprom_delay(ee_addr); 1032 } 1033 1034 /* Terminate the EEPROM access. */ 1035 writel(EE_Write0, ee_addr); 1036 writel(0, ee_addr); 1037 return retval; 1038 } 1039 1040 /* MII transceiver control section. 1041 * The 83815 series has an internal transceiver, and we present the 1042 * internal management registers as if they were MII connected. 1043 * External Phy registers are referenced through the MII interface. 1044 */ 1045 1046 /* clock transitions >= 20ns (25MHz) 1047 * One readl should be good to PCI @ 100MHz 1048 */ 1049 #define mii_delay(ioaddr) readl(ioaddr + EECtrl) 1050 1051 static int mii_getbit (struct net_device *dev) 1052 { 1053 int data; 1054 void __iomem *ioaddr = ns_ioaddr(dev); 1055 1056 writel(MII_ShiftClk, ioaddr + EECtrl); 1057 data = readl(ioaddr + EECtrl); 1058 writel(0, ioaddr + EECtrl); 1059 mii_delay(ioaddr); 1060 return (data & MII_Data)? 1 : 0; 1061 } 1062 1063 static void mii_send_bits (struct net_device *dev, u32 data, int len) 1064 { 1065 u32 i; 1066 void __iomem *ioaddr = ns_ioaddr(dev); 1067 1068 for (i = (1 << (len-1)); i; i >>= 1) 1069 { 1070 u32 mdio_val = MII_Write | ((data & i)? MII_Data : 0); 1071 writel(mdio_val, ioaddr + EECtrl); 1072 mii_delay(ioaddr); 1073 writel(mdio_val | MII_ShiftClk, ioaddr + EECtrl); 1074 mii_delay(ioaddr); 1075 } 1076 writel(0, ioaddr + EECtrl); 1077 mii_delay(ioaddr); 1078 } 1079 1080 static int miiport_read(struct net_device *dev, int phy_id, int reg) 1081 { 1082 u32 cmd; 1083 int i; 1084 u32 retval = 0; 1085 1086 /* Ensure sync */ 1087 mii_send_bits (dev, 0xffffffff, 32); 1088 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1089 /* ST,OP = 0110'b for read operation */ 1090 cmd = (0x06 << 10) | (phy_id << 5) | reg; 1091 mii_send_bits (dev, cmd, 14); 1092 /* Turnaround */ 1093 if (mii_getbit (dev)) 1094 return 0; 1095 /* Read data */ 1096 for (i = 0; i < 16; i++) { 1097 retval <<= 1; 1098 retval |= mii_getbit (dev); 1099 } 1100 /* End cycle */ 1101 mii_getbit (dev); 1102 return retval; 1103 } 1104 1105 static void miiport_write(struct net_device *dev, int phy_id, int reg, u16 data) 1106 { 1107 u32 cmd; 1108 1109 /* Ensure sync */ 1110 mii_send_bits (dev, 0xffffffff, 32); 1111 /* ST(2), OP(2), ADDR(5), REG#(5), TA(2), Data(16) total 32 bits */ 1112 /* ST,OP,AAAAA,RRRRR,TA = 0101xxxxxxxxxx10'b = 0x5002 for write */ 1113 cmd = (0x5002 << 16) | (phy_id << 23) | (reg << 18) | data; 1114 mii_send_bits (dev, cmd, 32); 1115 /* End cycle */ 1116 mii_getbit (dev); 1117 } 1118 1119 static int mdio_read(struct net_device *dev, int reg) 1120 { 1121 struct netdev_private *np = netdev_priv(dev); 1122 void __iomem *ioaddr = ns_ioaddr(dev); 1123 1124 /* The 83815 series has two ports: 1125 * - an internal transceiver 1126 * - an external mii bus 1127 */ 1128 if (dev->if_port == PORT_TP) 1129 return readw(ioaddr+BasicControl+(reg<<2)); 1130 else 1131 return miiport_read(dev, np->phy_addr_external, reg); 1132 } 1133 1134 static void mdio_write(struct net_device *dev, int reg, u16 data) 1135 { 1136 struct netdev_private *np = netdev_priv(dev); 1137 void __iomem *ioaddr = ns_ioaddr(dev); 1138 1139 /* The 83815 series has an internal transceiver; handle separately */ 1140 if (dev->if_port == PORT_TP) 1141 writew(data, ioaddr+BasicControl+(reg<<2)); 1142 else 1143 miiport_write(dev, np->phy_addr_external, reg, data); 1144 } 1145 1146 static void init_phy_fixup(struct net_device *dev) 1147 { 1148 struct netdev_private *np = netdev_priv(dev); 1149 void __iomem *ioaddr = ns_ioaddr(dev); 1150 int i; 1151 u32 cfg; 1152 u16 tmp; 1153 1154 /* restore stuff lost when power was out */ 1155 tmp = mdio_read(dev, MII_BMCR); 1156 if (np->autoneg == AUTONEG_ENABLE) { 1157 /* renegotiate if something changed */ 1158 if ((tmp & BMCR_ANENABLE) == 0 || 1159 np->advertising != mdio_read(dev, MII_ADVERTISE)) 1160 { 1161 /* turn on autonegotiation and force negotiation */ 1162 tmp |= (BMCR_ANENABLE | BMCR_ANRESTART); 1163 mdio_write(dev, MII_ADVERTISE, np->advertising); 1164 } 1165 } else { 1166 /* turn off auto negotiation, set speed and duplexity */ 1167 tmp &= ~(BMCR_ANENABLE | BMCR_SPEED100 | BMCR_FULLDPLX); 1168 if (np->speed == SPEED_100) 1169 tmp |= BMCR_SPEED100; 1170 if (np->duplex == DUPLEX_FULL) 1171 tmp |= BMCR_FULLDPLX; 1172 /* 1173 * Note: there is no good way to inform the link partner 1174 * that our capabilities changed. The user has to unplug 1175 * and replug the network cable after some changes, e.g. 1176 * after switching from 10HD, autoneg off to 100 HD, 1177 * autoneg off. 1178 */ 1179 } 1180 mdio_write(dev, MII_BMCR, tmp); 1181 readl(ioaddr + ChipConfig); 1182 udelay(1); 1183 1184 /* find out what phy this is */ 1185 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1186 + mdio_read(dev, MII_PHYSID2); 1187 1188 /* handle external phys here */ 1189 switch (np->mii) { 1190 case PHYID_AM79C874: 1191 /* phy specific configuration for fibre/tp operation */ 1192 tmp = mdio_read(dev, MII_MCTRL); 1193 tmp &= ~(MII_FX_SEL | MII_EN_SCRM); 1194 if (dev->if_port == PORT_FIBRE) 1195 tmp |= MII_FX_SEL; 1196 else 1197 tmp |= MII_EN_SCRM; 1198 mdio_write(dev, MII_MCTRL, tmp); 1199 break; 1200 default: 1201 break; 1202 } 1203 cfg = readl(ioaddr + ChipConfig); 1204 if (cfg & CfgExtPhy) 1205 return; 1206 1207 /* On page 78 of the spec, they recommend some settings for "optimum 1208 performance" to be done in sequence. These settings optimize some 1209 of the 100Mbit autodetection circuitry. They say we only want to 1210 do this for rev C of the chip, but engineers at NSC (Bradley 1211 Kennedy) recommends always setting them. If you don't, you get 1212 errors on some autonegotiations that make the device unusable. 1213 1214 It seems that the DSP needs a few usec to reinitialize after 1215 the start of the phy. Just retry writing these values until they 1216 stick. 1217 */ 1218 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1219 1220 int dspcfg; 1221 writew(1, ioaddr + PGSEL); 1222 writew(PMDCSR_VAL, ioaddr + PMDCSR); 1223 writew(TSTDAT_VAL, ioaddr + TSTDAT); 1224 np->dspcfg = (np->srr <= SRR_DP83815_C)? 1225 DSPCFG_VAL : (DSPCFG_COEF | readw(ioaddr + DSPCFG)); 1226 writew(np->dspcfg, ioaddr + DSPCFG); 1227 writew(SDCFG_VAL, ioaddr + SDCFG); 1228 writew(0, ioaddr + PGSEL); 1229 readl(ioaddr + ChipConfig); 1230 udelay(10); 1231 1232 writew(1, ioaddr + PGSEL); 1233 dspcfg = readw(ioaddr + DSPCFG); 1234 writew(0, ioaddr + PGSEL); 1235 if (np->dspcfg == dspcfg) 1236 break; 1237 } 1238 1239 if (netif_msg_link(np)) { 1240 if (i==NATSEMI_HW_TIMEOUT) { 1241 printk(KERN_INFO 1242 "%s: DSPCFG mismatch after retrying for %d usec.\n", 1243 dev->name, i*10); 1244 } else { 1245 printk(KERN_INFO 1246 "%s: DSPCFG accepted after %d usec.\n", 1247 dev->name, i*10); 1248 } 1249 } 1250 /* 1251 * Enable PHY Specific event based interrupts. Link state change 1252 * and Auto-Negotiation Completion are among the affected. 1253 * Read the intr status to clear it (needed for wake events). 1254 */ 1255 readw(ioaddr + MIntrStatus); 1256 writew(MICRIntEn, ioaddr + MIntrCtrl); 1257 } 1258 1259 static int switch_port_external(struct net_device *dev) 1260 { 1261 struct netdev_private *np = netdev_priv(dev); 1262 void __iomem *ioaddr = ns_ioaddr(dev); 1263 u32 cfg; 1264 1265 cfg = readl(ioaddr + ChipConfig); 1266 if (cfg & CfgExtPhy) 1267 return 0; 1268 1269 if (netif_msg_link(np)) { 1270 printk(KERN_INFO "%s: switching to external transceiver.\n", 1271 dev->name); 1272 } 1273 1274 /* 1) switch back to external phy */ 1275 writel(cfg | (CfgExtPhy | CfgPhyDis), ioaddr + ChipConfig); 1276 readl(ioaddr + ChipConfig); 1277 udelay(1); 1278 1279 /* 2) reset the external phy: */ 1280 /* resetting the external PHY has been known to cause a hub supplying 1281 * power over Ethernet to kill the power. We don't want to kill 1282 * power to this computer, so we avoid resetting the phy. 1283 */ 1284 1285 /* 3) reinit the phy fixup, it got lost during power down. */ 1286 move_int_phy(dev, np->phy_addr_external); 1287 init_phy_fixup(dev); 1288 1289 return 1; 1290 } 1291 1292 static int switch_port_internal(struct net_device *dev) 1293 { 1294 struct netdev_private *np = netdev_priv(dev); 1295 void __iomem *ioaddr = ns_ioaddr(dev); 1296 int i; 1297 u32 cfg; 1298 u16 bmcr; 1299 1300 cfg = readl(ioaddr + ChipConfig); 1301 if (!(cfg &CfgExtPhy)) 1302 return 0; 1303 1304 if (netif_msg_link(np)) { 1305 printk(KERN_INFO "%s: switching to internal transceiver.\n", 1306 dev->name); 1307 } 1308 /* 1) switch back to internal phy: */ 1309 cfg = cfg & ~(CfgExtPhy | CfgPhyDis); 1310 writel(cfg, ioaddr + ChipConfig); 1311 readl(ioaddr + ChipConfig); 1312 udelay(1); 1313 1314 /* 2) reset the internal phy: */ 1315 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1316 writel(bmcr | BMCR_RESET, ioaddr+BasicControl+(MII_BMCR<<2)); 1317 readl(ioaddr + ChipConfig); 1318 udelay(10); 1319 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1320 bmcr = readw(ioaddr+BasicControl+(MII_BMCR<<2)); 1321 if (!(bmcr & BMCR_RESET)) 1322 break; 1323 udelay(10); 1324 } 1325 if (i==NATSEMI_HW_TIMEOUT && netif_msg_link(np)) { 1326 printk(KERN_INFO 1327 "%s: phy reset did not complete in %d usec.\n", 1328 dev->name, i*10); 1329 } 1330 /* 3) reinit the phy fixup, it got lost during power down. */ 1331 init_phy_fixup(dev); 1332 1333 return 1; 1334 } 1335 1336 /* Scan for a PHY on the external mii bus. 1337 * There are two tricky points: 1338 * - Do not scan while the internal phy is enabled. The internal phy will 1339 * crash: e.g. reads from the DSPCFG register will return odd values and 1340 * the nasty random phy reset code will reset the nic every few seconds. 1341 * - The internal phy must be moved around, an external phy could 1342 * have the same address as the internal phy. 1343 */ 1344 static int find_mii(struct net_device *dev) 1345 { 1346 struct netdev_private *np = netdev_priv(dev); 1347 int tmp; 1348 int i; 1349 int did_switch; 1350 1351 /* Switch to external phy */ 1352 did_switch = switch_port_external(dev); 1353 1354 /* Scan the possible phy addresses: 1355 * 1356 * PHY address 0 means that the phy is in isolate mode. Not yet 1357 * supported due to lack of test hardware. User space should 1358 * handle it through ethtool. 1359 */ 1360 for (i = 1; i <= 31; i++) { 1361 move_int_phy(dev, i); 1362 tmp = miiport_read(dev, i, MII_BMSR); 1363 if (tmp != 0xffff && tmp != 0x0000) { 1364 /* found something! */ 1365 np->mii = (mdio_read(dev, MII_PHYSID1) << 16) 1366 + mdio_read(dev, MII_PHYSID2); 1367 if (netif_msg_probe(np)) { 1368 printk(KERN_INFO "natsemi %s: found external phy %08x at address %d.\n", 1369 pci_name(np->pci_dev), np->mii, i); 1370 } 1371 break; 1372 } 1373 } 1374 /* And switch back to internal phy: */ 1375 if (did_switch) 1376 switch_port_internal(dev); 1377 return i; 1378 } 1379 1380 /* CFG bits [13:16] [18:23] */ 1381 #define CFG_RESET_SAVE 0xfde000 1382 /* WCSR bits [0:4] [9:10] */ 1383 #define WCSR_RESET_SAVE 0x61f 1384 /* RFCR bits [20] [22] [27:31] */ 1385 #define RFCR_RESET_SAVE 0xf8500000 1386 1387 static void natsemi_reset(struct net_device *dev) 1388 { 1389 int i; 1390 u32 cfg; 1391 u32 wcsr; 1392 u32 rfcr; 1393 u16 pmatch[3]; 1394 u16 sopass[3]; 1395 struct netdev_private *np = netdev_priv(dev); 1396 void __iomem *ioaddr = ns_ioaddr(dev); 1397 1398 /* 1399 * Resetting the chip causes some registers to be lost. 1400 * Natsemi suggests NOT reloading the EEPROM while live, so instead 1401 * we save the state that would have been loaded from EEPROM 1402 * on a normal power-up (see the spec EEPROM map). This assumes 1403 * whoever calls this will follow up with init_registers() eventually. 1404 */ 1405 1406 /* CFG */ 1407 cfg = readl(ioaddr + ChipConfig) & CFG_RESET_SAVE; 1408 /* WCSR */ 1409 wcsr = readl(ioaddr + WOLCmd) & WCSR_RESET_SAVE; 1410 /* RFCR */ 1411 rfcr = readl(ioaddr + RxFilterAddr) & RFCR_RESET_SAVE; 1412 /* PMATCH */ 1413 for (i = 0; i < 3; i++) { 1414 writel(i*2, ioaddr + RxFilterAddr); 1415 pmatch[i] = readw(ioaddr + RxFilterData); 1416 } 1417 /* SOPAS */ 1418 for (i = 0; i < 3; i++) { 1419 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1420 sopass[i] = readw(ioaddr + RxFilterData); 1421 } 1422 1423 /* now whack the chip */ 1424 writel(ChipReset, ioaddr + ChipCmd); 1425 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1426 if (!(readl(ioaddr + ChipCmd) & ChipReset)) 1427 break; 1428 udelay(5); 1429 } 1430 if (i==NATSEMI_HW_TIMEOUT) { 1431 printk(KERN_WARNING "%s: reset did not complete in %d usec.\n", 1432 dev->name, i*5); 1433 } else if (netif_msg_hw(np)) { 1434 printk(KERN_DEBUG "%s: reset completed in %d usec.\n", 1435 dev->name, i*5); 1436 } 1437 1438 /* restore CFG */ 1439 cfg |= readl(ioaddr + ChipConfig) & ~CFG_RESET_SAVE; 1440 /* turn on external phy if it was selected */ 1441 if (dev->if_port == PORT_TP) 1442 cfg &= ~(CfgExtPhy | CfgPhyDis); 1443 else 1444 cfg |= (CfgExtPhy | CfgPhyDis); 1445 writel(cfg, ioaddr + ChipConfig); 1446 /* restore WCSR */ 1447 wcsr |= readl(ioaddr + WOLCmd) & ~WCSR_RESET_SAVE; 1448 writel(wcsr, ioaddr + WOLCmd); 1449 /* read RFCR */ 1450 rfcr |= readl(ioaddr + RxFilterAddr) & ~RFCR_RESET_SAVE; 1451 /* restore PMATCH */ 1452 for (i = 0; i < 3; i++) { 1453 writel(i*2, ioaddr + RxFilterAddr); 1454 writew(pmatch[i], ioaddr + RxFilterData); 1455 } 1456 for (i = 0; i < 3; i++) { 1457 writel(0xa+(i*2), ioaddr + RxFilterAddr); 1458 writew(sopass[i], ioaddr + RxFilterData); 1459 } 1460 /* restore RFCR */ 1461 writel(rfcr, ioaddr + RxFilterAddr); 1462 } 1463 1464 static void reset_rx(struct net_device *dev) 1465 { 1466 int i; 1467 struct netdev_private *np = netdev_priv(dev); 1468 void __iomem *ioaddr = ns_ioaddr(dev); 1469 1470 np->intr_status &= ~RxResetDone; 1471 1472 writel(RxReset, ioaddr + ChipCmd); 1473 1474 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1475 np->intr_status |= readl(ioaddr + IntrStatus); 1476 if (np->intr_status & RxResetDone) 1477 break; 1478 udelay(15); 1479 } 1480 if (i==NATSEMI_HW_TIMEOUT) { 1481 printk(KERN_WARNING "%s: RX reset did not complete in %d usec.\n", 1482 dev->name, i*15); 1483 } else if (netif_msg_hw(np)) { 1484 printk(KERN_WARNING "%s: RX reset took %d usec.\n", 1485 dev->name, i*15); 1486 } 1487 } 1488 1489 static void natsemi_reload_eeprom(struct net_device *dev) 1490 { 1491 struct netdev_private *np = netdev_priv(dev); 1492 void __iomem *ioaddr = ns_ioaddr(dev); 1493 int i; 1494 1495 writel(EepromReload, ioaddr + PCIBusCfg); 1496 for (i=0;i<NATSEMI_HW_TIMEOUT;i++) { 1497 udelay(50); 1498 if (!(readl(ioaddr + PCIBusCfg) & EepromReload)) 1499 break; 1500 } 1501 if (i==NATSEMI_HW_TIMEOUT) { 1502 printk(KERN_WARNING "natsemi %s: EEPROM did not reload in %d usec.\n", 1503 pci_name(np->pci_dev), i*50); 1504 } else if (netif_msg_hw(np)) { 1505 printk(KERN_DEBUG "natsemi %s: EEPROM reloaded in %d usec.\n", 1506 pci_name(np->pci_dev), i*50); 1507 } 1508 } 1509 1510 static void natsemi_stop_rxtx(struct net_device *dev) 1511 { 1512 void __iomem * ioaddr = ns_ioaddr(dev); 1513 struct netdev_private *np = netdev_priv(dev); 1514 int i; 1515 1516 writel(RxOff | TxOff, ioaddr + ChipCmd); 1517 for(i=0;i< NATSEMI_HW_TIMEOUT;i++) { 1518 if ((readl(ioaddr + ChipCmd) & (TxOn|RxOn)) == 0) 1519 break; 1520 udelay(5); 1521 } 1522 if (i==NATSEMI_HW_TIMEOUT) { 1523 printk(KERN_WARNING "%s: Tx/Rx process did not stop in %d usec.\n", 1524 dev->name, i*5); 1525 } else if (netif_msg_hw(np)) { 1526 printk(KERN_DEBUG "%s: Tx/Rx process stopped in %d usec.\n", 1527 dev->name, i*5); 1528 } 1529 } 1530 1531 static int netdev_open(struct net_device *dev) 1532 { 1533 struct netdev_private *np = netdev_priv(dev); 1534 void __iomem * ioaddr = ns_ioaddr(dev); 1535 const int irq = np->pci_dev->irq; 1536 int i; 1537 1538 /* Reset the chip, just in case. */ 1539 natsemi_reset(dev); 1540 1541 i = request_irq(irq, intr_handler, IRQF_SHARED, dev->name, dev); 1542 if (i) return i; 1543 1544 if (netif_msg_ifup(np)) 1545 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n", 1546 dev->name, irq); 1547 i = alloc_ring(dev); 1548 if (i < 0) { 1549 free_irq(irq, dev); 1550 return i; 1551 } 1552 napi_enable(&np->napi); 1553 1554 init_ring(dev); 1555 spin_lock_irq(&np->lock); 1556 init_registers(dev); 1557 /* now set the MAC address according to dev->dev_addr */ 1558 for (i = 0; i < 3; i++) { 1559 u16 mac = (dev->dev_addr[2*i+1]<<8) + dev->dev_addr[2*i]; 1560 1561 writel(i*2, ioaddr + RxFilterAddr); 1562 writew(mac, ioaddr + RxFilterData); 1563 } 1564 writel(np->cur_rx_mode, ioaddr + RxFilterAddr); 1565 spin_unlock_irq(&np->lock); 1566 1567 netif_start_queue(dev); 1568 1569 if (netif_msg_ifup(np)) 1570 printk(KERN_DEBUG "%s: Done netdev_open(), status: %#08x.\n", 1571 dev->name, (int)readl(ioaddr + ChipCmd)); 1572 1573 /* Set the timer to check for link beat. */ 1574 init_timer(&np->timer); 1575 np->timer.expires = round_jiffies(jiffies + NATSEMI_TIMER_FREQ); 1576 np->timer.data = (unsigned long)dev; 1577 np->timer.function = netdev_timer; /* timer handler */ 1578 add_timer(&np->timer); 1579 1580 return 0; 1581 } 1582 1583 static void do_cable_magic(struct net_device *dev) 1584 { 1585 struct netdev_private *np = netdev_priv(dev); 1586 void __iomem *ioaddr = ns_ioaddr(dev); 1587 1588 if (dev->if_port != PORT_TP) 1589 return; 1590 1591 if (np->srr >= SRR_DP83816_A5) 1592 return; 1593 1594 /* 1595 * 100 MBit links with short cables can trip an issue with the chip. 1596 * The problem manifests as lots of CRC errors and/or flickering 1597 * activity LED while idle. This process is based on instructions 1598 * from engineers at National. 1599 */ 1600 if (readl(ioaddr + ChipConfig) & CfgSpeed100) { 1601 u16 data; 1602 1603 writew(1, ioaddr + PGSEL); 1604 /* 1605 * coefficient visibility should already be enabled via 1606 * DSPCFG | 0x1000 1607 */ 1608 data = readw(ioaddr + TSTDAT) & 0xff; 1609 /* 1610 * the value must be negative, and within certain values 1611 * (these values all come from National) 1612 */ 1613 if (!(data & 0x80) || ((data >= 0xd8) && (data <= 0xff))) { 1614 np = netdev_priv(dev); 1615 1616 /* the bug has been triggered - fix the coefficient */ 1617 writew(TSTDAT_FIXED, ioaddr + TSTDAT); 1618 /* lock the value */ 1619 data = readw(ioaddr + DSPCFG); 1620 np->dspcfg = data | DSPCFG_LOCK; 1621 writew(np->dspcfg, ioaddr + DSPCFG); 1622 } 1623 writew(0, ioaddr + PGSEL); 1624 } 1625 } 1626 1627 static void undo_cable_magic(struct net_device *dev) 1628 { 1629 u16 data; 1630 struct netdev_private *np = netdev_priv(dev); 1631 void __iomem * ioaddr = ns_ioaddr(dev); 1632 1633 if (dev->if_port != PORT_TP) 1634 return; 1635 1636 if (np->srr >= SRR_DP83816_A5) 1637 return; 1638 1639 writew(1, ioaddr + PGSEL); 1640 /* make sure the lock bit is clear */ 1641 data = readw(ioaddr + DSPCFG); 1642 np->dspcfg = data & ~DSPCFG_LOCK; 1643 writew(np->dspcfg, ioaddr + DSPCFG); 1644 writew(0, ioaddr + PGSEL); 1645 } 1646 1647 static void check_link(struct net_device *dev) 1648 { 1649 struct netdev_private *np = netdev_priv(dev); 1650 void __iomem * ioaddr = ns_ioaddr(dev); 1651 int duplex = np->duplex; 1652 u16 bmsr; 1653 1654 /* If we are ignoring the PHY then don't try reading it. */ 1655 if (np->ignore_phy) 1656 goto propagate_state; 1657 1658 /* The link status field is latched: it remains low after a temporary 1659 * link failure until it's read. We need the current link status, 1660 * thus read twice. 1661 */ 1662 mdio_read(dev, MII_BMSR); 1663 bmsr = mdio_read(dev, MII_BMSR); 1664 1665 if (!(bmsr & BMSR_LSTATUS)) { 1666 if (netif_carrier_ok(dev)) { 1667 if (netif_msg_link(np)) 1668 printk(KERN_NOTICE "%s: link down.\n", 1669 dev->name); 1670 netif_carrier_off(dev); 1671 undo_cable_magic(dev); 1672 } 1673 return; 1674 } 1675 if (!netif_carrier_ok(dev)) { 1676 if (netif_msg_link(np)) 1677 printk(KERN_NOTICE "%s: link up.\n", dev->name); 1678 netif_carrier_on(dev); 1679 do_cable_magic(dev); 1680 } 1681 1682 duplex = np->full_duplex; 1683 if (!duplex) { 1684 if (bmsr & BMSR_ANEGCOMPLETE) { 1685 int tmp = mii_nway_result( 1686 np->advertising & mdio_read(dev, MII_LPA)); 1687 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 1688 duplex = 1; 1689 } else if (mdio_read(dev, MII_BMCR) & BMCR_FULLDPLX) 1690 duplex = 1; 1691 } 1692 1693 propagate_state: 1694 /* if duplex is set then bit 28 must be set, too */ 1695 if (duplex ^ !!(np->rx_config & RxAcceptTx)) { 1696 if (netif_msg_link(np)) 1697 printk(KERN_INFO 1698 "%s: Setting %s-duplex based on negotiated " 1699 "link capability.\n", dev->name, 1700 duplex ? "full" : "half"); 1701 if (duplex) { 1702 np->rx_config |= RxAcceptTx; 1703 np->tx_config |= TxCarrierIgn | TxHeartIgn; 1704 } else { 1705 np->rx_config &= ~RxAcceptTx; 1706 np->tx_config &= ~(TxCarrierIgn | TxHeartIgn); 1707 } 1708 writel(np->tx_config, ioaddr + TxConfig); 1709 writel(np->rx_config, ioaddr + RxConfig); 1710 } 1711 } 1712 1713 static void init_registers(struct net_device *dev) 1714 { 1715 struct netdev_private *np = netdev_priv(dev); 1716 void __iomem * ioaddr = ns_ioaddr(dev); 1717 1718 init_phy_fixup(dev); 1719 1720 /* clear any interrupts that are pending, such as wake events */ 1721 readl(ioaddr + IntrStatus); 1722 1723 writel(np->ring_dma, ioaddr + RxRingPtr); 1724 writel(np->ring_dma + RX_RING_SIZE * sizeof(struct netdev_desc), 1725 ioaddr + TxRingPtr); 1726 1727 /* Initialize other registers. 1728 * Configure the PCI bus bursts and FIFO thresholds. 1729 * Configure for standard, in-spec Ethernet. 1730 * Start with half-duplex. check_link will update 1731 * to the correct settings. 1732 */ 1733 1734 /* DRTH: 2: start tx if 64 bytes are in the fifo 1735 * FLTH: 0x10: refill with next packet if 512 bytes are free 1736 * MXDMA: 0: up to 256 byte bursts. 1737 * MXDMA must be <= FLTH 1738 * ECRETRY=1 1739 * ATP=1 1740 */ 1741 np->tx_config = TxAutoPad | TxCollRetry | TxMxdma_256 | 1742 TX_FLTH_VAL | TX_DRTH_VAL_START; 1743 writel(np->tx_config, ioaddr + TxConfig); 1744 1745 /* DRTH 0x10: start copying to memory if 128 bytes are in the fifo 1746 * MXDMA 0: up to 256 byte bursts 1747 */ 1748 np->rx_config = RxMxdma_256 | RX_DRTH_VAL; 1749 /* if receive ring now has bigger buffers than normal, enable jumbo */ 1750 if (np->rx_buf_sz > NATSEMI_LONGPKT) 1751 np->rx_config |= RxAcceptLong; 1752 1753 writel(np->rx_config, ioaddr + RxConfig); 1754 1755 /* Disable PME: 1756 * The PME bit is initialized from the EEPROM contents. 1757 * PCI cards probably have PME disabled, but motherboard 1758 * implementations may have PME set to enable WakeOnLan. 1759 * With PME set the chip will scan incoming packets but 1760 * nothing will be written to memory. */ 1761 np->SavedClkRun = readl(ioaddr + ClkRun); 1762 writel(np->SavedClkRun & ~PMEEnable, ioaddr + ClkRun); 1763 if (np->SavedClkRun & PMEStatus && netif_msg_wol(np)) { 1764 printk(KERN_NOTICE "%s: Wake-up event %#08x\n", 1765 dev->name, readl(ioaddr + WOLCmd)); 1766 } 1767 1768 check_link(dev); 1769 __set_rx_mode(dev); 1770 1771 /* Enable interrupts by setting the interrupt mask. */ 1772 writel(DEFAULT_INTR, ioaddr + IntrMask); 1773 natsemi_irq_enable(dev); 1774 1775 writel(RxOn | TxOn, ioaddr + ChipCmd); 1776 writel(StatsClear, ioaddr + StatsCtrl); /* Clear Stats */ 1777 } 1778 1779 /* 1780 * netdev_timer: 1781 * Purpose: 1782 * 1) check for link changes. Usually they are handled by the MII interrupt 1783 * but it doesn't hurt to check twice. 1784 * 2) check for sudden death of the NIC: 1785 * It seems that a reference set for this chip went out with incorrect info, 1786 * and there exist boards that aren't quite right. An unexpected voltage 1787 * drop can cause the PHY to get itself in a weird state (basically reset). 1788 * NOTE: this only seems to affect revC chips. The user can disable 1789 * this check via dspcfg_workaround sysfs option. 1790 * 3) check of death of the RX path due to OOM 1791 */ 1792 static void netdev_timer(unsigned long data) 1793 { 1794 struct net_device *dev = (struct net_device *)data; 1795 struct netdev_private *np = netdev_priv(dev); 1796 void __iomem * ioaddr = ns_ioaddr(dev); 1797 int next_tick = NATSEMI_TIMER_FREQ; 1798 const int irq = np->pci_dev->irq; 1799 1800 if (netif_msg_timer(np)) { 1801 /* DO NOT read the IntrStatus register, 1802 * a read clears any pending interrupts. 1803 */ 1804 printk(KERN_DEBUG "%s: Media selection timer tick.\n", 1805 dev->name); 1806 } 1807 1808 if (dev->if_port == PORT_TP) { 1809 u16 dspcfg; 1810 1811 spin_lock_irq(&np->lock); 1812 /* check for a nasty random phy-reset - use dspcfg as a flag */ 1813 writew(1, ioaddr+PGSEL); 1814 dspcfg = readw(ioaddr+DSPCFG); 1815 writew(0, ioaddr+PGSEL); 1816 if (np->dspcfg_workaround && dspcfg != np->dspcfg) { 1817 if (!netif_queue_stopped(dev)) { 1818 spin_unlock_irq(&np->lock); 1819 if (netif_msg_drv(np)) 1820 printk(KERN_NOTICE "%s: possible phy reset: " 1821 "re-initializing\n", dev->name); 1822 disable_irq(irq); 1823 spin_lock_irq(&np->lock); 1824 natsemi_stop_rxtx(dev); 1825 dump_ring(dev); 1826 reinit_ring(dev); 1827 init_registers(dev); 1828 spin_unlock_irq(&np->lock); 1829 enable_irq(irq); 1830 } else { 1831 /* hurry back */ 1832 next_tick = HZ; 1833 spin_unlock_irq(&np->lock); 1834 } 1835 } else { 1836 /* init_registers() calls check_link() for the above case */ 1837 check_link(dev); 1838 spin_unlock_irq(&np->lock); 1839 } 1840 } else { 1841 spin_lock_irq(&np->lock); 1842 check_link(dev); 1843 spin_unlock_irq(&np->lock); 1844 } 1845 if (np->oom) { 1846 disable_irq(irq); 1847 np->oom = 0; 1848 refill_rx(dev); 1849 enable_irq(irq); 1850 if (!np->oom) { 1851 writel(RxOn, ioaddr + ChipCmd); 1852 } else { 1853 next_tick = 1; 1854 } 1855 } 1856 1857 if (next_tick > 1) 1858 mod_timer(&np->timer, round_jiffies(jiffies + next_tick)); 1859 else 1860 mod_timer(&np->timer, jiffies + next_tick); 1861 } 1862 1863 static void dump_ring(struct net_device *dev) 1864 { 1865 struct netdev_private *np = netdev_priv(dev); 1866 1867 if (netif_msg_pktdata(np)) { 1868 int i; 1869 printk(KERN_DEBUG " Tx ring at %p:\n", np->tx_ring); 1870 for (i = 0; i < TX_RING_SIZE; i++) { 1871 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1872 i, np->tx_ring[i].next_desc, 1873 np->tx_ring[i].cmd_status, 1874 np->tx_ring[i].addr); 1875 } 1876 printk(KERN_DEBUG " Rx ring %p:\n", np->rx_ring); 1877 for (i = 0; i < RX_RING_SIZE; i++) { 1878 printk(KERN_DEBUG " #%d desc. %#08x %#08x %#08x.\n", 1879 i, np->rx_ring[i].next_desc, 1880 np->rx_ring[i].cmd_status, 1881 np->rx_ring[i].addr); 1882 } 1883 } 1884 } 1885 1886 static void ns_tx_timeout(struct net_device *dev) 1887 { 1888 struct netdev_private *np = netdev_priv(dev); 1889 void __iomem * ioaddr = ns_ioaddr(dev); 1890 const int irq = np->pci_dev->irq; 1891 1892 disable_irq(irq); 1893 spin_lock_irq(&np->lock); 1894 if (!np->hands_off) { 1895 if (netif_msg_tx_err(np)) 1896 printk(KERN_WARNING 1897 "%s: Transmit timed out, status %#08x," 1898 " resetting...\n", 1899 dev->name, readl(ioaddr + IntrStatus)); 1900 dump_ring(dev); 1901 1902 natsemi_reset(dev); 1903 reinit_ring(dev); 1904 init_registers(dev); 1905 } else { 1906 printk(KERN_WARNING 1907 "%s: tx_timeout while in hands_off state?\n", 1908 dev->name); 1909 } 1910 spin_unlock_irq(&np->lock); 1911 enable_irq(irq); 1912 1913 netif_trans_update(dev); /* prevent tx timeout */ 1914 dev->stats.tx_errors++; 1915 netif_wake_queue(dev); 1916 } 1917 1918 static int alloc_ring(struct net_device *dev) 1919 { 1920 struct netdev_private *np = netdev_priv(dev); 1921 np->rx_ring = pci_alloc_consistent(np->pci_dev, 1922 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 1923 &np->ring_dma); 1924 if (!np->rx_ring) 1925 return -ENOMEM; 1926 np->tx_ring = &np->rx_ring[RX_RING_SIZE]; 1927 return 0; 1928 } 1929 1930 static void refill_rx(struct net_device *dev) 1931 { 1932 struct netdev_private *np = netdev_priv(dev); 1933 1934 /* Refill the Rx ring buffers. */ 1935 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) { 1936 struct sk_buff *skb; 1937 int entry = np->dirty_rx % RX_RING_SIZE; 1938 if (np->rx_skbuff[entry] == NULL) { 1939 unsigned int buflen = np->rx_buf_sz+NATSEMI_PADDING; 1940 skb = netdev_alloc_skb(dev, buflen); 1941 np->rx_skbuff[entry] = skb; 1942 if (skb == NULL) 1943 break; /* Better luck next round. */ 1944 np->rx_dma[entry] = pci_map_single(np->pci_dev, 1945 skb->data, buflen, PCI_DMA_FROMDEVICE); 1946 if (pci_dma_mapping_error(np->pci_dev, 1947 np->rx_dma[entry])) { 1948 dev_kfree_skb_any(skb); 1949 np->rx_skbuff[entry] = NULL; 1950 break; /* Better luck next round. */ 1951 } 1952 np->rx_ring[entry].addr = cpu_to_le32(np->rx_dma[entry]); 1953 } 1954 np->rx_ring[entry].cmd_status = cpu_to_le32(np->rx_buf_sz); 1955 } 1956 if (np->cur_rx - np->dirty_rx == RX_RING_SIZE) { 1957 if (netif_msg_rx_err(np)) 1958 printk(KERN_WARNING "%s: going OOM.\n", dev->name); 1959 np->oom = 1; 1960 } 1961 } 1962 1963 static void set_bufsize(struct net_device *dev) 1964 { 1965 struct netdev_private *np = netdev_priv(dev); 1966 if (dev->mtu <= ETH_DATA_LEN) 1967 np->rx_buf_sz = ETH_DATA_LEN + NATSEMI_HEADERS; 1968 else 1969 np->rx_buf_sz = dev->mtu + NATSEMI_HEADERS; 1970 } 1971 1972 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */ 1973 static void init_ring(struct net_device *dev) 1974 { 1975 struct netdev_private *np = netdev_priv(dev); 1976 int i; 1977 1978 /* 1) TX ring */ 1979 np->dirty_tx = np->cur_tx = 0; 1980 for (i = 0; i < TX_RING_SIZE; i++) { 1981 np->tx_skbuff[i] = NULL; 1982 np->tx_ring[i].next_desc = cpu_to_le32(np->ring_dma 1983 +sizeof(struct netdev_desc) 1984 *((i+1)%TX_RING_SIZE+RX_RING_SIZE)); 1985 np->tx_ring[i].cmd_status = 0; 1986 } 1987 1988 /* 2) RX ring */ 1989 np->dirty_rx = 0; 1990 np->cur_rx = RX_RING_SIZE; 1991 np->oom = 0; 1992 set_bufsize(dev); 1993 1994 np->rx_head_desc = &np->rx_ring[0]; 1995 1996 /* Please be careful before changing this loop - at least gcc-2.95.1 1997 * miscompiles it otherwise. 1998 */ 1999 /* Initialize all Rx descriptors. */ 2000 for (i = 0; i < RX_RING_SIZE; i++) { 2001 np->rx_ring[i].next_desc = cpu_to_le32(np->ring_dma 2002 +sizeof(struct netdev_desc) 2003 *((i+1)%RX_RING_SIZE)); 2004 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 2005 np->rx_skbuff[i] = NULL; 2006 } 2007 refill_rx(dev); 2008 dump_ring(dev); 2009 } 2010 2011 static void drain_tx(struct net_device *dev) 2012 { 2013 struct netdev_private *np = netdev_priv(dev); 2014 int i; 2015 2016 for (i = 0; i < TX_RING_SIZE; i++) { 2017 if (np->tx_skbuff[i]) { 2018 pci_unmap_single(np->pci_dev, 2019 np->tx_dma[i], np->tx_skbuff[i]->len, 2020 PCI_DMA_TODEVICE); 2021 dev_kfree_skb(np->tx_skbuff[i]); 2022 dev->stats.tx_dropped++; 2023 } 2024 np->tx_skbuff[i] = NULL; 2025 } 2026 } 2027 2028 static void drain_rx(struct net_device *dev) 2029 { 2030 struct netdev_private *np = netdev_priv(dev); 2031 unsigned int buflen = np->rx_buf_sz; 2032 int i; 2033 2034 /* Free all the skbuffs in the Rx queue. */ 2035 for (i = 0; i < RX_RING_SIZE; i++) { 2036 np->rx_ring[i].cmd_status = 0; 2037 np->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 2038 if (np->rx_skbuff[i]) { 2039 pci_unmap_single(np->pci_dev, np->rx_dma[i], 2040 buflen + NATSEMI_PADDING, 2041 PCI_DMA_FROMDEVICE); 2042 dev_kfree_skb(np->rx_skbuff[i]); 2043 } 2044 np->rx_skbuff[i] = NULL; 2045 } 2046 } 2047 2048 static void drain_ring(struct net_device *dev) 2049 { 2050 drain_rx(dev); 2051 drain_tx(dev); 2052 } 2053 2054 static void free_ring(struct net_device *dev) 2055 { 2056 struct netdev_private *np = netdev_priv(dev); 2057 pci_free_consistent(np->pci_dev, 2058 sizeof(struct netdev_desc) * (RX_RING_SIZE+TX_RING_SIZE), 2059 np->rx_ring, np->ring_dma); 2060 } 2061 2062 static void reinit_rx(struct net_device *dev) 2063 { 2064 struct netdev_private *np = netdev_priv(dev); 2065 int i; 2066 2067 /* RX Ring */ 2068 np->dirty_rx = 0; 2069 np->cur_rx = RX_RING_SIZE; 2070 np->rx_head_desc = &np->rx_ring[0]; 2071 /* Initialize all Rx descriptors. */ 2072 for (i = 0; i < RX_RING_SIZE; i++) 2073 np->rx_ring[i].cmd_status = cpu_to_le32(DescOwn); 2074 2075 refill_rx(dev); 2076 } 2077 2078 static void reinit_ring(struct net_device *dev) 2079 { 2080 struct netdev_private *np = netdev_priv(dev); 2081 int i; 2082 2083 /* drain TX ring */ 2084 drain_tx(dev); 2085 np->dirty_tx = np->cur_tx = 0; 2086 for (i=0;i<TX_RING_SIZE;i++) 2087 np->tx_ring[i].cmd_status = 0; 2088 2089 reinit_rx(dev); 2090 } 2091 2092 static netdev_tx_t start_tx(struct sk_buff *skb, struct net_device *dev) 2093 { 2094 struct netdev_private *np = netdev_priv(dev); 2095 void __iomem * ioaddr = ns_ioaddr(dev); 2096 unsigned entry; 2097 unsigned long flags; 2098 2099 /* Note: Ordering is important here, set the field with the 2100 "ownership" bit last, and only then increment cur_tx. */ 2101 2102 /* Calculate the next Tx descriptor entry. */ 2103 entry = np->cur_tx % TX_RING_SIZE; 2104 2105 np->tx_skbuff[entry] = skb; 2106 np->tx_dma[entry] = pci_map_single(np->pci_dev, 2107 skb->data,skb->len, PCI_DMA_TODEVICE); 2108 if (pci_dma_mapping_error(np->pci_dev, np->tx_dma[entry])) { 2109 np->tx_skbuff[entry] = NULL; 2110 dev_kfree_skb_irq(skb); 2111 dev->stats.tx_dropped++; 2112 return NETDEV_TX_OK; 2113 } 2114 2115 np->tx_ring[entry].addr = cpu_to_le32(np->tx_dma[entry]); 2116 2117 spin_lock_irqsave(&np->lock, flags); 2118 2119 if (!np->hands_off) { 2120 np->tx_ring[entry].cmd_status = cpu_to_le32(DescOwn | skb->len); 2121 /* StrongARM: Explicitly cache flush np->tx_ring and 2122 * skb->data,skb->len. */ 2123 wmb(); 2124 np->cur_tx++; 2125 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) { 2126 netdev_tx_done(dev); 2127 if (np->cur_tx - np->dirty_tx >= TX_QUEUE_LEN - 1) 2128 netif_stop_queue(dev); 2129 } 2130 /* Wake the potentially-idle transmit channel. */ 2131 writel(TxOn, ioaddr + ChipCmd); 2132 } else { 2133 dev_kfree_skb_irq(skb); 2134 dev->stats.tx_dropped++; 2135 } 2136 spin_unlock_irqrestore(&np->lock, flags); 2137 2138 if (netif_msg_tx_queued(np)) { 2139 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n", 2140 dev->name, np->cur_tx, entry); 2141 } 2142 return NETDEV_TX_OK; 2143 } 2144 2145 static void netdev_tx_done(struct net_device *dev) 2146 { 2147 struct netdev_private *np = netdev_priv(dev); 2148 2149 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) { 2150 int entry = np->dirty_tx % TX_RING_SIZE; 2151 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescOwn)) 2152 break; 2153 if (netif_msg_tx_done(np)) 2154 printk(KERN_DEBUG 2155 "%s: tx frame #%d finished, status %#08x.\n", 2156 dev->name, np->dirty_tx, 2157 le32_to_cpu(np->tx_ring[entry].cmd_status)); 2158 if (np->tx_ring[entry].cmd_status & cpu_to_le32(DescPktOK)) { 2159 dev->stats.tx_packets++; 2160 dev->stats.tx_bytes += np->tx_skbuff[entry]->len; 2161 } else { /* Various Tx errors */ 2162 int tx_status = 2163 le32_to_cpu(np->tx_ring[entry].cmd_status); 2164 if (tx_status & (DescTxAbort|DescTxExcColl)) 2165 dev->stats.tx_aborted_errors++; 2166 if (tx_status & DescTxFIFO) 2167 dev->stats.tx_fifo_errors++; 2168 if (tx_status & DescTxCarrier) 2169 dev->stats.tx_carrier_errors++; 2170 if (tx_status & DescTxOOWCol) 2171 dev->stats.tx_window_errors++; 2172 dev->stats.tx_errors++; 2173 } 2174 pci_unmap_single(np->pci_dev,np->tx_dma[entry], 2175 np->tx_skbuff[entry]->len, 2176 PCI_DMA_TODEVICE); 2177 /* Free the original skb. */ 2178 dev_kfree_skb_irq(np->tx_skbuff[entry]); 2179 np->tx_skbuff[entry] = NULL; 2180 } 2181 if (netif_queue_stopped(dev) && 2182 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) { 2183 /* The ring is no longer full, wake queue. */ 2184 netif_wake_queue(dev); 2185 } 2186 } 2187 2188 /* The interrupt handler doesn't actually handle interrupts itself, it 2189 * schedules a NAPI poll if there is anything to do. */ 2190 static irqreturn_t intr_handler(int irq, void *dev_instance) 2191 { 2192 struct net_device *dev = dev_instance; 2193 struct netdev_private *np = netdev_priv(dev); 2194 void __iomem * ioaddr = ns_ioaddr(dev); 2195 2196 /* Reading IntrStatus automatically acknowledges so don't do 2197 * that while interrupts are disabled, (for example, while a 2198 * poll is scheduled). */ 2199 if (np->hands_off || !readl(ioaddr + IntrEnable)) 2200 return IRQ_NONE; 2201 2202 np->intr_status = readl(ioaddr + IntrStatus); 2203 2204 if (!np->intr_status) 2205 return IRQ_NONE; 2206 2207 if (netif_msg_intr(np)) 2208 printk(KERN_DEBUG 2209 "%s: Interrupt, status %#08x, mask %#08x.\n", 2210 dev->name, np->intr_status, 2211 readl(ioaddr + IntrMask)); 2212 2213 prefetch(&np->rx_skbuff[np->cur_rx % RX_RING_SIZE]); 2214 2215 if (napi_schedule_prep(&np->napi)) { 2216 /* Disable interrupts and register for poll */ 2217 natsemi_irq_disable(dev); 2218 __napi_schedule(&np->napi); 2219 } else 2220 printk(KERN_WARNING 2221 "%s: Ignoring interrupt, status %#08x, mask %#08x.\n", 2222 dev->name, np->intr_status, 2223 readl(ioaddr + IntrMask)); 2224 2225 return IRQ_HANDLED; 2226 } 2227 2228 /* This is the NAPI poll routine. As well as the standard RX handling 2229 * it also handles all other interrupts that the chip might raise. 2230 */ 2231 static int natsemi_poll(struct napi_struct *napi, int budget) 2232 { 2233 struct netdev_private *np = container_of(napi, struct netdev_private, napi); 2234 struct net_device *dev = np->dev; 2235 void __iomem * ioaddr = ns_ioaddr(dev); 2236 int work_done = 0; 2237 2238 do { 2239 if (netif_msg_intr(np)) 2240 printk(KERN_DEBUG 2241 "%s: Poll, status %#08x, mask %#08x.\n", 2242 dev->name, np->intr_status, 2243 readl(ioaddr + IntrMask)); 2244 2245 /* netdev_rx() may read IntrStatus again if the RX state 2246 * machine falls over so do it first. */ 2247 if (np->intr_status & 2248 (IntrRxDone | IntrRxIntr | RxStatusFIFOOver | 2249 IntrRxErr | IntrRxOverrun)) { 2250 netdev_rx(dev, &work_done, budget); 2251 } 2252 2253 if (np->intr_status & 2254 (IntrTxDone | IntrTxIntr | IntrTxIdle | IntrTxErr)) { 2255 spin_lock(&np->lock); 2256 netdev_tx_done(dev); 2257 spin_unlock(&np->lock); 2258 } 2259 2260 /* Abnormal error summary/uncommon events handlers. */ 2261 if (np->intr_status & IntrAbnormalSummary) 2262 netdev_error(dev, np->intr_status); 2263 2264 if (work_done >= budget) 2265 return work_done; 2266 2267 np->intr_status = readl(ioaddr + IntrStatus); 2268 } while (np->intr_status); 2269 2270 napi_complete_done(napi, work_done); 2271 2272 /* Reenable interrupts providing nothing is trying to shut 2273 * the chip down. */ 2274 spin_lock(&np->lock); 2275 if (!np->hands_off) 2276 natsemi_irq_enable(dev); 2277 spin_unlock(&np->lock); 2278 2279 return work_done; 2280 } 2281 2282 /* This routine is logically part of the interrupt handler, but separated 2283 for clarity and better register allocation. */ 2284 static void netdev_rx(struct net_device *dev, int *work_done, int work_to_do) 2285 { 2286 struct netdev_private *np = netdev_priv(dev); 2287 int entry = np->cur_rx % RX_RING_SIZE; 2288 int boguscnt = np->dirty_rx + RX_RING_SIZE - np->cur_rx; 2289 s32 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2290 unsigned int buflen = np->rx_buf_sz; 2291 void __iomem * ioaddr = ns_ioaddr(dev); 2292 2293 /* If the driver owns the next entry it's a new packet. Send it up. */ 2294 while (desc_status < 0) { /* e.g. & DescOwn */ 2295 int pkt_len; 2296 if (netif_msg_rx_status(np)) 2297 printk(KERN_DEBUG 2298 " netdev_rx() entry %d status was %#08x.\n", 2299 entry, desc_status); 2300 if (--boguscnt < 0) 2301 break; 2302 2303 if (*work_done >= work_to_do) 2304 break; 2305 2306 (*work_done)++; 2307 2308 pkt_len = (desc_status & DescSizeMask) - 4; 2309 if ((desc_status&(DescMore|DescPktOK|DescRxLong)) != DescPktOK){ 2310 if (desc_status & DescMore) { 2311 unsigned long flags; 2312 2313 if (netif_msg_rx_err(np)) 2314 printk(KERN_WARNING 2315 "%s: Oversized(?) Ethernet " 2316 "frame spanned multiple " 2317 "buffers, entry %#08x " 2318 "status %#08x.\n", dev->name, 2319 np->cur_rx, desc_status); 2320 dev->stats.rx_length_errors++; 2321 2322 /* The RX state machine has probably 2323 * locked up beneath us. Follow the 2324 * reset procedure documented in 2325 * AN-1287. */ 2326 2327 spin_lock_irqsave(&np->lock, flags); 2328 reset_rx(dev); 2329 reinit_rx(dev); 2330 writel(np->ring_dma, ioaddr + RxRingPtr); 2331 check_link(dev); 2332 spin_unlock_irqrestore(&np->lock, flags); 2333 2334 /* We'll enable RX on exit from this 2335 * function. */ 2336 break; 2337 2338 } else { 2339 /* There was an error. */ 2340 dev->stats.rx_errors++; 2341 if (desc_status & (DescRxAbort|DescRxOver)) 2342 dev->stats.rx_over_errors++; 2343 if (desc_status & (DescRxLong|DescRxRunt)) 2344 dev->stats.rx_length_errors++; 2345 if (desc_status & (DescRxInvalid|DescRxAlign)) 2346 dev->stats.rx_frame_errors++; 2347 if (desc_status & DescRxCRC) 2348 dev->stats.rx_crc_errors++; 2349 } 2350 } else if (pkt_len > np->rx_buf_sz) { 2351 /* if this is the tail of a double buffer 2352 * packet, we've already counted the error 2353 * on the first part. Ignore the second half. 2354 */ 2355 } else { 2356 struct sk_buff *skb; 2357 /* Omit CRC size. */ 2358 /* Check if the packet is long enough to accept 2359 * without copying to a minimally-sized skbuff. */ 2360 if (pkt_len < rx_copybreak && 2361 (skb = netdev_alloc_skb(dev, pkt_len + RX_OFFSET)) != NULL) { 2362 /* 16 byte align the IP header */ 2363 skb_reserve(skb, RX_OFFSET); 2364 pci_dma_sync_single_for_cpu(np->pci_dev, 2365 np->rx_dma[entry], 2366 buflen, 2367 PCI_DMA_FROMDEVICE); 2368 skb_copy_to_linear_data(skb, 2369 np->rx_skbuff[entry]->data, pkt_len); 2370 skb_put(skb, pkt_len); 2371 pci_dma_sync_single_for_device(np->pci_dev, 2372 np->rx_dma[entry], 2373 buflen, 2374 PCI_DMA_FROMDEVICE); 2375 } else { 2376 pci_unmap_single(np->pci_dev, np->rx_dma[entry], 2377 buflen + NATSEMI_PADDING, 2378 PCI_DMA_FROMDEVICE); 2379 skb_put(skb = np->rx_skbuff[entry], pkt_len); 2380 np->rx_skbuff[entry] = NULL; 2381 } 2382 skb->protocol = eth_type_trans(skb, dev); 2383 netif_receive_skb(skb); 2384 dev->stats.rx_packets++; 2385 dev->stats.rx_bytes += pkt_len; 2386 } 2387 entry = (++np->cur_rx) % RX_RING_SIZE; 2388 np->rx_head_desc = &np->rx_ring[entry]; 2389 desc_status = le32_to_cpu(np->rx_head_desc->cmd_status); 2390 } 2391 refill_rx(dev); 2392 2393 /* Restart Rx engine if stopped. */ 2394 if (np->oom) 2395 mod_timer(&np->timer, jiffies + 1); 2396 else 2397 writel(RxOn, ioaddr + ChipCmd); 2398 } 2399 2400 static void netdev_error(struct net_device *dev, int intr_status) 2401 { 2402 struct netdev_private *np = netdev_priv(dev); 2403 void __iomem * ioaddr = ns_ioaddr(dev); 2404 2405 spin_lock(&np->lock); 2406 if (intr_status & LinkChange) { 2407 u16 lpa = mdio_read(dev, MII_LPA); 2408 if (mdio_read(dev, MII_BMCR) & BMCR_ANENABLE && 2409 netif_msg_link(np)) { 2410 printk(KERN_INFO 2411 "%s: Autonegotiation advertising" 2412 " %#04x partner %#04x.\n", dev->name, 2413 np->advertising, lpa); 2414 } 2415 2416 /* read MII int status to clear the flag */ 2417 readw(ioaddr + MIntrStatus); 2418 check_link(dev); 2419 } 2420 if (intr_status & StatsMax) { 2421 __get_stats(dev); 2422 } 2423 if (intr_status & IntrTxUnderrun) { 2424 if ((np->tx_config & TxDrthMask) < TX_DRTH_VAL_LIMIT) { 2425 np->tx_config += TX_DRTH_VAL_INC; 2426 if (netif_msg_tx_err(np)) 2427 printk(KERN_NOTICE 2428 "%s: increased tx threshold, txcfg %#08x.\n", 2429 dev->name, np->tx_config); 2430 } else { 2431 if (netif_msg_tx_err(np)) 2432 printk(KERN_NOTICE 2433 "%s: tx underrun with maximum tx threshold, txcfg %#08x.\n", 2434 dev->name, np->tx_config); 2435 } 2436 writel(np->tx_config, ioaddr + TxConfig); 2437 } 2438 if (intr_status & WOLPkt && netif_msg_wol(np)) { 2439 int wol_status = readl(ioaddr + WOLCmd); 2440 printk(KERN_NOTICE "%s: Link wake-up event %#08x\n", 2441 dev->name, wol_status); 2442 } 2443 if (intr_status & RxStatusFIFOOver) { 2444 if (netif_msg_rx_err(np) && netif_msg_intr(np)) { 2445 printk(KERN_NOTICE "%s: Rx status FIFO overrun\n", 2446 dev->name); 2447 } 2448 dev->stats.rx_fifo_errors++; 2449 dev->stats.rx_errors++; 2450 } 2451 /* Hmmmmm, it's not clear how to recover from PCI faults. */ 2452 if (intr_status & IntrPCIErr) { 2453 printk(KERN_NOTICE "%s: PCI error %#08x\n", dev->name, 2454 intr_status & IntrPCIErr); 2455 dev->stats.tx_fifo_errors++; 2456 dev->stats.tx_errors++; 2457 dev->stats.rx_fifo_errors++; 2458 dev->stats.rx_errors++; 2459 } 2460 spin_unlock(&np->lock); 2461 } 2462 2463 static void __get_stats(struct net_device *dev) 2464 { 2465 void __iomem * ioaddr = ns_ioaddr(dev); 2466 2467 /* The chip only need report frame silently dropped. */ 2468 dev->stats.rx_crc_errors += readl(ioaddr + RxCRCErrs); 2469 dev->stats.rx_missed_errors += readl(ioaddr + RxMissed); 2470 } 2471 2472 static struct net_device_stats *get_stats(struct net_device *dev) 2473 { 2474 struct netdev_private *np = netdev_priv(dev); 2475 2476 /* The chip only need report frame silently dropped. */ 2477 spin_lock_irq(&np->lock); 2478 if (netif_running(dev) && !np->hands_off) 2479 __get_stats(dev); 2480 spin_unlock_irq(&np->lock); 2481 2482 return &dev->stats; 2483 } 2484 2485 #ifdef CONFIG_NET_POLL_CONTROLLER 2486 static void natsemi_poll_controller(struct net_device *dev) 2487 { 2488 struct netdev_private *np = netdev_priv(dev); 2489 const int irq = np->pci_dev->irq; 2490 2491 disable_irq(irq); 2492 intr_handler(irq, dev); 2493 enable_irq(irq); 2494 } 2495 #endif 2496 2497 #define HASH_TABLE 0x200 2498 static void __set_rx_mode(struct net_device *dev) 2499 { 2500 void __iomem * ioaddr = ns_ioaddr(dev); 2501 struct netdev_private *np = netdev_priv(dev); 2502 u8 mc_filter[64]; /* Multicast hash filter */ 2503 u32 rx_mode; 2504 2505 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 2506 rx_mode = RxFilterEnable | AcceptBroadcast 2507 | AcceptAllMulticast | AcceptAllPhys | AcceptMyPhys; 2508 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2509 (dev->flags & IFF_ALLMULTI)) { 2510 rx_mode = RxFilterEnable | AcceptBroadcast 2511 | AcceptAllMulticast | AcceptMyPhys; 2512 } else { 2513 struct netdev_hw_addr *ha; 2514 int i; 2515 2516 memset(mc_filter, 0, sizeof(mc_filter)); 2517 netdev_for_each_mc_addr(ha, dev) { 2518 int b = (ether_crc(ETH_ALEN, ha->addr) >> 23) & 0x1ff; 2519 mc_filter[b/8] |= (1 << (b & 0x07)); 2520 } 2521 rx_mode = RxFilterEnable | AcceptBroadcast 2522 | AcceptMulticast | AcceptMyPhys; 2523 for (i = 0; i < 64; i += 2) { 2524 writel(HASH_TABLE + i, ioaddr + RxFilterAddr); 2525 writel((mc_filter[i + 1] << 8) + mc_filter[i], 2526 ioaddr + RxFilterData); 2527 } 2528 } 2529 writel(rx_mode, ioaddr + RxFilterAddr); 2530 np->cur_rx_mode = rx_mode; 2531 } 2532 2533 static int natsemi_change_mtu(struct net_device *dev, int new_mtu) 2534 { 2535 dev->mtu = new_mtu; 2536 2537 /* synchronized against open : rtnl_lock() held by caller */ 2538 if (netif_running(dev)) { 2539 struct netdev_private *np = netdev_priv(dev); 2540 void __iomem * ioaddr = ns_ioaddr(dev); 2541 const int irq = np->pci_dev->irq; 2542 2543 disable_irq(irq); 2544 spin_lock(&np->lock); 2545 /* stop engines */ 2546 natsemi_stop_rxtx(dev); 2547 /* drain rx queue */ 2548 drain_rx(dev); 2549 /* change buffers */ 2550 set_bufsize(dev); 2551 reinit_rx(dev); 2552 writel(np->ring_dma, ioaddr + RxRingPtr); 2553 /* restart engines */ 2554 writel(RxOn | TxOn, ioaddr + ChipCmd); 2555 spin_unlock(&np->lock); 2556 enable_irq(irq); 2557 } 2558 return 0; 2559 } 2560 2561 static void set_rx_mode(struct net_device *dev) 2562 { 2563 struct netdev_private *np = netdev_priv(dev); 2564 spin_lock_irq(&np->lock); 2565 if (!np->hands_off) 2566 __set_rx_mode(dev); 2567 spin_unlock_irq(&np->lock); 2568 } 2569 2570 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2571 { 2572 struct netdev_private *np = netdev_priv(dev); 2573 strlcpy(info->driver, DRV_NAME, sizeof(info->driver)); 2574 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 2575 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info)); 2576 } 2577 2578 static int get_regs_len(struct net_device *dev) 2579 { 2580 return NATSEMI_REGS_SIZE; 2581 } 2582 2583 static int get_eeprom_len(struct net_device *dev) 2584 { 2585 struct netdev_private *np = netdev_priv(dev); 2586 return np->eeprom_size; 2587 } 2588 2589 static int get_link_ksettings(struct net_device *dev, 2590 struct ethtool_link_ksettings *ecmd) 2591 { 2592 struct netdev_private *np = netdev_priv(dev); 2593 spin_lock_irq(&np->lock); 2594 netdev_get_ecmd(dev, ecmd); 2595 spin_unlock_irq(&np->lock); 2596 return 0; 2597 } 2598 2599 static int set_link_ksettings(struct net_device *dev, 2600 const struct ethtool_link_ksettings *ecmd) 2601 { 2602 struct netdev_private *np = netdev_priv(dev); 2603 int res; 2604 spin_lock_irq(&np->lock); 2605 res = netdev_set_ecmd(dev, ecmd); 2606 spin_unlock_irq(&np->lock); 2607 return res; 2608 } 2609 2610 static void get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2611 { 2612 struct netdev_private *np = netdev_priv(dev); 2613 spin_lock_irq(&np->lock); 2614 netdev_get_wol(dev, &wol->supported, &wol->wolopts); 2615 netdev_get_sopass(dev, wol->sopass); 2616 spin_unlock_irq(&np->lock); 2617 } 2618 2619 static int set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2620 { 2621 struct netdev_private *np = netdev_priv(dev); 2622 int res; 2623 spin_lock_irq(&np->lock); 2624 netdev_set_wol(dev, wol->wolopts); 2625 res = netdev_set_sopass(dev, wol->sopass); 2626 spin_unlock_irq(&np->lock); 2627 return res; 2628 } 2629 2630 static void get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf) 2631 { 2632 struct netdev_private *np = netdev_priv(dev); 2633 regs->version = NATSEMI_REGS_VER; 2634 spin_lock_irq(&np->lock); 2635 netdev_get_regs(dev, buf); 2636 spin_unlock_irq(&np->lock); 2637 } 2638 2639 static u32 get_msglevel(struct net_device *dev) 2640 { 2641 struct netdev_private *np = netdev_priv(dev); 2642 return np->msg_enable; 2643 } 2644 2645 static void set_msglevel(struct net_device *dev, u32 val) 2646 { 2647 struct netdev_private *np = netdev_priv(dev); 2648 np->msg_enable = val; 2649 } 2650 2651 static int nway_reset(struct net_device *dev) 2652 { 2653 int tmp; 2654 int r = -EINVAL; 2655 /* if autoneg is off, it's an error */ 2656 tmp = mdio_read(dev, MII_BMCR); 2657 if (tmp & BMCR_ANENABLE) { 2658 tmp |= (BMCR_ANRESTART); 2659 mdio_write(dev, MII_BMCR, tmp); 2660 r = 0; 2661 } 2662 return r; 2663 } 2664 2665 static u32 get_link(struct net_device *dev) 2666 { 2667 /* LSTATUS is latched low until a read - so read twice */ 2668 mdio_read(dev, MII_BMSR); 2669 return (mdio_read(dev, MII_BMSR)&BMSR_LSTATUS) ? 1:0; 2670 } 2671 2672 static int get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) 2673 { 2674 struct netdev_private *np = netdev_priv(dev); 2675 u8 *eebuf; 2676 int res; 2677 2678 eebuf = kmalloc(np->eeprom_size, GFP_KERNEL); 2679 if (!eebuf) 2680 return -ENOMEM; 2681 2682 eeprom->magic = PCI_VENDOR_ID_NS | (PCI_DEVICE_ID_NS_83815<<16); 2683 spin_lock_irq(&np->lock); 2684 res = netdev_get_eeprom(dev, eebuf); 2685 spin_unlock_irq(&np->lock); 2686 if (!res) 2687 memcpy(data, eebuf+eeprom->offset, eeprom->len); 2688 kfree(eebuf); 2689 return res; 2690 } 2691 2692 static const struct ethtool_ops ethtool_ops = { 2693 .get_drvinfo = get_drvinfo, 2694 .get_regs_len = get_regs_len, 2695 .get_eeprom_len = get_eeprom_len, 2696 .get_wol = get_wol, 2697 .set_wol = set_wol, 2698 .get_regs = get_regs, 2699 .get_msglevel = get_msglevel, 2700 .set_msglevel = set_msglevel, 2701 .nway_reset = nway_reset, 2702 .get_link = get_link, 2703 .get_eeprom = get_eeprom, 2704 .get_link_ksettings = get_link_ksettings, 2705 .set_link_ksettings = set_link_ksettings, 2706 }; 2707 2708 static int netdev_set_wol(struct net_device *dev, u32 newval) 2709 { 2710 struct netdev_private *np = netdev_priv(dev); 2711 void __iomem * ioaddr = ns_ioaddr(dev); 2712 u32 data = readl(ioaddr + WOLCmd) & ~WakeOptsSummary; 2713 2714 /* translate to bitmasks this chip understands */ 2715 if (newval & WAKE_PHY) 2716 data |= WakePhy; 2717 if (newval & WAKE_UCAST) 2718 data |= WakeUnicast; 2719 if (newval & WAKE_MCAST) 2720 data |= WakeMulticast; 2721 if (newval & WAKE_BCAST) 2722 data |= WakeBroadcast; 2723 if (newval & WAKE_ARP) 2724 data |= WakeArp; 2725 if (newval & WAKE_MAGIC) 2726 data |= WakeMagic; 2727 if (np->srr >= SRR_DP83815_D) { 2728 if (newval & WAKE_MAGICSECURE) { 2729 data |= WakeMagicSecure; 2730 } 2731 } 2732 2733 writel(data, ioaddr + WOLCmd); 2734 2735 return 0; 2736 } 2737 2738 static int netdev_get_wol(struct net_device *dev, u32 *supported, u32 *cur) 2739 { 2740 struct netdev_private *np = netdev_priv(dev); 2741 void __iomem * ioaddr = ns_ioaddr(dev); 2742 u32 regval = readl(ioaddr + WOLCmd); 2743 2744 *supported = (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST 2745 | WAKE_ARP | WAKE_MAGIC); 2746 2747 if (np->srr >= SRR_DP83815_D) { 2748 /* SOPASS works on revD and higher */ 2749 *supported |= WAKE_MAGICSECURE; 2750 } 2751 *cur = 0; 2752 2753 /* translate from chip bitmasks */ 2754 if (regval & WakePhy) 2755 *cur |= WAKE_PHY; 2756 if (regval & WakeUnicast) 2757 *cur |= WAKE_UCAST; 2758 if (regval & WakeMulticast) 2759 *cur |= WAKE_MCAST; 2760 if (regval & WakeBroadcast) 2761 *cur |= WAKE_BCAST; 2762 if (regval & WakeArp) 2763 *cur |= WAKE_ARP; 2764 if (regval & WakeMagic) 2765 *cur |= WAKE_MAGIC; 2766 if (regval & WakeMagicSecure) { 2767 /* this can be on in revC, but it's broken */ 2768 *cur |= WAKE_MAGICSECURE; 2769 } 2770 2771 return 0; 2772 } 2773 2774 static int netdev_set_sopass(struct net_device *dev, u8 *newval) 2775 { 2776 struct netdev_private *np = netdev_priv(dev); 2777 void __iomem * ioaddr = ns_ioaddr(dev); 2778 u16 *sval = (u16 *)newval; 2779 u32 addr; 2780 2781 if (np->srr < SRR_DP83815_D) { 2782 return 0; 2783 } 2784 2785 /* enable writing to these registers by disabling the RX filter */ 2786 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2787 addr &= ~RxFilterEnable; 2788 writel(addr, ioaddr + RxFilterAddr); 2789 2790 /* write the three words to (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2791 writel(addr | 0xa, ioaddr + RxFilterAddr); 2792 writew(sval[0], ioaddr + RxFilterData); 2793 2794 writel(addr | 0xc, ioaddr + RxFilterAddr); 2795 writew(sval[1], ioaddr + RxFilterData); 2796 2797 writel(addr | 0xe, ioaddr + RxFilterAddr); 2798 writew(sval[2], ioaddr + RxFilterData); 2799 2800 /* re-enable the RX filter */ 2801 writel(addr | RxFilterEnable, ioaddr + RxFilterAddr); 2802 2803 return 0; 2804 } 2805 2806 static int netdev_get_sopass(struct net_device *dev, u8 *data) 2807 { 2808 struct netdev_private *np = netdev_priv(dev); 2809 void __iomem * ioaddr = ns_ioaddr(dev); 2810 u16 *sval = (u16 *)data; 2811 u32 addr; 2812 2813 if (np->srr < SRR_DP83815_D) { 2814 sval[0] = sval[1] = sval[2] = 0; 2815 return 0; 2816 } 2817 2818 /* read the three words from (undocumented) RFCR vals 0xa, 0xc, 0xe */ 2819 addr = readl(ioaddr + RxFilterAddr) & ~RFCRAddressMask; 2820 2821 writel(addr | 0xa, ioaddr + RxFilterAddr); 2822 sval[0] = readw(ioaddr + RxFilterData); 2823 2824 writel(addr | 0xc, ioaddr + RxFilterAddr); 2825 sval[1] = readw(ioaddr + RxFilterData); 2826 2827 writel(addr | 0xe, ioaddr + RxFilterAddr); 2828 sval[2] = readw(ioaddr + RxFilterData); 2829 2830 writel(addr, ioaddr + RxFilterAddr); 2831 2832 return 0; 2833 } 2834 2835 static int netdev_get_ecmd(struct net_device *dev, 2836 struct ethtool_link_ksettings *ecmd) 2837 { 2838 struct netdev_private *np = netdev_priv(dev); 2839 u32 supported, advertising; 2840 u32 tmp; 2841 2842 ecmd->base.port = dev->if_port; 2843 ecmd->base.speed = np->speed; 2844 ecmd->base.duplex = np->duplex; 2845 ecmd->base.autoneg = np->autoneg; 2846 advertising = 0; 2847 2848 if (np->advertising & ADVERTISE_10HALF) 2849 advertising |= ADVERTISED_10baseT_Half; 2850 if (np->advertising & ADVERTISE_10FULL) 2851 advertising |= ADVERTISED_10baseT_Full; 2852 if (np->advertising & ADVERTISE_100HALF) 2853 advertising |= ADVERTISED_100baseT_Half; 2854 if (np->advertising & ADVERTISE_100FULL) 2855 advertising |= ADVERTISED_100baseT_Full; 2856 supported = (SUPPORTED_Autoneg | 2857 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | 2858 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | 2859 SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_FIBRE); 2860 ecmd->base.phy_address = np->phy_addr_external; 2861 /* 2862 * We intentionally report the phy address of the external 2863 * phy, even if the internal phy is used. This is necessary 2864 * to work around a deficiency of the ethtool interface: 2865 * It's only possible to query the settings of the active 2866 * port. Therefore 2867 * # ethtool -s ethX port mii 2868 * actually sends an ioctl to switch to port mii with the 2869 * settings that are used for the current active port. 2870 * If we would report a different phy address in this 2871 * command, then 2872 * # ethtool -s ethX port tp;ethtool -s ethX port mii 2873 * would unintentionally change the phy address. 2874 * 2875 * Fortunately the phy address doesn't matter with the 2876 * internal phy... 2877 */ 2878 2879 /* set information based on active port type */ 2880 switch (ecmd->base.port) { 2881 default: 2882 case PORT_TP: 2883 advertising |= ADVERTISED_TP; 2884 break; 2885 case PORT_MII: 2886 advertising |= ADVERTISED_MII; 2887 break; 2888 case PORT_FIBRE: 2889 advertising |= ADVERTISED_FIBRE; 2890 break; 2891 } 2892 2893 /* if autonegotiation is on, try to return the active speed/duplex */ 2894 if (ecmd->base.autoneg == AUTONEG_ENABLE) { 2895 advertising |= ADVERTISED_Autoneg; 2896 tmp = mii_nway_result( 2897 np->advertising & mdio_read(dev, MII_LPA)); 2898 if (tmp == LPA_100FULL || tmp == LPA_100HALF) 2899 ecmd->base.speed = SPEED_100; 2900 else 2901 ecmd->base.speed = SPEED_10; 2902 if (tmp == LPA_100FULL || tmp == LPA_10FULL) 2903 ecmd->base.duplex = DUPLEX_FULL; 2904 else 2905 ecmd->base.duplex = DUPLEX_HALF; 2906 } 2907 2908 /* ignore maxtxpkt, maxrxpkt for now */ 2909 2910 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.supported, 2911 supported); 2912 ethtool_convert_legacy_u32_to_link_mode(ecmd->link_modes.advertising, 2913 advertising); 2914 2915 return 0; 2916 } 2917 2918 static int netdev_set_ecmd(struct net_device *dev, 2919 const struct ethtool_link_ksettings *ecmd) 2920 { 2921 struct netdev_private *np = netdev_priv(dev); 2922 u32 advertising; 2923 2924 ethtool_convert_link_mode_to_legacy_u32(&advertising, 2925 ecmd->link_modes.advertising); 2926 2927 if (ecmd->base.port != PORT_TP && 2928 ecmd->base.port != PORT_MII && 2929 ecmd->base.port != PORT_FIBRE) 2930 return -EINVAL; 2931 if (ecmd->base.autoneg == AUTONEG_ENABLE) { 2932 if ((advertising & (ADVERTISED_10baseT_Half | 2933 ADVERTISED_10baseT_Full | 2934 ADVERTISED_100baseT_Half | 2935 ADVERTISED_100baseT_Full)) == 0) { 2936 return -EINVAL; 2937 } 2938 } else if (ecmd->base.autoneg == AUTONEG_DISABLE) { 2939 u32 speed = ecmd->base.speed; 2940 if (speed != SPEED_10 && speed != SPEED_100) 2941 return -EINVAL; 2942 if (ecmd->base.duplex != DUPLEX_HALF && 2943 ecmd->base.duplex != DUPLEX_FULL) 2944 return -EINVAL; 2945 } else { 2946 return -EINVAL; 2947 } 2948 2949 /* 2950 * If we're ignoring the PHY then autoneg and the internal 2951 * transceiver are really not going to work so don't let the 2952 * user select them. 2953 */ 2954 if (np->ignore_phy && (ecmd->base.autoneg == AUTONEG_ENABLE || 2955 ecmd->base.port == PORT_TP)) 2956 return -EINVAL; 2957 2958 /* 2959 * maxtxpkt, maxrxpkt: ignored for now. 2960 * 2961 * transceiver: 2962 * PORT_TP is always XCVR_INTERNAL, PORT_MII and PORT_FIBRE are always 2963 * XCVR_EXTERNAL. The implementation thus ignores ecmd->transceiver and 2964 * selects based on ecmd->port. 2965 * 2966 * Actually PORT_FIBRE is nearly identical to PORT_MII: it's for fibre 2967 * phys that are connected to the mii bus. It's used to apply fibre 2968 * specific updates. 2969 */ 2970 2971 /* WHEW! now lets bang some bits */ 2972 2973 /* save the parms */ 2974 dev->if_port = ecmd->base.port; 2975 np->autoneg = ecmd->base.autoneg; 2976 np->phy_addr_external = ecmd->base.phy_address & PhyAddrMask; 2977 if (np->autoneg == AUTONEG_ENABLE) { 2978 /* advertise only what has been requested */ 2979 np->advertising &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4); 2980 if (advertising & ADVERTISED_10baseT_Half) 2981 np->advertising |= ADVERTISE_10HALF; 2982 if (advertising & ADVERTISED_10baseT_Full) 2983 np->advertising |= ADVERTISE_10FULL; 2984 if (advertising & ADVERTISED_100baseT_Half) 2985 np->advertising |= ADVERTISE_100HALF; 2986 if (advertising & ADVERTISED_100baseT_Full) 2987 np->advertising |= ADVERTISE_100FULL; 2988 } else { 2989 np->speed = ecmd->base.speed; 2990 np->duplex = ecmd->base.duplex; 2991 /* user overriding the initial full duplex parm? */ 2992 if (np->duplex == DUPLEX_HALF) 2993 np->full_duplex = 0; 2994 } 2995 2996 /* get the right phy enabled */ 2997 if (ecmd->base.port == PORT_TP) 2998 switch_port_internal(dev); 2999 else 3000 switch_port_external(dev); 3001 3002 /* set parms and see how this affected our link status */ 3003 init_phy_fixup(dev); 3004 check_link(dev); 3005 return 0; 3006 } 3007 3008 static int netdev_get_regs(struct net_device *dev, u8 *buf) 3009 { 3010 int i; 3011 int j; 3012 u32 rfcr; 3013 u32 *rbuf = (u32 *)buf; 3014 void __iomem * ioaddr = ns_ioaddr(dev); 3015 3016 /* read non-mii page 0 of registers */ 3017 for (i = 0; i < NATSEMI_PG0_NREGS/2; i++) { 3018 rbuf[i] = readl(ioaddr + i*4); 3019 } 3020 3021 /* read current mii registers */ 3022 for (i = NATSEMI_PG0_NREGS/2; i < NATSEMI_PG0_NREGS; i++) 3023 rbuf[i] = mdio_read(dev, i & 0x1f); 3024 3025 /* read only the 'magic' registers from page 1 */ 3026 writew(1, ioaddr + PGSEL); 3027 rbuf[i++] = readw(ioaddr + PMDCSR); 3028 rbuf[i++] = readw(ioaddr + TSTDAT); 3029 rbuf[i++] = readw(ioaddr + DSPCFG); 3030 rbuf[i++] = readw(ioaddr + SDCFG); 3031 writew(0, ioaddr + PGSEL); 3032 3033 /* read RFCR indexed registers */ 3034 rfcr = readl(ioaddr + RxFilterAddr); 3035 for (j = 0; j < NATSEMI_RFDR_NREGS; j++) { 3036 writel(j*2, ioaddr + RxFilterAddr); 3037 rbuf[i++] = readw(ioaddr + RxFilterData); 3038 } 3039 writel(rfcr, ioaddr + RxFilterAddr); 3040 3041 /* the interrupt status is clear-on-read - see if we missed any */ 3042 if (rbuf[4] & rbuf[5]) { 3043 printk(KERN_WARNING 3044 "%s: shoot, we dropped an interrupt (%#08x)\n", 3045 dev->name, rbuf[4] & rbuf[5]); 3046 } 3047 3048 return 0; 3049 } 3050 3051 #define SWAP_BITS(x) ( (((x) & 0x0001) << 15) | (((x) & 0x0002) << 13) \ 3052 | (((x) & 0x0004) << 11) | (((x) & 0x0008) << 9) \ 3053 | (((x) & 0x0010) << 7) | (((x) & 0x0020) << 5) \ 3054 | (((x) & 0x0040) << 3) | (((x) & 0x0080) << 1) \ 3055 | (((x) & 0x0100) >> 1) | (((x) & 0x0200) >> 3) \ 3056 | (((x) & 0x0400) >> 5) | (((x) & 0x0800) >> 7) \ 3057 | (((x) & 0x1000) >> 9) | (((x) & 0x2000) >> 11) \ 3058 | (((x) & 0x4000) >> 13) | (((x) & 0x8000) >> 15) ) 3059 3060 static int netdev_get_eeprom(struct net_device *dev, u8 *buf) 3061 { 3062 int i; 3063 u16 *ebuf = (u16 *)buf; 3064 void __iomem * ioaddr = ns_ioaddr(dev); 3065 struct netdev_private *np = netdev_priv(dev); 3066 3067 /* eeprom_read reads 16 bits, and indexes by 16 bits */ 3068 for (i = 0; i < np->eeprom_size/2; i++) { 3069 ebuf[i] = eeprom_read(ioaddr, i); 3070 /* The EEPROM itself stores data bit-swapped, but eeprom_read 3071 * reads it back "sanely". So we swap it back here in order to 3072 * present it to userland as it is stored. */ 3073 ebuf[i] = SWAP_BITS(ebuf[i]); 3074 } 3075 return 0; 3076 } 3077 3078 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3079 { 3080 struct mii_ioctl_data *data = if_mii(rq); 3081 struct netdev_private *np = netdev_priv(dev); 3082 3083 switch(cmd) { 3084 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 3085 data->phy_id = np->phy_addr_external; 3086 /* Fall Through */ 3087 3088 case SIOCGMIIREG: /* Read MII PHY register. */ 3089 /* The phy_id is not enough to uniquely identify 3090 * the intended target. Therefore the command is sent to 3091 * the given mii on the current port. 3092 */ 3093 if (dev->if_port == PORT_TP) { 3094 if ((data->phy_id & 0x1f) == np->phy_addr_external) 3095 data->val_out = mdio_read(dev, 3096 data->reg_num & 0x1f); 3097 else 3098 data->val_out = 0; 3099 } else { 3100 move_int_phy(dev, data->phy_id & 0x1f); 3101 data->val_out = miiport_read(dev, data->phy_id & 0x1f, 3102 data->reg_num & 0x1f); 3103 } 3104 return 0; 3105 3106 case SIOCSMIIREG: /* Write MII PHY register. */ 3107 if (dev->if_port == PORT_TP) { 3108 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3109 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3110 np->advertising = data->val_in; 3111 mdio_write(dev, data->reg_num & 0x1f, 3112 data->val_in); 3113 } 3114 } else { 3115 if ((data->phy_id & 0x1f) == np->phy_addr_external) { 3116 if ((data->reg_num & 0x1f) == MII_ADVERTISE) 3117 np->advertising = data->val_in; 3118 } 3119 move_int_phy(dev, data->phy_id & 0x1f); 3120 miiport_write(dev, data->phy_id & 0x1f, 3121 data->reg_num & 0x1f, 3122 data->val_in); 3123 } 3124 return 0; 3125 default: 3126 return -EOPNOTSUPP; 3127 } 3128 } 3129 3130 static void enable_wol_mode(struct net_device *dev, int enable_intr) 3131 { 3132 void __iomem * ioaddr = ns_ioaddr(dev); 3133 struct netdev_private *np = netdev_priv(dev); 3134 3135 if (netif_msg_wol(np)) 3136 printk(KERN_INFO "%s: remaining active for wake-on-lan\n", 3137 dev->name); 3138 3139 /* For WOL we must restart the rx process in silent mode. 3140 * Write NULL to the RxRingPtr. Only possible if 3141 * rx process is stopped 3142 */ 3143 writel(0, ioaddr + RxRingPtr); 3144 3145 /* read WoL status to clear */ 3146 readl(ioaddr + WOLCmd); 3147 3148 /* PME on, clear status */ 3149 writel(np->SavedClkRun | PMEEnable | PMEStatus, ioaddr + ClkRun); 3150 3151 /* and restart the rx process */ 3152 writel(RxOn, ioaddr + ChipCmd); 3153 3154 if (enable_intr) { 3155 /* enable the WOL interrupt. 3156 * Could be used to send a netlink message. 3157 */ 3158 writel(WOLPkt | LinkChange, ioaddr + IntrMask); 3159 natsemi_irq_enable(dev); 3160 } 3161 } 3162 3163 static int netdev_close(struct net_device *dev) 3164 { 3165 void __iomem * ioaddr = ns_ioaddr(dev); 3166 struct netdev_private *np = netdev_priv(dev); 3167 const int irq = np->pci_dev->irq; 3168 3169 if (netif_msg_ifdown(np)) 3170 printk(KERN_DEBUG 3171 "%s: Shutting down ethercard, status was %#04x.\n", 3172 dev->name, (int)readl(ioaddr + ChipCmd)); 3173 if (netif_msg_pktdata(np)) 3174 printk(KERN_DEBUG 3175 "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n", 3176 dev->name, np->cur_tx, np->dirty_tx, 3177 np->cur_rx, np->dirty_rx); 3178 3179 napi_disable(&np->napi); 3180 3181 /* 3182 * FIXME: what if someone tries to close a device 3183 * that is suspended? 3184 * Should we reenable the nic to switch to 3185 * the final WOL settings? 3186 */ 3187 3188 del_timer_sync(&np->timer); 3189 disable_irq(irq); 3190 spin_lock_irq(&np->lock); 3191 natsemi_irq_disable(dev); 3192 np->hands_off = 1; 3193 spin_unlock_irq(&np->lock); 3194 enable_irq(irq); 3195 3196 free_irq(irq, dev); 3197 3198 /* Interrupt disabled, interrupt handler released, 3199 * queue stopped, timer deleted, rtnl_lock held 3200 * All async codepaths that access the driver are disabled. 3201 */ 3202 spin_lock_irq(&np->lock); 3203 np->hands_off = 0; 3204 readl(ioaddr + IntrMask); 3205 readw(ioaddr + MIntrStatus); 3206 3207 /* Freeze Stats */ 3208 writel(StatsFreeze, ioaddr + StatsCtrl); 3209 3210 /* Stop the chip's Tx and Rx processes. */ 3211 natsemi_stop_rxtx(dev); 3212 3213 __get_stats(dev); 3214 spin_unlock_irq(&np->lock); 3215 3216 /* clear the carrier last - an interrupt could reenable it otherwise */ 3217 netif_carrier_off(dev); 3218 netif_stop_queue(dev); 3219 3220 dump_ring(dev); 3221 drain_ring(dev); 3222 free_ring(dev); 3223 3224 { 3225 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3226 if (wol) { 3227 /* restart the NIC in WOL mode. 3228 * The nic must be stopped for this. 3229 */ 3230 enable_wol_mode(dev, 0); 3231 } else { 3232 /* Restore PME enable bit unmolested */ 3233 writel(np->SavedClkRun, ioaddr + ClkRun); 3234 } 3235 } 3236 return 0; 3237 } 3238 3239 3240 static void natsemi_remove1(struct pci_dev *pdev) 3241 { 3242 struct net_device *dev = pci_get_drvdata(pdev); 3243 void __iomem * ioaddr = ns_ioaddr(dev); 3244 3245 NATSEMI_REMOVE_FILE(pdev, dspcfg_workaround); 3246 unregister_netdev (dev); 3247 pci_release_regions (pdev); 3248 iounmap(ioaddr); 3249 free_netdev (dev); 3250 } 3251 3252 #ifdef CONFIG_PM 3253 3254 /* 3255 * The ns83815 chip doesn't have explicit RxStop bits. 3256 * Kicking the Rx or Tx process for a new packet reenables the Rx process 3257 * of the nic, thus this function must be very careful: 3258 * 3259 * suspend/resume synchronization: 3260 * entry points: 3261 * netdev_open, netdev_close, netdev_ioctl, set_rx_mode, intr_handler, 3262 * start_tx, ns_tx_timeout 3263 * 3264 * No function accesses the hardware without checking np->hands_off. 3265 * the check occurs under spin_lock_irq(&np->lock); 3266 * exceptions: 3267 * * netdev_ioctl: noncritical access. 3268 * * netdev_open: cannot happen due to the device_detach 3269 * * netdev_close: doesn't hurt. 3270 * * netdev_timer: timer stopped by natsemi_suspend. 3271 * * intr_handler: doesn't acquire the spinlock. suspend calls 3272 * disable_irq() to enforce synchronization. 3273 * * natsemi_poll: checks before reenabling interrupts. suspend 3274 * sets hands_off, disables interrupts and then waits with 3275 * napi_disable(). 3276 * 3277 * Interrupts must be disabled, otherwise hands_off can cause irq storms. 3278 */ 3279 3280 static int natsemi_suspend (struct pci_dev *pdev, pm_message_t state) 3281 { 3282 struct net_device *dev = pci_get_drvdata (pdev); 3283 struct netdev_private *np = netdev_priv(dev); 3284 void __iomem * ioaddr = ns_ioaddr(dev); 3285 3286 rtnl_lock(); 3287 if (netif_running (dev)) { 3288 const int irq = np->pci_dev->irq; 3289 3290 del_timer_sync(&np->timer); 3291 3292 disable_irq(irq); 3293 spin_lock_irq(&np->lock); 3294 3295 natsemi_irq_disable(dev); 3296 np->hands_off = 1; 3297 natsemi_stop_rxtx(dev); 3298 netif_stop_queue(dev); 3299 3300 spin_unlock_irq(&np->lock); 3301 enable_irq(irq); 3302 3303 napi_disable(&np->napi); 3304 3305 /* Update the error counts. */ 3306 __get_stats(dev); 3307 3308 /* pci_power_off(pdev, -1); */ 3309 drain_ring(dev); 3310 { 3311 u32 wol = readl(ioaddr + WOLCmd) & WakeOptsSummary; 3312 /* Restore PME enable bit */ 3313 if (wol) { 3314 /* restart the NIC in WOL mode. 3315 * The nic must be stopped for this. 3316 * FIXME: use the WOL interrupt 3317 */ 3318 enable_wol_mode(dev, 0); 3319 } else { 3320 /* Restore PME enable bit unmolested */ 3321 writel(np->SavedClkRun, ioaddr + ClkRun); 3322 } 3323 } 3324 } 3325 netif_device_detach(dev); 3326 rtnl_unlock(); 3327 return 0; 3328 } 3329 3330 3331 static int natsemi_resume (struct pci_dev *pdev) 3332 { 3333 struct net_device *dev = pci_get_drvdata (pdev); 3334 struct netdev_private *np = netdev_priv(dev); 3335 int ret = 0; 3336 3337 rtnl_lock(); 3338 if (netif_device_present(dev)) 3339 goto out; 3340 if (netif_running(dev)) { 3341 const int irq = np->pci_dev->irq; 3342 3343 BUG_ON(!np->hands_off); 3344 ret = pci_enable_device(pdev); 3345 if (ret < 0) { 3346 dev_err(&pdev->dev, 3347 "pci_enable_device() failed: %d\n", ret); 3348 goto out; 3349 } 3350 /* pci_power_on(pdev); */ 3351 3352 napi_enable(&np->napi); 3353 3354 natsemi_reset(dev); 3355 init_ring(dev); 3356 disable_irq(irq); 3357 spin_lock_irq(&np->lock); 3358 np->hands_off = 0; 3359 init_registers(dev); 3360 netif_device_attach(dev); 3361 spin_unlock_irq(&np->lock); 3362 enable_irq(irq); 3363 3364 mod_timer(&np->timer, round_jiffies(jiffies + 1*HZ)); 3365 } 3366 netif_device_attach(dev); 3367 out: 3368 rtnl_unlock(); 3369 return ret; 3370 } 3371 3372 #endif /* CONFIG_PM */ 3373 3374 static struct pci_driver natsemi_driver = { 3375 .name = DRV_NAME, 3376 .id_table = natsemi_pci_tbl, 3377 .probe = natsemi_probe1, 3378 .remove = natsemi_remove1, 3379 #ifdef CONFIG_PM 3380 .suspend = natsemi_suspend, 3381 .resume = natsemi_resume, 3382 #endif 3383 }; 3384 3385 static int __init natsemi_init_mod (void) 3386 { 3387 /* when a module, this is printed whether or not devices are found in probe */ 3388 #ifdef MODULE 3389 printk(version); 3390 #endif 3391 3392 return pci_register_driver(&natsemi_driver); 3393 } 3394 3395 static void __exit natsemi_exit_mod (void) 3396 { 3397 pci_unregister_driver (&natsemi_driver); 3398 } 3399 3400 module_init(natsemi_init_mod); 3401 module_exit(natsemi_exit_mod); 3402 3403