193f7848bSJeff Kirsher #ifndef __MYRI10GE_MCP_H__ 293f7848bSJeff Kirsher #define __MYRI10GE_MCP_H__ 393f7848bSJeff Kirsher 493f7848bSJeff Kirsher #define MXGEFW_VERSION_MAJOR 1 593f7848bSJeff Kirsher #define MXGEFW_VERSION_MINOR 4 693f7848bSJeff Kirsher 793f7848bSJeff Kirsher /* 8 Bytes */ 893f7848bSJeff Kirsher struct mcp_dma_addr { 993f7848bSJeff Kirsher __be32 high; 1093f7848bSJeff Kirsher __be32 low; 1193f7848bSJeff Kirsher }; 1293f7848bSJeff Kirsher 1393f7848bSJeff Kirsher /* 4 Bytes */ 1493f7848bSJeff Kirsher struct mcp_slot { 1593f7848bSJeff Kirsher __sum16 checksum; 1693f7848bSJeff Kirsher __be16 length; 1793f7848bSJeff Kirsher }; 1893f7848bSJeff Kirsher 1993f7848bSJeff Kirsher /* 64 Bytes */ 2093f7848bSJeff Kirsher struct mcp_cmd { 2193f7848bSJeff Kirsher __be32 cmd; 2293f7848bSJeff Kirsher __be32 data0; /* will be low portion if data > 32 bits */ 2393f7848bSJeff Kirsher /* 8 */ 2493f7848bSJeff Kirsher __be32 data1; /* will be high portion if data > 32 bits */ 2593f7848bSJeff Kirsher __be32 data2; /* currently unused.. */ 2693f7848bSJeff Kirsher /* 16 */ 2793f7848bSJeff Kirsher struct mcp_dma_addr response_addr; 2893f7848bSJeff Kirsher /* 24 */ 2993f7848bSJeff Kirsher u8 pad[40]; 3093f7848bSJeff Kirsher }; 3193f7848bSJeff Kirsher 3293f7848bSJeff Kirsher /* 8 Bytes */ 3393f7848bSJeff Kirsher struct mcp_cmd_response { 3493f7848bSJeff Kirsher __be32 data; 3593f7848bSJeff Kirsher __be32 result; 3693f7848bSJeff Kirsher }; 3793f7848bSJeff Kirsher 3893f7848bSJeff Kirsher /* 3993f7848bSJeff Kirsher * flags used in mcp_kreq_ether_send_t: 4093f7848bSJeff Kirsher * 4193f7848bSJeff Kirsher * The SMALL flag is only needed in the first segment. It is raised 4293f7848bSJeff Kirsher * for packets that are total less or equal 512 bytes. 4393f7848bSJeff Kirsher * 4493f7848bSJeff Kirsher * The CKSUM flag must be set in all segments. 4593f7848bSJeff Kirsher * 4693f7848bSJeff Kirsher * The PADDED flags is set if the packet needs to be padded, and it 4793f7848bSJeff Kirsher * must be set for all segments. 4893f7848bSJeff Kirsher * 4993f7848bSJeff Kirsher * The MXGEFW_FLAGS_ALIGN_ODD must be set if the cumulative 5093f7848bSJeff Kirsher * length of all previous segments was odd. 5193f7848bSJeff Kirsher */ 5293f7848bSJeff Kirsher 5393f7848bSJeff Kirsher #define MXGEFW_FLAGS_SMALL 0x1 5493f7848bSJeff Kirsher #define MXGEFW_FLAGS_TSO_HDR 0x1 5593f7848bSJeff Kirsher #define MXGEFW_FLAGS_FIRST 0x2 5693f7848bSJeff Kirsher #define MXGEFW_FLAGS_ALIGN_ODD 0x4 5793f7848bSJeff Kirsher #define MXGEFW_FLAGS_CKSUM 0x8 5893f7848bSJeff Kirsher #define MXGEFW_FLAGS_TSO_LAST 0x8 5993f7848bSJeff Kirsher #define MXGEFW_FLAGS_NO_TSO 0x10 6093f7848bSJeff Kirsher #define MXGEFW_FLAGS_TSO_CHOP 0x10 6193f7848bSJeff Kirsher #define MXGEFW_FLAGS_TSO_PLD 0x20 6293f7848bSJeff Kirsher 6393f7848bSJeff Kirsher #define MXGEFW_SEND_SMALL_SIZE 1520 6493f7848bSJeff Kirsher #define MXGEFW_MAX_MTU 9400 6593f7848bSJeff Kirsher 6693f7848bSJeff Kirsher union mcp_pso_or_cumlen { 6793f7848bSJeff Kirsher u16 pseudo_hdr_offset; 6893f7848bSJeff Kirsher u16 cum_len; 6993f7848bSJeff Kirsher }; 7093f7848bSJeff Kirsher 7193f7848bSJeff Kirsher #define MXGEFW_MAX_SEND_DESC 12 7293f7848bSJeff Kirsher #define MXGEFW_PAD 2 7393f7848bSJeff Kirsher 7493f7848bSJeff Kirsher /* 16 Bytes */ 7593f7848bSJeff Kirsher struct mcp_kreq_ether_send { 7693f7848bSJeff Kirsher __be32 addr_high; 7793f7848bSJeff Kirsher __be32 addr_low; 7893f7848bSJeff Kirsher __be16 pseudo_hdr_offset; 7993f7848bSJeff Kirsher __be16 length; 8093f7848bSJeff Kirsher u8 pad; 8193f7848bSJeff Kirsher u8 rdma_count; 8293f7848bSJeff Kirsher u8 cksum_offset; /* where to start computing cksum */ 8393f7848bSJeff Kirsher u8 flags; /* as defined above */ 8493f7848bSJeff Kirsher }; 8593f7848bSJeff Kirsher 8693f7848bSJeff Kirsher /* 8 Bytes */ 8793f7848bSJeff Kirsher struct mcp_kreq_ether_recv { 8893f7848bSJeff Kirsher __be32 addr_high; 8993f7848bSJeff Kirsher __be32 addr_low; 9093f7848bSJeff Kirsher }; 9193f7848bSJeff Kirsher 9293f7848bSJeff Kirsher /* Commands */ 9393f7848bSJeff Kirsher 9493f7848bSJeff Kirsher #define MXGEFW_BOOT_HANDOFF 0xfc0000 9593f7848bSJeff Kirsher #define MXGEFW_BOOT_DUMMY_RDMA 0xfc01c0 9693f7848bSJeff Kirsher 9793f7848bSJeff Kirsher #define MXGEFW_ETH_CMD 0xf80000 9893f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_4 0x200000 9993f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_1 0x240000 10093f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_2 0x280000 10193f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_3 0x2c0000 10293f7848bSJeff Kirsher #define MXGEFW_ETH_RECV_SMALL 0x300000 10393f7848bSJeff Kirsher #define MXGEFW_ETH_RECV_BIG 0x340000 10493f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_GO 0x380000 10593f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_STOP 0x3C0000 10693f7848bSJeff Kirsher 10793f7848bSJeff Kirsher #define MXGEFW_ETH_SEND(n) (0x200000 + (((n) & 0x03) * 0x40000)) 10893f7848bSJeff Kirsher #define MXGEFW_ETH_SEND_OFFSET(n) (MXGEFW_ETH_SEND(n) - MXGEFW_ETH_SEND_4) 10993f7848bSJeff Kirsher 11093f7848bSJeff Kirsher enum myri10ge_mcp_cmd_type { 11193f7848bSJeff Kirsher MXGEFW_CMD_NONE = 0, 11293f7848bSJeff Kirsher /* Reset the mcp, it is left in a safe state, waiting 11393f7848bSJeff Kirsher * for the driver to set all its parameters */ 11493f7848bSJeff Kirsher MXGEFW_CMD_RESET = 1, 11593f7848bSJeff Kirsher 11693f7848bSJeff Kirsher /* get the version number of the current firmware.. 11793f7848bSJeff Kirsher * (may be available in the eeprom strings..? */ 11893f7848bSJeff Kirsher MXGEFW_GET_MCP_VERSION = 2, 11993f7848bSJeff Kirsher 12093f7848bSJeff Kirsher /* Parameters which must be set by the driver before it can 12193f7848bSJeff Kirsher * issue MXGEFW_CMD_ETHERNET_UP. They persist until the next 12293f7848bSJeff Kirsher * MXGEFW_CMD_RESET is issued */ 12393f7848bSJeff Kirsher 12493f7848bSJeff Kirsher MXGEFW_CMD_SET_INTRQ_DMA = 3, 12593f7848bSJeff Kirsher /* data0 = LSW of the host address 12693f7848bSJeff Kirsher * data1 = MSW of the host address 12793f7848bSJeff Kirsher * data2 = slice number if multiple slices are used 12893f7848bSJeff Kirsher */ 12993f7848bSJeff Kirsher 13093f7848bSJeff Kirsher MXGEFW_CMD_SET_BIG_BUFFER_SIZE = 4, /* in bytes, power of 2 */ 13193f7848bSJeff Kirsher MXGEFW_CMD_SET_SMALL_BUFFER_SIZE = 5, /* in bytes */ 13293f7848bSJeff Kirsher 13393f7848bSJeff Kirsher /* Parameters which refer to lanai SRAM addresses where the 13493f7848bSJeff Kirsher * driver must issue PIO writes for various things */ 13593f7848bSJeff Kirsher 13693f7848bSJeff Kirsher MXGEFW_CMD_GET_SEND_OFFSET = 6, 13793f7848bSJeff Kirsher MXGEFW_CMD_GET_SMALL_RX_OFFSET = 7, 13893f7848bSJeff Kirsher MXGEFW_CMD_GET_BIG_RX_OFFSET = 8, 13993f7848bSJeff Kirsher /* data0 = slice number if multiple slices are used */ 14093f7848bSJeff Kirsher 14193f7848bSJeff Kirsher MXGEFW_CMD_GET_IRQ_ACK_OFFSET = 9, 14293f7848bSJeff Kirsher MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET = 10, 14393f7848bSJeff Kirsher 14493f7848bSJeff Kirsher /* Parameters which refer to rings stored on the MCP, 14593f7848bSJeff Kirsher * and whose size is controlled by the mcp */ 14693f7848bSJeff Kirsher 14793f7848bSJeff Kirsher MXGEFW_CMD_GET_SEND_RING_SIZE = 11, /* in bytes */ 14893f7848bSJeff Kirsher MXGEFW_CMD_GET_RX_RING_SIZE = 12, /* in bytes */ 14993f7848bSJeff Kirsher 15093f7848bSJeff Kirsher /* Parameters which refer to rings stored in the host, 15193f7848bSJeff Kirsher * and whose size is controlled by the host. Note that 15293f7848bSJeff Kirsher * all must be physically contiguous and must contain 15393f7848bSJeff Kirsher * a power of 2 number of entries. */ 15493f7848bSJeff Kirsher 15593f7848bSJeff Kirsher MXGEFW_CMD_SET_INTRQ_SIZE = 13, /* in bytes */ 15693f7848bSJeff Kirsher #define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK (1 << 31) 15793f7848bSJeff Kirsher 15893f7848bSJeff Kirsher /* command to bring ethernet interface up. Above parameters 15993f7848bSJeff Kirsher * (plus mtu & mac address) must have been exchanged prior 16093f7848bSJeff Kirsher * to issuing this command */ 16193f7848bSJeff Kirsher MXGEFW_CMD_ETHERNET_UP = 14, 16293f7848bSJeff Kirsher 16393f7848bSJeff Kirsher /* command to bring ethernet interface down. No further sends 16493f7848bSJeff Kirsher * or receives may be processed until an MXGEFW_CMD_ETHERNET_UP 16593f7848bSJeff Kirsher * is issued, and all interrupt queues must be flushed prior 16693f7848bSJeff Kirsher * to ack'ing this command */ 16793f7848bSJeff Kirsher 16893f7848bSJeff Kirsher MXGEFW_CMD_ETHERNET_DOWN = 15, 16993f7848bSJeff Kirsher 17093f7848bSJeff Kirsher /* commands the driver may issue live, without resetting 17193f7848bSJeff Kirsher * the nic. Note that increasing the mtu "live" should 17293f7848bSJeff Kirsher * only be done if the driver has already supplied buffers 17393f7848bSJeff Kirsher * sufficiently large to handle the new mtu. Decreasing 17493f7848bSJeff Kirsher * the mtu live is safe */ 17593f7848bSJeff Kirsher 17693f7848bSJeff Kirsher MXGEFW_CMD_SET_MTU = 16, 17793f7848bSJeff Kirsher MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET = 17, /* in microseconds */ 17893f7848bSJeff Kirsher MXGEFW_CMD_SET_STATS_INTERVAL = 18, /* in microseconds */ 17993f7848bSJeff Kirsher MXGEFW_CMD_SET_STATS_DMA_OBSOLETE = 19, /* replaced by SET_STATS_DMA_V2 */ 18093f7848bSJeff Kirsher 18193f7848bSJeff Kirsher MXGEFW_ENABLE_PROMISC = 20, 18293f7848bSJeff Kirsher MXGEFW_DISABLE_PROMISC = 21, 18393f7848bSJeff Kirsher MXGEFW_SET_MAC_ADDRESS = 22, 18493f7848bSJeff Kirsher 18593f7848bSJeff Kirsher MXGEFW_ENABLE_FLOW_CONTROL = 23, 18693f7848bSJeff Kirsher MXGEFW_DISABLE_FLOW_CONTROL = 24, 18793f7848bSJeff Kirsher 18893f7848bSJeff Kirsher /* do a DMA test 18993f7848bSJeff Kirsher * data0,data1 = DMA address 19093f7848bSJeff Kirsher * data2 = RDMA length (MSH), WDMA length (LSH) 19193f7848bSJeff Kirsher * command return data = repetitions (MSH), 0.5-ms ticks (LSH) 19293f7848bSJeff Kirsher */ 19393f7848bSJeff Kirsher MXGEFW_DMA_TEST = 25, 19493f7848bSJeff Kirsher 19593f7848bSJeff Kirsher MXGEFW_ENABLE_ALLMULTI = 26, 19693f7848bSJeff Kirsher MXGEFW_DISABLE_ALLMULTI = 27, 19793f7848bSJeff Kirsher 19893f7848bSJeff Kirsher /* returns MXGEFW_CMD_ERROR_MULTICAST 19993f7848bSJeff Kirsher * if there is no room in the cache 20093f7848bSJeff Kirsher * data0,MSH(data1) = multicast group address */ 20193f7848bSJeff Kirsher MXGEFW_JOIN_MULTICAST_GROUP = 28, 20293f7848bSJeff Kirsher /* returns MXGEFW_CMD_ERROR_MULTICAST 20393f7848bSJeff Kirsher * if the address is not in the cache, 20493f7848bSJeff Kirsher * or is equal to FF-FF-FF-FF-FF-FF 20593f7848bSJeff Kirsher * data0,MSH(data1) = multicast group address */ 20693f7848bSJeff Kirsher MXGEFW_LEAVE_MULTICAST_GROUP = 29, 20793f7848bSJeff Kirsher MXGEFW_LEAVE_ALL_MULTICAST_GROUPS = 30, 20893f7848bSJeff Kirsher 20993f7848bSJeff Kirsher MXGEFW_CMD_SET_STATS_DMA_V2 = 31, 21093f7848bSJeff Kirsher /* data0, data1 = bus addr, 21193f7848bSJeff Kirsher * data2 = sizeof(struct mcp_irq_data) from driver point of view, allows 21293f7848bSJeff Kirsher * adding new stuff to mcp_irq_data without changing the ABI 21393f7848bSJeff Kirsher * 21493f7848bSJeff Kirsher * If multiple slices are used, data2 contains both the size of the 21593f7848bSJeff Kirsher * structure (in the lower 16 bits) and the slice number 21693f7848bSJeff Kirsher * (in the upper 16 bits). 21793f7848bSJeff Kirsher */ 21893f7848bSJeff Kirsher 21993f7848bSJeff Kirsher MXGEFW_CMD_UNALIGNED_TEST = 32, 22093f7848bSJeff Kirsher /* same than DMA_TEST (same args) but abort with UNALIGNED on unaligned 22193f7848bSJeff Kirsher * chipset */ 22293f7848bSJeff Kirsher 22393f7848bSJeff Kirsher MXGEFW_CMD_UNALIGNED_STATUS = 33, 22493f7848bSJeff Kirsher /* return data = boolean, true if the chipset is known to be unaligned */ 22593f7848bSJeff Kirsher 22693f7848bSJeff Kirsher MXGEFW_CMD_ALWAYS_USE_N_BIG_BUFFERS = 34, 22793f7848bSJeff Kirsher /* data0 = number of big buffers to use. It must be 0 or a power of 2. 22893f7848bSJeff Kirsher * 0 indicates that the NIC consumes as many buffers as they are required 22993f7848bSJeff Kirsher * for packet. This is the default behavior. 23093f7848bSJeff Kirsher * A power of 2 number indicates that the NIC always uses the specified 23193f7848bSJeff Kirsher * number of buffers for each big receive packet. 23293f7848bSJeff Kirsher * It is up to the driver to ensure that this value is big enough for 23393f7848bSJeff Kirsher * the NIC to be able to receive maximum-sized packets. 23493f7848bSJeff Kirsher */ 23593f7848bSJeff Kirsher 23693f7848bSJeff Kirsher MXGEFW_CMD_GET_MAX_RSS_QUEUES = 35, 23793f7848bSJeff Kirsher MXGEFW_CMD_ENABLE_RSS_QUEUES = 36, 23893f7848bSJeff Kirsher /* data0 = number of slices n (0, 1, ..., n-1) to enable 23993f7848bSJeff Kirsher * data1 = interrupt mode | use of multiple transmit queues. 24093f7848bSJeff Kirsher * 0=share one INTx/MSI. 24193f7848bSJeff Kirsher * 1=use one MSI-X per queue. 24293f7848bSJeff Kirsher * If all queues share one interrupt, the driver must have set 24393f7848bSJeff Kirsher * RSS_SHARED_INTERRUPT_DMA before enabling queues. 24493f7848bSJeff Kirsher * 2=enable both receive and send queues. 24593f7848bSJeff Kirsher * Without this bit set, only one send queue (slice 0's send queue) 24693f7848bSJeff Kirsher * is enabled. The receive queues are always enabled. 24793f7848bSJeff Kirsher */ 24893f7848bSJeff Kirsher #define MXGEFW_SLICE_INTR_MODE_SHARED 0x0 24993f7848bSJeff Kirsher #define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 0x1 25093f7848bSJeff Kirsher #define MXGEFW_SLICE_ENABLE_MULTIPLE_TX_QUEUES 0x2 25193f7848bSJeff Kirsher 25293f7848bSJeff Kirsher MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET = 37, 25393f7848bSJeff Kirsher MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA = 38, 25493f7848bSJeff Kirsher /* data0, data1 = bus address lsw, msw */ 25593f7848bSJeff Kirsher MXGEFW_CMD_GET_RSS_TABLE_OFFSET = 39, 25693f7848bSJeff Kirsher /* get the offset of the indirection table */ 25793f7848bSJeff Kirsher MXGEFW_CMD_SET_RSS_TABLE_SIZE = 40, 25893f7848bSJeff Kirsher /* set the size of the indirection table */ 25993f7848bSJeff Kirsher MXGEFW_CMD_GET_RSS_KEY_OFFSET = 41, 26093f7848bSJeff Kirsher /* get the offset of the secret key */ 26193f7848bSJeff Kirsher MXGEFW_CMD_RSS_KEY_UPDATED = 42, 26293f7848bSJeff Kirsher /* tell nic that the secret key's been updated */ 26393f7848bSJeff Kirsher MXGEFW_CMD_SET_RSS_ENABLE = 43, 26493f7848bSJeff Kirsher /* data0 = enable/disable rss 26593f7848bSJeff Kirsher * 0: disable rss. nic does not distribute receive packets. 26693f7848bSJeff Kirsher * 1: enable rss. nic distributes receive packets among queues. 26793f7848bSJeff Kirsher * data1 = hash type 26893f7848bSJeff Kirsher * 1: IPV4 (required by RSS) 26993f7848bSJeff Kirsher * 2: TCP_IPV4 (required by RSS) 27093f7848bSJeff Kirsher * 3: IPV4 | TCP_IPV4 (required by RSS) 27193f7848bSJeff Kirsher * 4: source port 27293f7848bSJeff Kirsher * 5: source port + destination port 27393f7848bSJeff Kirsher */ 27493f7848bSJeff Kirsher #define MXGEFW_RSS_HASH_TYPE_IPV4 0x1 27593f7848bSJeff Kirsher #define MXGEFW_RSS_HASH_TYPE_TCP_IPV4 0x2 27693f7848bSJeff Kirsher #define MXGEFW_RSS_HASH_TYPE_SRC_PORT 0x4 27793f7848bSJeff Kirsher #define MXGEFW_RSS_HASH_TYPE_SRC_DST_PORT 0x5 27893f7848bSJeff Kirsher #define MXGEFW_RSS_HASH_TYPE_MAX 0x5 27993f7848bSJeff Kirsher 28093f7848bSJeff Kirsher MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE = 44, 28193f7848bSJeff Kirsher /* Return data = the max. size of the entire headers of a IPv6 TSO packet. 28293f7848bSJeff Kirsher * If the header size of a IPv6 TSO packet is larger than the specified 28393f7848bSJeff Kirsher * value, then the driver must not use TSO. 28493f7848bSJeff Kirsher * This size restriction only applies to IPv6 TSO. 28593f7848bSJeff Kirsher * For IPv4 TSO, the maximum size of the headers is fixed, and the NIC 28693f7848bSJeff Kirsher * always has enough header buffer to store maximum-sized headers. 28793f7848bSJeff Kirsher */ 28893f7848bSJeff Kirsher 28993f7848bSJeff Kirsher MXGEFW_CMD_SET_TSO_MODE = 45, 29093f7848bSJeff Kirsher /* data0 = TSO mode. 29193f7848bSJeff Kirsher * 0: Linux/FreeBSD style (NIC default) 29293f7848bSJeff Kirsher * 1: NDIS/NetBSD style 29393f7848bSJeff Kirsher */ 29493f7848bSJeff Kirsher #define MXGEFW_TSO_MODE_LINUX 0 29593f7848bSJeff Kirsher #define MXGEFW_TSO_MODE_NDIS 1 29693f7848bSJeff Kirsher 29793f7848bSJeff Kirsher MXGEFW_CMD_MDIO_READ = 46, 29893f7848bSJeff Kirsher /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */ 29993f7848bSJeff Kirsher MXGEFW_CMD_MDIO_WRITE = 47, 30093f7848bSJeff Kirsher /* data0 = dev_addr, data1 = register/addr, data2 = value */ 30193f7848bSJeff Kirsher 30293f7848bSJeff Kirsher MXGEFW_CMD_I2C_READ = 48, 30393f7848bSJeff Kirsher /* Starts to get a fresh copy of one byte or of the module i2c table, the 30493f7848bSJeff Kirsher * obtained data is cached inside the xaui-xfi chip : 30593f7848bSJeff Kirsher * data0 : 0 => get one byte, 1=> get 256 bytes 30693f7848bSJeff Kirsher * data1 : If data0 == 0: location to refresh 30793f7848bSJeff Kirsher * bit 7:0 register location 30893f7848bSJeff Kirsher * bit 8:15 is the i2c slave addr (0 is interpreted as 0xA1) 30993f7848bSJeff Kirsher * bit 23:16 is the i2c bus number (for multi-port NICs) 31093f7848bSJeff Kirsher * If data0 == 1: unused 31193f7848bSJeff Kirsher * The operation might take ~1ms for a single byte or ~65ms when refreshing all 256 bytes 31293f7848bSJeff Kirsher * During the i2c operation, MXGEFW_CMD_I2C_READ or MXGEFW_CMD_I2C_BYTE attempts 31393f7848bSJeff Kirsher * will return MXGEFW_CMD_ERROR_BUSY 31493f7848bSJeff Kirsher */ 31593f7848bSJeff Kirsher MXGEFW_CMD_I2C_BYTE = 49, 31693f7848bSJeff Kirsher /* Return the last obtained copy of a given byte in the xfp i2c table 31793f7848bSJeff Kirsher * (copy cached during the last relevant MXGEFW_CMD_I2C_READ) 31893f7848bSJeff Kirsher * data0 : index of the desired table entry 31993f7848bSJeff Kirsher * Return data = the byte stored at the requested index in the table 32093f7848bSJeff Kirsher */ 32193f7848bSJeff Kirsher 32293f7848bSJeff Kirsher MXGEFW_CMD_GET_VPUMP_OFFSET = 50, 32393f7848bSJeff Kirsher /* Return data = NIC memory offset of mcp_vpump_public_global */ 32493f7848bSJeff Kirsher MXGEFW_CMD_RESET_VPUMP = 51, 32593f7848bSJeff Kirsher /* Resets the VPUMP state */ 32693f7848bSJeff Kirsher 32793f7848bSJeff Kirsher MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE = 52, 32893f7848bSJeff Kirsher /* data0 = mcp_slot type to use. 32993f7848bSJeff Kirsher * 0 = the default 4B mcp_slot 33093f7848bSJeff Kirsher * 1 = 8B mcp_slot_8 33193f7848bSJeff Kirsher */ 33293f7848bSJeff Kirsher #define MXGEFW_RSS_MCP_SLOT_TYPE_MIN 0 33393f7848bSJeff Kirsher #define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH 1 33493f7848bSJeff Kirsher 33593f7848bSJeff Kirsher MXGEFW_CMD_SET_THROTTLE_FACTOR = 53, 33693f7848bSJeff Kirsher /* set the throttle factor for ethp_z8e 33793f7848bSJeff Kirsher * data0 = throttle_factor 33893f7848bSJeff Kirsher * throttle_factor = 256 * pcie-raw-speed / tx_speed 33993f7848bSJeff Kirsher * tx_speed = 256 * pcie-raw-speed / throttle_factor 34093f7848bSJeff Kirsher * 34193f7848bSJeff Kirsher * For PCI-E x8: pcie-raw-speed == 16Gb/s 34293f7848bSJeff Kirsher * For PCI-E x4: pcie-raw-speed == 8Gb/s 34393f7848bSJeff Kirsher * 34493f7848bSJeff Kirsher * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s 34593f7848bSJeff Kirsher * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s 34693f7848bSJeff Kirsher * 34793f7848bSJeff Kirsher * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s 34893f7848bSJeff Kirsher * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s 34993f7848bSJeff Kirsher */ 35093f7848bSJeff Kirsher 35193f7848bSJeff Kirsher MXGEFW_CMD_VPUMP_UP = 54, 35293f7848bSJeff Kirsher /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */ 35393f7848bSJeff Kirsher MXGEFW_CMD_GET_VPUMP_CLK = 55, 35493f7848bSJeff Kirsher /* Get the lanai clock */ 35593f7848bSJeff Kirsher 35693f7848bSJeff Kirsher MXGEFW_CMD_GET_DCA_OFFSET = 56, 35793f7848bSJeff Kirsher /* offset of dca control for WDMAs */ 35893f7848bSJeff Kirsher 35981259c61SVinson Lee /* VMware NetQueue commands */ 36093f7848bSJeff Kirsher MXGEFW_CMD_NETQ_GET_FILTERS_PER_QUEUE = 57, 36193f7848bSJeff Kirsher MXGEFW_CMD_NETQ_ADD_FILTER = 58, 36293f7848bSJeff Kirsher /* data0 = filter_id << 16 | queue << 8 | type */ 36393f7848bSJeff Kirsher /* data1 = MS4 of MAC Addr */ 36493f7848bSJeff Kirsher /* data2 = LS2_MAC << 16 | VLAN_tag */ 36593f7848bSJeff Kirsher MXGEFW_CMD_NETQ_DEL_FILTER = 59, 36693f7848bSJeff Kirsher /* data0 = filter_id */ 36793f7848bSJeff Kirsher MXGEFW_CMD_NETQ_QUERY1 = 60, 36893f7848bSJeff Kirsher MXGEFW_CMD_NETQ_QUERY2 = 61, 36993f7848bSJeff Kirsher MXGEFW_CMD_NETQ_QUERY3 = 62, 37093f7848bSJeff Kirsher MXGEFW_CMD_NETQ_QUERY4 = 63, 37193f7848bSJeff Kirsher 37293f7848bSJeff Kirsher MXGEFW_CMD_RELAX_RXBUFFER_ALIGNMENT = 64, 37393f7848bSJeff Kirsher /* When set, small receive buffers can cross page boundaries. 37493f7848bSJeff Kirsher * Both small and big receive buffers may start at any address. 37593f7848bSJeff Kirsher * This option has performance implications, so use with caution. 37693f7848bSJeff Kirsher */ 37793f7848bSJeff Kirsher }; 37893f7848bSJeff Kirsher 37993f7848bSJeff Kirsher enum myri10ge_mcp_cmd_status { 38093f7848bSJeff Kirsher MXGEFW_CMD_OK = 0, 38193f7848bSJeff Kirsher MXGEFW_CMD_UNKNOWN = 1, 38293f7848bSJeff Kirsher MXGEFW_CMD_ERROR_RANGE = 2, 38393f7848bSJeff Kirsher MXGEFW_CMD_ERROR_BUSY = 3, 38493f7848bSJeff Kirsher MXGEFW_CMD_ERROR_EMPTY = 4, 38593f7848bSJeff Kirsher MXGEFW_CMD_ERROR_CLOSED = 5, 38693f7848bSJeff Kirsher MXGEFW_CMD_ERROR_HASH_ERROR = 6, 38793f7848bSJeff Kirsher MXGEFW_CMD_ERROR_BAD_PORT = 7, 38893f7848bSJeff Kirsher MXGEFW_CMD_ERROR_RESOURCES = 8, 38993f7848bSJeff Kirsher MXGEFW_CMD_ERROR_MULTICAST = 9, 39093f7848bSJeff Kirsher MXGEFW_CMD_ERROR_UNALIGNED = 10, 39193f7848bSJeff Kirsher MXGEFW_CMD_ERROR_NO_MDIO = 11, 39293f7848bSJeff Kirsher MXGEFW_CMD_ERROR_I2C_FAILURE = 12, 39393f7848bSJeff Kirsher MXGEFW_CMD_ERROR_I2C_ABSENT = 13, 39493f7848bSJeff Kirsher MXGEFW_CMD_ERROR_BAD_PCIE_LINK = 14 39593f7848bSJeff Kirsher }; 39693f7848bSJeff Kirsher 39793f7848bSJeff Kirsher #define MXGEFW_OLD_IRQ_DATA_LEN 40 39893f7848bSJeff Kirsher 39993f7848bSJeff Kirsher struct mcp_irq_data { 40093f7848bSJeff Kirsher /* add new counters at the beginning */ 40193f7848bSJeff Kirsher __be32 future_use[1]; 40293f7848bSJeff Kirsher __be32 dropped_pause; 40393f7848bSJeff Kirsher __be32 dropped_unicast_filtered; 40493f7848bSJeff Kirsher __be32 dropped_bad_crc32; 40593f7848bSJeff Kirsher __be32 dropped_bad_phy; 40693f7848bSJeff Kirsher __be32 dropped_multicast_filtered; 40793f7848bSJeff Kirsher /* 40 Bytes */ 40893f7848bSJeff Kirsher __be32 send_done_count; 40993f7848bSJeff Kirsher 41093f7848bSJeff Kirsher #define MXGEFW_LINK_DOWN 0 41193f7848bSJeff Kirsher #define MXGEFW_LINK_UP 1 41293f7848bSJeff Kirsher #define MXGEFW_LINK_MYRINET 2 41393f7848bSJeff Kirsher #define MXGEFW_LINK_UNKNOWN 3 41493f7848bSJeff Kirsher __be32 link_up; 41593f7848bSJeff Kirsher __be32 dropped_link_overflow; 41693f7848bSJeff Kirsher __be32 dropped_link_error_or_filtered; 41793f7848bSJeff Kirsher __be32 dropped_runt; 41893f7848bSJeff Kirsher __be32 dropped_overrun; 41993f7848bSJeff Kirsher __be32 dropped_no_small_buffer; 42093f7848bSJeff Kirsher __be32 dropped_no_big_buffer; 42193f7848bSJeff Kirsher __be32 rdma_tags_available; 42293f7848bSJeff Kirsher 42393f7848bSJeff Kirsher u8 tx_stopped; 42493f7848bSJeff Kirsher u8 link_down; 42593f7848bSJeff Kirsher u8 stats_updated; 42693f7848bSJeff Kirsher u8 valid; 42793f7848bSJeff Kirsher }; 42893f7848bSJeff Kirsher 42993f7848bSJeff Kirsher /* definitions for NETQ filter type */ 43093f7848bSJeff Kirsher #define MXGEFW_NETQ_FILTERTYPE_NONE 0 43193f7848bSJeff Kirsher #define MXGEFW_NETQ_FILTERTYPE_MACADDR 1 43293f7848bSJeff Kirsher #define MXGEFW_NETQ_FILTERTYPE_VLAN 2 43393f7848bSJeff Kirsher #define MXGEFW_NETQ_FILTERTYPE_VLANMACADDR 3 43493f7848bSJeff Kirsher 43593f7848bSJeff Kirsher #endif /* __MYRI10GE_MCP_H__ */ 436