1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Microsemi Ocelot Switch driver 4 * 5 * Copyright (c) 2017 Microsemi Corporation 6 * Copyright (c) 2021 Innovative Advantage 7 */ 8 #include <soc/mscc/ocelot_vcap.h> 9 #include <soc/mscc/vsc7514_regs.h> 10 #include "ocelot.h" 11 12 const u32 vsc7514_ana_regmap[] = { 13 REG(ANA_ADVLEARN, 0x009000), 14 REG(ANA_VLANMASK, 0x009004), 15 REG(ANA_PORT_B_DOMAIN, 0x009008), 16 REG(ANA_ANAGEFIL, 0x00900c), 17 REG(ANA_ANEVENTS, 0x009010), 18 REG(ANA_STORMLIMIT_BURST, 0x009014), 19 REG(ANA_STORMLIMIT_CFG, 0x009018), 20 REG(ANA_ISOLATED_PORTS, 0x009028), 21 REG(ANA_COMMUNITY_PORTS, 0x00902c), 22 REG(ANA_AUTOAGE, 0x009030), 23 REG(ANA_MACTOPTIONS, 0x009034), 24 REG(ANA_LEARNDISC, 0x009038), 25 REG(ANA_AGENCTRL, 0x00903c), 26 REG(ANA_MIRRORPORTS, 0x009040), 27 REG(ANA_EMIRRORPORTS, 0x009044), 28 REG(ANA_FLOODING, 0x009048), 29 REG(ANA_FLOODING_IPMC, 0x00904c), 30 REG(ANA_SFLOW_CFG, 0x009050), 31 REG(ANA_PORT_MODE, 0x009080), 32 REG(ANA_PGID_PGID, 0x008c00), 33 REG(ANA_TABLES_ANMOVED, 0x008b30), 34 REG(ANA_TABLES_MACHDATA, 0x008b34), 35 REG(ANA_TABLES_MACLDATA, 0x008b38), 36 REG(ANA_TABLES_MACACCESS, 0x008b3c), 37 REG(ANA_TABLES_MACTINDX, 0x008b40), 38 REG(ANA_TABLES_VLANACCESS, 0x008b44), 39 REG(ANA_TABLES_VLANTIDX, 0x008b48), 40 REG(ANA_TABLES_ISDXACCESS, 0x008b4c), 41 REG(ANA_TABLES_ISDXTIDX, 0x008b50), 42 REG(ANA_TABLES_ENTRYLIM, 0x008b00), 43 REG(ANA_TABLES_PTP_ID_HIGH, 0x008b54), 44 REG(ANA_TABLES_PTP_ID_LOW, 0x008b58), 45 REG(ANA_MSTI_STATE, 0x008e00), 46 REG(ANA_PORT_VLAN_CFG, 0x007000), 47 REG(ANA_PORT_DROP_CFG, 0x007004), 48 REG(ANA_PORT_QOS_CFG, 0x007008), 49 REG(ANA_PORT_VCAP_CFG, 0x00700c), 50 REG(ANA_PORT_VCAP_S1_KEY_CFG, 0x007010), 51 REG(ANA_PORT_VCAP_S2_CFG, 0x00701c), 52 REG(ANA_PORT_PCP_DEI_MAP, 0x007020), 53 REG(ANA_PORT_CPU_FWD_CFG, 0x007060), 54 REG(ANA_PORT_CPU_FWD_BPDU_CFG, 0x007064), 55 REG(ANA_PORT_CPU_FWD_GARP_CFG, 0x007068), 56 REG(ANA_PORT_CPU_FWD_CCM_CFG, 0x00706c), 57 REG(ANA_PORT_PORT_CFG, 0x007070), 58 REG(ANA_PORT_POL_CFG, 0x007074), 59 REG(ANA_PORT_PTP_CFG, 0x007078), 60 REG(ANA_PORT_PTP_DLY1_CFG, 0x00707c), 61 REG(ANA_OAM_UPM_LM_CNT, 0x007c00), 62 REG(ANA_PORT_PTP_DLY2_CFG, 0x007080), 63 REG(ANA_PFC_PFC_CFG, 0x008800), 64 REG(ANA_PFC_PFC_TIMER, 0x008804), 65 REG(ANA_IPT_OAM_MEP_CFG, 0x008000), 66 REG(ANA_IPT_IPT, 0x008004), 67 REG(ANA_PPT_PPT, 0x008ac0), 68 REG(ANA_FID_MAP_FID_MAP, 0x000000), 69 REG(ANA_AGGR_CFG, 0x0090b4), 70 REG(ANA_CPUQ_CFG, 0x0090b8), 71 REG(ANA_CPUQ_CFG2, 0x0090bc), 72 REG(ANA_CPUQ_8021_CFG, 0x0090c0), 73 REG(ANA_DSCP_CFG, 0x009100), 74 REG(ANA_DSCP_REWR_CFG, 0x009200), 75 REG(ANA_VCAP_RNG_TYPE_CFG, 0x009240), 76 REG(ANA_VCAP_RNG_VAL_CFG, 0x009260), 77 REG(ANA_VRAP_CFG, 0x009280), 78 REG(ANA_VRAP_HDR_DATA, 0x009284), 79 REG(ANA_VRAP_HDR_MASK, 0x009288), 80 REG(ANA_DISCARD_CFG, 0x00928c), 81 REG(ANA_FID_CFG, 0x009290), 82 REG(ANA_POL_PIR_CFG, 0x004000), 83 REG(ANA_POL_CIR_CFG, 0x004004), 84 REG(ANA_POL_MODE_CFG, 0x004008), 85 REG(ANA_POL_PIR_STATE, 0x00400c), 86 REG(ANA_POL_CIR_STATE, 0x004010), 87 REG(ANA_POL_STATE, 0x004014), 88 REG(ANA_POL_FLOWC, 0x008b80), 89 REG(ANA_POL_HYST, 0x008bec), 90 REG(ANA_POL_MISC_CFG, 0x008bf0), 91 }; 92 EXPORT_SYMBOL(vsc7514_ana_regmap); 93 94 const u32 vsc7514_qs_regmap[] = { 95 REG(QS_XTR_GRP_CFG, 0x000000), 96 REG(QS_XTR_RD, 0x000008), 97 REG(QS_XTR_FRM_PRUNING, 0x000010), 98 REG(QS_XTR_FLUSH, 0x000018), 99 REG(QS_XTR_DATA_PRESENT, 0x00001c), 100 REG(QS_XTR_CFG, 0x000020), 101 REG(QS_INJ_GRP_CFG, 0x000024), 102 REG(QS_INJ_WR, 0x00002c), 103 REG(QS_INJ_CTRL, 0x000034), 104 REG(QS_INJ_STATUS, 0x00003c), 105 REG(QS_INJ_ERR, 0x000040), 106 REG(QS_INH_DBG, 0x000048), 107 }; 108 EXPORT_SYMBOL(vsc7514_qs_regmap); 109 110 const u32 vsc7514_qsys_regmap[] = { 111 REG(QSYS_PORT_MODE, 0x011200), 112 REG(QSYS_SWITCH_PORT_MODE, 0x011234), 113 REG(QSYS_STAT_CNT_CFG, 0x011264), 114 REG(QSYS_EEE_CFG, 0x011268), 115 REG(QSYS_EEE_THRES, 0x011294), 116 REG(QSYS_IGR_NO_SHARING, 0x011298), 117 REG(QSYS_EGR_NO_SHARING, 0x01129c), 118 REG(QSYS_SW_STATUS, 0x0112a0), 119 REG(QSYS_EXT_CPU_CFG, 0x0112d0), 120 REG(QSYS_PAD_CFG, 0x0112d4), 121 REG(QSYS_CPU_GROUP_MAP, 0x0112d8), 122 REG(QSYS_QMAP, 0x0112dc), 123 REG(QSYS_ISDX_SGRP, 0x011400), 124 REG(QSYS_TIMED_FRAME_ENTRY, 0x014000), 125 REG(QSYS_TFRM_MISC, 0x011310), 126 REG(QSYS_TFRM_PORT_DLY, 0x011314), 127 REG(QSYS_TFRM_TIMER_CFG_1, 0x011318), 128 REG(QSYS_TFRM_TIMER_CFG_2, 0x01131c), 129 REG(QSYS_TFRM_TIMER_CFG_3, 0x011320), 130 REG(QSYS_TFRM_TIMER_CFG_4, 0x011324), 131 REG(QSYS_TFRM_TIMER_CFG_5, 0x011328), 132 REG(QSYS_TFRM_TIMER_CFG_6, 0x01132c), 133 REG(QSYS_TFRM_TIMER_CFG_7, 0x011330), 134 REG(QSYS_TFRM_TIMER_CFG_8, 0x011334), 135 REG(QSYS_RED_PROFILE, 0x011338), 136 REG(QSYS_RES_QOS_MODE, 0x011378), 137 REG(QSYS_RES_CFG, 0x012000), 138 REG(QSYS_RES_STAT, 0x012004), 139 REG(QSYS_EGR_DROP_MODE, 0x01137c), 140 REG(QSYS_EQ_CTRL, 0x011380), 141 REG(QSYS_EVENTS_CORE, 0x011384), 142 REG(QSYS_CIR_CFG, 0x000000), 143 REG(QSYS_EIR_CFG, 0x000004), 144 REG(QSYS_SE_CFG, 0x000008), 145 REG(QSYS_SE_DWRR_CFG, 0x00000c), 146 REG(QSYS_SE_CONNECT, 0x00003c), 147 REG(QSYS_SE_DLB_SENSE, 0x000040), 148 REG(QSYS_CIR_STATE, 0x000044), 149 REG(QSYS_EIR_STATE, 0x000048), 150 REG(QSYS_SE_STATE, 0x00004c), 151 REG(QSYS_HSCH_MISC_CFG, 0x011388), 152 }; 153 EXPORT_SYMBOL(vsc7514_qsys_regmap); 154 155 const u32 vsc7514_rew_regmap[] = { 156 REG(REW_PORT_VLAN_CFG, 0x000000), 157 REG(REW_TAG_CFG, 0x000004), 158 REG(REW_PORT_CFG, 0x000008), 159 REG(REW_DSCP_CFG, 0x00000c), 160 REG(REW_PCP_DEI_QOS_MAP_CFG, 0x000010), 161 REG(REW_PTP_CFG, 0x000050), 162 REG(REW_PTP_DLY1_CFG, 0x000054), 163 REG(REW_DSCP_REMAP_DP1_CFG, 0x000690), 164 REG(REW_DSCP_REMAP_CFG, 0x000790), 165 REG(REW_STAT_CFG, 0x000890), 166 REG(REW_PPT, 0x000680), 167 }; 168 EXPORT_SYMBOL(vsc7514_rew_regmap); 169 170 const u32 vsc7514_sys_regmap[] = { 171 REG(SYS_COUNT_RX_OCTETS, 0x000000), 172 REG(SYS_COUNT_RX_UNICAST, 0x000004), 173 REG(SYS_COUNT_RX_MULTICAST, 0x000008), 174 REG(SYS_COUNT_RX_BROADCAST, 0x00000c), 175 REG(SYS_COUNT_RX_SHORTS, 0x000010), 176 REG(SYS_COUNT_RX_FRAGMENTS, 0x000014), 177 REG(SYS_COUNT_RX_JABBERS, 0x000018), 178 REG(SYS_COUNT_RX_CRC_ALIGN_ERRS, 0x00001c), 179 REG(SYS_COUNT_RX_SYM_ERRS, 0x000020), 180 REG(SYS_COUNT_RX_64, 0x000024), 181 REG(SYS_COUNT_RX_65_127, 0x000028), 182 REG(SYS_COUNT_RX_128_255, 0x00002c), 183 REG(SYS_COUNT_RX_256_1023, 0x000030), 184 REG(SYS_COUNT_RX_1024_1526, 0x000034), 185 REG(SYS_COUNT_RX_1527_MAX, 0x000038), 186 REG(SYS_COUNT_RX_PAUSE, 0x00003c), 187 REG(SYS_COUNT_RX_CONTROL, 0x000040), 188 REG(SYS_COUNT_RX_LONGS, 0x000044), 189 REG(SYS_COUNT_RX_CLASSIFIED_DROPS, 0x000048), 190 REG(SYS_COUNT_TX_OCTETS, 0x000100), 191 REG(SYS_COUNT_TX_UNICAST, 0x000104), 192 REG(SYS_COUNT_TX_MULTICAST, 0x000108), 193 REG(SYS_COUNT_TX_BROADCAST, 0x00010c), 194 REG(SYS_COUNT_TX_COLLISION, 0x000110), 195 REG(SYS_COUNT_TX_DROPS, 0x000114), 196 REG(SYS_COUNT_TX_PAUSE, 0x000118), 197 REG(SYS_COUNT_TX_64, 0x00011c), 198 REG(SYS_COUNT_TX_65_127, 0x000120), 199 REG(SYS_COUNT_TX_128_511, 0x000124), 200 REG(SYS_COUNT_TX_512_1023, 0x000128), 201 REG(SYS_COUNT_TX_1024_1526, 0x00012c), 202 REG(SYS_COUNT_TX_1527_MAX, 0x000130), 203 REG(SYS_COUNT_TX_AGING, 0x000170), 204 REG(SYS_RESET_CFG, 0x000508), 205 REG(SYS_CMID, 0x00050c), 206 REG(SYS_VLAN_ETYPE_CFG, 0x000510), 207 REG(SYS_PORT_MODE, 0x000514), 208 REG(SYS_FRONT_PORT_MODE, 0x000548), 209 REG(SYS_FRM_AGING, 0x000574), 210 REG(SYS_STAT_CFG, 0x000578), 211 REG(SYS_SW_STATUS, 0x00057c), 212 REG(SYS_MISC_CFG, 0x0005ac), 213 REG(SYS_REW_MAC_HIGH_CFG, 0x0005b0), 214 REG(SYS_REW_MAC_LOW_CFG, 0x0005dc), 215 REG(SYS_CM_ADDR, 0x000500), 216 REG(SYS_CM_DATA, 0x000504), 217 REG(SYS_PAUSE_CFG, 0x000608), 218 REG(SYS_PAUSE_TOT_CFG, 0x000638), 219 REG(SYS_ATOP, 0x00063c), 220 REG(SYS_ATOP_TOT_CFG, 0x00066c), 221 REG(SYS_MAC_FC_CFG, 0x000670), 222 REG(SYS_MMGT, 0x00069c), 223 REG(SYS_MMGT_FAST, 0x0006a0), 224 REG(SYS_EVENTS_DIF, 0x0006a4), 225 REG(SYS_EVENTS_CORE, 0x0006b4), 226 REG(SYS_CNT, 0x000000), 227 REG(SYS_PTP_STATUS, 0x0006b8), 228 REG(SYS_PTP_TXSTAMP, 0x0006bc), 229 REG(SYS_PTP_NXT, 0x0006c0), 230 REG(SYS_PTP_CFG, 0x0006c4), 231 }; 232 EXPORT_SYMBOL(vsc7514_sys_regmap); 233 234 const u32 vsc7514_vcap_regmap[] = { 235 /* VCAP_CORE_CFG */ 236 REG(VCAP_CORE_UPDATE_CTRL, 0x000000), 237 REG(VCAP_CORE_MV_CFG, 0x000004), 238 /* VCAP_CORE_CACHE */ 239 REG(VCAP_CACHE_ENTRY_DAT, 0x000008), 240 REG(VCAP_CACHE_MASK_DAT, 0x000108), 241 REG(VCAP_CACHE_ACTION_DAT, 0x000208), 242 REG(VCAP_CACHE_CNT_DAT, 0x000308), 243 REG(VCAP_CACHE_TG_DAT, 0x000388), 244 /* VCAP_CONST */ 245 REG(VCAP_CONST_VCAP_VER, 0x000398), 246 REG(VCAP_CONST_ENTRY_WIDTH, 0x00039c), 247 REG(VCAP_CONST_ENTRY_CNT, 0x0003a0), 248 REG(VCAP_CONST_ENTRY_SWCNT, 0x0003a4), 249 REG(VCAP_CONST_ENTRY_TG_WIDTH, 0x0003a8), 250 REG(VCAP_CONST_ACTION_DEF_CNT, 0x0003ac), 251 REG(VCAP_CONST_ACTION_WIDTH, 0x0003b0), 252 REG(VCAP_CONST_CNT_WIDTH, 0x0003b4), 253 REG(VCAP_CONST_CORE_CNT, 0x0003b8), 254 REG(VCAP_CONST_IF_CNT, 0x0003bc), 255 }; 256 EXPORT_SYMBOL(vsc7514_vcap_regmap); 257 258 const u32 vsc7514_ptp_regmap[] = { 259 REG(PTP_PIN_CFG, 0x000000), 260 REG(PTP_PIN_TOD_SEC_MSB, 0x000004), 261 REG(PTP_PIN_TOD_SEC_LSB, 0x000008), 262 REG(PTP_PIN_TOD_NSEC, 0x00000c), 263 REG(PTP_PIN_WF_HIGH_PERIOD, 0x000014), 264 REG(PTP_PIN_WF_LOW_PERIOD, 0x000018), 265 REG(PTP_CFG_MISC, 0x0000a0), 266 REG(PTP_CLK_CFG_ADJ_CFG, 0x0000a4), 267 REG(PTP_CLK_CFG_ADJ_FREQ, 0x0000a8), 268 }; 269 EXPORT_SYMBOL(vsc7514_ptp_regmap); 270 271 const u32 vsc7514_dev_gmii_regmap[] = { 272 REG(DEV_CLOCK_CFG, 0x0), 273 REG(DEV_PORT_MISC, 0x4), 274 REG(DEV_EVENTS, 0x8), 275 REG(DEV_EEE_CFG, 0xc), 276 REG(DEV_RX_PATH_DELAY, 0x10), 277 REG(DEV_TX_PATH_DELAY, 0x14), 278 REG(DEV_PTP_PREDICT_CFG, 0x18), 279 REG(DEV_MAC_ENA_CFG, 0x1c), 280 REG(DEV_MAC_MODE_CFG, 0x20), 281 REG(DEV_MAC_MAXLEN_CFG, 0x24), 282 REG(DEV_MAC_TAGS_CFG, 0x28), 283 REG(DEV_MAC_ADV_CHK_CFG, 0x2c), 284 REG(DEV_MAC_IFG_CFG, 0x30), 285 REG(DEV_MAC_HDX_CFG, 0x34), 286 REG(DEV_MAC_DBG_CFG, 0x38), 287 REG(DEV_MAC_FC_MAC_LOW_CFG, 0x3c), 288 REG(DEV_MAC_FC_MAC_HIGH_CFG, 0x40), 289 REG(DEV_MAC_STICKY, 0x44), 290 REG(PCS1G_CFG, 0x48), 291 REG(PCS1G_MODE_CFG, 0x4c), 292 REG(PCS1G_SD_CFG, 0x50), 293 REG(PCS1G_ANEG_CFG, 0x54), 294 REG(PCS1G_ANEG_NP_CFG, 0x58), 295 REG(PCS1G_LB_CFG, 0x5c), 296 REG(PCS1G_DBG_CFG, 0x60), 297 REG(PCS1G_CDET_CFG, 0x64), 298 REG(PCS1G_ANEG_STATUS, 0x68), 299 REG(PCS1G_ANEG_NP_STATUS, 0x6c), 300 REG(PCS1G_LINK_STATUS, 0x70), 301 REG(PCS1G_LINK_DOWN_CNT, 0x74), 302 REG(PCS1G_STICKY, 0x78), 303 REG(PCS1G_DEBUG_STATUS, 0x7c), 304 REG(PCS1G_LPI_CFG, 0x80), 305 REG(PCS1G_LPI_WAKE_ERROR_CNT, 0x84), 306 REG(PCS1G_LPI_STATUS, 0x88), 307 REG(PCS1G_TSTPAT_MODE_CFG, 0x8c), 308 REG(PCS1G_TSTPAT_STATUS, 0x90), 309 REG(DEV_PCS_FX100_CFG, 0x94), 310 REG(DEV_PCS_FX100_STATUS, 0x98), 311 }; 312 EXPORT_SYMBOL(vsc7514_dev_gmii_regmap); 313 314 const struct vcap_field vsc7514_vcap_es0_keys[] = { 315 [VCAP_ES0_EGR_PORT] = { 0, 4 }, 316 [VCAP_ES0_IGR_PORT] = { 4, 4 }, 317 [VCAP_ES0_RSV] = { 8, 2 }, 318 [VCAP_ES0_L2_MC] = { 10, 1 }, 319 [VCAP_ES0_L2_BC] = { 11, 1 }, 320 [VCAP_ES0_VID] = { 12, 12 }, 321 [VCAP_ES0_DP] = { 24, 1 }, 322 [VCAP_ES0_PCP] = { 25, 3 }, 323 }; 324 EXPORT_SYMBOL(vsc7514_vcap_es0_keys); 325 326 const struct vcap_field vsc7514_vcap_es0_actions[] = { 327 [VCAP_ES0_ACT_PUSH_OUTER_TAG] = { 0, 2 }, 328 [VCAP_ES0_ACT_PUSH_INNER_TAG] = { 2, 1 }, 329 [VCAP_ES0_ACT_TAG_A_TPID_SEL] = { 3, 2 }, 330 [VCAP_ES0_ACT_TAG_A_VID_SEL] = { 5, 1 }, 331 [VCAP_ES0_ACT_TAG_A_PCP_SEL] = { 6, 2 }, 332 [VCAP_ES0_ACT_TAG_A_DEI_SEL] = { 8, 2 }, 333 [VCAP_ES0_ACT_TAG_B_TPID_SEL] = { 10, 2 }, 334 [VCAP_ES0_ACT_TAG_B_VID_SEL] = { 12, 1 }, 335 [VCAP_ES0_ACT_TAG_B_PCP_SEL] = { 13, 2 }, 336 [VCAP_ES0_ACT_TAG_B_DEI_SEL] = { 15, 2 }, 337 [VCAP_ES0_ACT_VID_A_VAL] = { 17, 12 }, 338 [VCAP_ES0_ACT_PCP_A_VAL] = { 29, 3 }, 339 [VCAP_ES0_ACT_DEI_A_VAL] = { 32, 1 }, 340 [VCAP_ES0_ACT_VID_B_VAL] = { 33, 12 }, 341 [VCAP_ES0_ACT_PCP_B_VAL] = { 45, 3 }, 342 [VCAP_ES0_ACT_DEI_B_VAL] = { 48, 1 }, 343 [VCAP_ES0_ACT_RSV] = { 49, 24 }, 344 [VCAP_ES0_ACT_HIT_STICKY] = { 73, 1 }, 345 }; 346 EXPORT_SYMBOL(vsc7514_vcap_es0_actions); 347 348 const struct vcap_field vsc7514_vcap_is1_keys[] = { 349 [VCAP_IS1_HK_TYPE] = { 0, 1 }, 350 [VCAP_IS1_HK_LOOKUP] = { 1, 2 }, 351 [VCAP_IS1_HK_IGR_PORT_MASK] = { 3, 12 }, 352 [VCAP_IS1_HK_RSV] = { 15, 9 }, 353 [VCAP_IS1_HK_OAM_Y1731] = { 24, 1 }, 354 [VCAP_IS1_HK_L2_MC] = { 25, 1 }, 355 [VCAP_IS1_HK_L2_BC] = { 26, 1 }, 356 [VCAP_IS1_HK_IP_MC] = { 27, 1 }, 357 [VCAP_IS1_HK_VLAN_TAGGED] = { 28, 1 }, 358 [VCAP_IS1_HK_VLAN_DBL_TAGGED] = { 29, 1 }, 359 [VCAP_IS1_HK_TPID] = { 30, 1 }, 360 [VCAP_IS1_HK_VID] = { 31, 12 }, 361 [VCAP_IS1_HK_DEI] = { 43, 1 }, 362 [VCAP_IS1_HK_PCP] = { 44, 3 }, 363 /* Specific Fields for IS1 Half Key S1_NORMAL */ 364 [VCAP_IS1_HK_L2_SMAC] = { 47, 48 }, 365 [VCAP_IS1_HK_ETYPE_LEN] = { 95, 1 }, 366 [VCAP_IS1_HK_ETYPE] = { 96, 16 }, 367 [VCAP_IS1_HK_IP_SNAP] = { 112, 1 }, 368 [VCAP_IS1_HK_IP4] = { 113, 1 }, 369 /* Layer-3 Information */ 370 [VCAP_IS1_HK_L3_FRAGMENT] = { 114, 1 }, 371 [VCAP_IS1_HK_L3_FRAG_OFS_GT0] = { 115, 1 }, 372 [VCAP_IS1_HK_L3_OPTIONS] = { 116, 1 }, 373 [VCAP_IS1_HK_L3_DSCP] = { 117, 6 }, 374 [VCAP_IS1_HK_L3_IP4_SIP] = { 123, 32 }, 375 /* Layer-4 Information */ 376 [VCAP_IS1_HK_TCP_UDP] = { 155, 1 }, 377 [VCAP_IS1_HK_TCP] = { 156, 1 }, 378 [VCAP_IS1_HK_L4_SPORT] = { 157, 16 }, 379 [VCAP_IS1_HK_L4_RNG] = { 173, 8 }, 380 /* Specific Fields for IS1 Half Key S1_5TUPLE_IP4 */ 381 [VCAP_IS1_HK_IP4_INNER_TPID] = { 47, 1 }, 382 [VCAP_IS1_HK_IP4_INNER_VID] = { 48, 12 }, 383 [VCAP_IS1_HK_IP4_INNER_DEI] = { 60, 1 }, 384 [VCAP_IS1_HK_IP4_INNER_PCP] = { 61, 3 }, 385 [VCAP_IS1_HK_IP4_IP4] = { 64, 1 }, 386 [VCAP_IS1_HK_IP4_L3_FRAGMENT] = { 65, 1 }, 387 [VCAP_IS1_HK_IP4_L3_FRAG_OFS_GT0] = { 66, 1 }, 388 [VCAP_IS1_HK_IP4_L3_OPTIONS] = { 67, 1 }, 389 [VCAP_IS1_HK_IP4_L3_DSCP] = { 68, 6 }, 390 [VCAP_IS1_HK_IP4_L3_IP4_DIP] = { 74, 32 }, 391 [VCAP_IS1_HK_IP4_L3_IP4_SIP] = { 106, 32 }, 392 [VCAP_IS1_HK_IP4_L3_PROTO] = { 138, 8 }, 393 [VCAP_IS1_HK_IP4_TCP_UDP] = { 146, 1 }, 394 [VCAP_IS1_HK_IP4_TCP] = { 147, 1 }, 395 [VCAP_IS1_HK_IP4_L4_RNG] = { 148, 8 }, 396 [VCAP_IS1_HK_IP4_IP_PAYLOAD_S1_5TUPLE] = { 156, 32 }, 397 }; 398 EXPORT_SYMBOL(vsc7514_vcap_is1_keys); 399 400 const struct vcap_field vsc7514_vcap_is1_actions[] = { 401 [VCAP_IS1_ACT_DSCP_ENA] = { 0, 1 }, 402 [VCAP_IS1_ACT_DSCP_VAL] = { 1, 6 }, 403 [VCAP_IS1_ACT_QOS_ENA] = { 7, 1 }, 404 [VCAP_IS1_ACT_QOS_VAL] = { 8, 3 }, 405 [VCAP_IS1_ACT_DP_ENA] = { 11, 1 }, 406 [VCAP_IS1_ACT_DP_VAL] = { 12, 1 }, 407 [VCAP_IS1_ACT_PAG_OVERRIDE_MASK] = { 13, 8 }, 408 [VCAP_IS1_ACT_PAG_VAL] = { 21, 8 }, 409 [VCAP_IS1_ACT_RSV] = { 29, 9 }, 410 /* The fields below are incorrectly shifted by 2 in the manual */ 411 [VCAP_IS1_ACT_VID_REPLACE_ENA] = { 38, 1 }, 412 [VCAP_IS1_ACT_VID_ADD_VAL] = { 39, 12 }, 413 [VCAP_IS1_ACT_FID_SEL] = { 51, 2 }, 414 [VCAP_IS1_ACT_FID_VAL] = { 53, 13 }, 415 [VCAP_IS1_ACT_PCP_DEI_ENA] = { 66, 1 }, 416 [VCAP_IS1_ACT_PCP_VAL] = { 67, 3 }, 417 [VCAP_IS1_ACT_DEI_VAL] = { 70, 1 }, 418 [VCAP_IS1_ACT_VLAN_POP_CNT_ENA] = { 71, 1 }, 419 [VCAP_IS1_ACT_VLAN_POP_CNT] = { 72, 2 }, 420 [VCAP_IS1_ACT_CUSTOM_ACE_TYPE_ENA] = { 74, 4 }, 421 [VCAP_IS1_ACT_HIT_STICKY] = { 78, 1 }, 422 }; 423 EXPORT_SYMBOL(vsc7514_vcap_is1_actions); 424 425 const struct vcap_field vsc7514_vcap_is2_keys[] = { 426 /* Common: 46 bits */ 427 [VCAP_IS2_TYPE] = { 0, 4 }, 428 [VCAP_IS2_HK_FIRST] = { 4, 1 }, 429 [VCAP_IS2_HK_PAG] = { 5, 8 }, 430 [VCAP_IS2_HK_IGR_PORT_MASK] = { 13, 12 }, 431 [VCAP_IS2_HK_RSV2] = { 25, 1 }, 432 [VCAP_IS2_HK_HOST_MATCH] = { 26, 1 }, 433 [VCAP_IS2_HK_L2_MC] = { 27, 1 }, 434 [VCAP_IS2_HK_L2_BC] = { 28, 1 }, 435 [VCAP_IS2_HK_VLAN_TAGGED] = { 29, 1 }, 436 [VCAP_IS2_HK_VID] = { 30, 12 }, 437 [VCAP_IS2_HK_DEI] = { 42, 1 }, 438 [VCAP_IS2_HK_PCP] = { 43, 3 }, 439 /* MAC_ETYPE / MAC_LLC / MAC_SNAP / OAM common */ 440 [VCAP_IS2_HK_L2_DMAC] = { 46, 48 }, 441 [VCAP_IS2_HK_L2_SMAC] = { 94, 48 }, 442 /* MAC_ETYPE (TYPE=000) */ 443 [VCAP_IS2_HK_MAC_ETYPE_ETYPE] = { 142, 16 }, 444 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD0] = { 158, 16 }, 445 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD1] = { 174, 8 }, 446 [VCAP_IS2_HK_MAC_ETYPE_L2_PAYLOAD2] = { 182, 3 }, 447 /* MAC_LLC (TYPE=001) */ 448 [VCAP_IS2_HK_MAC_LLC_L2_LLC] = { 142, 40 }, 449 /* MAC_SNAP (TYPE=010) */ 450 [VCAP_IS2_HK_MAC_SNAP_L2_SNAP] = { 142, 40 }, 451 /* MAC_ARP (TYPE=011) */ 452 [VCAP_IS2_HK_MAC_ARP_SMAC] = { 46, 48 }, 453 [VCAP_IS2_HK_MAC_ARP_ADDR_SPACE_OK] = { 94, 1 }, 454 [VCAP_IS2_HK_MAC_ARP_PROTO_SPACE_OK] = { 95, 1 }, 455 [VCAP_IS2_HK_MAC_ARP_LEN_OK] = { 96, 1 }, 456 [VCAP_IS2_HK_MAC_ARP_TARGET_MATCH] = { 97, 1 }, 457 [VCAP_IS2_HK_MAC_ARP_SENDER_MATCH] = { 98, 1 }, 458 [VCAP_IS2_HK_MAC_ARP_OPCODE_UNKNOWN] = { 99, 1 }, 459 [VCAP_IS2_HK_MAC_ARP_OPCODE] = { 100, 2 }, 460 [VCAP_IS2_HK_MAC_ARP_L3_IP4_DIP] = { 102, 32 }, 461 [VCAP_IS2_HK_MAC_ARP_L3_IP4_SIP] = { 134, 32 }, 462 [VCAP_IS2_HK_MAC_ARP_DIP_EQ_SIP] = { 166, 1 }, 463 /* IP4_TCP_UDP / IP4_OTHER common */ 464 [VCAP_IS2_HK_IP4] = { 46, 1 }, 465 [VCAP_IS2_HK_L3_FRAGMENT] = { 47, 1 }, 466 [VCAP_IS2_HK_L3_FRAG_OFS_GT0] = { 48, 1 }, 467 [VCAP_IS2_HK_L3_OPTIONS] = { 49, 1 }, 468 [VCAP_IS2_HK_IP4_L3_TTL_GT0] = { 50, 1 }, 469 [VCAP_IS2_HK_L3_TOS] = { 51, 8 }, 470 [VCAP_IS2_HK_L3_IP4_DIP] = { 59, 32 }, 471 [VCAP_IS2_HK_L3_IP4_SIP] = { 91, 32 }, 472 [VCAP_IS2_HK_DIP_EQ_SIP] = { 123, 1 }, 473 /* IP4_TCP_UDP (TYPE=100) */ 474 [VCAP_IS2_HK_TCP] = { 124, 1 }, 475 [VCAP_IS2_HK_L4_DPORT] = { 125, 16 }, 476 [VCAP_IS2_HK_L4_SPORT] = { 141, 16 }, 477 [VCAP_IS2_HK_L4_RNG] = { 157, 8 }, 478 [VCAP_IS2_HK_L4_SPORT_EQ_DPORT] = { 165, 1 }, 479 [VCAP_IS2_HK_L4_SEQUENCE_EQ0] = { 166, 1 }, 480 [VCAP_IS2_HK_L4_FIN] = { 167, 1 }, 481 [VCAP_IS2_HK_L4_SYN] = { 168, 1 }, 482 [VCAP_IS2_HK_L4_RST] = { 169, 1 }, 483 [VCAP_IS2_HK_L4_PSH] = { 170, 1 }, 484 [VCAP_IS2_HK_L4_ACK] = { 171, 1 }, 485 [VCAP_IS2_HK_L4_URG] = { 172, 1 }, 486 [VCAP_IS2_HK_L4_1588_DOM] = { 173, 8 }, 487 [VCAP_IS2_HK_L4_1588_VER] = { 181, 4 }, 488 /* IP4_OTHER (TYPE=101) */ 489 [VCAP_IS2_HK_IP4_L3_PROTO] = { 124, 8 }, 490 [VCAP_IS2_HK_L3_PAYLOAD] = { 132, 56 }, 491 /* IP6_STD (TYPE=110) */ 492 [VCAP_IS2_HK_IP6_L3_TTL_GT0] = { 46, 1 }, 493 [VCAP_IS2_HK_L3_IP6_SIP] = { 47, 128 }, 494 [VCAP_IS2_HK_IP6_L3_PROTO] = { 175, 8 }, 495 /* OAM (TYPE=111) */ 496 [VCAP_IS2_HK_OAM_MEL_FLAGS] = { 142, 7 }, 497 [VCAP_IS2_HK_OAM_VER] = { 149, 5 }, 498 [VCAP_IS2_HK_OAM_OPCODE] = { 154, 8 }, 499 [VCAP_IS2_HK_OAM_FLAGS] = { 162, 8 }, 500 [VCAP_IS2_HK_OAM_MEPID] = { 170, 16 }, 501 [VCAP_IS2_HK_OAM_CCM_CNTS_EQ0] = { 186, 1 }, 502 [VCAP_IS2_HK_OAM_IS_Y1731] = { 187, 1 }, 503 }; 504 EXPORT_SYMBOL(vsc7514_vcap_is2_keys); 505 506 const struct vcap_field vsc7514_vcap_is2_actions[] = { 507 [VCAP_IS2_ACT_HIT_ME_ONCE] = { 0, 1 }, 508 [VCAP_IS2_ACT_CPU_COPY_ENA] = { 1, 1 }, 509 [VCAP_IS2_ACT_CPU_QU_NUM] = { 2, 3 }, 510 [VCAP_IS2_ACT_MASK_MODE] = { 5, 2 }, 511 [VCAP_IS2_ACT_MIRROR_ENA] = { 7, 1 }, 512 [VCAP_IS2_ACT_LRN_DIS] = { 8, 1 }, 513 [VCAP_IS2_ACT_POLICE_ENA] = { 9, 1 }, 514 [VCAP_IS2_ACT_POLICE_IDX] = { 10, 9 }, 515 [VCAP_IS2_ACT_POLICE_VCAP_ONLY] = { 19, 1 }, 516 [VCAP_IS2_ACT_PORT_MASK] = { 20, 11 }, 517 [VCAP_IS2_ACT_REW_OP] = { 31, 9 }, 518 [VCAP_IS2_ACT_SMAC_REPLACE_ENA] = { 40, 1 }, 519 [VCAP_IS2_ACT_RSV] = { 41, 2 }, 520 [VCAP_IS2_ACT_ACL_ID] = { 43, 6 }, 521 [VCAP_IS2_ACT_HIT_CNT] = { 49, 32 }, 522 }; 523 EXPORT_SYMBOL(vsc7514_vcap_is2_actions); 524